CN107644815A

CN107644815A - A kind of semiconductor devices and its manufacture method and electronic installation

Info

Publication number: CN107644815A
Application number: CN201610578207.6A
Authority: CN
Inventors: 周飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Zhongxin Nanfang integrated circuit manufacturing Co.,Ltd.; Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-07-21
Filing date: 2016-07-21
Publication date: 2018-01-30
Anticipated expiration: 2036-07-21
Also published as: CN107644815B

Abstract

The present invention provides a kind of semiconductor devices and its manufacture method and electronic installation, is related to technical field of semiconductors.This method includes：Using the mask layer of the patterning of the part of first dummy gate structure of the exposure above the second well region as mask, the ion implanting of the first conductive type impurity is carried out to the first exposed dummy grid material layer；Remove the second dummy grid material layer and part the first dummy grid material layer；The second dummy grid dielectric layer and part the first dummy grid dielectric layer are removed, to form the first grid groove and second grid groove positioned at I/O device regions and core device region respectively, remaining first dummy grid dielectric layer is stepped ramp type；Metal gate structure is formed in first grid groove and second grid groove.The method of the present invention, stepped ramp type dummy grid dielectric layer is formed in the I/O device regions of FinFET, the breakdown voltage of device is enhanced, improves the overall performance of device.

Description

A kind of semiconductor devices and its manufacture method and electronic installation

Technical field

The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method and electronics Device.

Background technology

With the continuous development of semiconductor technology, cross bimoment (LDMOS) device is widely used in power integrated circuit because it has good short-channel properties.LDMOS device is non- Often it is suitably applied RF (radio frequency) base stations and power MOSFET (mos field effect transistor) conversions.In RF skills In the application of art, because LDMOS has high power performance, high-gain, the excellent linearity (linearity) and low is manufactured into This, LDMOS device is mainly used in base station circuitry.In power MOSFET application, such as in DC-CD converters, LDMOS device has outstanding conversion performance, and LDMOS device can reduce conversion damage compared with other power converters Consumption.Therefore, LDMOS technologies are that base station of new generation brings higher power PAR, more high-gain and the linearity, simultaneously Higher data transmission rate is brought for multimedia service.

Because LDMOS device is generally used in power circuit, such as RF technologies and power MOSFETs devices, power circuit Need to obtain high-voltage power amplification and larger power output, therefore LDMOS device must be able to bear higher voltage.With LDMOS extensive use power integrated circuit, to LDMOS device performance requirements also more and more higher, it is desirable to higher LDMOS devices The breakdown voltage of part, it is also possible to it is required that increase threshold drift and good performance, in a word, to higher breakdown voltage The demand of LDMOS device is more and more urgent.Existing LDMOS device is difficult to meet the requirement with high breakdown voltage.

With the continuous diminution of device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin knot The development of structure field-effect transistor (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work The advanced semiconductor device of skill node, its can effectively control device it is scaled caused by the short channel for being difficult to overcome effect Answer, the density of the transistor array formed on substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin knot Structure (fin-shaped channel) is set, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.

In FinFET manufacture craft, LDMOS device is generally transformed into fin structure structure devices by planar device, After FinFET techniques are changed into, the breakdown voltage of LDMOS device will reduce LDMOS planar technologies.For LDMOS especially LDNMOS devices, grid oxygen breakdown are one of an important factor for limiting device total breakdown voltage (BVDs).

Therefore, the breakdown voltage of LDMOS device how is improved in FinFET techniques, is further to improve device performance Urgent problem.

The content of the invention

A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.

In view of the shortcomings of the prior art, a kind of manufacture method of semiconductor devices is provided in the embodiment of the present invention one, it is described Method includes：

Semiconductor substrate is provided, the Semiconductor substrate includes I/O device regions and core device region, in the I/O devices The first well region with the first conduction type, and the with the second conduction type are formed in the Semiconductor substrate in area Two well regions；

The first fin respectively in the I/O device regions and the core device region is formed on the semiconductor substrate Chip architecture and the second fin structure, wherein, the first fin structure part is located on first well region, partly positioned at described On second well region；

Isolation structure is formed in the Semiconductor substrate on the outside of first fin structure and second fin structure, institute The top surface of isolation structure is stated less than first fin structure and the top surface of second fin structure；

It is developed across the first dummy gate structure of part first fin structure and across second fin structure The second dummy gate structure, wherein, first dummy gate structure include the first dummy grid dielectric layer for being laminated from bottom to top and First dummy grid material layer, first dummy gate structure cover that first fin structure is located on second well region One edge, and extend outwardly on the isolation structure of the part on the outside of the first edge, the second dummy gate structure bag Include the second dummy grid dielectric layer being laminated from bottom to top and the second dummy grid material layer；

Exposure first dummy gate structure and the second dummy gate structure top surface are formed on the semiconductor substrate Interlayer dielectric layer；

Pattern is formed in the interlayer dielectric layer, part first dummy gate structure and second dummy gate structure The mask layer of change, the mask layer exposure of the patterning are located at the portion of first dummy gate structure above second well region Point；

Using the mask layer as mask, the first conductive type impurity is carried out to exposed the first dummy grid material layer Ion implanting；

The second dummy grid material layer and part the first dummy grid material layer are removed, wherein, the first pseudo- grid The part that pole material layer is located on first well region is completely removed, part of the residue on second well region described the The first dummy grid material layer of one conductive type impurity doping；

Using the remaining first dummy grid material layer as mask, the second dummy grid dielectric layer and part institute are removed The first dummy grid dielectric layer is stated, to be formed respectively positioned at the first grid groove of the I/O device regions and core device region and the Two gate trench, wherein, the remaining first dummy grid dielectric layer is stepped ramp type；

Metal gate structure is formed in the first grid groove and second grid groove.

Further, before the first fin structure and second fin structure is formed, the core devices are additionally included in The step of three well region with the first conduction type is formed in the Semiconductor substrate in area.

Further, second fin structure is formed on the 3rd well region.

Further, the thickness of the first dummy grid dielectric layer is more than the thickness of the second dummy grid dielectric layer.

Further, when forming first fin structure and second fin structure, in addition to：In the semiconductor The step of three fin structure on second well region is formed on substrate, wherein, the 3rd fin structure with it is described First fin structure is arranged at intervals.

Further, after first dummy gate structure is formed, formed before the interlayer dielectric layer, be additionally included in position Source electrode is formed in part first fin structure above first well region and is formed in the 3rd fin structure Drain electrode, wherein the source electrode and the drain electrode have the second conduction type.

Further, also include being formed in the side wall of first dummy gate structure before the source electrode and drain electrode is formed The step of side wall.

Further, the step of forming the metal gate structure includes：

Sequentially formed on the bottom and side wall of the first grid groove and the second grid groove high k dielectric layer and Work-function layer；

Gate electrode layer is filled in the first grid groove and the second grid groove.

Further, before the high k dielectric layer is formed, the first grid groove and the second grid are additionally included in The step of boundary layer, is formed on the bottom of groove.

Further, in the first grid groove, the remaining first dummy grid material layer is unformed silicon.

Further, the second dummy grid material layer and part the first dummy grid material are removed using wet etching Layer.

Further, using corrosive liquid of the tetramethyl ammonium hydroxide solution as the wet etching.

Further, first conduction type is p-type, and second conduction type is N-type, or, described first is conductive Type is N-type, and second conduction type is p-type.

Further, first conductive type impurity includes boron.

Another aspect of the present invention provides a kind of semiconductor devices, including：

Semiconductor substrate, the Semiconductor substrate include I/O device regions, the semiconductor in the I/O device regions The first well region with the first conduction type, and the second well region with the second conduction type are provided with substrate；

On the semiconductor substrate formed with the first fin structure in the I/O device regions, wherein, described One fin structure part is located on first well region, partly on second well region；

Isolation structure, the top surface of the isolation structure are provided with the Semiconductor substrate on the outside of first fin structure Less than the top surface of first fin structure；

Across the dummy grid dielectric layer of part first fin structure, wherein, the dummy grid dielectric layer is located at part On the first fin structure above first well region and second well region, and cover first fin structure and be located at institute The first edge on the second well region is stated, and is extended outwardly on the isolation structure of the part on the outside of the first edge；

Dummy grid material layer is provided with the dummy grid dielectric layer of part, doped with the dummy grid material layer One conductive type impurity, the dummy grid material layer is located on second well region of part, and covers first fin structure The first edge on second well region, and the part isolation junction extended outwardly on the outside of the first edge On structure,

Wherein, it is more than by the thickness of the dummy grid dielectric layer of dummy grid material layer covering pseudo- described in remainder The thickness of gate dielectric, it is stepped ramp type to make the dummy grid dielectric layer；

The first metal gate structure across part first fin structure is provided with the dummy grid dielectric layer, Wherein, part first metal gate structure is located in the dummy grid material layer.

Further, the Semiconductor substrate also includes core device region, the semiconductor in the core device region The second fin structure is provided with substrate, second across second fin structure is provided with second fin structure Metal gate structure.

Further, formed with interlayer dielectric layer, the first metal gate structure position on the semiconductor substrate surface In the interlayer dielectric layer, the top surface of the interlayer dielectric layer flushes with the top surface of first metal gate structure.

Further, the 3rd fin structure being provided with the semiconductor substrate on second well region, wherein, 3rd fin structure is arranged at intervals with first fin structure.

Further, formed with source electrode and in institute in part first fin structure above first well region State formed with drain electrode in the 3rd fin structure, wherein the source electrode and the drain electrode have the second conduction type.

Further, first metal gate structure includes high k dielectric layer, work-function layer and the gate electrode stacked gradually Layer.

Further, side wall is provided with the two side of first metal gate structure, wherein close to the dummy grid The side wall of material layer is located on the isolation structure.

Further, the first conductive type impurity includes boron.

Further, the material of the dummy grid material layer is unformed silicon.

Further aspect of the present invention provides a kind of electronic installation, and it includes foregoing semiconductor devices.

Manufacturing method according to the invention, step is formed in the I/O device regions (namely LDMOS device area) of FinFET Type dummy grid dielectric layer, because (namely the first fin structure is corresponding on the second well region in the extension area in LDMOS device area Region) thicker dummy grid dielectric layer is remained, therefore the breakdown voltage of device is enhanced, improve the overall performance of device.

Brief description of the drawings

The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, for explaining the principle of the present invention.

In accompanying drawing：

Figure 1A-Fig. 1 C show a kind of schematic diagram of conventional FinFET LDMOS device structure, and wherein Figure 1A is vertical view Figure, Figure 1B and Fig. 1 C are sectional view；

Fig. 2A to Fig. 2 F shows a kind of related step of the manufacture method of semiconductor devices of one embodiment of the present of invention Suddenly the sectional view of the structure formed；

Fig. 3 shows a kind of indicative flowchart of the manufacture method of semiconductor devices of one embodiment of the present of invention；

Fig. 4 shows the sectional view of the FinFET of one embodiment of the present of invention LDMOS device；

Fig. 5 shows the schematic diagram of electronic installation according to an embodiment of the present invention.

Embodiment

In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So And it is obvious to the skilled person that the present invention can be able to without one or more of these details Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art Row description.

It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end Same reference numerals represent identical element.

It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion Part, area, floor or part are represented by the second element, part, area, floor or part.

Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.

The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation, The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items There is combination.

Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore, Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic , their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.

In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions Outside, the present invention can also have other embodiment.

Figure 1A is according to the overlooking the structure diagram of the FinFET of prior art making LDMOS device, and accompanying drawing 1B For the cross-sectional view of the LDMOS device of the FinFET obtained by doing section along Figure 1A section lines.Such as Figure 1A and Figure 1B Shown, by taking NLDMOS device as an example, FinFET LDMOS device includes Semiconductor substrate 100, in the Semiconductor substrate 100 In be provided with p-well (PW) and N traps (NW), the first fin structure 1011 is provided with the Semiconductor substrate 100, wherein, One fin structure part is located in p-well, partly on N traps, in addition to the first fin structure 1011 spaced second Fin structure 1012, across the grid structure 102 of the first fin structure 1011, and the grid structure 102 covers the first fin knot One edge of structure 1011 is simultaneously extended on part fleet plough groove isolation structure (STI), and the grid structure 102 includes dummy grid dielectric layer (namely grid oxygen) 1021 and the gate material layers 1022 on dummy grid dielectric layer 1021, gate material layers 1022 are polysilicon Layer, formed with source electrode 1031 in the first fin structure 1011 not covered by grid structure 102, in the second fin structure 1012 In formed with drain electrode 1032, as shown in Figure 1 C, another p-well is also formed with the Semiconductor substrate 100 of the side of drain electrode, at this Be additionally provided with another grid structure 104 in p-well, and formed with another source electrode 1033 in the p-well, source electrode, drain electrode and Composition can be distinguished on grid and forms metal interconnection structure extraction source electrode, drain electrode and grid.

Wherein, in LDMOS device structure design, the polysilicon gate stacks in STI region are special for strengthening grid oxygen breakdown Property is extremely important, but in FinFET LDMOS device, the oxide in fleet plough groove isolation structure (STI) is recessed in source electrode In the STI region of drain side, the grid oxygen in STI bottoms is easy to breakdown voltage (BVDs) that is breakdown, and causing LDMOS device Performance reduces, and then influences the overall performance of LDMOS device.

Embodiment one

Presence in view of the above problems, the present invention propose a kind of manufacture method of semiconductor devices, as shown in figure 3, should Manufacture method includes following key step：

In step S301, there is provided Semiconductor substrate, the Semiconductor substrate include I/O device regions and core device region, The first well region with the first conduction type is formed in the Semiconductor substrate in the I/O device regions, and with the Second well region of two conduction types；

In step s 302, formed on the semiconductor substrate and be located at the I/O device regions and the core device respectively The first fin structure and the second fin structure in part area, wherein, the first fin structure part is located at first well region On, partly on second well region；

In step S303, the shape in the Semiconductor substrate on the outside of first fin structure and second fin structure Into isolation structure, the top surface of the isolation structure is less than first fin structure and the top surface of second fin structure；

In step s 304, it is developed across the first dummy gate structure of part first fin structure and across described Second dummy gate structure of the second fin structure, wherein, first dummy gate structure includes the first puppet being laminated from bottom to top Gate dielectric and the first dummy grid material layer, first dummy gate structure cover first fin structure positioned at described the First edge on two well regions, and extend outwardly on the isolation structure of the part on the outside of the first edge, described second Dummy gate structure includes the second dummy grid dielectric layer and the second dummy grid material layer being laminated from bottom to top；

In step S305, exposure first dummy gate structure and second puppet are formed on the semiconductor substrate The interlayer dielectric layer of grid structure top surface；

In step S306, in the interlayer dielectric layer, part first dummy gate structure and second dummy grid The mask layer of patterning is formed in structure, described first that the mask layer exposure of the patterning is located above second well region is pseudo- The part of grid structure；

In step S307, using the mask layer as mask, first is carried out to exposed the first dummy grid material layer The ion implanting of conductive type impurity；

In step S308, the second dummy grid material layer and part the first dummy grid material layer are removed, wherein, The part that the first dummy grid material layer is located on first well region is completely removed, and residue is on second well region Part first conductive type impurity doping the first dummy grid material layer；

In step S309, using the remaining first dummy grid material layer as mask, remove second dummy grid and be situated between Electric layer and part the first dummy grid dielectric layer, to be formed respectively positioned at the of the I/O device regions and core device region One gate trench and second grid groove, wherein, the remaining first dummy grid dielectric layer is stepped ramp type；

In step S310, metal gate structure is formed in the first grid groove and second grid groove.

Manufacturing method according to the invention, step is formed in the I/O device regions (namely LDMOS device area) of FinFET Type dummy grid dielectric layer, the breakdown voltage of device is enhanced, improve the overall performance of device.

Below, a kind of manufacture of semiconductor devices of one embodiment of the present of invention proposition is described with reference to figure 2A to Fig. 2 F Method, wherein, Fig. 2A to Fig. 2 F is a kind of correlation step of the manufacture method of semiconductor devices of one embodiment of the present of invention The sectional view of the structure of formation.

First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, it is (defeated that the Semiconductor substrate 200 includes I/O device regions 10 Enter output device area) and core device region (CORE), formed in the Semiconductor substrate 200 in the I/O device regions 10 The first well region 2011 with the first conduction type, and the second well region 2012 with the second conduction type.

The Semiconductor substrate 200 can be at least one of following material being previously mentioned in this step：Silicon, insulation Silicon (SOI) on body, silicon (SSOI) is laminated on insulator, is laminated SiGe (S-SiGeOI), germanium on insulator SiClx on insulator And germanium on insulator (GeOI) etc. (SiGeOI).Semiconductor substrate 200 selects silicon substrate in this embodiment.

It should be noted that the first conduction type is p-type, the second conduction type is N-type, or the first conduction type can be with For N-type, the second conduction type is p-type, is rationally set with specific reference to the type of device for needing to make, such as NLDMOS Device, then the first conduction type is p-type, and the second conduction type is N-type.

In the present embodiment, I/O device regions 10 include LDMOS device area, can be used for forming LDMOS devices in the region Part.

Wherein, various types of well regions can be formed in Semiconductor substrate 200 by the method for ion implanting, shown at one Example in, first conduction type is p-type, and second conduction type is N-type, then can by into Semiconductor substrate 200 from Sub- implanting p-type impurity such as boron, formed p-well region, by the intermediate ion of Semiconductor substrate 200 inject N-type impurity for example phosphorus or Arsenic etc., to form N well regions.

Exemplarily, the depth of the well region 2022 of the first well region 2011 and second is greater than the fin structure of predetermined formation Height, specifically reasonably set according to the requirement of practical devices.

Also further, as shown in Figure 2 D, it is additionally included in the Semiconductor substrate 200 in the core device region 20 The 3rd well region 2013 with the first conduction type is formed, for example, the 3rd well region 2013 can be p-well region.

Then, with continued reference to Fig. 2A and Fig. 2 D, formed in the Semiconductor substrate 200 and be located at the I/O devices respectively The first fin structure 2021 and the second fin structure 2022 in area 10 and the core device region 20, wherein, first fin The part of chip architecture 2021 is located on first well region 2011, partly on second well region 2012.

In one example, in addition to formed simultaneously in the Semiconductor substrate 200 and be located at second well region 2012 On the 3rd fin structure 2023 the step of, wherein, between the 3rd fin structure 2023 and first fin structure 2021 Every setting.

Wherein, multiple fin structures can be formed simultaneously on a semiconductor substrate, the width and length of fin structure can be complete Portion is identical, or fin structure is divided into multiple fin structure groups with different in width and length.Fin structure is to be formed at half Multiple strip structures on conductor substrate 200.

Specifically, the forming method of the first fin structure 2021, the second fin structure 2022 and the 3rd fin structure 2023 A certain kind is not limited to, a kind of exemplary forming method is given below：Hard mask layer is formed on semiconductor substrate 200 (not shown), form the various suitable techniques that the hard mask layer can use those skilled in the art to be familiar with, example Such as chemical vapor deposition method, the hard mask layer can be the oxide skin(coating) and silicon nitride layer being laminated from bottom to top；Patterning The hard mask layer, formed for etching Semiconductor substrate to be formed on multiple masks being isolated from each other of fin structure, The hard mask layer of the wherein patterning defines the width including fin structure, length and position etc.；In one embodiment, Using patterning process described in self-aligned double patterning case (SADP) process implementing；Using the hard mask layer of patterning as mask, etching half Conductor substrate 200, can be formed on the first fin structure 2021, the second fin structure 2022 and the 3rd fin structure 2023 Above-mentioned etching is carried out using the methods of dry etching or wet etching, wherein, deep dry etch process can be reactive ion etching, Ion beam etching, plasma etching, any combination of laser ablation or these methods.Single etching side can also be used Method, or more than one lithographic method can also be used.

Wherein, the part of the first fin structure 2021 is located on first well region 2011, partly positioned at described second On well region 2012, the 3rd fin structure 2023 is located on second well region 2012, due to formed the first fin structure 2021, Before second fin structure 2022 and the 3rd fin structure 2023, various well regions are formd in Semiconductor substrate 200, because This, the first fin structure 2021 being correspondingly formed include with the part of the identical conduction type of the first well region 2011 and with The part of the identical conduction type of second well region 2012, the 3rd fin structure 2023 then have and second well region 2012 Identical conduction type, the second fin structure 2022 have and the identical conduction type of the 3rd well region 2013.

Then, continue as shown in Figure 2 A, in first fin structure 2021 and the outside of second fin structure 2022 Semiconductor substrate on form isolation structure 204, the top surface of the isolation structure 202 is less than the He of the first fin structure 2021 The top surface of second fin structure 2022.

Specifically, depositing isolation material layer, with the gap being filled up completely with Semiconductor substrate between all fin structures. In one embodiment, the deposition is implemented using the chemical vapor deposition method with flowable.The material of spacer material layer Silica can be specifically as follows with selective oxidation thing, such as high-aspect-ratio technique (HARP) oxide.

Then spacer material layer described in etch-back, to the target of fin structure (the first fin structure, the second fin structure) Highly, isolation structure 204 is formed.Specifically, spacer material layer described in etch-back, with exposed portion fin structure, and then formed Fin structure with certain height.

With continued reference to Fig. 2A and Fig. 2 D, the first dummy gate structure of part first fin structure 2021 is developed across 203 and the second dummy gate structure across second fin structure 2022, wherein, first dummy gate structure 203 is wrapped Include the first dummy grid dielectric layer 2031 being laminated from bottom to top and the first dummy grid material layer 2032, first dummy gate structure 203 covering first fin structures 2021 are located at the first edge on second well region 2012, and extend outwardly into described On the part isolation structure 204 on the outside of first edge, second dummy gate structure includes second be laminated from bottom to top The dummy grid material layer of dummy grid dielectric layer 2081 and second.

It is pointed out that the term " across " used in the present invention, such as across fin structure (such as the first fin Structure, second fin structure etc.) dummy gate structure, refer to be each formed with puppet in the upper surface of the part of fin structure and side Grid structure, and the dummy gate structure is also formed on the part surface of Semiconductor substrate.Herein for the explanation of " across " It is equally applicable to cited below across metal gate structure of fin structure etc..

In one example, first can be sequentially depositing to form dummy grid dielectric layer and dummy grid material on a semiconductor substrate Layer.

Wherein, the dummy grid dielectric layer can select conventional oxide, such as SiO₂, the dummy grid material layer can To select semi-conducting material commonly used in the art, such as polysilicon etc. can be selected, it is not limited to it is a certain, it is not another herein One enumerate,

The deposition process of the dummy grid material layer can select the methods of chemical vapor deposition or ald.

Then the dummy grid dielectric layer and dummy grid material layer are patterned, to form first dummy gate structure 203 With the second dummy gate structure.Specifically, photoresist layer is formed in the dummy grid material layer, then exposure imaging, to be formed Opening, then using the photoresist layer as dummy grid material layer described in mask etch.

Afterwards, also optionally, side wall is formed in the side wall of the first dummy gate structure 203 and the second dummy gate structure (Spacer)2033。

Specifically, the side wall 2033 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure Into.As embodiment in the one of the present embodiment, the side wall is that silica, silicon nitride collectively constitute, and concrete technology is：Half The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on conductor substrate, is then formed using engraving method Side wall 2033.Side wall material can also be respectively formed in the top surface and side wall of the first dummy gate structure 203 and the second dummy gate structure The bed of material, afterwards the step of in by the method for planarization, such as cmp, the spacer material layer on top surface is gone Remove, form the side wall 2033 being located only within side wall.

Afterwards, can be with：The shape in part first fin structure 2021 above first well region 2011 Drain electrode 2052 is formed into source electrode 2051 and in the 3rd fin 2023, wherein the source electrode 2051 and the tool of drain electrode 2052 There is the second conduction type.

Forming the method for source electrode 2051 and drain electrode 2052 includes：Ion note is carried out to the predetermined region for forming source electrode and drain electrode Enter,, then can be to pre- for example, for nmos device wherein according to the suitable impurity of type selecting of the predetermined device formed The region for being shaped as source electrode and drain electrode carries out the ion implanting of N-type impurity (for example, boron), then can be to predetermined for PMOS device The ion implanting of source electrode and the region progress p type impurity of drain electrode is formed, p type impurity can include phosphorus or arsenic etc..

In one example, can also be in the region of source electrode 2051 and the 3rd fin 2023 in the first fin structure 2021 2052 area epitaxies that drain grow semiconductor material layer, to form lifting source and drain.

Alternatively, for PMOS device, groove can be formed respectively in the region of source electrode 2051 and 2052 regions of drain electrode, the groove Can be preferably " ∑ " connected in star, then epitaxial growth stressor layers in a groove, to form PMOS source leakage, for PMOS devices Part, stressor layers can select SiGe, and the extension can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid in the present invention One kind in phase epitaxy, hetero-epitaxy, molecular beam epitaxy.

In another example, for nmos device, groove is formed respectively in the region of source electrode 2051 and 2052 regions of drain electrode, And epitaxial growth stressor layers in the groove, to form NMOS source and drain, can select SiP, SiC or other the suitable of tension can be provided Stressor layers of the material of conjunction as NMOS, reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heterogeneous outer can be selected Prolong, one kind in molecular beam epitaxy forms the stressor layers.

It is noted that can be synchronously in the second fin structure of the second dummy gate structure both sides in core device region Formed the second source electrode and second drain electrode, second source electrode and second drain electrode can be nmos device source electrode and drain electrode, for example, N Type source electrode and drain electrode, at the same also can epitaxial growth stressor layers, will not be described here.

Then, interlevel dielectric deposition 206, to cover the Semiconductor substrate 200, and fill adjacent dummy gate structure it Between space.

Wherein, the interlayer dielectric layer 206 can select dielectric material commonly used in the art, such as various oxides Deng interlayer dielectric layer 206 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or height The material layer for having doped or undoped silica that density plasma (HDP) manufacturing process is formed, for example, it is undoped Silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer 206 can also be doping boron Or the spin cloth of coating-type glass (spin-on-glass, SOG) of doping phosphorus, the tetraethoxysilane (PTEOS) of doping phosphorus or doping The tetraethoxysilane (BTEOS) of boron.

So far, structure as shown in Figure 2 A is obtained.

Then, as shown in Figure 2 B, interlayer dielectric layer 206 is planarized, stopped to first dummy gate structure On 203 top surface.

The planarization on surface can be realized using flattening method conventional in field of semiconductor manufacture.The planarization side The non-limiting examples of method include mechanical planarization method and chemically mechanical polishing flattening method (CMP).Chemically mechanical polishing Flattening method is more often used.

Ultimately form the interlayer dielectric of the top surface of exposure first dummy gate structure 203 and second dummy gate structure Layer 206.

And the film layers such as the side wall on dummy gate structure top surface can also be removed in the lump in the planarization process.

Then, as shown in Figure 2 C, in the interlayer dielectric layer 206, part first dummy gate structure 203 and described The mask layer 207 of patterning is formed in two dummy gate structures, the exposure of mask layer 207 of the patterning is located at second well region The part of first dummy gate structure 203 of 2012 tops.

Specifically, mask layer 207 can generally include any one of several mask materials, include but is not limited to：Cover firmly Mold materials and photoresist mask material.Preferably, mask layer includes photoresist mask material.Photoresist mask material can include Other substrate materials in the group including positive-tone photo glue material, negative photo glue material and mixing Other substrate materials.Generally, Mask layer includes positive-tone photo glue material or negative photo glue material with from about 2000 to about 5000 angstroms of thickness.

In one example, photoresist mask material, then profit can be formed on semiconductor substrate 200 by the method for spin coating With photoetching process, the step such as including exposure imaging, photoresist mask material is patterned, to form the mask layer of patterning 207, it exposes the part of first dummy gate structure 203 positioned at the top of the second well region 2012.

Then, it is mask with the mask layer 207, carrying out first to exposed the first dummy grid material layer 2032 leads The ion implanting of electric type dopant, it is not incorporated than others so that the first dummy grid material layer 2032 including the impurity has The lower wet-etch rate of miscellaneous dummy grid material layer.

Specifically, the first conductive type impurity that the injection of this step intermediate ion uses can be closed according to the type of device The selection of reason, for example, for nmos device, first conductive type impurity can use p type impurity, such as boron etc..For PMOS device, first conductive type impurity can then use N-type impurity, such as phosphorus or arsenic etc..

In one example, first conductive type impurity includes boron, is pointed to using such as boron or boron fluoride described The part of the first dummy grid material layer 2032 of the top of second well region 2012 carries out ion implanting, with respect to other regions for example The part of the first undoped dummy grid material layer 2032 on first well region 2011, and in core device region it is undoped Dummy grid material layer etc., the first dummy grid material layer 2032 after the doping of the part is in wet etching (for example, tetramethyl hydrogen-oxygen Change ammonium salt solution wet etching) in there is lower etch rate.

First dummy grid material layer 2032 of doping can be unformed silicon, and undoped dummy grid material layer is mostly Polysilicon.

Then, as shown in Figure 2 D, while the second dummy grid material layer and institute in the core device region 20 are removed Part the first dummy grid material layer 2032 in I/O device regions is stated, wherein, the first dummy grid material layer 2032 is located at Part on first well region 2011 is completely removed, and part described first of the residue on second well region 2012 is led The first dummy grid material layer 2032 of electric type dopant doping.

Any suitable wet etching method well known to those skilled in the art can be used to remove the second dummy grid material The bed of material and part the first dummy grid material layer 2032, in one example, it is preferred that molten using TMAH (TMAH) Corrosive liquid of the liquid as the wet etching.

Wherein, do not mixed due to adulterating the first dummy grid material layer 2032 of (for example, boron doping) and being compared in TMAH solution Miscellaneous dummy grid material layer has lower etch rate, therefore, the second dummy grid material layer in by core device region 20 , still can be and the part that is located on first well region 2011 of the first dummy grid material layer 2032 is when removing completely The first dummy grid material layer 2032 that remainder adulterates on two well regions 2012, as shown in Figure 2 D.

Wherein, the second dummy grid dielectric layer in core device region 20 is exposed after the second dummy grid material layer of removal 2081, and remove part the first dummy grid material layer and expose part the first dummy grid dielectric layer in 10 in I/O device regions 2031。

Then, as shown in Figure 2 E, it is mask with the remaining first dummy grid material layer 2032, while removes described Two dummy grid dielectric layers 2081 and part the first dummy grid dielectric layer 2031, it is located at the I/O devices respectively to be formed Area 10 and the first grid groove 2091 and second grid groove 2092 of core device region 20, wherein, remaining described first is pseudo- Gate dielectric 2031 is stepped ramp type.

Specifically, dry etching can be used or removed using wet etching and remove the second dummy grid dielectric Layer 2081 and part the first dummy grid dielectric layer 2031.Dry etching can use each to different based on carbon fluoride gas Property etching method.Wet etching can use hydrofluoric acid solution, such as buffer oxide etch agent (buffer oxide etchant ) or hydrofluoric acid cushioning liquid (buffer solution of hydrofluoric acid (BHF)) (BOE).

Wherein, because the thickness of the first dummy grid dielectric layer 2031 is more than the thickness of the second dummy grid dielectric layer 2081, because This, when the second dummy grid dielectric layer 2081 is completely removed, remove only exposed part the first dummy grid dielectric layer 2031, And the first dummy grid dielectric layer 2031 covered by the remaining first dummy grid material layer 2032 will not be etched into, because This, ultimately forms the first dummy grid dielectric layer 2031 of stepped ramp type, and the first dummy grid dielectric layer 2031 is by remaining described The thickness for the part that first dummy grid material layer 2032 is covered is more than the thickness of uncovered part.

Then, as shown in Figure 2 F, metal gate is formed in the first grid groove 2091 and second grid groove 2092 Pole structure 210.

In one example, the step of forming metal gate structure 210 includes：

High k dielectric layer is sequentially formed on the bottom and side wall of the first grid groove and the second grid groove 2101 and work-function layer 2102；Gate electrode layer 2103 is filled in the first grid groove and the second grid groove.

Alternatively, before the high k dielectric layer 2101 is formed, the first grid groove and described second are additionally included in The step of boundary layer (not shown), is formed on the bottom of gate trench.

To put it more simply, the signal that metal gate structure 210 is formed in first grid groove 2091 is illustrate only in Fig. 2 F Figure, and can perform essentially identical technique in second grid groove 2092 and form metal gate structure, it will not be repeated here.

The constituent material of interface (IL) layer includes Si oxide (SiOx), and the effect for forming boundary layer is to improve high k dielectric Interfacial characteristics between layer and Semiconductor substrate.IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or Other suitable film layers.Thermal oxide, chemical vapor deposition (CVD), ald (ALD) or physical vapor can be used Deposit the suitable technique such as (PVD) and form boundary layer.The thickness range of boundary layer is 5 angstroms to 10 angstroms.

The k values (dielectric constant) of high k dielectric layer 2101 are usually more than 3.9, and its constituent material includes hafnium oxide, hafnium oxide Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia Titanium, aluminum oxide etc., preferably hafnium oxide, zirconium oxide or aluminum oxide.Chemical vapour deposition technique (CVD), atomic layer can be used The suitable technique such as sedimentation (ALD) or physical vaporous deposition (PVD) forms high k dielectric layer 2101.High k dielectric layer 2101 Thickness range be 10 angstroms to 30 angstroms.

In one example, for PMOS device, the work-function layer 2102 can be P-type workfunction layer (PWF), its material It can select to be but be not limited to TixN1-x, TaC, MoN, TaN either combinations thereof or other suitable film layers.Can be with The technique being adapted to using CVD, ALD or PVD etc. forms P-type workfunction layer.The thickness range of P-type workfunction layer be 10 angstroms extremely 580 angstroms.

In another example, for nmos device, the work-function layer 2102 can be N-type workfunction layer (NWF), N-type The material of work-function layer can select to be but be not limited to TaAlC, TaC, Ti, Al, TixAl1-x or other suitable film layers. The material of N-type workfunction layer is preferably TiAl.The suitable technique such as CVD, ALD or PVD can be used to form N-type work function Layer.The thickness range of N-type workfunction layer is 10 angstroms to 80 angstroms.

The material of gate electrode layer 2103 can select to be but be not limited to Al, W or other suitable film layers.It can use CVD, ALD or PVD etc. suitable technique forms gate electrode layer 2103.

In one example, form metal W using chemical vapor deposition method and be used as gate electrode layer 2103.Wherein, CVD works Skill uses WF₆As reacting gas, WF is decomposed₆Deposition forms metal W.

Exemplarily, depositing gate electrode layer fills all gate recess, and spills on the surface of interlayer dielectric layer 206 Side, then flatening process is performed, for example (,) cmp or wet etching etc., the table until exposing interlayer dielectric layer 206 Face, also the multiple film layers deposited in abovementioned steps on the surface of interlayer dielectric layer 206 can be removed in the lump in the lump in the process.

Due to also remaining with the first dummy grid material layer of part doping, the part dummy grid below metal gate structure The material of material layer includes unformed silicon (a-Si), and the unformed silicon instead of part metals grid structure as LDMOS device Grid structure.

So far the introduction of the committed step of the manufacture method to the semiconductor devices of invention is completed, for complete device The step of making also needs other, such as the making for the metal interconnection structure for drawing source electrode, drain electrode, grid is formed in back end of line Deng will not be repeated here.

In summary, manufacturing method according to the invention, in I/O device regions (namely the LDMOS device of FinFET Area) stepped ramp type dummy grid dielectric layer is formed, due to the extension area in LDMOS device area, (namely the first fin structure is correspondingly located at Region on second well region) thicker dummy grid dielectric layer is remained, therefore the breakdown voltage of device is enhanced, improve device Overall performance.

Embodiment two

The present invention also provides the semiconductor devices that a kind of manufacture method using in embodiment one is formed, the semiconductor devices LDMOS device including FinFET.

Below with reference to Fig. 4, the structure of the semiconductor devices of the present invention is described in detail, semiconductor devices of the invention Including：Semiconductor substrate 300.

The Semiconductor substrate 300 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator (SOI) silicon (SSOI), is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator And germanium on insulator (GeOI) etc. (SiGeOI).Semiconductor substrate 300 selects silicon substrate in this embodiment.

In the present embodiment, I/O device regions include LDMOS device area, in this region formed with LDMOS device.

In one example, the first well region 3011 is P type trap zone, and the second well region 3012 is N-type well region.

Formed with the first fin structure 3021 in the I/O device regions in the Semiconductor substrate 300, its In, the part of the first fin structure 3021 is located on first well region 3011, partly on second well region 3012.

In one example, the Semiconductor substrate also includes core device region, described in the core device region The second fin structure is provided with Semiconductor substrate, is also formed with having first to lead in Semiconductor substrate corresponding to core device region 3rd well region of electric type, wherein the second fin structure is located on the 3rd well region.

Exemplarily, the 3rd fin on second well region 3012 is provided with the Semiconductor substrate 300 Structure 3023, wherein, the 3rd fin structure 3023 is arranged at intervals with first fin structure 3021.

Wherein, the multiple fin structure width and length formed on a semiconductor substrate can be all identical, or fin Structure is divided into multiple fin structure groups with different in width and length.Each fin structure can be to be formed at Semiconductor substrate Strip structure on 300.

Wherein, the part of the first fin structure 3021 is located on first well region 3011, partly positioned at described second On well region 3012, the 3rd fin structure 3023 is located on second well region 3012, due to formed the first fin structure 3021, Before second fin structure and the 3rd fin structure 3023, various well regions are formd in Semiconductor substrate 300, therefore, The first fin structure 3021 being correspondingly formed include with the part of the identical conduction type of the first well region 3011 and with institute The part of the identical conduction type of the second well region 3012 is stated, the 3rd fin structure 3023 then has and the phase of the second well region 3012 Same conduction type, the second fin structure has and the 3rd well region identical conduction type.

Wherein, isolation structure 304, institute are provided with the Semiconductor substrate 300 in the outside of the first fin structure 3021 The top surface for stating isolation structure 304 is less than the top surface of first fin structure 3021.

Further, the portion in the gap on the filling semiconductor substrate 300 of isolation structure 304 between all adjacent fin structures Point, and top surface is less than the top surface of arbitrary fin structure.

The material of isolation structure 304 can be with selective oxidation thing, such as high-aspect-ratio technique (HARP) oxide, specifically can be with Can also be that silica obtained etc. is deposited by the chemical vapor deposition method of flowable for silica.

The semiconductor devices of the present invention also includes：Across the dummy grid dielectric layer of part first fin structure 3021 3031, wherein, the dummy grid dielectric layer 3031 is located on part first well region 3011 and second well region 3012 On first fin structure 3021 of side, and cover first fin structure 3021 is located on second well region 3012 first Edge, and extend outwardly on the isolation structure 304 of the part on the outside of the first edge.

Dummy grid material layer 3032, the dummy grid material layer are provided with the dummy grid dielectric layer 3031 of part Doped with the first conductive type impurity in 3032, the dummy grid material layer 3032 is located on second well region 3012 of part, And the first edge that first fin structure 3021 is located on second well region 3012 is covered, and extend outwardly into described On the part isolation structure 304 on the outside of one edge.

Wherein, the thickness of the dummy grid dielectric layer 3031 covered by the dummy grid material layer 3032 is more than its remaining part Divide the thickness of the dummy grid dielectric layer 3031, it is stepped ramp type to make the dummy grid dielectric layer 3031.

The dummy grid dielectric layer 3031 can select conventional oxide, such as SiO₂, the dummy grid material layer 3032 can select semi-conducting material commonly used in the art, it is not limited to and it is a certain, it will not enumerate herein, wherein, institute State doped with the first conductive type impurity in dummy grid material layer 3032, first conductive type impurity can be N-type impurity, example Such as boron, that is, dummy grid material layer 3032 is boron doped unformed silicon.

The first metal across part first fin structure 3021 is provided with the dummy grid dielectric layer 3031 Grid structure 310, wherein, part first metal gate structure 310 is located in the dummy grid material layer 3032.

Further, it is provided with second fin structure in core device region across second fin structure The second metal gate structure.

Each metal gate structure (such as the first metal gate structure and second metal gate structure) includes sequentially forming High k dielectric layer 3101, work-function layer 3102 and gate electrode layer 3103.

Wherein, the lamination of high k dielectric layer 3101 and work-function layer 3102 composition surrounds the bottom and side of gate electrode layer 3103 Wall.

In one example, it is additionally provided with boundary layer between the dummy grid dielectric layer 3031 and high k dielectric layer 3101 (not shown).

The constituent material of interface (IL) layer includes Si oxide (SiOx), and the effect for forming boundary layer is to improve high k dielectric Interfacial characteristics between layer and Semiconductor substrate.IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or Other suitable film layers.The thickness range of boundary layer is 5 angstroms to 10 angstroms.

The k values (dielectric constant) of high k dielectric layer 3101 are usually more than 3.9, and its constituent material includes hafnium oxide, hafnium oxide Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia Titanium, aluminum oxide etc., preferably hafnium oxide, zirconium oxide or aluminum oxide.The thickness range of high k dielectric layer 3101 is 10 angstroms to 30 Angstrom.

In one example, for PMOS device, the work-function layer 3102 can be P-type workfunction layer (PWF), its material It can select to be but be not limited to TixN1-x, TaC, MoN, TaN either combinations thereof or other suitable film layers.P-type work( The thickness range of function layer is 10 angstroms to 580 angstroms.

In another example, for nmos device, the work-function layer 3102 can be N-type workfunction layer (NWF), N-type The material of work-function layer can select to be but be not limited to TaAlC, TaC, Ti, Al, TixAl1-x or other suitable film layers. The material of N-type workfunction layer is preferably TiAl.The thickness range of N-type workfunction layer is 10 angstroms to 80 angstroms.

The material of gate electrode layer 3103 can select to be but be not limited to Al, W or other suitable film layers.

Side wall 3033 is provided with the two side of first metal gate structure 310, wherein close to the dummy grid The side wall 3033 of material layer 3032 is located on the isolation structure 304.

The side wall 3033 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and formed.It is used as this Embodiment in the one of embodiment, the side wall is silica, silicon nitride collectively constitutes

Further, formed with source electrode in part first fin structure above first well region 3011 3051 and in the 3rd fin structure 3023 formed with drain electrode 3052, wherein the source electrode 3051 and it is described drain electrode 3052 tool There is the second conduction type, such as it is N-type source and drain electrode.Source electrode 3051 is formed at not by the He of the first metal gate structure 310 In the subregion for the first fin structure that side wall 3033 is covered.

The stressor layers of epitaxial growth, the material of the stressor layers are also provided with corresponding source electrode 3051 and 3052 regions of drain electrode Matter can differ according to the type of device, and for nmos device, stressor layers can be SiP, SiC or other can provide drawing The material of stress, for PMOS device, the stressor layers are preferably " Σ " type, and its material can be that SiGe can provide compression Material.

It is noted that form in the second fin structure of the second dummy gate structure both sides in core device region Two source electrodes and the second drain electrode, second source electrode and the second drain electrode can be source electrode and the drain electrode of nmos device, for example, N-type source And drain electrode, while also can epitaxial growth stressor layers, will not be described here.

Formed with interlayer dielectric layer 306, first metal gate structure 310 on the surface of Semiconductor substrate 300 In the interlayer dielectric layer 306, the top surface of the top surface of the interlayer dielectric layer 306 and first metal gate structure is neat It is flat.

The interlayer dielectric layer 306 can select dielectric material commonly used in the art, such as various oxides etc., interlayer Dielectric layer 306 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or high density etc. from The material layer for having doped or undoped silica that daughter (HDP) manufacturing process is formed, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer 306 can also be doping boron or doping The spin cloth of coating-type glass (spin-on-glass, SOG) of phosphorus, the tetraethoxysilane (PTEOS) for adulterating phosphorus adulterate the four of boron Ethoxysilane (BTEOS).

Other elements are also possible that for complete device, for example, the metal of the extractions such as source electrode, drain electrode, grid is mutual Link structure etc., will not be repeated here.

Obtain because the semiconductor devices of the present invention is made using foregoing manufacture method, have in foregoing manufacture method During excellent effect, therefore the semiconductor devices formed has same technique effect, due to the LDMOS devices of the semiconductor devices Formed with stepped ramp type dummy grid dielectric layer in part area, therefore the device has stronger breakdown voltage, higher performance.

Embodiment three

Present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment two, the semiconductor device Part is prepared according to the methods described of embodiment one.

The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV Any electronic product such as machine, VCD, DVD, navigator, DPF, camera, video camera, recording pen, MP3, MP4, PSP is set It is standby, or any intermediate products including circuit.The electronic installation of the embodiment of the present invention, due to having used above-mentioned circuit, Thus there is better performance.

Wherein, Fig. 5 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401 Display portion 402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..

Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：

It is provided with dummy grid dielectric layer and dummy grid material layer across part first fin structure, the dummy grid Doped with the first conductive type impurity in material layer, wherein, the dummy grid dielectric layer be located at part first well region and Above second well region, the dummy grid material is located at the top of the dummy grid dielectric layer, the dummy grid material layer position In on second well region of part, covering first fin structure is located at the first edge on second well region, and outwards Extend on the isolation structure of the part on the outside of the first edge, the dummy grid covered by the dummy grid material layer The thickness of dielectric layer is more than the thickness of dummy grid dielectric layer described in remainder, and it is stepped ramp type to make the dummy grid dielectric layer；

The first metal gate structure across part first fin structure is provided with, wherein, first metal gate Pole structure is located on the dummy grid dielectric layer and the dummy grid material layer.

Because the LDMOS device area of semiconductor devices of the invention is formed with stepped ramp type dummy grid dielectric layer, therefore it has There are stronger breakdown voltage, higher performance, and then the electronic installation including the semiconductor devices also to have accordingly higher Performance.

The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims

1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：

Semiconductor substrate is provided, the Semiconductor substrate includes I/O device regions and core device region, in the I/O device regions The Semiconductor substrate in formed with the first conduction type the first well region, and with the second conduction type the second trap Area；

The first fin knot respectively in the I/O device regions and the core device region is formed on the semiconductor substrate Structure and the second fin structure, wherein, the first fin structure part is located on first well region, partly positioned at described second On well region；

Form isolation structure in the Semiconductor substrate on the outside of first fin structure and second fin structure, it is described every Top surface from structure is less than the top surface of first fin structure and second fin structure；

Be developed across the first dummy gate structure of part first fin structure and across second fin structure Two dummy gate structures, wherein, first dummy gate structure includes the first dummy grid dielectric layer and first being laminated from bottom to top Dummy grid material layer, first dummy gate structure cover the first side that first fin structure is located on second well region Edge, and extend outwardly on the isolation structure of the part on the outside of the first edge, second dummy gate structure is included certainly The the second dummy grid dielectric layer and the second dummy grid material layer of lower and upper stacking；

The layer of exposure first dummy gate structure and the second dummy gate structure top surface is formed on the semiconductor substrate Between dielectric layer；

Patterning is formed in the interlayer dielectric layer, part first dummy gate structure and second dummy gate structure Mask layer, the mask layer exposure of the patterning are located at the part of first dummy gate structure above second well region；

Using the mask layer as mask, the ion of the first conductive type impurity is carried out to exposed the first dummy grid material layer Injection；

The second dummy grid material layer and part the first dummy grid material layer are removed, wherein, the first dummy grid material The part that the bed of material is located on first well region is completely removed, and part described first of the residue on second well region is led The first dummy grid material layer of electric type dopant doping；

Using the remaining first dummy grid material layer as mask, the second dummy grid dielectric layer and part described the are removed One dummy grid dielectric layer, to form the first grid groove and second gate positioned at the I/O device regions and core device region respectively Pole groove, wherein, the remaining first dummy grid dielectric layer is stepped ramp type；

Metal gate structure is formed in the first grid groove and second grid groove.

2. manufacture method as claimed in claim 1, it is characterised in that forming the first fin structure and the second fin knot Before structure, it is additionally included in and the 3rd trap with the first conduction type is formed the Semiconductor substrate in the core device region Nei The step of area.

3. manufacture method as claimed in claim 2, it is characterised in that second fin structure is formed at the 3rd well region On.

4. manufacture method as claimed in claim 1, it is characterised in that the thickness of the first dummy grid dielectric layer is more than described The thickness of second dummy grid dielectric layer.

5. manufacture method as claimed in claim 1, it is characterised in that forming first fin structure and second fin During chip architecture, in addition to：The step of forming three fin structure on second well region on the semiconductor substrate, Wherein, the 3rd fin structure is arranged at intervals with first fin structure.

6. manufacture method as claimed in claim 5, it is characterised in that after first dummy gate structure is formed, formed Before the interlayer dielectric layer, it is additionally included in first fin structure of the part above first well region and forms source Pole simultaneously forms drain electrode in the 3rd fin structure, wherein the source electrode and the drain electrode have the second conduction type.

7. manufacture method as claimed in claim 6, it is characterised in that be additionally included in institute before the source electrode and drain electrode is formed State the step of side wall is formed in the side wall of the first dummy gate structure.

8. manufacture method as claimed in claim 1, it is characterised in that the step of forming the metal gate structure includes：

High k dielectric layer and work content are sequentially formed on the bottom and side wall of the first grid groove and the second grid groove Several layers；

9. manufacture method as claimed in claim 8, it is characterised in that before the high k dielectric layer is formed, be additionally included in institute State the step of boundary layer is formed on the bottom of first grid groove and the second grid groove.

10. manufacture method as claimed in claim 1, it is characterised in that in the first grid groove, remaining described One dummy grid material layer is unformed silicon.

11. manufacture method as claimed in claim 1, it is characterised in that remove the second dummy grid material using wet etching The bed of material and part the first dummy grid material layer.

12. manufacture method as claimed in claim 11, it is characterised in that using tetramethyl ammonium hydroxide solution as described wet The corrosive liquid of method etching.

13. the manufacture method as described in any one of claim 1 to 12, it is characterised in that first conduction type is p-type, Second conduction type is N-type, or, first conduction type is N-type, and second conduction type is p-type.

14. manufacture method as claimed in claim 1, it is characterised in that first conductive type impurity includes boron.

A kind of 15. semiconductor devices, it is characterised in that including：

Semiconductor substrate, the Semiconductor substrate include I/O device regions, the Semiconductor substrate in the I/O device regions In be provided with the first well region with the first conduction type, and the second well region with the second conduction type；

On the semiconductor substrate formed with the first fin structure in the I/O device regions, wherein, first fin Chip architecture part is located on first well region, partly on second well region；

Isolation structure is provided with the Semiconductor substrate on the outside of first fin structure, the top surface of the isolation structure is less than The top surface of first fin structure；

Across the dummy grid dielectric layer of part first fin structure, wherein, the dummy grid dielectric layer is located at described in part On the first fin structure above first well region and second well region, and first fin structure is covered positioned at described the First edge on two well regions, and extend outwardly on the isolation structure of the part on the outside of the first edge；

Dummy grid material layer is provided with the dummy grid dielectric layer of part, is led in the dummy grid material layer doped with first Electric type dopant, the dummy grid material layer are located on second well region of part, and cover first fin structure and be located at The first edge on second well region, and the part isolation structure extended outwardly on the outside of the first edge On,

Wherein, dummy grid described in remainder is more than by the thickness of the dummy grid dielectric layer of dummy grid material layer covering The thickness of dielectric layer, it is stepped ramp type to make the dummy grid dielectric layer；

The first metal gate structure across part first fin structure is provided with the dummy grid dielectric layer, its In, part first metal gate structure is located in the dummy grid material layer.

16. semiconductor devices as claimed in claim 15, it is characterised in that the Semiconductor substrate also includes core devices Area, the second fin structure is provided with the Semiconductor substrate in the core device region, in second fin structure On be provided with the second metal gate structure across second fin structure.

17. semiconductor devices as claimed in claim 15, it is characterised in that formed with layer on the semiconductor substrate surface Between dielectric layer, first metal gate structure is located in the interlayer dielectric layer, the top surface of the interlayer dielectric layer and described the The top surface of one metal gate structure flushes.

18. semiconductor devices as claimed in claim 15, it is characterised in that be provided with the semiconductor substrate positioned at institute The 3rd fin structure on the second well region is stated, wherein, the 3rd fin structure is arranged at intervals with first fin structure.

19. semiconductor devices as claimed in claim 18, it is characterised in that in the part institute above first well region State in the first fin structure formed with source electrode and in the 3rd fin structure formed with drain electrode, wherein the source electrode and described Drain electrode has the second conduction type.

20. semiconductor devices as claimed in claim 15, it is characterised in that first metal gate structure includes layer successively Folded high k dielectric layer, work-function layer and gate electrode layer.

21. semiconductor devices as claimed in claim 15, it is characterised in that in the two side of first metal gate structure On be provided with side wall, wherein the side wall close to the dummy grid material layer is located on the isolation structure.

22. semiconductor devices as claimed in claim 15, it is characterised in that the first conductive type impurity includes boron.

23. semiconductor devices as claimed in claim 15, it is characterised in that the material of the dummy grid material layer is unformed Silicon.

24. the semiconductor devices as any one of claim 15 to 23, it is characterised in that first conduction type is P-type, second conduction type are N-type, or, first conduction type is N-type, and second conduction type is p-type.

25. a kind of electronic installation, it is characterised in that including the semiconductor devices as any one of claim 15-24.