CN106531632B

CN106531632B - Method for manufacturing stacked nanowire MOS transistor

Info

Publication number: CN106531632B
Application number: CN201510575026.3A
Authority: CN
Inventors: 殷华湘; 马小龙; 秦长亮; 朱慧珑; 陈大鹏
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2015-09-10
Filing date: 2015-09-10
Publication date: 2020-01-03
Anticipated expiration: 2035-09-10
Also published as: CN106531632A

Abstract

A stacked nanowire MOS transistor manufacturing method comprises the following steps: forming a plurality of fins extending in a first direction on a substrate; forming a plurality of nanowires in each fin, with a protective layer between adjacent nanowires; forming a dummy gate stack on the nanowire extending in a second direction and surrounding the plurality of nanowires; forming source and drain regions on two sides of the pseudo gate stack, wherein a plurality of nanowires between the source and drain regions form a channel region; etching to remove the pseudo gate stack; etching to remove the protective layer and expose a plurality of suspended nanowires; a gate stack is formed on the plurality of nanowires extending in the second direction and surrounding the plurality of nanowires. According to the manufacturing method of the stacked nanowire MOS transistor, the groove is etched back and laterally and filled for multiple times, the nanowire channel with good quality is formed, meanwhile, the surface defects of the nanowire are reduced by the protective layer, and the effective width of the conductive channel is fully increased at low cost, so that the driving current and the reliability are improved.

Description

Method for manufacturing stacked nanowire MOS transistor

Technical Field

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a stacked nanowire MOS transistor in a back gate structure.

Background

In current sub-20 nm technology, a three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances gate control capability, suppresses leakage and short channel effects.

For example, compared with a conventional single-gate bulk Si or SOI MOSFET, a MOSFET with a dual-gate SOI structure can suppress a Short Channel Effect (SCE) and a Drain Induced Barrier Lowering (DIBL) effect, has a lower junction capacitance, can implement channel light doping, can adjust a threshold voltage by setting a work function of a metal gate, can obtain about 2 times of a driving current, and reduces a requirement for an effective gate oxide thickness (EOT). Compared with the double-gate device, the triple-gate device has the advantages that the gate surrounds the top surface and two side surfaces of the channel region, and the control capability of the gate is stronger. Further, a fully-wrapped nanowire multi-gate device is more advantageous.

Although the gate-all-around nanowire device has a better gate control effect, can control a short channel effect more effectively, and has more advantages in the reduction process of the sub-14 nm technology, one key problem is that a small conductive channel cannot provide more driving current in an equivalent silicon plane area.

For example, for a device with an equivalent line width of 1 μm, the size of the gate-all-around nanowire device is satisfied: d n + (n-1) s 1 μm, and pi d n >1 μm. Where d is the diameter of a single Nanowire (NW), n is the number of nanowires, and s is the spacing between nanowires. Therefore, for diameters d of 3, 5, 7, 10nm, respectively, the nanowire pitch s must be less than 6.4, 10.6, 15, 21.4nm, respectively. That is, if a gate width equivalent to 1um for bulk silicon is to be obtained, the parallel alignment of the nanowire devices is very tight. According to the existing FinFET exposure and etching technology (Fin spacing is about 60 nanometers), the nanowire three-dimensional arrangement structure with extremely small spacing is difficult to realize.

In summary, implementing the stacked gate-all-around nanowire structure in the vertical direction is an effective method for increasing the driving current of the transistor, but the implementation process (fabrication method) is very difficult, and compatibility with the conventional process and reduction of the process cost face significant challenges. For example, one existing approach to achieving stacked nanowires is to use Si/SiGe multi-layer heteroepitaxy and perform selective etching, i.e., alternating a plurality of stacks of Si and SiGe sequentially on a buried oxide layer (BOX), and then selectively removing the SiGe by methods such as wet etching, thereby leaving a stack of Si nanowires. This method is severely affected by the quality of the epitaxial thin layer, which greatly increases the process cost.

Therefore, a new nanowire device structure and a method for fabricating the same are needed to increase the effective width of the conductive channel to increase the driving current.

Disclosure of Invention

In view of the above, the present invention is directed to overcoming the above technical difficulties and providing a nanowire device structure and a method for fabricating the same, which can increase the effective width of a conductive channel to increase the driving current.

Therefore, the invention provides a method for manufacturing a stacked nanowire MOS transistor, which comprises the following steps: forming a plurality of fins extending in a first direction on a substrate; forming a plurality of nanowires in each fin, with a protective layer between adjacent nanowires; forming a dummy gate stack on the nanowire extending in a second direction and surrounding the plurality of nanowires; forming source and drain regions on two sides of the pseudo gate stack, wherein a plurality of nanowires between the source and drain regions form a channel region; etching to remove the pseudo gate stack; etching to remove the protective layer and expose a plurality of suspended nanowires; a gate stack is formed on the plurality of nanowires extending in the second direction and surrounding the plurality of nanowires.

Wherein the step of forming a plurality of nanowires in each fin further comprises: depositing shallow trench isolation between the fins; etching back the shallow trench isolation to expose the first part of the top of the fin; laterally etching a first part of the top of the fin to form a first through groove, wherein the rest part of the first part of the top of the fin forms a first nanowire; depositing a first protective layer to fill at least the first recess.

Wherein, after forming the first nanowire, further comprising: anisotropically back-etching the first protective layer to isolate the shallow trench and expose the second part in the middle of the fin; laterally etching the second part in the middle of the fin to form a through second groove, wherein the rest part of the second part in the middle of the fin forms a second nanowire; depositing a second protective layer to at least fill the second groove; and repeating the steps to form a plurality of nanowires, wherein the first protective layer and the second protective layer jointly form a protective layer.

Wherein the shape of the first groove and/or the second groove comprises a rectangle, a trapezoid, an inverted trapezoid, a sigma, a D, a C and combinations thereof.

The step of laterally etching the fins comprises isotropic plasma dry etching with transverse etching depth, or a combination method of isotropic etching and anisotropic etching, or a wet etching method of selectively etching in different crystal directions.

Wherein, the removing the protective layer further comprises surface treatment and rounding processes of the nanowires.

Wherein, further including after forming the source drain region: and depositing an interlayer dielectric layer, and flattening the interlayer dielectric layer until the dummy gate stack is exposed.

Wherein, the step of forming the source and drain regions further comprises: etching the plurality of nanowires along a second direction until the substrate is exposed; and selectively epitaxially growing a raised source-drain region on the substrate.

The material of the protective layer includes any one or combination of silicon oxide, silicon nitride, amorphous silicon, amorphous germanium, amorphous carbon, SiOC and low-k material.

Wherein the protective layer is isotropically etched away.

According to the manufacturing method of the stacked nanowire MOS transistor, the groove is etched back and laterally and filled for multiple times, the nanowire channel with good quality is formed, meanwhile, the surface defects of the nanowire are reduced by the protective layer, and the effective width of the conductive channel is fully increased at low cost, so that the driving current and the reliability are improved.

Drawings

The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:

FIGS. 1 (1A and 1B) to 13 (13A and 13B) are schematic cross-sectional views of steps of a method for fabricating a stacked nanowire MOS transistor according to the present invention, wherein FIGS. 1A to 13A are cross-sectional views taken along a direction perpendicular to a channel direction, and FIGS. 1B to 13B are cross-sectional views taken along a direction parallel to the channel direction; and

fig. 14 is a schematic perspective view of a FinFET device structure in accordance with the present invention.

Detailed Description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with exemplary embodiments, disclosing a stacked nanowire MOS transistor and a method of manufacturing the same that substantially increases the effective width of the conduction channel to increase the drive current. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures or fabrication processes. Such modifications do not imply a spatial, sequential, or hierarchical relationship to the structure or fabrication process of the modified device unless specifically stated.

Fig. 14 is a schematic perspective view of a stacked nanowire MOS transistor fabricated according to the present invention, where the stacked nanowire MOS transistor includes a plurality of nanowire stacks extending along a first direction on a substrate, a plurality of metal gates extending along a second direction and crossing each nanowire stack, a plurality of source/drain regions at two sides of the nanowire stacks extending along the first direction, and a plurality of channel regions formed by the nanowire stacks located between the plurality of source/drain regions, where the metal gates surround the channel regions. The various cross-sectional views of the fabrication method will be described first with reference to fig. 1A-13B, and finally the device structure of fig. 14 will be described in further detail back.

Specifically, fig. 1A to 13A below are sectional views taken perpendicular to the channel direction (in the second direction), and fig. 1B to 13B are sectional views taken parallel to the channel direction (in the first direction).

Referring to fig. 1A and 1B, a plurality of fin structures extending along a first direction are formed, wherein the first direction is a future device channel region extension direction. A substrate 1 is provided, the substrate 1 being chosen appropriately according to the device application requirements and may comprise single crystal silicon (Si), single crystal germanium (Ge), Strained Si, silicon germanium (SiGe), or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon based semiconductors such as graphene, SiC, carbon nanotubes, and the like. The substrate 1 is preferably bulk Si for compatibility with CMOS processes. Photoetching/etching the substrate 1, and forming a plurality of grooves 1G distributed in parallel along the first direction in the substrate 1 and fins 1F formed by the residual substrate 1 material between the grooves 1G. The aspect ratio of the trench 1G is preferably greater than 5: 1. Preferably, a hard mask layer HM, which may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and preferably silicon nitride, is deposited on top of the plurality of fin structures.

Referring to fig. 2A and 2B, an insulating isolation dielectric layer, such as silicon oxide, silicon oxynitride, silicon oxycarbide, low-k, etc., is deposited in the trenches 1G between the fins 1F by PECVD, HDPCVD, RTO (rapid thermal oxidation), etc., thereby forming Shallow Trench Isolations (STI) 2.

Referring to fig. 3A and 3B, STI2 is etched back, exposing the top of fin 1F. For the STI2 made of silicon oxide, it may be removed by a wet etching method using HF-based etchant, or by a dry etching method using fluorine-based plasma, and the STI2 is etched downward to expose the top 1C of the fin 1F (the subsequently exposed top is numbered as 1C1, 1C2 … … in order from small to large, that is, from top to bottom, from the HM layer on the top), where the top 1C will be used as a channel region of a later device, specifically, the topmost layer of the nanowire stack, and the remaining middle will be used to repeatedly form a plurality of nanowire channel regions in order in the subsequent process, and the bottommost portion will be etched to be used as an isolation region of the device. Preferably, the height of the exposed top 1C of the fin 1F is greater than the overall height of the fin 1F, which is 1/5-1/3, so as to form at least 3-5 nanowires.

Referring to fig. 4A and 4B, a first trench 1T1 is etched into the top 1C of fin 1F in a first direction, exposing the top (the portion that will form the top layer channel region in the future) 1C of fin 1F above STI2 in fig. 3A. The shape of the side wall of the first groove 1T1 may be rectangular, trapezoidal, inverted trapezoidal, Σ (multiple broken lines connected), C (more than 1/2 curved surface, which may be circular surface, elliptical surface, hyperboloid), D (1/2 curved surface, which may be circular surface, elliptical surface, hyperboloid). The etching method may be fluorine-based or chlorine-based plasma dry etching, or TMAH wet etching, depending on the material. Preferably, the first groove 1T1 is pierced in a first direction so that the topmost portion 1C1 of the fin 1F is isolated from other portions, forming the topmost silicon nanowire.

Referring to fig. 5A and 5B, a first protective layer 1P1 is deposited over the entire device, and is preferably made of silicon oxide, silicon nitride, amorphous silicon, amorphous germanium, amorphous carbon, SiOC, low-k materials, and the like, and combinations thereof, preferably to be distinguished from the STI 2/hard mask layer HM material, so as to avoid being accidentally removed during the subsequent etching process.

Referring to fig. 6A and 6B, the first protective layer 1P1 is anisotropically etched to expose the top nanowire 1C1 and the STI 2. The anisotropic etching method is, for example, a fluorocarbon based gas plasma etching, and the etching gas composition is adjusted so that STI2, for example, silicon oxide is not substantially etched, and only the first protective layer 1P1 of silicon nitride is vertically etched. As shown in fig. 6A and 6B, the first protective layer 1P1 is filled and remained in the first groove 1T1, thereby protecting the top portion 1C1 of the fin 1F for subsequent use as a nanowire.

Referring to fig. 7A and 7B, similar to fig. 3A and 3B, STI2 is etched back, exposing a middle portion of fin 1F. For the STI2 made of silicon oxide, it can be removed by a wet etching method using HF-based etchant, or by a dry anisotropic etching method using fluorine-based plasma, and the STI2 is etched downward to expose the middle portion 1C2 of the fin 1F, where the middle portion 1C2 will be used as a channel region of a later device, specifically, a middle layer of the nanowire stack, and the bottom will be etched to be used as an isolation region of the device. Preferably, the height of the exposed central part 1C2 of the fin 1F is larger than the whole height 1/5-1/3 of the fin 1F, so as to form at least 3-5 nanowires.

Subsequently, the above steps are repeated, for example, fig. 4A to 6B, and the second groove 1T2, the second protective layer 1P2, the second protective layer 1P2, the middle portion 1C3 of the fin 1F exposed by etching the STI2, the third groove 1T3, the third protective layer 1P3, and the anisotropic etching 1P3 … … are sequentially formed by etching, and finally the structure shown in fig. 8A and 8B is formed. The nanowire array comprises a plurality of fin structures on a substrate 1, each fin structure comprises a nanowire stack formed by stacking nanowires 1C1, 1C2, 1C3 and the like, each nanowire in the fin structures is isolated and protected by a protective layer 1P1, 1P2, 1P3 and the like, and the top of each fin structure is a hard mask layer HM.

Referring to fig. 9A and 9B, the hard mask layer HM is removed and a dummy gate stack is deposited. Preferably, the hard mask layer HM is removed by wet etching, for example, by removing silicon nitride by hot phosphoric acid, or by wet removing a hard mask layer of an oxide material by a hydrofluoric acid solution, such as a diluted hydrofluoric acid solution. A pad oxide layer 3 made of silicon oxide is deposited by methods such as LPCVD, PECVD, HDPCVD, RTO, chemical oxidation, etc. to protect the nanowire stack 1C from being over-etched in the subsequent etching process. The dummy gate layer 4 is formed on the pad oxide layer 3 by PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, and other deposition methods, and may be made of polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, poly-germanium, amorphous germanium, and the like, and combinations thereof. The thicknesses of the above layers are not necessarily in the proportions shown, but are rather set appropriately according to the specific device dimensions and electrical performance requirements. The dummy gate stack 3/4 completely surrounds each of the nanowires 1C 1-1C 3 and the passivation layers 1P 1-1P 3 between the nanowires. In a preferred embodiment of the present invention, the pad layer 3 and the protection layers 1P 1-1P 3 are made of silicon oxide, so that they can be removed by a wet process at a later step, thereby reducing the number of steps and saving the time and cost of the process.

Referring to fig. 10A and 10B, source and drain regions are formed at both sides of the nanowire stack 1C in the second direction. Forming a mask (not shown) on the middle part of the nanowire stack 1C serving as a future channel region, etching the nanowire stack 1C along a second direction until the substrate 1 is exposed, and forming raised source and

drain regions

1S and 1D through selective epitaxy such as UHVCVD, MOCVD, ALD, MBE, atmospheric pressure epitaxy and the like, wherein the material of the raised source and drain regions may be Si as same as that of the substrate 1; or for PMOS, the source and drain regions can be SiGe, SiSn, GeSn, Si, etc. and their combination, thereby applying compressive stress to the channel region 1C and improving hole mobility; for NMOS, the source and drain regions may be Si: C, Si: H, SiGe: C, Si, etc., and combinations thereof, thereby applying tensile stress to the channel region 1C and improving electron mobility. Preferably, doping is implanted in situ while epitaxy or after epitaxy and activated by annealing so that the source and drain regions 1S/D have a different doping type and concentration from the substrate 1 to control the electrical characteristics of the device. The top of source drain regions 1S/D is lower than the top of nanowire stack 1C to expose at least the top nanowire 1C 1. Preferably, a sidewall 5 may be formed on the side of the nanowire 1C1 along the second direction before the source/drain regions are epitaxial to protect the dummy gate stack, and then a lightly doped source/drain extension region and a heavily doped source/drain region (neither shown separately) may be formed by using the sidewall 5 after the source/drain regions are epitaxial.

Referring to fig. 11A and 11B, an interlayer dielectric (ILD)6 of low-k material is formed on the device and the ILD 6 is planarized using a process such as CMP until the dummy gate stack is exposed. Low-k materials include, but are not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials (e.g., amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glass, BSG, PSG, BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymers). The ILD 6 formation process includes screen printing, spray coating, spin coating, CVD, and the like.

Referring to fig. 12A and 12B, the dummy gate stack 3/4 is etched away, leaving a gate trench 1TG in ILD 6, exposing the underlying nanowire stack 1C (e.g., the top nanowire channel 1C 1). Preferably, a wet etching process is used, for example, TMAH wet etching is used for the dummy gate layer 4 of polysilicon, amorphous silicon, and microcrystalline silicon, and HF wet etching is used for the pad layer 3 of silicon oxide. Further, the protective layer 1P1, etc. between the nanowire stacks 1C is isotropically etched away, re-exposing the grooves 1T1, 1T2, etc. between the nanowires 1C, leaving the suspended nanowire stacks 1C1, 1C2 … 1 CN. The protective layer 1P is preferably removed by wet etching, for example, by wet etching silicon oxide or SiOC material with HF, wet etching silicon nitride with hot phosphoric acid, combined etching with strong oxidizer and strong acid to remove inorganic low-k material, and removing organic low-k material with acetone or ethanol. When the protective layer 1P is amorphous carbon, oxygen plasma dry etching may also be used to convert C in the protective layer into carbon dioxide gas and draw out of the reaction chamber. In the invention, the protective layer always covers the nanowire before the pseudo gate is removed, so that the erosion of a wet etching agent or a dry etching gas to the nanowire when the pseudo gate stack is removed in a gate-last process can be avoided, the surface defect of a nanowire channel is reduced, and the reliability of a device is improved.

Finally, referring to fig. 13A and 13B, the subsequent device fabrication is completed. Preferably, surface treatment, rounding and other processes are performed to convert the cross-sectional morphology of the nanowire 1C1, 1C2, 1C3 and the like to a circular shape, so as to improve the symmetry of the gate and the channel region, thereby improving the uniformity of the device performance. The surface treatment, rounding and other processes are, for example, a method of surface oxidation followed by wet micro-etching, and the surface oxidation process includes furnace temperature oxidation or oxidation with a strong oxidant solution. The surface treatment, rounding and other processes can also select hydrogen high-temperature baking and the like. The processes of surface treatment, rounding and the like can also select isotropic etching silicon and the like. A gate insulating layer 7 of a high-k material and a gate conductive layer 8 of a metal material are sequentially deposited in the gate trench 1TG,a gate stack structure is formed. High-k materials include, but are not limited to, materials including materials selected from HfO₂、HfSiO_x、HfSiON、HfAlO_x、HfTaO_x、HfLaO_x、HfAlSiO_x、HfLaSiO_xThe hafnium-based material (wherein each material has a reasonable oxygen atom content x, such as 1-6 and not limited to an integer, according to the distribution ratio and chemical valence of the multi-metal component), or comprises ZrO₂、La₂O₃、LaAlO₃、TiO₂、Y₂O₃Or a rare earth based high-K dielectric material of (2), or including Al₂O₃And a composite layer of the above materials. The gate conductive layer may be polysilicon, poly-silicon germanium, or a metal, wherein the metal may include simple metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc., or alloys of these metals, and nitrides of these metals, and the gate conductive layer may be doped with elements such as C, F, N, O, B, P, As to adjust the work function. A nitride barrier layer (not shown) is preferably formed between the gate conductive layer and the gate insulating layer by PVD, CVD, ALD, etc., and the barrier layer is preferably M_xN_y、M_xSi_yN_z、M_xAl_yN_z、M_aAl_xSi_yN_zWherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. More preferably, the gate conductive layer and the blocking layer not only adopt a composite layer structure stacked up and down, but also adopt a mixed implantation doping layer structure, that is, the materials constituting the gate conductive layer and the blocking layer are simultaneously deposited on the gate insulating layer, so that the gate conductive layer comprises the materials of the blocking layer. CMP planarizes the gate stack structure until ILD 6 is exposed. Thereafter, source and drain contact holes (not shown) are etched in the ILD 10 to the source and drain regions 1S/D, and a barrier layer of metal nitride and a conductive layer of metal material are deposited in the source and drain contact holes to form source and drain contact plugs (not shown) according to standard processes.

The resulting device structure is shown in fig. 14 in a perspective view, comprising: the nanowire array comprises a plurality of nanowire stacks extending along a first direction on a substrate, a plurality of metal gates extending along a second direction and spanning each nanowire stack, a plurality of source-drain regions at two sides of each nanowire stack extending along the first direction, and a plurality of channel regions formed in the middle of each nanowire stack between the plurality of source-drain regions, wherein the metal gates surround the channel regions. The materials and geometries of these structures are described in detail in the description of the methods and are therefore not described in detail herein.

While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.

Claims

1. A stacked nanowire MOS transistor manufacturing method comprises the following steps:

forming a plurality of fins extending in a first direction on a substrate;

etching and forming a plurality of nanowires in each fin;

depositing a protective layer between adjacent nanowires;

forming a dummy gate stack on the nanowires, the dummy gate stack extending in a second direction and surrounding the plurality of nanowires and the protective layer deposited between the nanowires, the dummy gate stack including a pad oxide layer and a dummy gate layer;

forming source and drain regions on two sides of the pseudo gate stack, wherein a plurality of nanowires between the source and drain regions form a channel region;

etching to remove the pseudo gate layer;

removing the protective layer and the pad oxide layer by one-time etching to expose the suspended nanowires;

a gate stack is formed on the plurality of nanowires extending in the second direction and surrounding the plurality of nanowires.

2. The method of claim 1, wherein etching a plurality of nanowires in each fin and depositing a protective layer between adjacent nanowires further comprises:

depositing shallow trench isolation between the fins;

etching back the shallow trench isolation to expose the first part of the top of the fin;

laterally etching a first part of the top of the fin to form a first through groove, wherein the rest part of the first part of the top of the fin forms a first nanowire;

depositing a first protective layer to fill at least the first recess.

3. The method of claim 2, wherein forming the first nanowire is further followed by:

anisotropically back-etching the first protective layer to isolate the shallow trench and expose the second part in the middle of the fin;

laterally etching the second part in the middle of the fin to form a through second groove, wherein the rest part of the second part in the middle of the fin forms a second nanowire;

depositing a second protective layer to at least fill the second groove;

and repeating the steps to form a plurality of nanowires, wherein the first protective layer and the second protective layer jointly form a protective layer.

4. The method of claim 2 or 3, wherein the shape of the first groove and/or the second groove comprises a rectangle, a trapezoid, an inverted trapezoid, a sigma, a D, a C, and combinations thereof.

5. A method as claimed in claim 2 or 3, wherein the step of laterally etching the fins comprises an isotropic plasma dry etch with a lateral etch depth, or a combination of an isotropic etch with an anisotropic etch, or a wet etch using selective etching in different crystallographic directions.

6. The method of claim 1, wherein removing the protective layer further comprises performing a surface treatment, rounding process on the plurality of nanowires.

7. The method of claim 1, wherein forming source and drain regions further comprises: and depositing an interlayer dielectric layer, and flattening the interlayer dielectric layer until the dummy gate stack is exposed.

8. The method of claim 1, wherein the step of forming source and drain regions further comprises: etching the plurality of nanowires along a second direction until the substrate is exposed; and selectively epitaxially growing a raised source-drain region on the substrate.

9. The method of claim 1, wherein the material of the passivation layer comprises any one or a combination of silicon oxide, silicon nitride, amorphous silicon, amorphous germanium, amorphous carbon, and SiOC.

10. The method of claim 1, wherein the material of the protective layer comprises a low-k material.

11. The method of claim 1, wherein the protective layer is isotropically etched away.