CN106531632A - Manufacturing method of stacked nanowire MOS transistor - Google Patents
Manufacturing method of stacked nanowire MOS transistor Download PDFInfo
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- CN106531632A CN106531632A CN201510575026.3A CN201510575026A CN106531632A CN 106531632 A CN106531632 A CN 106531632A CN 201510575026 A CN201510575026 A CN 201510575026A CN 106531632 A CN106531632 A CN 106531632A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method of a stacked nanowire MOS transistor. The method comprises the steps of forming a plurality of fins which extend along a first direction on a substrate; forming a plurality of nanowires in each fin and arranging protective layers between adjacent nanowires; forming pseudo gate stacks which extend along a second direction and surround the plurality of nanowires on the nanowires; forming a source region and a drain region at two sides of each pseudo gate stack and forming one channel region by the plurality of nanowires between each source region and the corresponding drain region; removing the pseudo gate stacks through etching; removing the protective layers through etching and exposing the suspended nanowires; and forming gate stacks which extend along the second direction and surround the plurality of nanowires on the plurality of nanowires. According to the manufacturing method of the stacked nanowire MOS transistor, nanowire channels with good quality are formed through multiple back-etching, and lateral etching and filling of channels; and meanwhile, surface defects of the nanowires are reduced by using the protective layers and the effective widths of conducting channels are fully increased at relatively low cost, thereby improving the drive current and the reliability.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, more particularly to a kind of rear grid structure
Middle stacking nanowire MOS transistor preparation method.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device (FinFET or Tri-gate) is
Main device architecture, this structure enhance grid control ability, inhibit electric leakage and short ditch
Channel effect.
For example, the MOSFET of double gate SOI structure and traditional single grid body Si or SOI
MOSFET is compared, and short-channel effect (SCE) and leakage can be suppressed to cause induced barrier to reduce
(DIBL) effect, with lower junction capacity, can realize that raceway groove is lightly doped, can be by setting
The work function for putting metal gates carrys out adjusting threshold voltage, can obtain about 2 times of driving current, reduces
Requirement for effective gate oxide thickness (EOT).And tri-gate devices are compared with double-gated devices, grid
Pole encloses channel region top surface and two sides, and grid control ability is higher.Further, entirely
It is more advantageous around nano wire multi-gate device.
Although ring gate nano line device has more preferable grid control function, can more effectively control short channel effect
Should, have more advantage during the reduction of sub- 14 nanometer technology, but key issue be due to
Small conducting channel, can not provide more driving currents in the equivalent silicon area of plane.
For example, for the device of 1 μm of equivalent live width, the size of ring gate nano line device will expire
Foot：D*n+ (n-1) * s=1 μm, and π * d*n>1μm.Wherein, d is single nano wire (NW)
Diameter, n for nano wire number, s be nano wire between spacing.Therefore, for diameter d point
Not Wei 3,5,7, for the situation of 10nm, nano wire distance s must be respectively smaller than 6.4,10.6,
15、21.4nm.That is, if the grid width for being equal to body silicon 1um will be obtained, nano-wire devices
It is arranged in parallel very tight.According to existing FinFET exposures, (Fin spacing exists with lithographic technique
60 rans), it is difficult to realize to make this extremely closely spaced nanometer DNA mitochondrial DNA arrangement architecture.
In a word, realize that stacked rings gate nano line structure is to improve transistor driving electricity in vertical direction
The effective ways of stream, but realizing that technique (in preparation method) is very difficult, it is simultaneous with traditional handicraft
Hold and reduce process costs and face significant challenge.For example, a kind of existing realization stacks nano wire
It is using Si/SiGe heterogeneous multi-layers extension and carries out selective etching, namely on oxygen buried layer (BOX)
Replace the stacking of the multiple Si of hetero-epitaxy and SiGe successively, then for example, by methods such as wet etchings
Selective removal SiGe, so as to leave the stacking of Si nano wires.This method is seriously limited by extension
The impact of thin layer quality, significantly increases process costs.
It is, thus, sought for a kind of abundant increase conducting channel effective width improves the new of driving current
Type nano-wire devices structure and its manufacture method.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose that a kind of type is received
Nanowire device structure and its manufacture method, fully increase conducting channel effective width so as to improve driving
Electric current.
For this purpose, the invention provides a kind of stacking nanowire MOS transistor preparation method, including：
The multiple fins for extending in a first direction are formed on substrate；Multiple receiving is formed in each fin
Rice noodles, have protective layer between adjacent nanowires；Formed on nano wire and extended in a second direction
And surround the dummy grid stacking of multiple nano wires；Source-drain area, source are formed in dummy grid stacking both sides
Multiple nano wire constituting channel areas between drain region；Etching removes dummy grid stacking；Etching is removed
Protective layer, exposes hanging multiple nano wires；Formed on multiple nano wires and prolonged in a second direction
Stretch and surround the gate stack of multiple nano wires.
Wherein, the step of forming multiple nano wires in each fin further includes：In fin
Between deposit shallow trench isolation；Return and carve shallow trench isolation, expose the Part I at the top of fin；
Part I at the top of sideetching fin, forms the first groove of break-through, the at the top of fin
A part of remaining part constitutes the first nano wire；The first protective layer is deposited, at least to fill
One groove.
Wherein, further include after forming the first nano wire：Anisotropy is returned and carves the first protection
Layer is isolated with shallow trench, exposes the Part II in the middle part of fin；In the middle part of sideetching fin
Part II, forms the second groove of break-through, the remaining part structure of the Part II in the middle part of fin
Into the second nano wire；The second protective layer is deposited, at least to fill the second groove；Walk more than repeating
Suddenly, multiple nano wires are formed, the first protective layer and the second protective layer collectively form protective layer.
Wherein, the shape of the first groove and/or the second groove include rectangle, trapezoidal, inverted trapezoidal,
Σ shapes, D-shaped, C-shaped and combinations thereof.
Wherein, include with the isotropic of lateral etching depth the step of sideetching fin
Plasma dry etch, or the combined method of isotropic etching and anisotropic etching,
Or using the wet etching method of selective etching on different crystal orientations.
Wherein, further include after removing protective layer, multiple nano wires are carried out being surface-treated,
Rounding process.
Wherein, further include after forming source-drain area：Interlayer dielectric layer, planarization layer
Between dielectric layer until exposure dummy grid stacking.
Wherein, the step of forming source-drain area further includes：Multiple nanometers are etched in a second direction
Line, until exposure substrate；The selective epitaxial growth lifting source-drain area on substrate.
Wherein, the material of protective layer includes silica, silicon nitride, non-crystalline silicon, amorphous germanium, non-
Any one or combination of brilliant carbon, SiOC, low-k materials.
Wherein, isotropically etching removes protective layer.
According to the stacking nanowire MOS transistor preparation method of the present invention, by repeatedly return carve,
Laterally etched groove is simultaneously filled, and defines the second best in quality nanowire channel, while using protection
Layer reduce nanowire surface defect, with relatively low cost fully increase conducting channel effective width so as to
Improve driving current and reliability.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 (Figure 1A and Figure 1B) to Figure 13 (Figure 13 A and Figure 13 B) is according to this
The generalized section of the bright each step of stacking nanowire MOS transistor manufacture method, wherein certain figure
A is that, along the sectional view perpendicular to channel direction, certain figure B is along the section view parallel to channel direction
Figure；And
Figure 14 is the schematic perspective view of the FinFET structure according to the present invention.
Specific embodiment
The technology of the present invention side is described in detail referring to the drawings and with reference to schematic embodiment
The feature and its technique effect of case, discloses fully increase conducting channel effective width so as to improve drive
The stacking nanowire MOS transistor of streaming current and its manufacture method.It is pointed out that similar
Reference represent similar structure, term " first " use herein, " second ",
" on ", D score etc. can be used to modify various device architectures or manufacturing process.These modifications
Space, order or the layer of modified device architecture or manufacturing process are not implied that unless stated otherwise
Level relation.
Figure 14 show the solid of the stacking nanowire MOS transistor according to present invention manufacture and shows
It is intended to, wherein stacking what is extended in a first direction on nanowire MOS transistor, including substrate
Multiple nano wire stackings, extend and span the multiple of each nano wire stacking in a second direction
Metal gates, the nano wire for extending in a first direction stack multiple source-drain areas of both sides, positioned at many
Multiple channel regions that nano wire stacking between individual source-drain area is constituted, wherein metal gates are around ditch
Road area.Below by with initial reference to Fig. 1 to Figure 13 describing each sectional view of manufacture method, most
The device architecture of Figure 14 will be later described in further detail afterwards.
Especially, certain figure A is perpendicular to channel direction (in a second direction) along Figure 14 below
Sectional view, certain figure B is the cuing open parallel to channel direction (in the first direction) along Figure 14
View.
With reference to Figure 1A and Figure 1B, the multiple fin structures for extending in a first direction are formed, its
Middle first direction is future device channel region bearing of trend.Substrate 1 is provided, substrate 1 is according to device
Part purposes need and reasonable selection, it may include monocrystalline silicon (Si), monocrystal germanium (Ge),
Strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, example
Such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb),
And carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc..For with CMOS technology
Compatible consideration, substrate 1 are preferably body Si.Photoetching/etched substrate 1, the shape in substrate 1
Into remaining substrate 1 between the groove 1G and groove 1G of multiple distributions parallel in the first direction
The fin 1F constituted by material.The depth-to-width ratio of groove 1G is preferably more than 5:1.Preferably,
In the deposited atop hard mask layer HM of multiple fin structures, its material can be silica, nitrogen
SiClx, silicon oxynitride and combinations thereof, and preferably silicon nitride.
With reference to Fig. 2A and Fig. 2 B, in the groove 1G between fin 1F by PECVD,
The process deposits such as HDPCVD, RTO (rapid thermal oxidation) filling material be, for example, silica,
Silicon oxynitride, silicon oxide carbide, low-k's etc. is dielectrically separated from dielectric layer, so as to constitute shallow ridges
Groove isolates (STI) 2.
Reference picture 3A and Fig. 3 B, return and carve STI2, expose the top of fin 1F.For oxygen
The STI2 of SiClx material, can be removed using HF base corrosive liquids wet method, it would however also be possible to employ fluorine-based
Plasma dry etch, downwards etching STI2 with expose fin 1F top 1C (after
The continuous top exposed according to apart from top HM layers from it is little to big, namely from top to bottom sequentially according to
Secondary numbering is 1C1,1C2 ...), at the top of this, 1C will act as the channel region of device after a while,
The top that specially nano wire is stacked, and remaining middle part will be repeated in subsequent handling
Multiple nanowire channel areas are formed, bottommost will be etched and as the isolated area of device.It is preferred that
Ground, the exposed top 1C of fin 1F are highly more than the 1/5～1/3 of fin 1F whole heights,
At least to form 3～5 nano wires.
Reference picture 4A and Fig. 4 B, in 1C at the top of fin 1F, etching is formed in the first direction
First groove 1T1, exposes top (following shapes of the fin 1F above STI2 in Fig. 3
Into the part of top layer channel region) 1C.The sidewall shape of the first groove 1T1 can be rectangle,
Trapezoidal, inverted trapezoidal, Σ shapes (multistage broken line is connected), C-shaped are (more than 1/2 curved surface, curved surface
Can be disc, ellipsoid, hyperboloid), D-shaped (1/2 curved surface, curved surface can be disc,
Ellipsoid, hyperboloid).It is different according to material, lithographic method can be fluorine-based or chloro etc. from
Daughter dry etching, or TMAH wet etchings.Preferably, the first groove 1T1 is
Break-through on one direction, so that top 1C1 of fin 1F is kept apart with other parts,
Define the silicon nanowires of top.
Reference picture 5A and Fig. 5 B, deposit the first protective layer 1P1, its material on whole device
Matter includes silica, silicon nitride, non-crystalline silicon, amorphous germanium, amorphous carbon, SiOC, low-k materials
Deng and combinations thereof, it is therefore preferable to distinguish with 2/ hard mask layer HM materials of STI, so as to keep away
Unexpectedly removed during exempting from subsequent etching.
Reference picture 6A and Fig. 6 B, anisotropic etching the first protective layer 1P1 expose top
Nano wire 1C1 and STI 2.Anisotropic etching method be, for example, carbon fluorine hydrogen based gas etc. from
Son etching, and etching gas composition is adjusted so that the STI 2 of such as silica is not carved substantially
Erosion, and only the first protective layer 1P1 of vertical etch silicon nitride.As shown in Figure 6 A and 6 B,
First protective layer 1P1 fillings are retained in the first groove 1T1, thus protect fin 1F to push up
Portion part 1C1 is in order to being subsequently used as nano wire.
Reference picture 7A and Fig. 7 B, it is similar with Fig. 3 A and Fig. 3 B, return and carve STI2, exposure
The middle part of fin 1F.For the STI2 of silica material, can be wet using HF base corrosive liquids
Method is removed, it would however also be possible to employ fluorine-based plasma anisotropic dry etch, etches downwards STI2
To expose the middle part 1C2 of fin 1F, in the middle part of this, 1C2 will act as the channel region of device after a while,
Specially nano wire stacking middle part layer, bottommost will be etched and as the isolated area of device.
Preferably, the exposed middle part 1C2 of fin 1F highly more than fin 1F whole heights 1/5～
1/3, at least to form 3～5 nano wires.
Subsequently, repeat above step, such as Fig. 4 A～Fig. 6 B are sequentially etched that to form second recessed
Groove 1T2, the second protective layer 1P2 of deposition, anisotropic etching the second protective layer 1P2, time quarter
STI2 exposes the middle part 1C3 of fin 1F, etching and forms the 3rd groove 1T3, the 3rd guarantor of deposition
Sheath 1P3, anisotropic etching 1P3 ..., ultimately form shown in Fig. 8 A and Fig. 8 B
Structure.Including multiple fin structures on substrate 1, include in each fin structure by
The nano wire stacking that nano wire 1C1,1C2,1C3 etc. stacking is constituted, it is every in fin structure
Insulation blocking, fin structure are come by protective layer 1P1,1P2,1P3 etc. between individual nano wire
Top is hard mask layer HM.
Reference picture 9A and Fig. 9 B, remove hard mask layer HM, deposition dummy grid stacking.It is preferred that
Ground, removes hard mask layer HM using wet etching, removes silicon nitride for example with hot phosphoric acid,
Or hydrofluoric acid solution, the hydrofluoric acid solution for such as diluting carry out wet method and remove covering firmly for oxide material
Mold layer.It is heavy by methods such as LPCVD, PECVD, HDPCVD, RTO, chemical oxidations
Product forms the pad oxide 3 of silica material, for protecting nano wire to stack 1C not follow-up
By over etching in etching process.On pad oxide 3 by PECVD, HDPCVD,
The deposition process such as MOCVD, MBE, ALD, evaporation, sputtering form false grid layer 4, material
Matter can be polysilicon, non-crystalline silicon, microcrystal silicon, amorphous carbon, polycrystalline germanium, amorphous germanium etc. and
Its combination.Ratio of the thickness of each layer of the above not necessarily in diagram, but according to specific device
Size and electric property demand and reasonable set.False grid stacking 3/4 is entirely around enclosing
Protective layer 1P1～1P3 of each nano wire 1C1～between 1C3 and nano wire etc..
In a preferred embodiment of the invention, bed course 3 is with protective layer 1P1～1P3 by silica material
Matter is made, therefore disposably wet method can remove so as to reduce technique in removing step after a while
Step, saving process time and cost.
Reference picture 10A and Figure 10 B, form in nano wire stacking 1C both sides in a second direction
Source-drain area.Mask is formed (not on the middle part of the nano wire stacking 1C as future channel area
Illustrate), nano wire stacking 1C is etched in a second direction, until exposure substrate 1, passes through
The selective epitaxials such as UHVCVD, MOCVD, ALD, MBE, normal pressure extension form lifting
Source-drain area 1S and 1D, its material identical with substrate 1 can be Si；Or for PMOS
For, source-drain area can be SiGe, SiSn, GeSn, Si etc. and combinations thereof, so as to ditch
Road area 1C applies compression, improves hole mobility；And for NMOS, source-drain area
Can be Si:C、Si:H、SiGe:C, Si etc. and combinations thereof, so as to apply to channel region 1C
Tensile stress, improves electron mobility.Preferably, in extension doping in situ simultaneously or in extension
Injection afterwards is adulterated and activation of annealing so that source-drain area 1S/D is mixed with different from substrate 1
Miscellany type, concentration, with the electrology characteristic of control device.The top of source-drain area 1S/D will be less than
Nano wire stacks the top of 1C, at least to expose the nano wire 1C1 at top.Preferably,
Side wall 5 can be formed to protect with the side before extension source-drain area in nano wire 1C1 in a second direction
Shield dummy grid stacking, and subsequently lightly doped source is formed using side wall 5 after extension source-drain area
Leakage expansion area (is not shown respectively) with heavily doped source-drain area.
Reference picture 11A and Figure 11 B, form the interlayer dielectric layer of low k materials on device
(ILD) 6 and using the technique such as CMP planarization ILD 6 until exposure dummy grid stacking.It is low
K materials include but is not limited to organic low-k materials and (for example gather containing aryl or the organic of many yuan of rings
Compound), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silicon
Glass, BSG, PSG, BPSG), porous low k material (three oxygen alkane (SSQ) of such as two silicon
Quito hole low-k materials, porous silica, porous SiOCH, mix C silica, mix F
Porous amorphous carbon, porous diamond, porous organic polymer).The formation process of ILD 6
Including serigraphy, spraying, spin coating, CVD etc..
Reference picture 12A and Figure 12 B, etching remove false grid stacking 3/4, stay in ILD 6
Lower gate trench 1TG, exposes nano wire stacking 1C (such as nanometer ducts at top of lower section
Road 1C1).It is preferred that adopt wet corrosion technique, such as polysilicon, non-crystalline silicon, crystallite
The dummy gate layer 4 of silicon adopts TMAH wet etchings, adopts HF for the bed course 3 of silica
Wet etching.Further, isotropically etching removes the guarantor between nano wire stacking 1C
Sheath 1P1 etc., groove 1T1,1T2 between exposure nano wire 1C etc., stays again
Hanging nano wire stacking 1C1,1C2 ... 1CN.It is preferred that removing protective layer using wet etching
1P, for example with HF wet etching silica, SiOC materials, hot phosphoric acid wet etching nitrogen
SiClx, strong oxidizer are combined the inorganic low k materials of erosion removal, acetone, ethanol etc. and are gone with strong acid
Except organic low k materials.When protective layer 1P is amorphous carbon, it would however also be possible to employ oxygen plasma is done
The C of protective layer is converted into carbon dioxide and extraction chamber by method etching.In the present invention
In, nano wire is covered always by protective layer before removing dummy grid, therefore rear grid work can be avoided
Remove wet etchant or dry etching gas when dummy grid is stacked to invade nano wire in skill
Erosion, reduces nanowire channel surface defect, improves the reliability of device.
Finally, reference picture 13A and Figure 13 B, complete subsequent device manufacture.Preferably, carry out
The techniques such as surface treatment, sphering so that the profile morphology of nano wire 1C1,1C2,1C3 etc.
To circular transformation, to improve the symmetry of grid, channel region, so as to improve the equal of device performance
Even property.The techniques such as surface treatment, sphering are e.g. using rewetting method microcorrosion after surface oxidation
Method, surface oxidation technique include furnace temperature oxidation or strong oxidant solution oxidation etc..At surface
The techniques such as reason, sphering are also an option that hydrogen high-temperature baking etc..The techniques such as surface treatment, sphering
Isotropic etch silicon etc. is may be selected also.High-g value is sequentially depositing in gate trench 1TG
Gate insulator 7 and metal material grid conducting layer 8, constitute gate stack structure.
High-g value is included selected from HfO2、HfSiOx、HfSiON、HfAlOx、
HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnium sill (wherein, each material
It is different according to multi-element metal component proportion and chemical valence, oxygen atom content x can Reasonable adjustment,
Can for example be 1～6 and be not limited to integer), or including selected from ZrO2、La2O3、LaAlO3、
TiO2、Y2O3Rare earth base high K dielectric material, or including Al2O3, with its above-mentioned material
Composite bed.Grid conducting layer can be then polysilicon, poly-SiGe or metal, wherein metal
May include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr,
The alloy of the metal simple-substances such as W, Ir, Eu, Nd, Er, La or these metals and these
The nitride of metal, can also be doped with C, F, N, O, B, P, As in grid conducting layer
Deng element adjusting work function.Further preferably pass through between grid conducting layer and gate insulator
The conventional methods such as PVD, CVD, ALD form the barrier layer (not shown) of nitride, stop
Layer material is MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz, wherein M be Ta, Ti,
Hf, Zr, Mo, W or other elements.It is highly preferred that grid grid conducting layer and barrier layer
Not only with lamination layer structure stacked up and down, the injection doped layer knot for mixing can also be adopted
Structure, namely the material of grid conducting layer and barrier layer is constituted while being deposited on gate insulator,
Therefore grid conducting layer includes the material on above-mentioned barrier layer.Cmp planarization gate stack structure
Until exposure ILD 6.Hereafter, according to standard technology, source and drain contact hole is etched in ILD 10
The through source-drain area 1S/D of (not shown), the resistance of deposited metal nitride in source and drain contact hole
The conductive layer of barrier and metal material, forms source and drain contact plug (not shown).
The stereogram of the device architecture for eventually forming is as shown in figure 14, including：Along first on substrate
Multiple nano wire stackings that direction extends, extend and span each nano wire in a second direction
Multiple metal gates of stacking, the nano wire for extending in a first direction stack multiple source and drain of both sides
Area, multiple channel regions that the nano wire stacking middle part between multiple source-drain areas is constituted, wherein
Metal gates are around channel region.The material and geometry of above-mentioned these structures is described in method
Middle detailed description, therefore will not be described here.
According to the stacking nanowire MOS transistor preparation method of the present invention, by repeatedly return carve,
Laterally etched groove is simultaneously filled, and defines the second best in quality nanowire channel, while using protection
Layer reduce nanowire surface defect, with relatively low cost fully increase conducting channel effective width so as to
Improve driving current and reliability.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art
Member could be aware that and various suitable changes are made without departing from the scope of the invention and to device architecture
And equivalents.Additionally, by disclosed teaching can make many can be adapted to particular condition or
The modification of material is without deviating from the scope of the invention.Therefore, the purpose of the present invention does not lie in and is limited to
It is as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed
Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.
Claims (10)
1. it is a kind of to stack nanowire MOS transistor preparation method, including：
The multiple fins for extending in a first direction are formed on substrate；
Multiple nano wires are formed in each fin, there is between adjacent nanowires protective layer；
The dummy grid heap for extending and surrounding multiple nano wires in a second direction is formed on nano wire
It is folded；
Source-drain area is formed in dummy grid stacking both sides, the multiple nano wires between source-drain area constitute ditch
Road area；
Etching removes dummy grid stacking；
Etching removes protective layer, exposes hanging multiple nano wires；
The grid for extending and surrounding multiple nano wires in a second direction is formed on multiple nano wires
Stacking.
2. method as claimed in claim 1, wherein, the step of multiple nano wires is formed in each fin
Suddenly further include：
Shallow trench isolation is deposited between fin；
Return and carve shallow trench isolation, expose the Part I at the top of fin；
Part I at the top of sideetching fin, forms the first groove of break-through, fin top
The remaining part of Part I in portion constitutes the first nano wire；
The first protective layer is deposited, at least to fill the first groove.
3. method as claimed in claim 2, wherein, further include after forming the first nano wire：
Anisotropy is returned and carves the first protective layer and isolated with shallow trench, exposes the in the middle part of fin
Two parts；
Part II in the middle part of sideetching fin, forms the second groove of break-through, in fin
The remaining part of Part II in portion constitutes the second nano wire；
The second protective layer is deposited, at least to fill the second groove；
Repeat above step, form multiple nano wires, the first protective layer and the second protective layer are altogether
With composition protective layer.
4. such as the method for Claims 2 or 3, wherein, the shape of the first groove and/or the second groove
Including rectangle, trapezoidal, inverted trapezoidal, Σ shapes, D-shaped, C-shaped and combinations thereof.
5. include that there is laterally quarter such as the step of the method for Claims 2 or 3, sideetching fin
Erosion depth isotropic plasma dry etch, or isotropic etching with it is each
The combined method of anisotropy etching, or it is rotten using the wet method of selective etching on different crystal orientations
Etching method.
6. method as claimed in claim 1, wherein, further include after removing protective layer, to many
Individual nano wire carries out being surface-treated, rounding process.
7. method as claimed in claim 1, wherein, further include after forming source-drain area：Deposition
Interlayer dielectric layer, planarization interlayer dielectric layer is until exposure dummy grid stacking.
8. method as claimed in claim 1, wherein, further include the step of form source-drain area：Edge
Second direction etches multiple nano wires, until exposure substrate；The selective epitaxial on substrate
Growth lifting source-drain area.
9. method as claimed in claim 1, wherein, the material of protective layer include silica, silicon nitride,
Any one or combination of non-crystalline silicon, amorphous germanium, amorphous carbon, SiOC, low-k materials.
10. method as claimed in claim 1, wherein, isotropically etching removes protective layer.
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| CN108962750A (en) * | 2018-07-09 | 2018-12-07 | 中国科学院微电子研究所 | Nanowire wrap grate MOS device and preparation method thereof |
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| CN110896027A (en) * | 2019-12-05 | 2020-03-20 | 中国科学院微电子研究所 | Semiconductor device nanowire and preparation method thereof |
| TWI775995B (en) * | 2017-12-04 | 2022-09-01 | 日商東京威力科創股份有限公司 | Method for controlling transistor delay of nanowire or nanosheet transistor devices |
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