CN110896027A - Semiconductor device nanowire and preparation method thereof - Google Patents
Semiconductor device nanowire and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000002070 nanowire Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 76
- 239000010703 silicon Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 50
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 42
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 17
- 229910007264 Si2H6 Inorganic materials 0.000 claims description 12
- 239000002243 precursor Substances 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 20
- 230000010354 integration Effects 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 4
- -1 SiGeSnC Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000013341 scale-up Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a preparation method of a semiconductor device nanowire, which comprises the following steps: providing a semiconductor substrate; forming shallow trench isolation regions in a semiconductor substrate, wherein the semiconductor substrate between the shallow trench isolation regions is of a bulk silicon fin structure; selectively removing the bulk silicon fin structure, and recessing the bulk silicon fin structure to form a groove; alternately stacking and growing a plurality of epitaxial layers with etching selectivity at the groove along the vertical direction of the surface of the semiconductor substrate and carrying out surface planarization; recessing the shallow trench isolation regions so that a plurality of epitaxial layers alternately stacked and grown protrude from the shallow trench isolation regions on both sides; one or more epitaxial layers are selectively etched, and the remaining epitaxial layers form the nanowire structure. A semiconductor device nanowire is also provided. According to the invention, heterogeneous films of different materials are alternately stacked and grown on the semiconductor substrate, so that defects in the films are reduced, a high-quality nanowire structure is prepared, introduction and integration of different types of high-mobility materials are facilitated, and the performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a semiconductor device nanowire and a preparation method thereof.
Background
With the continuous development of semiconductor devices, fin field effect transistors (FinFET transistors) cannot be continuously reduced as process nodes are scaled down, the process requirements cannot be met, the contact area between a channel and a Gate needs to be increased for scale-up, and a Gate-All-around (gaa) structure is generally adopted for achieving the purpose. The structure of the GAA gate-all-around nanowire allows the size of the transistor to be adjusted to ensure that the gate is not only on the top and both sides, but also under the channel. The traditional GAA ring gate nanowire is subjected to photoetching after a nanowire material grows on the whole wafer to form the nanowire, so that the problems of poor etching precision and complex process exist, and the integration of high-mobility materials with large lattice difference is difficult to overcome in material growth.
Disclosure of Invention
In order to overcome the technical problem of difficult integration of high-mobility materials with large lattice difference in the prior art, a preparation method of a semiconductor device nanowire is further provided, so that different design requirements are met.
The invention provides a preparation method of a semiconductor device nanowire, which comprises the following steps:
providing a semiconductor substrate;
forming shallow trench isolation regions in a semiconductor substrate, wherein the semiconductor substrate between the shallow trench isolation regions is of a bulk silicon fin structure;
selectively removing the bulk silicon fin structure, and recessing the bulk silicon fin structure to form a groove;
alternately stacking and growing a plurality of epitaxial layers with etching selectivity at the groove along the vertical direction of the surface of the semiconductor substrate, and carrying out surface planarization;
recessing the shallow trench isolation regions so that multiple epitaxial layers alternately stacked and grown protrude from the shallow trench isolation regions on both sides;
one or more epitaxial layers are selectively etched, and the remaining epitaxial layers form the nanowire structure.
Further, the method for forming the silicon fin structure is as follows:
forming a mask layer on the semiconductor substrate, wherein the width of the mask layer is the same as that of the preset nanowire;
etching the area which is not shielded by the mask layer on the semiconductor substrate to form a groove;
the semiconductor substrate between the trenches constitutes a bulk silicon fin structure.
Further, the method for forming the shallow trench isolation region comprises the following steps:
removing the mask layer on the bulk silicon fin structure;
filling a dielectric material in the trench to enable the dielectric material to cover the trench and the surface of the bulk silicon fin structure;
etching back the dielectric material to expose a top surface of the bulk silicon fin structure;
the dielectric material regions filled on both sides of the bulk silicon fin structure form shallow trench isolation regions.
Further, when the bulk silicon fin structure is selectively removed, the adopted etching method is any one or combination of a plurality of dry etching, HCl CVD thermal etching and alkaline etching.
Further, when selectively removing the bulk silicon fin structure, the bulk silicon fin structure may be partially removed or completely removed or removed to a depth into the semiconductor substrate.
Further, after the bulk silicon fin structure is selectively removed, the cross section of one end of the removed shape close to the semiconductor substrate can be a horizontal plane, an inverted trapezoidal plane or a triangular plane.
Further, after the bulk silicon fin structure is recessed to form a groove, annealing treatment is carried out on the surface of the semiconductor substrate in the groove.
Further, the annealing temperature of the annealing treatment was 720%oC to 1050oC, annealing for 3s to 600s in the annealing environment of H2In the atmosphere.
Further, SiGe epitaxial layers and Si epitaxial layers are alternately stacked and grown at the grooves along the vertical direction of the surface of the semiconductor substrate, wherein the process conditions for growing the SiGe epitaxial layers are as follows: introducing HCl in situ at a low temperature of 500 deg.CoC to 600oC. SiH was added under a pressure of 10Torr2CL2、Si2H6、GeH6And GeH4Taking the precursor as a precursor, and carrying out reduced pressure epitaxial growth on a SiGe layer; the process conditions for growing the Si epitaxial layer are as follows: at low temperature 500oC to 600oC. Under the condition of 10Torr of pressure, HCl and SiH are used2CL2Or HCl and SiH4Or HCl and Si2H6Or HCl, SiH2CL2And SiH4Or HCl, SiH2CL2And Si2H6Or HCl, SiH2CL2、Si2H6And SiH4And (3) carrying out reduced pressure epitaxial growth on the Si epitaxial layer as a precursor.
The invention also provides a semiconductor device nanowire prepared by the preparation method of the semiconductor device nanowire.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, heterogeneous films of different materials are alternately stacked and epitaxially grown on the semiconductor substrate, the width of the groove in the epitaxial process defines the width of a future nanowire, and the epitaxial thickness defines the height of the nanowire, so that the number of layers and the process steps of photoetching can be reduced, the defects of the films can be further reduced, and the stacked nanowire is formed after selective etching. The preparation method simplifies the traditional nanowire forming process, reduces the defects in the thin film, can prepare a high-quality nanowire structure, is beneficial to the introduction and integration of different types of high-mobility materials, and improves the performance of devices.
Drawings
FIG. 1 is a flow chart illustrating a method for fabricating nanowires of a semiconductor device according to the present invention;
fig. 2 to 13 are schematic views illustrating a process of manufacturing a nanowire of a semiconductor device according to the present invention;
fig. 14 is a schematic cross-sectional view of a nanowire of a semiconductor device according to the present invention.
The silicon substrate is 1, the shallow trench isolation region is 2, the bulk silicon fin structure is 3, the mask layer is 4, the trench is 5, the groove is 6, the first epitaxial layer is 7, and the second epitaxial layer is 8.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. Additionally, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to overcome the technical problem of difficult integration of high-mobility materials with large lattice difference in the prior art, a method for preparing a semiconductor device nanowire is further provided (as shown in fig. 1), and the method comprises the following steps:
s1, providing a semiconductor substrate;
the substrate may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate, such as a bulk silicon substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate, such as a SiGe substrate, and the like. In the following description, for convenience of explanation, a silicon substrate 1 is described as an example (as shown in fig. 2). The substrate can be doped according to the needs by adopting the conventional technical scheme in the field, and the invention only elaborates the key point related to the inventive idea.
S2, forming shallow trench isolation regions 2 in the semiconductor substrate, wherein the semiconductor substrate between the shallow trench isolation regions 2 is a bulk silicon fin structure 3;
s20, specifically, as shown in fig. 2 and 3, the method for forming the bulk silicon fin structure 3 is as follows:
s201, forming a mask layer 4 on a semiconductor substrate, wherein the width of the mask layer 4 is the same as that of a preset nanowire;
as shown in fig. 2, in the present embodiment, the silicon substrate 1 is patterned to form ridges. Specifically, by forming a mask layer 4 such as a photoresist on the silicon substrate 1, the mask layer 4 is patterned into a shape corresponding to a ridge to be formed, for example, a long stripe shape (extending perpendicular to the paper surface) and the width of the mask layer 4 is ensured to be the same as the width of a predetermined nanowire.
S202, etching the area which is not shielded by the mask layer 4 on the semiconductor substrate to form a groove 5,
the semiconductor substrate between the trenches 5 constitutes the bulk silicon fin structure 3.
As shown in fig. 3, the mask layer 4 is used as a mask, and selective etching, such as Reactive Ion Etching (RIE), is used to etch the silicon substrate 1, i.e. the region of the silicon substrate 1 not covered by the mask layer 4 is etched, at this time, trenches 5 are formed on the silicon substrate 1, and the silicon substrate 1 between the trenches 5 is a ridge, i.e. the bulk silicon fin structure 3.
Only two bulk silicon fin structures 3 are shown, but those skilled in the art will appreciate that the present invention may also include more than two bulk silicon fin structures 3 and shallow trench isolation regions 2.
S21, specifically, as shown in fig. 4 and 5, the method of forming the shallow trench isolation region 2 is as follows:
s211, removing the mask layer 4 on the bulk silicon fin structure 3, and filling the trench 5 with a dielectric material so that the dielectric material covers the trench 5 and the surface of the bulk silicon fin structure 3;
as shown in fig. 4, in the present embodiment, after the body silicon fin structure 3 and the trench 5 are formed, the mask layer 4 is removed. A dielectric material, such as an oxide (e.g., silicon oxide), is filled in the trench 5 by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), so that the dielectric material covers the trench 5 and the surface of the bulk silicon fin structure 3.
S213, etching back the dielectric material to expose the top surface of the bulk silicon fin structure 3, and filling the dielectric material regions on both sides of the bulk silicon fin structure 3 to form the shallow trench isolation region 2.
As shown in fig. 5, the deposited dielectric material is planarized, such as by Chemical Mechanical Polishing (CMP) or sputtering, to expose the bulk silicon fin structure 3, and the dielectric material filled in the trench 5 fills the regions of the dielectric material on both sides of the bulk silicon fin structure 3 to form shallow trench isolation regions 2.
S3, selectively removing the bulk silicon fin structure 3, and recessing the bulk silicon fin structure 3 to form a groove 6;
specifically, the bulk silicon fin structure 3 is recessed by selective removal to form a groove 6, which facilitates later selective epitaxial growth of the thin film. When the bulk silicon fin structure 3 is selectively removed, the adopted etching method is any one or combination of a plurality of dry etching, HCl CVD thermal etching and alkaline etching, and the bulk silicon fin structure 3 can be partially removed or completely removed or removed deeply into the semiconductor substrate. In addition, according to different etching methods, after the bulk silicon fin structure 3 is selectively removed, the cross section of the removed shape close to one end of the substrate can be a horizontal plane, an inverted trapezoidal surface or a triangular surface.
Specifically, in an embodiment of the present invention, as shown in fig. 6, the bulk silicon fin structure 3 is selectively removed by dry (plasma) etching, the depth of the etched bulk silicon fin structure 3 can be freely grasped, etching is performed according to actual needs, and the cross section of one end of the removed shape close to the silicon substrate 1 is a horizontal plane;
specifically, in another embodiment of the present invention, as shown in fig. 7 and 8, the bulk silicon fin structure 3 is selectively removed by using an HCl CVD thermal etching method, the depth of the etched bulk silicon fin structure 3 can be freely controlled, etching is performed according to actual needs, and the cross section of one end of the removed shape close to the silicon substrate 1 is an inverted trapezoidal surface. In one embodiment of the invention, the process conditions for the hclpcvd thermal etching are as follows: temperature is 800oCTo 900oC. The flow rate of HCl is 20sccm to 200sccm, and the acting time is 10s to 300 s.
Specifically, in another embodiment of the present invention, as shown in fig. 9 and 10, the bulk silicon fin structure 3 is selectively removed by using an alkaline etching thermal etching method, the depth of the etched bulk silicon fin structure 3 can be freely controlled, etching is performed according to actual needs, and the cross section of one end of the removed shape close to the silicon substrate 1 is a triangular surface. In one embodiment of the present invention, the alkaline etching is performed by thermal etching mainly using a tetramethylammonium hydroxide (TMAH) solution, and in other embodiments, other etching solutions may be selected for thermal etching according to needs.
In the invention, when HCl CVD thermal etching or alkaline etching (TMAH solution) thermal etching is adopted, silicon oxide can be formed on the inclined plane and the side wall of the groove 6, and the formation of the silicon oxide is beneficial to annihilation of dislocation defects, and the growth of a large lattice mismatch material on a silicon substrate can be realized.
Through the different etching methods, the formed grooves 6 have different structures and can deal with various different conditions.
As shown in fig. 11, in an embodiment of the present invention, after the recess 6 is formed by recessing the bulk silicon fin structure 3, the surface of the silicon substrate 1 in the recess 6 may be further subjected to an annealing process. So that the surface of the groove 6 is less defective. Wherein the annealing treatment comprises any one of high-temperature annealing, rapid thermal annealing or laser annealing.
In one embodiment of the present invention, the annealing temperature of the annealing process is 720oC to 1050oC, annealing for 3s to 600s in the annealing environment of H2In the atmosphere.
S4, alternately stacking and growing a plurality of epitaxial layers with etching selectivity at the groove 6 along the vertical direction of the surface of the semiconductor substrate, and carrying out surface planarization;
specifically, in the groove 6 after the annealing treatment, a plurality of epitaxial layers are alternately stacked and grown in the vertical direction of the surface of the silicon substrate 1, and the filled surface is subjected to a planarization treatment, such as Chemical Mechanical Polishing (CMP) or sputtering, so that the surfaces of the plurality of epitaxial layers grown epitaxially are flat, thereby facilitating the subsequent treatment. Wherein the plurality of epitaxial layers may be one or an alternating stack of layers of material of SiGe, Si, SiGeC, SiGeSnC, GeSn, GeInP, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, or InAlGa. Of course, the choice of epitaxially grown material requires that the following two conditions be met:
(1) high-quality selective epitaxial growth is met;
(2) the epitaxially grown materials have an etch selectivity.
As shown in fig. 12, in an embodiment of the present invention, two epitaxial layer materials, i.e., a first epitaxial layer 7 and a second epitaxial layer 8, are alternately stacked and grown in a direction perpendicular to the surface of the silicon substrate 1, the first epitaxial layer 7 material is SiGe, wherein the thickness of SiGe is 5-20nm, and the mass ratio of Ge component in SiGe is greater than 0 and less than 30 wt%; the second epitaxial layer 8 is made of Si, wherein the thickness of the Si is 5 nm to 20 nm. Specifically, the process conditions for growing the SiGe epitaxial layer are as follows: introducing HCl in situ at a low temperature of 500 deg.CoC to 600oC. SiH was added under a pressure of 10Torr2CL2、Si2H6、GeH6And GeH4Taking the precursor as a precursor, and carrying out reduced pressure epitaxial growth on a SiGe layer; the process conditions for growing the Si epitaxial layer are as follows: at low temperature 500oC to 600oC. Under the condition of 10Torr of pressure, HCl and SiH are used2CL2Or HCl and SiH4Or HCl and Si2H6Or HCl, SiH2CL2And SiH4Or HCl, SiH2CL2And Si2H6Or HCl, SiH2CL2、Si2H6And SiH4And (3) carrying out reduced pressure epitaxial growth on the Si epitaxial layer as a precursor.
Under the above process conditions, SiGe epitaxial layers and Si epitaxial layers can be alternately stacked and selectively epitaxially grown at the recesses 6. The filled surface is subjected to a planarization process, such as Chemical Mechanical Polishing (CMP) or sputtering, so that the epitaxially grown first epitaxial layer 7 and second epitaxial layer 8 have a flat surface, which facilitates subsequent processing.
S5, making the shallow trench isolation 2 recessed so that the multiple epitaxial layers which are alternatively stacked and grown protrude from the shallow trench isolation 2 on both sides;
as shown in fig. 13, in one embodiment of the present invention, the shallow trench isolation region 2 is recessed by plasma etching, atomic etching or CVD etching, i.e. the filled dielectric material silicon dioxide is released to expose the epitaxially grown stack layer. In one embodiment of the present invention, plasma etching is used to recess the shallow trench isolation region 2, i.e., to release the filled dielectric material silicon dioxide, so that the stacked and grown SiGe epitaxial layer and Si epitaxial layer protrude from the shallow trench isolation region 2 on both sides, facilitating the post-processing.
And S6, selectively etching one or more epitaxial layers, wherein the remaining epitaxial layers form the nanowire structure.
Because the multiple epitaxial layers grown in a stacking mode have different selective etching ratios, one or more of the epitaxial layers are etched through selective etching, and a required nanowire structure is formed after etching.
In one embodiment of the present invention, as shown in fig. 14, since the first epitaxial layer 7 of epitaxial growth is a SiGe layer and the second epitaxial layer 8 is a Si layer, since there is an etching selectivity between SiGe and Si as the Ge composition increases, one of the materials can be selectively etched away, and the other material can be left to form the nanowire. For example, selectively etching portions of the Si layer to leave the SiGe layer, such that the SiGe layer constitutes the nanowire structure. The invention provides aIn the embodiment, SiGe and Si alternate epitaxial growth is selected, wherein the mass percentage of Ge in a SiGe component is more than 0 and less than 30%, and the etching conditions are as follows: using CF4、O2And a He etching system, and selectively etching Si under the condition that the cavity pressure is 5mt to obtain the SiGe nanowire.
The invention also provides a semiconductor device nanowire prepared by the preparation method of the semiconductor device nanowire.
According to the invention, the epitaxial layers of different materials are alternately stacked and grown on the silicon substrate, so that the defects in the epitaxial layers are reduced, the high-quality nanowire structure is prepared, the introduction and integration of different types of high-mobility materials are facilitated, and the performance of the device is improved.
The above examples are merely illustrative of the preferred embodiments of the present invention and do not limit the spirit and scope of the invention. Various modifications and improvements of the technical solutions of the present invention may be made by those skilled in the art without departing from the design concept of the present invention, and the technical contents of the present invention are all described in the claims.
Claims (10)
1. A method for preparing a semiconductor device nanowire is characterized by comprising the following steps:
providing a semiconductor substrate;
forming shallow trench isolation regions in the semiconductor substrate, wherein the semiconductor substrate between the shallow trench isolation regions is of a bulk silicon fin structure;
selectively removing the bulk silicon fin structure, and recessing the bulk silicon fin structure to form a groove;
alternately stacking and growing a plurality of epitaxial layers with etching selectivity at the groove along the vertical direction of the surface of the semiconductor substrate, and carrying out surface planarization;
recessing the shallow trench isolation regions so that a plurality of epitaxial layers which are alternately stacked and grown protrude from the shallow trench isolation regions on two sides;
and selectively etching one or more epitaxial layers, wherein the remained epitaxial layers form a nanowire structure.
2. The method of fabricating a nanowire for a semiconductor device of claim 1, wherein the bulk silicon fin structure is formed by a method comprising:
forming a mask layer on the semiconductor substrate, wherein the width of the mask layer is the same as that of a preset nanowire;
etching the area which is not shielded by the mask layer on the semiconductor substrate to form a groove;
the semiconductor substrate between the trenches constitutes the bulk silicon fin structure.
3. The method of claim 2, wherein the shallow trench isolation region is formed by:
removing the mask layer on the bulk silicon fin structure;
filling a dielectric material in the groove to enable the dielectric material to cover the groove and the surface of the bulk silicon fin structure;
etching back the dielectric material to expose a top surface of the bulk silicon fin structure;
and the dielectric material regions filled at two sides of the bulk silicon fin structure form the shallow trench isolation region.
4. The method of claim 1, wherein the selective removal of the bulk silicon fin structure is performed by any one or a combination of dry etching, HCl CVD thermal etching, and alkaline etching.
5. The method of claim 1 or 4, wherein the bulk silicon fin structure is selectively removed by removing the bulk silicon fin structure partially or completely or to a depth into the semiconductor substrate.
6. The method of claim 5, wherein after selectively removing the bulk silicon fin structure, the cross-section of the removed feature near the end of the semiconductor substrate can be a horizontal plane, an inverted trapezoidal plane, or a triangular plane.
7. The method of claim 1, wherein after recessing the bulk silicon fin structure to form the recess, the surface of the semiconductor substrate within the recess is further annealed.
8. The method for preparing nanowires of claim 7, wherein the annealing temperature of the annealing treatment is 720%oC to 1050oC, annealing for 3s to 600s in the annealing environment of H2In the atmosphere.
9. The method for preparing a nanowire of a semiconductor device according to claim 1, wherein SiGe epitaxial layers and Si epitaxial layers are alternately grown in a stack in a vertical direction of the surface of the semiconductor substrate at the recess, wherein the process conditions for growing the SiGe epitaxial layers are as follows: introducing HCl in situ at a low temperature of 500 deg.CoC to 600oC. SiH was added under a pressure of 10Torr2CL2、Si2H6、GeH6And GeH4Taking the precursor as a precursor, and carrying out reduced pressure epitaxial growth on a SiGe layer; the process conditions for growing the Si epitaxial layer are as follows: at low temperature 500oC to 600oC. Under the condition of 10Torr of pressure, HCl and SiH are used2CL2Or HCl and SiH4Or HCl and Si2H6Or HCl, SiH2CL2And SiH4Or HCl, SiH2CL2And Si2H6Or HCl, SiH2CL2、Si2H6And SiH4And (3) carrying out reduced pressure epitaxial growth on the Si epitaxial layer as a precursor.
10. A semiconductor device nanowire produced by the method for producing a semiconductor device nanowire according to any one of claims 1 to 9.
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