CN113053747B - Method for improving warpage of SiC wafer and preparation method of SiC semiconductor device - Google Patents
Method for improving warpage of SiC wafer and preparation method of SiC semiconductor device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 88
- 150000002500 ions Chemical class 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000001465 metallisation Methods 0.000 claims abstract description 19
- 230000004913 activation Effects 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 39
- 229910010271 silicon carbide Inorganic materials 0.000 description 38
- 230000008569 process Effects 0.000 description 22
- 230000000694 effects Effects 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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Abstract
The present disclosure provides a method of improving warpage of a SiC wafer and a method of manufacturing a SiC semiconductor device. The method for improving the warping of the SiC wafer comprises the following steps: providing a first conductive type SiC wafer, wherein the wafer is warped due to the fact that front-side ion implantation forms a front-side doped region, and the front-side doped region is a doped region required by a semiconductor device; forming a first back side doping area corresponding to the front side doping area on the back side of the wafer so as to enable stress generated by back side ion implantation and front side ion implantation to be mutually offset; carrying out high-temperature activation annealing on the wafer to eliminate residual stress on the wafer; etching the whole back of the wafer; forming a second back side doping region covering the entire back side of the wafer by implanting high energy ions of the first conductivity type; and carrying out metallization processing on the back of the wafer. By improving the warping degree of the wafer, the precision and consistency of the device processing technology are improved, the stability of the product is further improved, and the yield of the product is improved.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a method for improving warpage of a SiC wafer and a preparation method of a SiC semiconductor device.
Background
Silicon carbide (SiC) is one of the third-generation semiconductor materials, has the advantages of high breakdown electric field, high thermal conductivity, high saturation electron mobility and the like, has a good development prospect in the field of power devices, and has the characteristics of reduced device characteristic size and higher requirements on device processing technology along with the improvement of power density of the silicon carbide device.
After the SiC wafer is subjected to processes such as ion implantation, metallization annealing and the like, obvious warpage is generated, for a 4-inch SiC wafer, the warpage value accumulated by a multi-step process can reach more than 120um, on one hand, the subsequent photoetching process becomes difficult, the whole surface of the wafer is exposed inconsistently, and the photoetching precision and the line width uniformity are influenced; on the other hand, the wafer warpage is too large, which may cause the vacuum adsorption system of some equipment to fail to work normally, resulting in wafer positioning error, wafer identification failure, and further resulting in wafer falling, cracking and other consequences in the equipment.
Disclosure of Invention
In view of the above problems, the present disclosure provides a method of improving warpage of a SiC wafer and a method of manufacturing a SiC semiconductor device.
In a first aspect, the present disclosure provides a method of improving warpage of a SiC wafer, comprising:
providing a first conductive type SiC wafer, wherein the wafer is warped due to the fact that front-side ion implantation forms a front-side doped region, and the front-side doped region is a doped region required by a semiconductor device;
carrying out ion implantation on the back surface of the wafer for the first time to form a first back surface doping area which is arranged corresponding to the front surface doping area on the back surface of the wafer so as to enable stress generated by the back surface ion implantation and the front surface ion implantation to be mutually offset;
carrying out high-temperature activation annealing on the wafer to eliminate residual stress on the wafer;
etching the whole back of the wafer to etch away the first back doped region;
performing ion implantation on the back surface of the wafer again to form a second back surface doping area covering the whole back surface of the wafer by implanting high-energy ions of the first conductivity type, so that the wafer warping caused by etching is eliminated;
and carrying out metallization processing on the back surface of the wafer to form a back metal layer required by the semiconductor device and simultaneously counteract the wafer warping caused by carrying out ion implantation again on the back surface.
According to an embodiment of the present disclosure, preferably,
the ion doping concentration of the first back surface doping area is greater than or equal to that of the front surface doping area.
The depth of the first back side doped region is greater than or equal to the depth of the front side doped region.
According to the embodiment of the present disclosure, preferably, in the step of performing the first ion implantation on the back side of the wafer,
the ions implanted into the back side of the wafer are high-energy ions of a first conductivity type or a second conductivity type.
According to the embodiment of the present disclosure, preferably, in the step of etching the entire back surface of the wafer:
and etching the whole back of the wafer to a depth greater than that of the first back doped region.
In a second aspect, the present disclosure provides a method for manufacturing a SiC semiconductor device, including:
providing a first conductive type SiC wafer;
performing first ion implantation on the front surface of the wafer to form a first well region of a second conductivity type in the front surface of the wafer by implanting high-energy ions of the second conductivity type into the front surface of the wafer;
performing first ion implantation on the back of the wafer to form a second well region corresponding to the first well region in the back of the wafer by implanting high-energy ions into the back of the wafer;
performing second ion implantation on the front surface of the wafer to form a first conductive type first source region in the first well region on the front surface of the wafer by implanting first conductive type high-energy ions into the front surface of the wafer;
performing second ion implantation on the back surface of the wafer to form a second source region corresponding to the first source region in the second well region on the back surface of the wafer by implanting high-energy ions into the back surface of the wafer;
carrying out high-temperature activation annealing on the wafer;
etching the whole back of the wafer to etch away the second well region and the second source region;
performing third ion implantation on the back of the wafer to form a first conductive type doping area covering the whole back of the wafer by implanting high-energy ions of a first conductive type into the back of the wafer;
carrying out metallization processing on the back of the wafer to form a back metal layer; wherein, the stress generated by the metallization treatment and the stress generated by the third ion implantation on the back surface are mutually counteracted.
According to an embodiment of the present disclosure, it is preferable that,
the ion doping concentration of the second well region is greater than or equal to that of the first well region.
The depth of the second well region is greater than or equal to the depth of the first well region.
According to an embodiment of the present disclosure, preferably,
the ion doping concentration of the second source region is greater than or equal to that of the first source region;
the depth of the second source region is greater than or equal to the depth of the first source region.
According to the embodiment of the present disclosure, preferably, in the step of performing the first ion implantation on the back side of the wafer:
the ions implanted into the back side of the wafer are high-energy ions of a first conductivity type or a second conductivity type.
According to the embodiment of the present disclosure, preferably, in the step of performing the second ion implantation on the back side of the wafer:
the ions implanted into the back side of the wafer are high-energy ions of a first conductivity type or a second conductivity type.
According to the embodiment of the present disclosure, after the step of performing the high temperature activation annealing on the wafer, the method further includes:
forming a gate structure between two adjacent first well regions;
forming an interlayer dielectric layer covering the gate structure above the wafer;
forming a front side metal layer above the wafer, wherein the front side metal layer is electrically connected with the first source region.
According to the embodiment of the present disclosure, preferably, in the step of etching the entire back surface of the wafer:
and etching the whole back of the wafer to a depth greater than that of the second well region.
By adopting the technical scheme, the following technical effects can be at least achieved:
the invention provides a method for improving warpage of a SiC wafer and a preparation method of a SiC semiconductor device, wherein in the preparation process of the SiC semiconductor device, after each front ion implantation is finished, ion implantation is correspondingly carried out on the back to form a back doped region corresponding to the front doped region so as to counteract asymmetric warpage of the wafer caused by the front ion implantation, and then the back of the wafer is etched to etch the back doped region, so that the roughness of the back of the wafer can be increased, and the ohmic contact performance of the back is improved; and then carrying out ion implantation and back metallization treatment on the whole back of the wafer, wherein the stresses generated in the two processes are mutually offset, the warping of the wafer is reduced to a reasonable range, and simultaneously, the back doping concentration can be further increased, thereby being beneficial to forming better back ohmic contact. By improving the warping degree of the wafer, the precision and consistency of the device processing technology are improved, the stability of the product is further improved, and the yield of the product is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a schematic flow chart diagram illustrating a method of improving warpage in a SiC wafer in accordance with an exemplary embodiment of the present disclosure;
2-6 are schematic cross-sectional structures formed at steps associated with a method of improving warpage of a SiC wafer according to an exemplary embodiment of the present disclosure;
fig. 7-11 are schematic views illustrating wafer warpage states in steps associated with a method of improving warpage of a SiC wafer according to an exemplary embodiment of the disclosure.
Fig. 12 is a schematic flow chart diagram illustrating a method of fabricating a SiC semiconductor device in accordance with an exemplary embodiment of the present disclosure;
fig. 13 to 20 are schematic cross-sectional structure views formed at steps relevant to a manufacturing method of a SiC semiconductor device shown in an exemplary embodiment of the present disclosure;
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the following description, for purposes of explanation, specific details are set forth, such as particular arrangements, etc., in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
Example one
Fig. 1 is a schematic flow chart illustrating a method for improving warpage of a SiC wafer according to an embodiment of the disclosure. Fig. 2 to 6 are schematic cross-sectional structural diagrams formed by relevant steps of a method for improving warpage of a SiC wafer according to an embodiment of the present disclosure, and fig. 7 to 11 are schematic cross-sectional structural diagrams of a wafer in a warpage state of a SiC wafer according to a relevant step of a method for improving warpage of a SiC wafer according to an exemplary embodiment of the present disclosure. Detailed steps of an exemplary method for improving warpage of a SiC wafer according to an embodiment of the present disclosure are described below with reference to fig. 1 and 2 to 11.
As shown in fig. 1, the method for improving warpage of a SiC wafer of the present embodiment includes the following steps:
step S101: as shown in fig. 2 and 7, a first conductivity type SiC wafer 101 is provided, wherein the wafer 101 is warped due to front side ion implantation to form front side doped regions 102, the front side doped regions 102 being doped regions required to constitute a semiconductor device.
Specifically, the wafer 101 is warped with its edge facing downward.
Step S102: as shown in fig. 3 and 8, ion implantation is performed on the back surface of the wafer 101 to form a first back surface doped region 103 corresponding to the front surface doped region 102 on the back surface of the wafer 101, so that the stresses generated by the back surface ion implantation and the front surface ion implantation are mutually cancelled out, and the wafer warpage caused by the front surface ion implantation is improved.
Specifically, ion implantation is performed on the back surface of the wafer 101 through the mask layer as a mask, and high-energy ions of the first conductivity type or the second conductivity type are implanted into the back surface of the wafer 101, so as to form a first back surface doping region 103 on the back surface of the wafer 101; the first back-doped region 103 is aligned with the front-doped region 102.
The ion implantation of the back side of the wafer 101 and the ion implantation of the front side of the wafer 101 are both selected area ion implantation, the first back side doping area 103 and the front side doping area 102 are consistent in graph and aligned in position so as to offset asymmetric wafer warping caused by the front side ion implantation, the adjustment effect of the ion implantation process on the wafer warping is obvious, and compared with a stress film and back side etching, the ion implantation has a wider wafer warping adjustment range. The ion doping concentration of the first back side doping region 103 is greater than or equal to the ion doping concentration of the front side doping region 102, and the depth of the first back side doping region 103 is greater than or equal to the depth of the front side doping region 102.
Step S103: a high temperature activation anneal is performed on wafer 101 to relieve residual stress on wafer 101.
The high-temperature activation annealing can activate the doped ions and eliminate implantation damage, and the high-temperature activation annealing can also basically eliminate wafer warpage caused by previous processes, so that the wafer warpage cannot be accumulated backwards, and adverse effects on subsequent processes cannot be caused.
Step S104: as shown in fig. 4 and 9, the entire back side of the wafer 101 is etched to etch away the first back side doped region 103.
Specifically, the entire back surface of the wafer 101 is etched to a depth greater than the depth of the first back surface doping region 103, so as to etch away the first back surface doping region 103, thereby eliminating the influence of the first back surface doping region 103 on the consistency of the back surface ohmic contact, and simultaneously increasing the roughness of the back surface of the wafer 101 and improving the performance of the back surface ohmic contact. After step S104, the back surface of the wafer 101 is subjected to compressive stress, and the edge of the wafer 101 is warped downward.
Step S105: as shown in fig. 5 and 10, ion implantation is performed again on the back surface of the wafer 101 to form a first conductive type second back surface doping region 104 covering the entire back surface of the wafer 101 by implanting high energy ions of the first conductive type, thereby eliminating wafer warpage due to etching.
Specifically, the ion implantation again on the back surface of the wafer 101 is a full-surface ion implantation, which can counteract the wafer warpage caused by the etching process in step S104. The ion doping concentration and the depth of the second back doped region 104 need to consider the influence of the back metallization process in step S106 on the wafer warpage, and the wafer stresses generated by the two regions are opposite and cancel each other out. The conductivity type of the implanted ions needs to be the same as the original conductivity type of the wafer 101. The second ion implantation on the backside of the wafer 101 may further increase the backside doping concentration, which may help to form a better backside ohmic contact.
Step S106: as shown in fig. 6 and 11, the backside of the wafer 101 is metallized to form a backside metal layer 105 required to form the semiconductor device and to simultaneously counteract warpage caused by the backside re-implantation.
After the metallization process is completed, the stress generated by the metallization process and the re-ion implantation on the back side of the wafer 101 are opposite and cancel each other out. After step S106, the wafer 101 is restored to a flat state, and the wafer warpage is substantially eliminated.
In the present embodiment, the first conductivity type and the second conductivity type are opposite in conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.
The present disclosure provides a method for improving warpage of a SiC wafer, which performs ion implantation on a back surface of a SiC wafer 101 to obtain a first back surface doped region 103 corresponding to a front surface doped region 102, so as to reduce warpage of the wafer caused by the front surface ion implantation; etching the back of the wafer 101 can increase the roughness of the back of the wafer 101 and improve the ohmic contact performance of the back; and then the whole back surface of the wafer 101 is subjected to ion implantation and back surface metallization, the stresses generated in the two processes are mutually offset, the wafer warpage is reduced to a reasonable range, and meanwhile, the back surface doping concentration can be further increased by ion implantation again on the back surface, so that better back surface ohmic contact is formed. By improving the warping degree of the wafer, the precision and consistency of the device processing technology are improved, the stability of the product is improved, and the yield of the product is improved.
Example two
Fig. 12 is a schematic flow chart illustrating a method of manufacturing a SiC semiconductor device according to an embodiment of the present disclosure. Fig. 13 to fig. 20 are schematic cross-sectional structural views formed in relevant steps of a method for manufacturing a SiC semiconductor device according to an embodiment of the present disclosure. Next, detailed steps of an exemplary method of a method of manufacturing a SiC semiconductor device proposed by an embodiment of the present disclosure are described with reference to fig. 12 and fig. 13 to 20.
As shown in fig. 12, the method for manufacturing the SiC semiconductor device of the present embodiment includes the steps of:
step S201: a first conductivity type SiC wafer 201 is provided.
Step S202: as shown in fig. 13, a first ion implantation is performed on the front side of the wafer 201 to form a second conductive type first well region 202 in the front side of the wafer 201 by implanting energetic ions of a second conductive type into the front side of the wafer 201.
Specifically, the front surface of the wafer 201 is subjected to a first ion implantation through the mask layer as a mask, and high-energy ions of the second conductivity type are implanted into the front surface of the wafer 201, so as to form a plurality of second conductivity type first well regions 202 arranged at intervals in the wafer 201 on the front surface of the wafer 201. The first well region 202 is a doped region required for forming a SiC device.
Step S203: as shown in fig. 14, a first ion implantation is performed on the back side of the wafer 201, so as to form a second well region 203 corresponding to the first well region 202 in the back side of the wafer 201 by implanting high-energy ions into the back side of the wafer 201.
Specifically, a first ion implantation is performed on the back surface of the wafer 201 through the mask layer as a mask, and high-energy ions of the first conductivity type or the second conductivity type are implanted into the back surface of the wafer 201, so as to form a plurality of second well regions 203 of the first conductivity type or the second conductivity type at intervals in the wafer 201 on the back surface of the wafer 201; the second well region 203 is aligned with the first well region 202.
The first ion implantation on the back surface of the wafer 201 and the first ion implantation on the front surface of the wafer 201 are both selected region ion implantation, and the second well region 203 and the first well region 202 are arranged in a figure consistent and aligned mode so as to offset asymmetric wafer warping caused by the first ion implantation on the front surface.
The ion implantation process has an obvious effect of adjusting the wafer warpage, and has a wider wafer warpage adjusting range compared with stress films and back etching. The ion doping concentration of the second well region 203 is greater than or equal to the ion doping concentration of the first well region 202, and the depth of the second well region 203 is greater than or equal to the depth of the first well region 202.
Step S204: as shown in fig. 15, the front surface of the wafer 201 is subjected to a second ion implantation to form a first conductive type first source region 204 in the first well 202 on the front surface of the wafer 201 by implanting high energy ions of the first conductive type into the front surface of the wafer 201.
Specifically, a second ion implantation is performed on the front surface of the wafer 201 through the mask layer as a mask, and high-energy ions of the first conductivity type are implanted into the front surface of the wafer 201, so as to form a first source region 204 of the first conductivity type in the first well region 202 on the front surface of the wafer 201. The first source region 204 is a doped region required for forming a SiC device.
Step S205: as shown in fig. 16, a second ion implantation is performed on the back surface of the wafer 201, so as to form a second source region 205 corresponding to the first source region 204 in the second well region 203 on the back surface of the wafer 201 by implanting high-energy ions into the back surface of the wafer 201.
Specifically, a second ion implantation is performed on the back surface of the wafer 201 through the mask layer as a mask, and high-energy ions of the first conductivity type or the second conductivity type are implanted into the back surface of the wafer 201, so as to form a second source region 205 of the first conductivity type or the second conductivity type in the second well region 203 on the back surface of the wafer 201.
The second ion implantation on the back surface of the wafer 201 and the second ion implantation on the front surface of the wafer 201 are both selected area ion implantation, the second source area 205 and the first source area 204 are arranged in a pattern consistent and aligned mode to offset asymmetric wafer warping caused by the second ion implantation on the front surface, the adjusting effect of the ion implantation process on the wafer warping is obvious, and compared with a stress film and back surface etching, the ion implantation has a wider wafer warping adjusting range. The ion doping concentration of the second source region 205 is greater than or equal to the ion doping concentration of the first source region 204, and the depth of the second source region 205 is greater than or equal to the depth of the first source region 204.
Step S206: and carrying out high-temperature activation annealing on the wafer.
The high-temperature activation annealing can activate the doped ions and eliminate implantation damage, and the high-temperature activation annealing can also basically eliminate wafer warpage caused by previous processes, so that the wafer warpage cannot be accumulated backwards, and adverse effects on subsequent processes cannot be caused.
As shown in fig. 17, after step S206, the method further includes:
a gate structure is formed between two adjacent first well regions 202;
forming an interlayer dielectric layer 208 covering the gate structure above the wafer 201;
a front side metal layer 209 is formed over the wafer 201, wherein the front side metal layer 209 forms an electrical connection with the first source region 204.
The gate structure may include a gate insulating layer 206 and a gate electrode 207, wherein the gate insulating layer 206 is located above the wafer 201 and simultaneously contacts the first source region 204, the first well region 202 and the surface of the wafer 201; the gate electrode 207 is located over the gate insulating layer 206. The gate structure is a planar gate structure.
The gate structure may also be a trench gate structure (not shown). The groove gate structure comprises a gate groove, a gate insulating layer and a gate, wherein the gate groove is arranged in the wafer and is adjacent to the first well region, the gate insulating layer is arranged on the side wall and the bottom of the gate groove, the gate is filled in the gate groove, and the gate groove is also contacted with the first source region.
Step S207: as shown in fig. 18, the entire back side of the wafer 201 is etched to etch away the second well region 203 and the second source region 205.
Specifically, the whole back surface of the wafer 201 is etched, and the etching depth is greater than the depth of the second well region 203, so that the second well region 203 and the second source region 205 are etched, the influence of the second well region 203 and the second source region 205 on the consistency of the back ohmic contact is eliminated, meanwhile, the roughness of the back surface of the wafer 201 can be increased, and the performance of the back ohmic contact is improved. After step S207, the back surface of the wafer 201 is under compressive stress, and the edge of the wafer 201 is warped downward.
Step S208: as shown in fig. 19, a third ion implantation is performed on the back surface of the wafer 201 to form a first conductive-type doped region 210 covering the entire back surface of the wafer 201 by implanting high-energy ions of the first conductive type into the back surface of the wafer 201.
Specifically, the third ion implantation on the back surface of the wafer 201 is a full-surface ion implantation, which can not only counteract the wafer warpage caused by the etching process in step S207, but also counteract the wafer warpage caused by the metallization process in step S209. The ion doping concentration and the depth of the doped region 210 need to consider the influence of the back metallization process in step S209 on the wafer warpage, and the wafer stresses generated by the two are opposite to each other and cancel each other out. In step S208, the conductivity type of the implanted ions needs to be the same as the original conductivity type of the wafer 201. The third ion implantation on the back side of the wafer 201 may further increase the doping concentration on the back side of the wafer 201, which may help to form a better back ohmic contact.
Step S209: as shown in fig. 20, the back side of the wafer 201 is metallized to form a back side metal layer 211; the stress generated by the metallization treatment is opposite to the stress generated by the third ion implantation on the back surface, and the stress are mutually counteracted.
After the metallization process is completed, the stress generated by the metallization process and the third ion implantation on the back surface of the wafer 201 are opposite and offset. After step S209, the wafer 201 is restored to a flat state, and the wafer warpage is substantially eliminated.
In the present embodiment, the first conductivity type and the second conductivity type are opposite in conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P type, the second conductivity type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.
In the method for manufacturing a SiC semiconductor device provided in this embodiment, after ion implantation is performed on the front surface of the wafer 201 each time, ion implantation is correspondingly performed on the back surface to form a back second well region 203 and a second source region 205 corresponding to the front first well region 202 and the first source region 204, so as to counteract asymmetric wafer warpage caused by the front ion implantation, and then the back surface of the wafer 201 is etched to etch the back second well region 203 and the second source region 205, so that the roughness of the back surface of the wafer can be increased, and the back ohmic contact performance of the wafer can be improved; and then carrying out ion implantation and back metallization treatment on the whole back of the wafer, wherein the stresses generated in the two processes are mutually offset, the warping of the wafer is reduced to a reasonable range, and the back doping concentration can be further increased, so that better back ohmic contact can be formed. By improving the warping degree of the wafer, the precision and consistency of the device processing technology are improved, the stability of the product is further improved, and the yield of the product is improved.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.
Claims (11)
1. A method for improving warpage of a SiC wafer, comprising:
providing a first conductive type SiC wafer, wherein the wafer is warped due to the fact that front-side ion implantation forms a front-side doped region, and the front-side doped region is a doped region required by a semiconductor device;
carrying out ion implantation on the back surface of the wafer for the first time to form a first back surface doping area which is arranged corresponding to the front surface doping area on the back surface of the wafer so as to enable stress generated by the back surface ion implantation and the front surface ion implantation to be mutually offset;
carrying out high-temperature activation annealing on the wafer to eliminate residual stress on the wafer;
etching the whole back of the wafer to etch away the first back doped region;
performing ion implantation on the back surface of the wafer again to form a second back surface doping area covering the whole back surface of the wafer by implanting high-energy ions of the first conductivity type, so that the wafer warping caused by etching is eliminated;
and carrying out metallization processing on the back surface of the wafer to form a back metal layer required by the semiconductor device and simultaneously counteract the wafer warping caused by carrying out ion implantation again on the back surface.
2. The method for improving the warpage of the SiC wafer according to claim 1, wherein:
the ion doping concentration of the first back surface doping area is greater than or equal to that of the front surface doping area;
the depth of the first back side doped region is greater than or equal to the depth of the front side doped region.
3. The method for improving the warping of the SiC wafer according to claim 1, wherein in the step of performing the first ion implantation on the back surface of the wafer,
the ions implanted into the back side of the wafer are high-energy ions of a first conductivity type or a second conductivity type.
4. The method for improving the warping of the SiC wafer of claim 1, wherein in the step of etching the entire back side of the wafer:
and etching the whole back of the wafer to a depth greater than that of the first back doped region.
5. A method for manufacturing a SiC semiconductor device, comprising:
providing a first conductive type SiC wafer;
performing first ion implantation on the front surface of the wafer to form a first well region of a second conduction type in the front surface of the wafer by implanting high-energy ions of the second conduction type into the front surface of the wafer;
performing first ion implantation on the back surface of the wafer to form a second well region corresponding to the first well region in the back surface of the wafer by implanting high-energy ions into the back surface of the wafer;
performing second ion implantation on the front surface of the wafer to form a first conductive type first source region in the first well region on the front surface of the wafer by implanting first conductive type high-energy ions into the front surface of the wafer;
performing second ion implantation on the back surface of the wafer to form a second source region corresponding to the first source region in the second well region on the back surface of the wafer by implanting high-energy ions into the back surface of the wafer;
carrying out high-temperature activation annealing on the wafer;
etching the whole back of the wafer to etch away the second well region and the second source region;
performing third ion implantation on the back surface of the wafer to form a first conductive type doping area covering the whole back surface of the wafer by implanting high-energy ions of a first conductive type into the back surface of the wafer;
carrying out metallization processing on the back of the wafer to form a back metal layer; wherein, the stress generated by the metallization treatment and the stress generated by the third ion implantation on the back surface are mutually offset.
6. The method for producing the SiC semiconductor device according to claim 5, characterized in that:
the ion doping concentration of the second well region is greater than or equal to that of the first well region;
the depth of the second well region is greater than or equal to the depth of the first well region.
7. The method for producing the SiC semiconductor device according to claim 5, characterized in that:
the ion doping concentration of the second source region is greater than or equal to that of the first source region;
the depth of the second source region is greater than or equal to the depth of the first source region.
8. The method for producing the SiC semiconductor device according to claim 5, wherein in the step of performing the first ion implantation into the back surface of the wafer,
the ions implanted into the back side of the wafer are high-energy ions of a first conductivity type or a second conductivity type.
9. The method for producing the SiC semiconductor device according to claim 5, wherein in the step of performing the second ion implantation into the back surface of the wafer,
the ions implanted into the back side of the wafer are high-energy ions of a first conductivity type or a second conductivity type.
10. The method for manufacturing the SiC semiconductor device according to claim 5, further comprising, after the step of performing the high-temperature activation annealing on the wafer:
forming a gate structure between two adjacent first well regions;
forming an interlayer dielectric layer covering the gate structure above the wafer;
and forming a front metal layer above the wafer, wherein the front metal layer is electrically connected with the first source region.
11. The method for manufacturing the SiC semiconductor device according to claim 5, wherein in the step of etching the entire back surface of the wafer:
and etching the whole back of the wafer to a depth greater than that of the second well region.
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| EP0345380A2 (en) * | 1988-06-08 | 1989-12-13 | Mitsubishi Denki Kabushiki Kaisha | Manufacture of a semiconductor device |
| CN109148578A (en) * | 2017-06-16 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109727852A (en) * | 2018-12-29 | 2019-05-07 | 长江存储科技有限责任公司 | A kind of method, apparatus and equipment improving silicon wafer warpage |
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| US7407837B2 (en) * | 2004-01-27 | 2008-08-05 | Fuji Electric Holdings Co., Ltd. | Method of manufacturing silicon carbide semiconductor device |
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| JPS59152581A (en) * | 1983-02-18 | 1984-08-31 | Fujitsu Ltd | Production of bubble device |
| EP0345380A2 (en) * | 1988-06-08 | 1989-12-13 | Mitsubishi Denki Kabushiki Kaisha | Manufacture of a semiconductor device |
| CN109148578A (en) * | 2017-06-16 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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