CN210403736U - SGT device - Google Patents
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- CN210403736U CN210403736U CN201921682871.0U CN201921682871U CN210403736U CN 210403736 U CN210403736 U CN 210403736U CN 201921682871 U CN201921682871 U CN 201921682871U CN 210403736 U CN210403736 U CN 210403736U
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Abstract
The utility model provides a SGT device, SGT device includes: a substrate of a first conductivity type; the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type; a trench located within the epitaxial layer of the first conductivity type; the shielding gate dielectric layer covers the side wall and the bottom of the groove; the shielding grid electrode is positioned in the groove and positioned on the surface of the shielding grid dielectric layer far away from the epitaxial layer of the first conduction type; the polysilicon grid is positioned in the groove and is positioned above the shielding grid; the gate oxide is positioned on the side wall of the groove and positioned between the polycrystalline silicon gate and the epitaxial layer of the first conduction type; the insulating isolation layer is positioned in the groove and positioned between the polycrystalline silicon grid and the shielding grid; and the second conductive type injection region is positioned in the first conductive type epitaxial layer and is positioned below the groove. The utility model discloses a charge balance of slot bottom can be realized to the SGT device, the on-resistance of the unit area of SGT device can be reduced.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit design and manufacturing, especially, relate to a SGT device.
Background
SGT (Split Gate Trench) devices have found widespread use in the prior art. However, for the existing SGT device (especially, high voltage SGT device), for a Charge couple (Charge couple) structure, in order to achieve Charge balance (Charge balance) at the bottom of the trench and reduce the on-resistance of the SGT device per unit area, strict requirements on the depth of the trench and the thickness of the oxide layer in the trench need to be made; however, due to the limitation of the existing process, it is difficult to optimize the depth of the trench and the thickness of the oxide layer in the trench, and it is not possible to ensure the charge balance at the bottom of the trench in the SGT device, so that the on-resistance per unit area of the SGT device is large.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an SGT device for solving the problems of unbalanced trench bottom and large on-resistance per unit area existing in the SGT device in the prior art.
To achieve the above and other related objects, the present invention provides an SGT device, which includes:
a substrate of a first conductivity type;
the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type;
the groove is positioned in the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type;
the shielding grid dielectric layer covers the side wall and the bottom of the groove;
the shielding grid electrode is positioned in the groove and positioned on the surface of the shielding grid dielectric layer far away from the epitaxial layer of the first conductivity type;
the polysilicon grid is positioned in the groove and is positioned above the shielding grid;
the gate oxide layer is positioned on the side wall of the groove and positioned between the polycrystalline silicon gate and the epitaxial layer of the first conductivity type;
the insulating isolation layer is positioned in the groove and is positioned between the polycrystalline silicon grid and the shielding grid;
and the second conductive type injection region is positioned in the first conductive type epitaxial layer and is positioned below the groove.
Optionally, the trenches and the second conductivity type implantation regions are both multiple, and the multiple trenches are arranged at intervals in the first conductivity type epitaxial layer along a direction perpendicular to the direction in which the trenches extend; the second conductive type injection regions are correspondingly arranged below the grooves one by one.
Optionally, the first conductivity type comprises N-type and the second conductivity type comprises P-type.
Optionally, the first conductivity type comprises P-type and the second conductivity type comprises N-type.
Optionally, the implanted region of the second conductivity type wraps around the bottom of the trench.
Optionally, the SGT device further includes:
the body region of the second conduction type is positioned in the epitaxial layer of the first conduction type and positioned at the periphery of the gate oxide layer;
the source region of the first conduction type is positioned in the epitaxial layer of the first conduction type, positioned at the periphery of the gate oxide layer and positioned above the body region of the second conduction type;
a gate electrode connected to the polysilicon gate;
a source electrode connected to the body region of the second conductivity type;
and the drain electrode is positioned on the lower surface of the substrate of the first conduction type.
The utility model also provides a preparation method of SGT device, preparation method of SGT device includes following step:
providing a substrate of a first conductivity type;
forming an epitaxial layer of a first conductivity type on the upper surface of the substrate of the first conductivity type;
forming a groove in the epitaxial layer of the first conductivity type, wherein the groove extends along the thickness direction of the epitaxial layer of the first conductivity type;
forming an implantation region of a second conductivity type in the epitaxial layer of the first conductivity type under the trench;
forming a shielding gate dielectric layer on the side wall and the bottom of the groove;
forming a shielding grid electrode in the groove, wherein the shielding grid electrode is positioned on the surface of the shielding grid dielectric layer far away from the epitaxial layer of the first conductivity type;
forming an insulating isolation layer, a gate oxide layer and a polysilicon gate in the groove; wherein the polysilicon gate is located above the shield gate; the gate oxide layer is positioned on the side wall of the groove and is positioned between the polycrystalline silicon gate and the epitaxial layer of the first conduction type; the insulating isolation layer is located between the polysilicon gate and the shield gate.
Optionally, the number of the trenches formed in the epitaxial layer of the first conductivity type is multiple, and the multiple trenches are arranged at intervals in the epitaxial layer of the first conductivity type along a direction perpendicular to the direction in which the trenches extend; and forming an implantation region of the second conductivity type in the epitaxial layer of the first conductivity type under each trench.
Optionally, the second conductivity type implanted region is formed to wrap around the bottom of the trench.
Optionally, the first conductivity type includes N-type and the second conductivity type includes P-type, or the first conductivity type includes P-type and the second conductivity type includes N-type.
Optionally, the method further includes the following steps after forming the insulating isolation layer, the gate oxide layer and the polysilicon gate in the trench:
forming a body region of a second conductivity type in the epitaxial layer of the first conductivity type at the periphery of the trench, and forming a source region of the first conductivity type above the body region of the second conductivity type, wherein the source region of the first conductivity type is positioned at the periphery of the trench;
forming a source electrode and a gate electrode on the epitaxial layer of the first conductivity type, and forming a drain electrode on the lower surface of the substrate of the first conductivity type; the source electrode is connected with the body region of the second conduction type, and the gate electrode is connected with the polysilicon gate.
As described above, the SGT device of the present invention has the following advantageous effects:
the SGT device of the utility model can realize the charge balance at the bottom of the groove by forming the injection region of the second conductive type in the epitaxial layer of the first conductive type at the bottom of the groove, and can reduce the on-resistance of the unit area of the SGT device;
the utility model discloses a preparation method of SGT device does not receive the restriction of prior art to the depth of groove and ditch inslot oxide layer thickness, and the injection region through forming second conductivity type in the epitaxial layer of the first conductivity type of ditch groove bottom can be in order to realize the charge balance of ditch groove bottom, can reduce the on-resistance of the unit area of SGT device.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing an SGT device according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional structural diagram of the structure obtained in step 1) in the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 3 to the schematic cross-sectional structure shown as the structure obtained in step 2) in the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional structural diagram of the structure obtained in step 3) of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional structure diagram of the structure obtained in step 4) of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 6 is a schematic cross-sectional structure diagram of the structure obtained in step 5) of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 7 to fig. 8 are schematic cross-sectional structural diagrams of the structure obtained in step 6) of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 9 to fig. 10 are schematic cross-sectional structural diagrams of the structure obtained in step 7) of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 11 is a schematic cross-sectional structure diagram of the structure obtained in step 8) of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Fig. 12 is a schematic cross-sectional structural diagram of the structure obtained in step 9) of the method for manufacturing an SGT device according to the first embodiment of the present invention; fig. 12 is a schematic cross-sectional structure diagram of an SGT device provided in the second embodiment.
Description of the element reference numerals
10 substrate of a first conductivity type
11 epitaxial layer of a first conductivity type
12 grooves
13 implanted region of a second conductivity type
14 shield grid medium layer
15 shielded gate
151 shield gate material layer
16 insulating spacer layer
17 gate oxide layer
18 polysilicon gate
19 body region of the second conductivity type
20 source regions of a first conductivity type
21 source electrode
22 drain electrode
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only schematic and illustrative of the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, the present invention provides a method for manufacturing an SGT device, which includes the steps of:
1) providing a substrate of a first conductivity type;
2) forming an epitaxial layer of a first conductivity type on the upper surface of the substrate of the first conductivity type;
3) forming a groove in the epitaxial layer of the first conductivity type, wherein the groove extends along the thickness direction of the epitaxial layer of the first conductivity type;
4) forming an implantation region of a second conductivity type in the epitaxial layer of the first conductivity type under the trench;
5) forming a shielding gate dielectric layer on the side wall and the bottom of the groove;
6) forming a shielding grid electrode in the groove, wherein the shielding grid electrode is positioned on the surface of the shielding grid dielectric layer far away from the epitaxial layer of the first conductivity type;
7) forming an insulating isolation layer, a gate oxide layer and a polysilicon gate in the groove; wherein the polysilicon gate is located above the shield gate; the gate oxide layer is positioned on the side wall of the groove and is positioned between the polycrystalline silicon gate and the epitaxial layer of the first conduction type; the insulating isolation layer is located between the polysilicon gate and the shield gate.
In step 1), referring to step S1 in fig. 1 and fig. 2, a substrate 10 of a first conductivity type is provided.
As an example, the first conductive type substrate 10 may include, but is not limited to, a first conductive type silicon substrate, a first conductive type silicon carbide substrate, or a first conductive type silicon germanium substrate. Preferably, in this embodiment, the first conductive type substrate 10 is a first conductive type silicon substrate. Specifically, the first conductive type substrate 10 may be a substrate formed by performing ion implantation of a first conductive type to an intrinsic substrate.
In step 2), referring to step S2 of fig. 1 and fig. 3, an epitaxial layer 11 of the first conductivity type is formed on the upper surface of the substrate 10 of the first conductivity type.
As an example, the epitaxial layer 11 of the first conductivity type may be formed by epitaxial growth on the surface of the substrate 10 of the first conductivity type using an epitaxial process.
As an example, the epitaxial layer 11 of the first conductivity type may serve as a drift region.
In step 3), please refer to step S3 in fig. 1 and fig. 4, forming a trench 12 in the epitaxial layer 11 of the first conductivity type, wherein the trench 12 extends along a thickness direction of the epitaxial layer 11 of the first conductivity type.
As an example, the depth of the trench 12 may be set according to actual needs, and preferably, the depth of the trench 12 is smaller than the thickness of the epitaxial layer 11 of the first conductivity type; more preferably, the trenches 12 may be deep trenches, and the aspect ratios of the trenches 12 may be greater than 5: 1; more preferably, the aspect ratio of the trench 12 may be greater than 15: 1.
As an example, the number of the grooves 12 may be one or more; in fig. 4, the number of the grooves 12 is three as an example, and in an actual example, the number of the grooves 12 is not limited thereto. A plurality of the grooves 12 are arranged at intervals in a direction perpendicular to the direction in which the grooves 12 extend. The plurality of grooves 12 may be arranged at equal intervals or at unequal intervals.
As an example, the trench 12 may be formed using a photolithography etching process.
In step 4), referring to step S4 in fig. 1 and fig. 5, an implantation region 13 of the second conductivity type is formed in the epitaxial layer 11 of the first conductivity type under the trench 12.
As an example, an ion implantation process may be used to perform an ion implantation of the second conductivity type in the epitaxial layer 11 of the first conductivity type under the trench 12 to form an implantation region 13 of the second conductivity type. The second conductive type implant region 13 may coat the bottom of the trench 12 to maximally achieve charge balance at the bottom of the trench 12.
As an example, the longitudinal cross-sectional shape of the second conductivity type implantation region 13 may be circular, and of course, in other examples, the longitudinal cross-sectional shape of the second conductivity type implantation region 13 may also be elliptical, and so on. The implanted region 13 of the second conductivity type covers the bottom of the trench 12.
As an example, a patterned mask layer (not shown) may be formed first on the upper surface of the epitaxial layer 11 of the first conductivity type, wherein the opening pattern in the patterned mask layer exposes the trench 12, and the patterned mask layer serves as an ion implantation blocking layer; then, an ion implantation process is performed to implant ions of the second conductivity type into the epitaxial layer 11 of the first conductivity type under the trench 12 to form an implanted region 13 of the second conductivity type. It should be noted that, at the same time of forming the second conductive type implantation region 13, a shallow ion implantation region (not shown) of the second conductive type with a certain depth (shallow depth, insufficient for forming a body region) is formed in the epitaxial layer 11 of the first conductive type at the periphery of the trench 12.
As an example, in an ion implantation process, the implantation energy range may include, but is not limited to, between 10KeV and 200KeV, and the implantationDosage ranges may include, but are not limited to, 1012Per square centimeter to 1016One per square centimeter.
It should be noted that, when the number of the trenches 12 is multiple, the second conductive type implantation regions 13 are formed right below each trench 12, that is, the second conductive type implantation regions 13 are arranged in one-to-one correspondence with the trenches 12.
In step 5), referring to step S5 in fig. 1 and fig. 6, a shield gate dielectric layer 14 is formed on the sidewalls and bottom of the trench 12.
In one example, the shielding gate dielectric layer 14 may be formed directly on the sidewalls and bottom of the trench 12, and the top of the shielding gate dielectric layer 14 is formed not higher than the upper surface of the epitaxial layer 11 of the first conductivity type.
In another example, a dielectric layer may be formed prior to the sidewalls and bottom of the trench 12 and the upper surface of the epitaxial layer 11 of the first conductivity type; and then, removing the dielectric layer on the upper surface of the epitaxial layer 11 of the first conductivity type by using an etching process or a grinding process to form the shielding gate dielectric layer 14 on the sidewall and the bottom of the trench 12.
By way of example, the shield gate dielectric layer 14 may include, but is not limited to, a silicon oxide layer.
Illustratively, the thickness of the shield gate dielectric layer 14 is less than half the width of the trench 12.
In step 6), please refer to step S6 in fig. 1 and fig. 7 to 8, a shielding gate 15 is formed in the trench 12, and the shielding gate 15 is located on the surface of the shielding gate dielectric layer 14 away from the epitaxial layer 11 of the first conductivity type.
In an example, a shielding gate material layer 151 may be first deposited directly in the trench 12, and an upper surface of the shielding gate material layer 151 located in the trench 12 is flush with an upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 7; then, a part of the shielding gate material layer 151 and a part of the shielding gate dielectric layer 14 in the trench 12 are etched and removed, so that the upper surface of the shielding gate material layer 151 and the upper surface of the shielding gate dielectric layer 14 remaining in the trench 12 are both lower than the upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 8.
In another example, first, a shielding gate material layer 151 is formed in the trench 12 and on the upper surface of the epitaxial layer 11 of the first conductivity type; then, an etching process or a grinding process is used to remove the shielding gate material layer 151 on the upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 7; finally, etching and removing a part of the shielding gate material layer 151 and a part of the shielding gate dielectric layer 14 which are located in the trench 12, so that the upper surface of the shielding gate material layer 151 and the upper surface of the shielding gate dielectric layer 14 which remain in the trench 12 are both lower than the upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 8.
As an example, the shielding gate material layer 151 may be formed using a physical vapor deposition process or a chemical vapor deposition process; it should be noted that the shielding gate material layer 151 is preferably a doped polysilicon layer to ensure the conductivity of the shielding gate material layer 151.
In step 7), referring to step S7 in fig. 1 and fig. 9 to 10, forming an insulating isolation layer 16, a gate oxide layer 17 and a polysilicon gate 18 in the trench 12; wherein the polysilicon gate 18 is located above the shield gate 15; the gate oxide layer 17 is positioned on the side wall of the trench 12 and between the polysilicon gate 18 and the epitaxial layer 11 of the first conductivity type; the insulating spacer 16 is located between the polysilicon gate 18 and the shield gate 15.
As an example, step 7) may comprise the steps of:
7-1) forming the insulating isolation layer 16 on the upper surface of the shielding gate dielectric layer 14 and the upper surface of the shielding gate 15, as shown in fig. 9;
7-2) forming the gate oxide layer 17 on the upper side wall of the trench 12, and forming a polysilicon gate 18 in the trench 12, wherein the polysilicon gate 18 is located on the insulating isolation layer 16, as shown in fig. 10.
As an example, in step 7-1), the insulating isolation layer 16 may be formed by a physical vapor deposition process or a chemical vapor deposition process; the insulating isolation layer 16 at least completely covers the shield gate 15; preferably, the insulating isolation layer 16 covers the shielding gate 15 and the shielding gate dielectric layer 14.
As an example, the material of the insulating isolation layer 16 may be the same as the material of the shielding gate dielectric layer 14, and preferably, in this embodiment, the material of the insulating isolation layer 16 may include, but is not limited to, a silicon oxide layer.
As an example, step 7-2) may comprise the steps of:
7-2-1) forming said gate oxide layer 17 on the upper sidewall of said trench 12, on the upper surface of said insulating spacer 16 and on the upper surface of said epitaxial layer 11 of the first conductivity type;
7-2-2) forming the polysilicon layer (not marked) on the upper surface of the gate oxide layer 17, wherein the polysilicon layer fills the trench 12 and is partially positioned on the epitaxial layer 11 of the first conduction type;
7-2-3) removing said polysilicon layer on said epitaxial layer 11 of the first conductivity type and said gate oxide layer 17 on said epitaxial layer 11 of the first conductivity type.
As an example, in step 7-2 — 1), the gate oxide layer 17 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or a thermal oxidation process, where a thickness of the gate oxide layer 17 is less than half of a width of the trench 12, so as to ensure that a space of the polysilicon gate 18 is reserved in the trench 12 after the gate oxide layer 17 is formed. The gate oxide layer 17 may include, but is not limited to, a silicon oxide layer, and the thickness of the gate oxide layer 17 may be smaller than the thickness of the shielding gate dielectric layer 14, or may be the same as the thickness of the shielding gate dielectric layer 14.
As an example, in step 7-2-2), the polysilicon layer may be formed by a physical vapor deposition process or a chemical vapor deposition process; it should be noted that the polysilicon layer is preferably a doped polysilicon layer to ensure the conductivity of the polysilicon gate 18.
As an example, in step 7-2-3), the polysilicon layer on the first conductivity type epitaxial layer 11 and the gate oxide layer 17 on the first conductivity type epitaxial layer 11 may be removed by an etching process or a chemical mechanical polishing process.
As an example, step 7) is followed by the following steps:
8) forming a body region 19 of the second conductivity type in the epitaxial layer 11 of the first conductivity type at the periphery of the trench 12, and forming a source region 20 of the first conductivity type above the body region 19 of the second conductivity type, where the source region 20 of the first conductivity type is located at the periphery of the trench 12, as shown in fig. 11;
9) forming a source electrode 21 and a gate electrode (not shown) on the epitaxial layer 11 of the first conductivity type, and forming a drain electrode 22 on the lower surface of the substrate 10 of the first conductivity type, as shown in fig. 12; wherein the source electrode 21 is connected to the body region 19 of the second conductivity type and the gate electrode is connected to the polysilicon gate 18.
As an example, an ion implantation process may be employed to perform ion implantation of the second conductivity type from above the epitaxial layer 11 of the first conductivity type to form the body region 19 of the second conductivity type. Note that, after the second-conductivity-type body region 19 is formed, the second-conductivity-type shallow ion implantation region is covered with the second-conductivity-type body region 19.
As an example, an implantation of ions of the first conductivity type may be performed in the formed body region 19 of the second conductivity type, so that a portion of the body region 18 of the second conductivity type is inverted to form the source region 20 of the first conductivity type.
In an example, the source electrode 21 and the gate electrode may be formed on the epitaxial layer 11 of the first conductivity type, and the drain electrode 22 may be formed on the lower surface of the substrate 10 of the first conductivity type.
In another example, the drain electrode 22 may be formed on the lower surface of the first conductive type substrate 10, and the source electrode 21 and the gate electrode may be formed on the first conductive type epitaxial layer 11.
As an example, the source electrode 21, the gate electrode, and the drain electrode 22 may each include a metal electrode, such as a copper electrode, an aluminum electrode, a gold electrode, a silver electrode, a nickel electrode, or the like.
In an example, the first conductive type in each of the above steps may include an N type, and at this time, the second conductive type may include a P type.
In another example, the first conductive type in each of the above steps may include a P type, and in this case, the second conductive type may include an N type.
The utility model discloses a preparation method preparation of SGT device the SGT device is through slot 12 bottom form in first conductivity type's epitaxial layer 11 the injection region 13 of second conductivity type can realize the charge balance of slot 12 bottom can reduce the on-resistance of the unit area of SGT device.
Example two
With reference to fig. 12 with continued reference to fig. 2 to fig. 11, the present invention further provides an SGT device, which includes: a substrate 10 of a first conductivity type; an epitaxial layer 11 of a first conductivity type, the epitaxial layer 11 of the first conductivity type being located on an upper surface of the substrate 10 of the first conductivity type; a trench 12, wherein the trench 12 is located in the epitaxial layer 11 of the first conductivity type, and the trench 12 extends along the thickness direction of the epitaxial layer 11 of the first conductivity type; the shielding gate dielectric layer 14, wherein the shielding gate dielectric layer 14 covers the side wall and the bottom of the trench 12; a shielding gate 15, wherein the shielding gate 15 is located in the trench 12, and the shielding gate 15 is located on the surface of the shielding gate dielectric layer 14 away from the epitaxial layer 11 of the first conductivity type; a polysilicon gate 18, the polysilicon gate 18 being located within the trench 12, and the polysilicon gate 18 being located above the shield gate 15; a gate oxide layer 17, wherein the gate oxide layer 17 is positioned on the side wall of the trench 12, and the gate oxide layer 17 is positioned between the polysilicon gate 18 and the epitaxial layer 11 of the first conductivity type; an insulating spacer 16, said insulating spacer 16 being located within said trench 12, and said insulating spacer 16 being located between said polysilicon gate 18 and said shield gate 15; an implanted region 13 of a second conductivity type, said implanted region 13 of a second conductivity type being located within said epitaxial layer 11 of a first conductivity type, and said implanted region 13 of a second conductivity type being located below said trench 12.
As an example, the first conductive type substrate 10 may include, but is not limited to, a first conductive type silicon substrate, a first conductive type silicon carbide substrate, or a first conductive type silicon germanium substrate. Preferably, in this embodiment, the first conductive type substrate 10 is a first conductive type silicon substrate. Specifically, the first conductive type substrate 10 may be a substrate formed by performing ion implantation of a first conductive type to an intrinsic substrate.
As an example, the epitaxial layer 11 of the first conductivity type may serve as a drift region.
As an example, the depth of the trench 12 may be set according to actual needs, and preferably, the depth of the trench 12 is smaller than the thickness of the epitaxial layer 11 of the first conductivity type; more preferably, the trenches 12 may be deep trenches, and the aspect ratios of the trenches 12 may be greater than 5: 1; more preferably, the aspect ratio of the trench 12 may be greater than 15: 1.
As an example, the number of the grooves 12 may be one or more; in fig. 12, the number of the grooves 12 is three as an example, and in an actual example, the number of the grooves 12 is not limited thereto. A plurality of the grooves 12 are arranged at intervals in a direction perpendicular to the direction in which the grooves 12 extend. The plurality of grooves 12 may be arranged at equal intervals or at unequal intervals.
As an example, the longitudinal cross-sectional shape of the second conductivity type implantation region 13 may be circular, and of course, in other examples, the longitudinal cross-sectional shape of the second conductivity type implantation region 13 may also be elliptical, and so on.
As an example, the SGT device further comprises a body region 19 of a second conductivity type, said body region 19 of a second conductivity type being located within said epitaxial layer 11 of a first conductivity type, and said body region 19 of a second conductivity type being located at the periphery of said gate oxide layer 17.
As an example, the second conductive type implantation region 13 and the second conductive type body region 19 may be formed by using the same ion implantation process, in the ion implantation process, the implantation energy range may include, but is not limited to, 10KeV to 200KeV, and the implantation dose range may include, but is not limited to, 10KeV12Per square centimeter to 1016One per square centimeter.
As an example, the second conductive type implant region 13 may coat the bottom of the trench 12 to maximally achieve charge balance at the bottom of the trench 12.
It should be noted that, when the number of the trenches 12 is multiple, the second conductive type implantation regions 13 are formed right below each trench 12, that is, the second conductive type implantation regions 13 are arranged in one-to-one correspondence with the trenches 12.
By way of example, the shield gate dielectric layer 14 may include, but is not limited to, a silicon oxide layer.
Illustratively, the thickness of the shield gate dielectric layer 14 is less than half the width of the trench 12.
As an example, the shield gate 15 may be formed using a physical vapor deposition process or a chemical vapor deposition process; it should be noted that the shielding gate 15 is preferably a doped polysilicon layer to ensure the conductivity of the shielding gate 15.
As an example, the insulating isolation layer 16 may be formed using a physical vapor deposition process or a chemical vapor deposition process; the insulating isolation layer 16 at least completely covers the shield gate 15; preferably, the insulating isolation layer 16 covers the shielding gate 15 and the shielding gate dielectric layer 14.
As an example, the material of the insulating isolation layer 16 may be the same as the material of the shielding gate dielectric layer 14, and preferably, in this embodiment, the material of the insulating isolation layer 16 may include, but is not limited to, a silicon oxide layer.
As an example, the gate oxide layer 17 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or a thermal oxidation process, and the thickness of the gate oxide layer 17 is less than half of the width of the trench 12, so as to ensure that a space of the polysilicon gate 18 is reserved in the trench 12 after the gate oxide layer 17 is formed. The gate oxide layer 17 may include, but is not limited to, a silicon oxide layer, and the thickness of the gate oxide layer 17 may be smaller than the thickness of the shielding gate dielectric layer 14, or may be the same as the thickness of the shielding gate dielectric layer 14.
As an example, the polycrystalline silicon layer may be formed using a physical vapor deposition process or a chemical vapor deposition process; it should be noted that the polysilicon layer is preferably a doped polysilicon layer to ensure the conductivity of the polysilicon gate 18.
As an example, the SGT device further includes: a source region 20 of the first conductivity type, said source region 20 of the first conductivity type being located within said epitaxial layer 11 of the first conductivity type and at the periphery of said gate oxide 17 and above said body region 19 of the second conductivity type; a gate electrode (not shown) connected to the polysilicon gate 18; a source electrode 21, the source electrode 21 being connected to the body region 19 of the second conductivity type; a drain electrode 22, the drain electrode 22 being located on a lower surface of the first conductive type substrate 10.
As an example, the source electrode 21, the gate electrode, and the drain electrode 22 may each include a metal electrode, such as a copper electrode, an aluminum electrode, a gold electrode, a silver electrode, a nickel electrode, or the like.
In an example, the first conductive type may include an N-type, and at this time, the second conductive type may include a P-type.
In another example, the first conductive type described above may include a P type, and at this time, the second conductive type may include an N type.
SGT device through slot 12 bottom form in first conductivity type's epitaxial layer 11 the injection region 13 of second conductivity type can be realized the charge balance of slot 12 bottom can reduce the on-resistance of the unit area of SGT device.
To sum up, the utility model provides a SGT device, the SGT device includes: a substrate of a first conductivity type; the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type; the groove is positioned in the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type; the shielding grid dielectric layer covers the side wall and the bottom of the groove; the shielding grid electrode is positioned in the groove and positioned on the surface of the shielding grid dielectric layer far away from the epitaxial layer of the first conductivity type; the polysilicon grid is positioned in the groove and is positioned above the shielding grid; the gate oxide layer is positioned on the side wall of the groove and positioned between the polycrystalline silicon gate and the epitaxial layer of the first conductivity type; the insulating isolation layer is positioned in the groove and is positioned between the polycrystalline silicon grid and the shielding grid; and the second conductive type injection region is positioned in the first conductive type epitaxial layer and is positioned below the groove. The SGT device of the utility model can realize the charge balance at the bottom of the groove by forming the injection region of the second conductive type in the epitaxial layer of the first conductive type at the bottom of the groove, and can reduce the on-resistance of the unit area of the SGT device; the utility model discloses a preparation method of SGT device does not receive the restriction of prior art to the depth of groove and ditch inslot oxide layer thickness, and the injection region through forming second conductivity type in the epitaxial layer of the first conductivity type of ditch groove bottom can be in order to realize the charge balance of ditch groove bottom, can reduce the on-resistance of the unit area of SGT device.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. An SGT device, comprising:
a substrate of a first conductivity type;
the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type;
the groove is positioned in the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type;
the shielding grid dielectric layer covers the side wall and the bottom of the groove;
the shielding grid electrode is positioned in the groove and positioned on the surface of the shielding grid dielectric layer far away from the epitaxial layer of the first conductivity type;
the polysilicon grid is positioned in the groove and is positioned above the shielding grid;
the gate oxide layer is positioned on the side wall of the groove and positioned between the polycrystalline silicon gate and the epitaxial layer of the first conductivity type;
the insulating isolation layer is positioned in the groove and is positioned between the polycrystalline silicon grid and the shielding grid;
and the second conductive type injection region is positioned in the first conductive type epitaxial layer and is positioned below the groove.
2. The SGT device of claim 1, wherein: the grooves and the second conduction type injection regions are multiple, and the grooves are arranged at intervals in the first conduction type epitaxial layer along the direction perpendicular to the extending direction of the grooves; the second conductive type injection regions are correspondingly arranged below the grooves one by one.
3. The SGT device of claim 1, wherein: the first conductivity type includes an N-type and the second conductivity type includes a P-type.
4. The SGT device of claim 1, wherein: the first conductivity type includes a P-type, and the second conductivity type includes an N-type.
5. The SGT device of claim 1, wherein: the second conductive type implanted region wraps the bottom of the trench.
6. SGT device according to any one of claims 1 to 5, characterized in that: the SGT device further includes:
the body region of the second conduction type is positioned in the epitaxial layer of the first conduction type and positioned at the periphery of the gate oxide layer;
the source region of the first conduction type is positioned in the epitaxial layer of the first conduction type, positioned at the periphery of the gate oxide layer and positioned above the body region of the second conduction type;
a gate electrode connected to the polysilicon gate;
a source electrode connected to the body region of the second conductivity type;
and the drain electrode is positioned on the lower surface of the substrate of the first conduction type.
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| CN201921682871.0U CN210403736U (en) | 2019-09-29 | 2019-09-29 | SGT device |
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| CN201921682871.0U CN210403736U (en) | 2019-09-29 | 2019-09-29 | SGT device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987074A (en) * | 2020-09-30 | 2020-11-24 | 深圳市威兆半导体有限公司 | Anti-dv/dt SGT device |
| CN112002686A (en) * | 2020-09-30 | 2020-11-27 | 深圳市威兆半导体有限公司 | anti-EMI SGT device |
| CN112201583A (en) * | 2020-10-27 | 2021-01-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MOSFET (Metal-oxide-semiconductor field Effect transistor) device comprising SGT (silicon germanium transistor) structure |
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2019
- 2019-09-29 CN CN201921682871.0U patent/CN210403736U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987074A (en) * | 2020-09-30 | 2020-11-24 | 深圳市威兆半导体有限公司 | Anti-dv/dt SGT device |
| CN112002686A (en) * | 2020-09-30 | 2020-11-27 | 深圳市威兆半导体有限公司 | anti-EMI SGT device |
| CN112201583A (en) * | 2020-10-27 | 2021-01-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MOSFET (Metal-oxide-semiconductor field Effect transistor) device comprising SGT (silicon germanium transistor) structure |
| CN112201583B (en) * | 2020-10-27 | 2024-02-27 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MOSFET device containing SGT structure |
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