CN111987074A - Anti-dv/dt SGT device - Google Patents
Anti-dv/dt SGT device Download PDFInfo
- Publication number
- CN111987074A CN111987074A CN202011065162.5A CN202011065162A CN111987074A CN 111987074 A CN111987074 A CN 111987074A CN 202011065162 A CN202011065162 A CN 202011065162A CN 111987074 A CN111987074 A CN 111987074A
- Authority
- CN
- China
- Prior art keywords
- conductivity type
- conduction type
- groove
- gate
- body region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 210000000746 body region Anatomy 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000010355 oscillation Effects 0.000 abstract description 16
- 239000003990 capacitor Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses an anti-dv/dt SGT device, which comprises: the device comprises a substrate of a first conductivity type, an epitaxial layer of the first conductivity type positioned on the upper surface of the substrate of the first conductivity type, a groove positioned in the epitaxial layer of the first conductivity type, a first dielectric layer, a lightly doped body region of the first conductivity type positioned at the bottom of the groove, a heavily doped body region of the first conductivity type positioned at the periphery of the first dielectric layer, source metal positioned above the side surface of the epitaxial layer of the first conductivity type, a second dielectric layer positioned on the upper surface of the groove, a polysilicon gate positioned in the groove and a shielding gate. The invention can increase the drain-source capacitance Cds and reduce the switch oscillation, thereby reducing the voltage oscillation dv/dt failure possibility of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a dv/dt resistant SGT device.
Background
Shielded Gate MOSFET (abbreviated SGT-MOSFET) power devices have been widely used in the prior art. Meanwhile, a MOSFET (metal oxide semiconductor field effect transistor) is widely used in various fields such as a switching power supply, automotive electronics, and motor drive due to its advantages of large input resistance, easy driving, simple control, and high frequency characteristics. When the power switch tube is used as a power switch tube for controlling energy circulation and conversion, the power switch tube works in a fast switch conversion state, and in the face of very high voltage oscillation dv/dt and current oscillation di/dt between a drain electrode and a source electrode, on one hand, the high voltage oscillation dv/dt is superposed on a device, so that a parasitic triode is easily started, and the device is easy to fail; on the other hand, high voltage oscillation dv/dt is superposed in a switching system to cause great electromagnetic interference, so that serious electromagnetic pollution is generated to surrounding components and equipment.
The existing SGT-MOSFET connects a shielding grid electrode with a source electrode potential, improves the switching speed by reducing the Miller capacitance Cgd of a device, reduces the switching loss, inevitably leads to larger voltage oscillation dv/dt and current oscillation di/dt, and increases the voltage oscillation dv/dt failure possibility of the device.
Disclosure of Invention
The invention aims to provide a dv/dt resistant SGT device which can increase drain-source capacitance CdS and reduce switching oscillation, so that the voltage oscillation dv/dt failure possibility of the device is reduced.
In order to realize the purpose, the following technical scheme is adopted:
an anti-dv/dt SGT device comprising:
a substrate of a first conductivity type;
the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type;
the groove is positioned in the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type;
a polysilicon grid and a shielding grid are arranged in the groove;
the first dielectric layer is positioned on the bottom surface and the side surface of the shielding grid electrode and the side surface of the polycrystalline silicon grid electrode and is used for isolating the polycrystalline silicon grid electrode from the shielding grid electrode;
the lightly doped body region of the first conduction type is positioned at the bottom of the groove and is positioned below the shielding grid electrode;
the heavily doped body region of the first conductivity type is positioned between the first dielectric layer on the periphery of the shielding grid and the lower side wall of the groove, and is positioned between the first dielectric layer on the periphery of the shielding grid and the upper surface of the lightly doped body region of the first conductivity type;
the source metal is positioned above the side face of the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type;
and the second dielectric layer is positioned on the upper surface of the groove and extends to be in contact with the side wall of the source metal along the extending direction vertical to the groove.
Preferably, the shielding gate comprises a wide portion gate and a plurality of narrow portion gates, and the wide portion gate is located above the narrow portion gates; the narrow part grids are arranged at intervals along the direction perpendicular to the extending direction of the groove.
Preferably, the width of the wide portion gate is greater than that of the narrow portion gate, and the length of the wide portion gate is less than that of the narrow portion gate.
Preferably, the wide portion gate and the narrow portion gate are electrically connected to the source metal.
Preferably, the SGT device further includes:
the body region of the second conduction type is positioned at the periphery of the groove and is positioned on the upper surface of the epitaxial layer of the first conduction type;
the second conduction type body region is provided with a first conduction type source region and a second conduction type heavily doped contact region which are mutually contacted.
Preferably, the lower surface of the source metal is in direct contact with the heavily doped contact region of the second conductivity type, and the side surface of the source metal is also in direct contact with the source region of the first conductivity type and the heavily doped contact region of the second conductivity type.
Preferably, the SGT device further includes:
a gate electrode connected to the polysilicon gate;
and the drain metal is positioned on the lower surface of the substrate of the first conduction type.
Preferably, the doping concentration of the lightly doped body region of the first conductivity type is less than that of the heavily doped body region of the first conductivity type and less than that of the epitaxial layer of the first conductivity type.
By adopting the scheme, the invention has the beneficial effects that:
the invention provides an anti-dv/dt SGT device which comprises the following components:
1) a first dielectric layer and a heavily doped body region of the first conductivity type are arranged at the periphery of the narrow part grid to form a CMOS capacitor, and the CMOS capacitor is connected in series with the lightly doped body region of the first conductivity type below the narrow part grid, and an RC absorption loop is formed between the source electrode and the drain electrode, so that the switching oscillation of a device is effectively reduced, the dv/dt tolerance is improved, and the EMI electromagnetic radiation noise in a switching circuit is reduced; meanwhile, the heavily doped body region of the first conductivity type around the narrow part grid is utilized, so that the on-resistance of the device is not additionally increased; in the invention, from the perspective of device structure design, the dv/dt tolerance of the device is improved, no parasitic parameter in a switching circuit is additionally introduced, and the switching loss is not increased;
2) the wide part grid and the narrow part grid are electrically connected with the source electrode metal, and the potentials are equal, so that a grid signal of the polysilicon grid is effectively shielded, the Miller capacitance Cgd is reduced, the switching speed of a device is increased, and the switching loss of the device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of embodiment 1 (polysilicon gate and shield gate) of the present invention;
fig. 2 is a schematic structural diagram of embodiment 2 (polysilicon gate and shield gate) of the present invention;
FIG. 3 is a schematic diagram of an equivalent circuit of the present invention;
wherein the figures identify the description:
1-a substrate of a first conductivity type, 2-an epitaxial layer of the first conductivity type,
3-polysilicon gate, 4-first dielectric layer,
5-a lightly doped body region of the first conductivity type, 6-a heavily doped body region of the first conductivity type,
7-source metal, 8-second dielectric layer,
9/9 '-wide part gate, 10/10' -narrow part gate,
11-body regions of the second conductivity type, 12-source regions of the first conductivity type,
13-heavily doped contact region of the second conductivity type, 14-drain metal.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
Referring to fig. 1 to 3, the present invention provides a dv/dt resistant SGT device, comprising: a substrate 1 of a first conductivity type; an epitaxial layer 2 of the first conductivity type on the upper surface of the substrate 1 of the first conductivity type; the groove is positioned in the epitaxial layer 2 of the first conduction type and extends along the thickness direction of the epitaxial layer 2 of the first conduction type; a polysilicon gate 3 and a shielding gate are arranged in the groove; the first dielectric layer 4 is positioned on the bottom surface and the side surface of the shielding grid electrode and the side surface of the polycrystalline silicon grid electrode 3 and is used for isolating the polycrystalline silicon grid electrode 3 from the shielding grid electrode; a lightly doped body region 5 of the first conductivity type at the bottom of the trench and below the shield gate; the heavily doped body region 6 of the first conductivity type is positioned between the first dielectric layer 4 at the periphery of the shielding grid and the lower side wall of the groove, and is positioned between the first dielectric layer 4 at the periphery of the shielding grid and the upper surface of the lightly doped body region 5 of the first conductivity type; a source metal 7 located above the side surface of the epitaxial layer 2 of the first conductivity type and extending in the thickness direction of the epitaxial layer 2 of the first conductivity type; and the second dielectric layer 8 is positioned on the upper surface of the groove and extends to be in contact with the side wall of the source metal 7 along the direction vertical to the extending direction of the groove.
Wherein the shielding gate includes a wide portion gate 9/9 'and a plurality of narrow portion gates 10/10', and the wide portion gate 9/9 'is located above the narrow portion gates 10/10', and the width of the wide portion gate 9/9 'is greater (along the direction perpendicular to the extension direction of the trench), the length of the wide portion gate 9/9' is shorter (along the direction along the extension direction of the trench), the number of wide portion gates 9/9 'is 1, and the number of narrow portion gates 10/10' is greater than or equal to 2; the plurality of narrow portion gates 10/10' are spaced apart in a direction perpendicular to the direction in which the trench extends.
The shielding grid is electrically connected with the source metal 7, namely the wide part grid 9/9 'and the narrow part grid 10/10' are electrically connected with the source metal 7, and the potentials are equal, so that the grid signal of the polysilicon grid 3 is effectively shielded, the Miller capacitance Cgd of the device is greatly reduced, the switching speed of the device is improved, and the switching loss of the device is reduced. The invention improves the dv/dt tolerance of the device from the perspective of the structural design of the device, does not additionally introduce parasitic parameters in a switching circuit, and does not increase the switching loss.
The SGT device further comprises a body region 11 of the second conductivity type, which is positioned at the periphery of the groove and is positioned on the upper surface of the epitaxial layer 2 of the first conductivity type; the body region 11 of the second conductivity type has a source region 12 of the first conductivity type and a heavily doped contact region 13 of the second conductivity type in contact with each other. The lower surface of the source metal 7 is in direct contact with the heavily doped contact region 13 of the second conductivity type, and the side surface of the source metal 7 is also in direct contact with the source region 12 of the first conductivity type and the heavily doped contact region 13 of the second conductivity type.
The SGT device also comprises a grid electrode which is connected with the polysilicon grid 3; and a drain metal 7 on a lower surface of the first conductive type substrate 1.
The lightly doped body region 5 of the first conductivity type is located at the bottom of the trench, and the doping concentration of the lightly doped body region 5 of the first conductivity type is smaller than the heavily doped body region 6 of the first conductivity type and smaller than the epitaxial layer 2 of the first conductivity type.
According to the invention, the CMOS capacitor is formed by the narrow-part grids 10/10 ', the first dielectric layer 4 and the first conductive type heavy doping body 6 region on the periphery of the narrow-part grids 10/10 ', and the narrow-part grids 10/10 ' are connected in series with the first conductive type light doping body region 5 (equivalent resistor), so that an RC absorption loop is formed between the source electrode and the drain electrode, the switching oscillation of the device is effectively reduced, the dv/dt tolerance is improved, and the EMI electromagnetic radiation noise in a switching circuit is reduced. Because the potentials at two ends of the RC absorption circuit are divided into a source electrode and a drain electrode, and a heavily doped body region 6 of the first conduction type exists, the SGT device can absorb the switching oscillation (voltage oscillation dv/dt and current oscillation di/dt) between the source electrode and the drain electrode under the condition of not increasing the on-resistance, thereby reducing the dv/dt failure possibility and the EMI noise of the device.
The semiconductor involved in the SGT device can be made of bulk silicon, silicon carbide, gallium arsenide, indium phosphide, silicon germanium or other semiconductor materials.
By way of example, the first/second dielectric layer 4/8 may be an oxide layer or other dielectric layers.
As an example, the epitaxial layer 2 of the first conductivity type may serve as a drift region.
In one embodiment, the first conductive type may include an N-type, and at this time, the second conductive type may include a P-type.
In another embodiment, the first conductive type may include a P type, and at this time, the second conductive type may include an N type.
The shield gate and the polysilicon gate 3 are located as follows:
continuing to refer to fig. 1, example 1: the polysilicon gate 3 and the shield gate are vertically arranged, and the polysilicon gate 3 is located above the shield gate. At this time, the first dielectric layer 4 around the narrow portion gate 10 is entirely surrounded by the heavily doped body region 6 of the first conductivity type, the lower portion of the wide portion gate 9 is surrounded by the heavily doped body region 6 of the first conductivity type, and the upper portion of the wide portion gate 9 is surrounded by the first dielectric layer 4.
Continuing with reference to fig. 2, example 2: the positions of the polysilicon gate 3 and the shield gate are horizontally arranged, and the polysilicon gate 3 is positioned at two sides of the shield gate. The periphery of the narrow portion gate 10 'is still the first dielectric layer 4, and only a portion of the first dielectric layer 4 around the narrow portion gate 10' is surrounded by the heavily doped body region 6 of the first conductivity type. It can be equivalent to a CMOS equivalent capacitor and a resistor which are connected in series between the source and the drain.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. An anti-dv/dt SGT device, comprising:
a substrate of a first conductivity type;
the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type;
the groove is positioned in the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type;
a polysilicon grid and a shielding grid are arranged in the groove;
the first dielectric layer is positioned on the bottom surface and the side surface of the shielding grid electrode and the side surface of the polycrystalline silicon grid electrode and is used for isolating the polycrystalline silicon grid electrode from the shielding grid electrode;
the lightly doped body region of the first conduction type is positioned at the bottom of the groove and is positioned below the shielding grid electrode;
the heavily doped body region of the first conductivity type is positioned between the first dielectric layer on the periphery of the shielding grid and the lower side wall of the groove, and is positioned between the first dielectric layer on the periphery of the shielding grid and the upper surface of the lightly doped body region of the first conductivity type;
the source metal is positioned above the side face of the epitaxial layer of the first conduction type and extends along the thickness direction of the epitaxial layer of the first conduction type;
and the second dielectric layer is positioned on the upper surface of the groove and extends to be in contact with the side wall of the source metal along the extending direction vertical to the groove.
2. The dv/dt resistant SGT device of claim 1, wherein the shield gate comprises a wide portion gate and a plurality of narrow portion gates, and the wide portion gate is located above the narrow portion gates; the narrow part grids are arranged at intervals along the direction perpendicular to the extending direction of the groove.
3. The dv/dt resistant SGT device of claim 2, wherein the wide portion gate has a width greater than a width of the narrow portion gate, and wherein the length of the wide portion gate is less than the length of the narrow portion gate.
4. The dv/dt resistant SGT device according to claim 2, wherein the wide portion gate, narrow portion gate and source metal are electrically connected.
5. The dv/dt resistant SGT device according to claim 1, wherein said SGT device further comprises: the body region of the second conduction type is positioned at the periphery of the groove and is positioned on the upper surface of the epitaxial layer of the first conduction type; the second conduction type body region is provided with a first conduction type source region and a second conduction type heavily doped contact region which are mutually contacted.
6. The dv/dt resistant SGT device according to claim 5, wherein the lower surface of the source metal is in direct contact with a heavily doped contact region of the second conductivity type, and the side surface of the source metal is also in direct contact with the source region of the first conductivity type and the heavily doped contact region of the second conductivity type.
7. The dv/dt resistant SGT device according to claim 1, wherein said SGT device further comprises: a gate electrode connected to the polysilicon gate;
and the drain metal is positioned on the lower surface of the substrate of the first conduction type.
8. The dv/dt resistant SGT device according to claim 1, wherein the lightly doped body region of the first conductivity type has a doping concentration less than the heavily doped body region of the first conductivity type and less than the epitaxial layer of the first conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011065162.5A CN111987074A (en) | 2020-09-30 | 2020-09-30 | Anti-dv/dt SGT device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011065162.5A CN111987074A (en) | 2020-09-30 | 2020-09-30 | Anti-dv/dt SGT device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111987074A true CN111987074A (en) | 2020-11-24 |
Family
ID=73450592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011065162.5A Pending CN111987074A (en) | 2020-09-30 | 2020-09-30 | Anti-dv/dt SGT device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111987074A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920848A (en) * | 2017-04-19 | 2017-07-04 | 无锡新洁能股份有限公司 | Charged Couple power MOSFET device and its manufacture method |
| US20170278837A1 (en) * | 2016-03-25 | 2017-09-28 | Force Mos Technology Co., Ltd | Semiconductor power device having shielded gate structure and esd clamp diode manufactured with less mask process |
| CN110890427A (en) * | 2019-09-09 | 2020-03-17 | 电子科技大学 | Shielding grid MOSFET device with adjustable capacitance |
| CN210403736U (en) * | 2019-09-29 | 2020-04-24 | 恒泰柯半导体（上海）有限公司 | SGT device |
| CN111584622A (en) * | 2020-06-02 | 2020-08-25 | 无锡新洁能股份有限公司 | Shielding gate power semiconductor device |
| CN212342616U (en) * | 2020-09-30 | 2021-01-12 | 深圳市威兆半导体有限公司 | Anti-dv/dt SGT device |
-
2020
- 2020-09-30 CN CN202011065162.5A patent/CN111987074A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170278837A1 (en) * | 2016-03-25 | 2017-09-28 | Force Mos Technology Co., Ltd | Semiconductor power device having shielded gate structure and esd clamp diode manufactured with less mask process |
| CN106920848A (en) * | 2017-04-19 | 2017-07-04 | 无锡新洁能股份有限公司 | Charged Couple power MOSFET device and its manufacture method |
| CN110890427A (en) * | 2019-09-09 | 2020-03-17 | 电子科技大学 | Shielding grid MOSFET device with adjustable capacitance |
| CN210403736U (en) * | 2019-09-29 | 2020-04-24 | 恒泰柯半导体（上海）有限公司 | SGT device |
| CN111584622A (en) * | 2020-06-02 | 2020-08-25 | 无锡新洁能股份有限公司 | Shielding gate power semiconductor device |
| CN212342616U (en) * | 2020-09-30 | 2021-01-12 | 深圳市威兆半导体有限公司 | Anti-dv/dt SGT device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9478614B2 (en) | Semiconductor device | |
| US10192977B2 (en) | Power semiconductor device | |
| JP4785334B2 (en) | Semiconductor device | |
| US8809903B2 (en) | Semiconductor device and power conversion apparatus using the same | |
| CN112002686A (en) | anti-EMI SGT device | |
| JP4028333B2 (en) | Semiconductor device | |
| CN110518065B (en) | Low-power-consumption and high-reliability groove type silicon carbide MOSFET device | |
| JP2016184622A (en) | Semiconductor device and method of manufacturing the same | |
| JP6072445B2 (en) | Semiconductor device and power conversion device using the same | |
| CN109166923B (en) | Shielding gate MOSFET | |
| US6388280B2 (en) | Semiconductor device | |
| CN212342616U (en) | Anti-dv/dt SGT device | |
| US20040245597A1 (en) | Lateral field-effect-controllable semiconductor component for RF applications | |
| CN212659538U (en) | anti-EMI SGT device | |
| KR20150061202A (en) | Power semiconductor device | |
| CN111261698B (en) | RC-LIGBT device for eliminating voltage folding phenomenon | |
| CN116031303B (en) | Super junction device, manufacturing method thereof and electronic device | |
| CN111987074A (en) | Anti-dv/dt SGT device | |
| CN111244179B (en) | anti-EMI super-junction VDMOS device | |
| JP2019071384A (en) | Semiconductor device | |
| CN108767001B (en) | Trench IGBT device with shielding gate | |
| CN111969041B (en) | Super-junction VDMOS | |
| CN114068496B (en) | Integrated SGT-MOSFET device for voltage sampling | |
| US20230335590A1 (en) | Semiconductor device | |
| CN216054718U (en) | Semiconductor structure and insulated gate bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |