CN211182215U

CN211182215U - Deep trench MOSFET terminal structure

Info

Publication number: CN211182215U
Application number: CN201922234535.6U
Authority: CN
Inventors: 罗志云; 王飞; 潘梦瑜
Original assignee: Hunteck Semiconductor (shanghai) Co ltd
Current assignee: Hunteck Semiconductor (shanghai) Co ltd
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2020-08-04
Anticipated expiration: 2029-12-11

Abstract

The utility model provides a deep groove MOSFET terminal structure, deep groove MOSFET terminal structure includes: a substrate of a first conductivity type; an epitaxial layer of a first conductivity type; a plurality of first trenches; a first dielectric layer; a first source polysilicon layer; a first well region of a second conductivity type; a plurality of second trenches; a second dielectric layer; a second source polysilicon layer; a gate polysilicon layer; gate oxide and insulating isolation layer. The utility model discloses a deep groove MOSFET terminal structure sets up the first well region of second conductivity type as JTE structure through the first slot bottom in terminal protection area for the electric field of first slot bottom can disperse, and vertical electric field can transversely extend in terminal protection area, has improved deep groove MOSFET terminal structure's compressive property effectively, and terminal protection area's withstand voltage is higher than the withstand voltage of active area, does not receive the withstand voltage restriction in active area, can effectively carry out the terminal protection.

Description

Deep trench MOSFET terminal structure

Technical Field

The utility model belongs to the technical field of integrated circuit design and manufacturing, especially, relate to a deep groove MOSFET terminal structure.

Background

In designing a power semiconductor device, the design of a terminal protection region is very important. The design of the active region determines characteristics such as resistance, capacitance, breakdown voltage and the like of the power semiconductor device, but is limited by the effectiveness and the area of the terminal protection design. In a good terminal design, in order to ensure the reliability during the period, a voltage breakdown point is required to be located in an active region instead of a terminal protection region, and meanwhile, the occupied area of the terminal protection region can directly influence the on-resistance of the active region.

As the performance of the deep trench device is superior to that of the traditional trench device, the deep trench device occupies a larger and larger proportion in the power semiconductor device. However, the conventional terminal design is difficult to solve the problem that the longitudinal electric field distribution of the deep trench device is not balanced at the terminal, so that the terminal design of the deep trench device becomes difficult. At present, an Oxide layer is generally directly adopted as a terminal of a deep trench MOSFET (Metal-Oxide-semiconductor field Effect Transistor), although the process compatibility is good, the withstand voltage of a terminal protection region is lower than that of an active region, the whole withstand voltage of a device is limited, and the design on-resistance of the device is higher and the reliability is reduced.

Meanwhile, the conventional field limiting ring (guiding) and termination expansion structure (JTE) are generally only suitable for planar devices with transverse electric field distribution, and the conventional deep trench device is not suitable for deep trench devices with longitudinal electric field distribution because the voltage of an active region in the deep trench device is not uniformly distributed at the termination and the electric field is crowded.

SUMMERY OF THE UTILITY MODEL

In view of the above shortcomings in the prior art, an object of the present invention is to provide a deep trench MOSFET terminal structure and a method for manufacturing the same, for solving the problem that the withstand voltage of the terminal protection region existing in the MOSFET terminal device in the prior art is lower than the withstand voltage of the active region, which limits the overall withstand voltage of the device, resulting in higher on-resistance of the device design and reduced reliability.

In order to achieve the above objects and other related objects, the present invention provides a deep trench MOSFET terminal structure, which includes:

the semiconductor device comprises a substrate of a first conduction type, a first electrode and a second electrode, wherein the substrate of the first conduction type comprises an active area and a terminal protection area positioned on the periphery of the active area;

the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type and covers the active region and the terminal protection region;

a plurality of first trenches located within the epitaxial layer of the first conductivity type and within the termination protection region; the first grooves are arranged at intervals in the terminal protection area; the distance between the adjacent first grooves is the same, or gradually increases from the active region to the direction far away from the active region;

the first dielectric layer covers the side wall and the bottom of each first groove;

the first source electrode polycrystalline silicon layer is positioned in each first groove and positioned on the surface of the first dielectric layer far away from the epitaxial layer of the first conduction type;

a plurality of first well regions of a second conductivity type, located in the epitaxial layer of the first conductivity type, and located at the bottom of each first trench; the first well regions of the second conduction type are overlapped and superposed with the first grooves;

a plurality of second trenches located within the epitaxial layer of the first conductivity type and within the active region; the second grooves are arranged in the active region at intervals, and the distance between every two adjacent first grooves is the same, and the distance between every two adjacent second grooves is the same as the distance between every two adjacent first grooves;

the second dielectric layers are positioned on the side walls and the bottoms of the second grooves;

the second source electrode polycrystalline silicon layer is positioned in each second groove and positioned on the surface of the second medium layer far away from the epitaxial layer of the first conduction type;

the grid polycrystalline silicon layer is positioned in each second groove and positioned above the second source polycrystalline silicon layer or positioned on the periphery of the upper part of the second source polycrystalline silicon layer;

the gate oxide layer is positioned on the side wall of each second groove and is positioned between the gate polycrystalline silicon layer and the epitaxial layer of the first conduction type;

and the insulation isolation layer is positioned in each second groove and positioned between the grid polycrystalline silicon layer and the second source polycrystalline silicon layer.

Optionally, the first well region of the second conductivity type at the bottom of the first trench farthest from the active region has a spacing with the first well region of the second conductivity type adjacent thereto, and the rest of the first well regions of the second conductivity type adjacent to the first trench are overlapped with the first trench.

Optionally, the deep trench MOSFET terminal structure further includes a second well region of a second conductivity type located within the epitaxial layer of the first conductivity type and between adjacent ones of the first trenches.

Optionally, the deep trench MOSFET termination structure further comprises:

at least one third trench, located in the epitaxial layer of the first conductivity type, and located at a junction of the active region and the terminal protection region;

the third dielectric layer covers the side wall and the bottom of the third groove;

and the third source polycrystalline silicon layer is positioned in the third groove.

Optionally, a longitudinal cross-sectional shape of the first well region of the second conductivity type includes a circle.

Optionally, the first conductivity type includes N-type and the second conductivity type includes P-type, or the first conductivity type includes P-type and the second conductivity type includes N-type.

The utility model also provides a preparation method of deep groove MOSFET terminal structure, preparation method of deep groove MOSFET terminal structure includes following step:

providing a substrate of a first conduction type, wherein the substrate of the first conduction type comprises an active area and a terminal protection area positioned at the periphery of the active area;

forming an epitaxial layer of a first conductivity type on the upper surface of the substrate of the first conductivity type, wherein the epitaxial layer of the first conductivity type covers the active region and the terminal protection region;

forming a plurality of first trenches and a plurality of second trenches in the epitaxial layer of the first conductivity type, wherein the first trenches are located in the terminal protection region, the first trenches are arranged in the terminal protection region at intervals, and the distances between adjacent first trenches are the same or gradually increase from the active region to the direction away from the active region; the second trenches are positioned in the active region, the second trenches are arranged in the active region at intervals, and the distance between every two adjacent first trenches is the same, and the distance between every two adjacent second trenches is the same as the distance between every two adjacent first trenches;

forming a first well region of a second conductivity type at the bottom of the first trench; the first well regions of the second conduction type are overlapped and superposed with the first grooves;

forming a first dielectric layer on the side wall and the bottom of each first groove, and forming a second dielectric layer on the side wall and the bottom of each second groove;

forming a first source polycrystalline silicon layer in each first groove and forming a second source polycrystalline silicon layer in each second groove; the first source electrode polycrystalline silicon layer is positioned on the surface, far away from the first conductive type epitaxial layer, of the first dielectric layer, and the second source electrode polycrystalline silicon layer is positioned on the surface, far away from the first conductive type epitaxial layer, of the second dielectric layer;

forming an insulating isolation layer, a gate oxide layer and a gate polysilicon layer in each second trench; the grid polycrystalline silicon layer is positioned above the second source polycrystalline silicon layer or positioned on the upper periphery of the second source polycrystalline silicon layer; the gate oxide layer is positioned on the side wall of the second groove and is positioned between the gate polycrystalline silicon layer and the epitaxial layer of the first conduction type; the insulating isolation layer is located between the gate polysilicon layer and the second source polysilicon layer.

Optionally, while forming the first well region of the second conductivity type, a second well region of the second conductivity type is also formed in the epitaxial layer of the first conductivity type between adjacent first trenches.

Optionally, at the same time of forming the first trench and the second trench, at least one third trench is further formed in the epitaxial layer of the first conductivity type, where the third trench is located at a boundary between the active region and the terminal protection region; forming a third dielectric layer on the side wall and the bottom of the third groove while forming the first dielectric layer and the second dielectric layer; and forming the third source polycrystalline silicon layer in the third groove while forming the first source polycrystalline silicon layer and the second source polycrystalline silicon layer.

As described above, the utility model discloses a deep groove MOSFET terminal structure and preparation method thereof has following beneficial effect:

the utility model discloses a deep groove MOSFET terminal structure is through setting up the first well region of second conductivity type as JTE structure in the first trench bottom of terminal protection area for the electric field of first trench bottom can disperse, and the vertical electric field can transversely extend at the terminal protection area, has improved deep groove MOSFET terminal structure's withstand voltage characteristic effectively, and the withstand voltage of terminal protection area is higher than the withstand voltage of active area, does not receive the withstand voltage restriction in active area, can effectively carry out terminal protection;

the utility model discloses a thickness of the first dielectric layer that is arranged in the first slot, the second dielectric layer that is arranged in the second slot and the third dielectric layer that is arranged in the third slot in the deep trench MOSFET terminal structure can be made thinner, thereby optimizing the design of the epitaxial layer of the first conductivity type and effectively improving the on-resistance of the deep trench MOSFET terminal structure;

the depth of the first groove, the second groove and the third groove in the deep groove MOSFET terminal structure of the utility model is not required to be increased along with the rise of voltage, thereby reducing the process difficulty;

the longitudinal section of the first well region of the first conduction type in the deep groove MOSFET terminal structure is circular, so that the width of a terminal protection region can be effectively reduced, and the chip area is saved;

in the deep trench MOSFET terminal structure of the utility model, the injection concentration of the first well region of the first conductive type is smaller, thereby saving the cost; the distance between every two grooves is small, so that the area of a chip is saved;

the utility model discloses a preparation method of deep groove MOSFET terminal structure is compatible in current technology, does not need extra thermal annealing, and is with low costs, and application scope is wide, safe and reliable.

Drawings

Fig. 1 is a flowchart illustrating a method for manufacturing a deep trench MOSFET terminal structure according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional structure diagram of the structure obtained in step 1) in the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step 2) in the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 4 is a schematic cross-sectional structure diagram of the structure obtained in step 3) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 5 is a schematic cross-sectional structure diagram of the structure obtained in step 4) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 6 is a schematic cross-sectional structure diagram of the structure obtained in step 5) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 7 to fig. 8 are schematic cross-sectional structural diagrams of the structure obtained in step 6) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 9 to fig. 10 are schematic cross-sectional structural diagrams of the structure obtained in step 7) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 11 is a schematic cross-sectional structure diagram of the structures obtained in step 8) and step 9) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention.

Fig. 12 is a schematic cross-sectional structure diagram of the structure obtained in step 10) of the method for manufacturing a deep trench MOSFET terminal structure according to the first embodiment of the present invention; fig. 12 is a schematic cross-sectional view of the deep trench MOSFET terminal structure provided in the second embodiment.

Fig. 13 is a schematic cross-sectional structure diagram of the structure obtained in step 6) of the method for manufacturing a deep trench MOSFET terminal structure according to the third embodiment of the present invention.

Fig. 14 to fig. 15 are schematic cross-sectional structural views of the structure obtained in step 7) of the method for manufacturing a deep trench MOSFET terminal structure in the third embodiment of the present invention.

Fig. 16 is a schematic cross-sectional structure diagram of the structures obtained in step 8) and step 9) of the method for manufacturing a deep trench MOSFET terminal structure according to the third embodiment of the present invention.

Fig. 17 is a schematic cross-sectional structure diagram of the structure obtained in step 10) of the method for manufacturing a deep trench MOSFET terminal structure according to the third embodiment of the present invention; fig. 17 is a schematic cross-sectional view of the deep trench MOSFET terminal structure provided in the fourth embodiment.

Fig. 18 is a schematic cross-sectional structure diagram of the structure obtained in step 3) of the method for manufacturing a deep trench MOSFET terminal structure according to the fifth embodiment of the present invention.

Fig. 19 is a schematic cross-sectional structure diagram of the structure obtained in step 4) of the method for manufacturing a deep trench MOSFET terminal structure according to the fifth embodiment of the present invention.

Fig. 20 is a schematic cross-sectional view of the structure obtained in step 10) of the method for manufacturing a deep trench MOSFET terminal structure according to the fifth embodiment of the present invention; fig. 20 is a schematic cross-sectional view of the deep trench MOSFET terminal structure provided in the sixth embodiment.

Fig. 21 is a schematic cross-sectional view of the structure obtained in step 10) of the method for manufacturing a deep trench MOSFET terminal structure according to the seventh embodiment of the present invention; fig. 21 is a schematic cross-sectional view of the deep trench MOSFET terminal structure provided in the eighth embodiment.

Description of the element reference numerals

10 substrate of a first conductivity type

101 active region

102 terminal protection zone

11 epitaxial layer of a first conductivity type

12 first trench

13 second trench

14 first well region of a second conductivity type

15 first dielectric layer

16 first source polysilicon layer

17 second dielectric layer

18 second source polysilicon layer

19 insulating spacer

20 gate oxide layer

21 grid polysilicon layer

22 second well region of a second conductivity type

23 third groove

24 third dielectric layer

25 third source polysilicon layer

26 body region of the second conductivity type

27 source region of the first conductivity type

28 source electrode

29 drain electrode

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to fig. 1 to 21. It should be noted that the drawings provided in the present embodiment are only schematic and illustrative of the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

Example one

Referring to fig. 1, the present invention provides a method for manufacturing a deep trench MOSFET terminal structure, which comprises the steps of:

1) providing a substrate of a first conduction type, wherein the substrate of the first conduction type comprises an active area and a terminal protection area positioned at the periphery of the active area;

2) forming an epitaxial layer of a first conductivity type on the upper surface of the substrate of the first conductivity type, wherein the epitaxial layer of the first conductivity type covers the active region and the terminal protection region;

3) forming a plurality of first trenches and a plurality of second trenches in the epitaxial layer of the first conductivity type, wherein the first trenches are located in the terminal protection region, the first trenches are arranged in the terminal protection region at intervals, and the distances between adjacent first trenches are the same or gradually increase from the active region to the direction away from the active region; the second trenches are positioned in the active region, the second trenches are arranged in the active region at intervals, and the distance between every two adjacent first trenches is the same, and the distance between every two adjacent second trenches is the same as the distance between every two adjacent first trenches;

4) forming a first well region of a second conductivity type at the bottom of the first trench; the first well regions of the second conduction type are overlapped and superposed with the first grooves;

5) forming a first dielectric layer on the side wall and the bottom of each first groove, and forming a second dielectric layer on the side wall and the bottom of each second groove;

6) forming a first source polycrystalline silicon layer in each first groove and forming a second source polycrystalline silicon layer in each second groove; the first source electrode polycrystalline silicon layer is positioned on the surface, far away from the first conductive type epitaxial layer, of the first dielectric layer, and the second source electrode polycrystalline silicon layer is positioned on the surface, far away from the first conductive type epitaxial layer, of the second dielectric layer;

7) forming an insulating isolation layer, a gate oxide layer and a gate polysilicon layer in each second trench; the grid polycrystalline silicon layer is positioned above the second source polycrystalline silicon layer or positioned on the upper periphery of the second source polycrystalline silicon layer; the gate oxide layer is positioned on the side wall of the second groove and is positioned between the gate polycrystalline silicon layer and the epitaxial layer of the first conduction type; the insulating isolation layer is located between the gate polysilicon layer and the second source polysilicon layer.

In step 1), referring to step S1 in fig. 1 and fig. 2, a substrate 10 of a first conductivity type is provided, where the substrate 10 of the first conductivity type includes an active region 101 and a terminal protection region 102 distributed along a lateral direction.

As an example, the first conductive type substrate 10 may include, but is not limited to, a first conductive type silicon substrate, a first conductive type silicon carbide substrate, or a first conductive type silicon germanium substrate. Preferably, in this embodiment, the first conductive type substrate 10 is a first conductive type silicon substrate. Specifically, the first conductive type substrate 10 may be a substrate formed by performing ion implantation of a first conductive type to an intrinsic substrate.

In step 2), referring to step S2 in fig. 1 and fig. 3, an epitaxial layer 11 of the first conductivity type is formed on the upper surface of the substrate 10 of the first conductivity type, and the epitaxial layer 11 of the first conductivity type covers the active region 101 and the terminal protection region 102.

As an example, the epitaxial layer 11 of the first conductivity type may be formed by epitaxial growth on the surface of the substrate 10 of the first conductivity type using an epitaxial process.

As an example, the epitaxial layer 11 of the first conductivity type may serve as a drift region.

In step 3), please refer to step S3 in fig. 1 and fig. 4, forming a plurality of first trenches 12 and a plurality of second trenches 13 in the epitaxial layer 11 of the first conductivity type, wherein the first trenches 12 are located in the termination protection region 102, the plurality of first trenches 12 are spaced apart from each other in the termination protection region 102, and the distances between adjacent first trenches 12 are the same or gradually increase from the active region 101 to the direction away from the active region 101; the second trenches 13 are located in the active region 101, the second trenches 13 are spaced in the active region 101, and the distances between adjacent first trenches 12 are the same, and the distances between adjacent second trenches 13 are the same as the distances between adjacent first trenches 12.

As an example, forming the first trench 12 and the second trench 13 simultaneously includes forming at least one third trench 23 in the epitaxial layer 11 of the first conductivity type; the third trench 23 is located at the boundary between the active region 101 and the terminal protection region 102. The utility model discloses a deep groove MOSFET terminal structure is through first slot 12 with set up between the second slot 13 third slot 23 can provide a buffer area, thereby improves deep groove MOSFET terminal structure's field is gathered the effect and to can improving alignment error tolerance in the preparation technology of deep groove MOSFET terminal structure.

For example, the depth of the first trench 12, the depth of the second trench 13, and the depth of the third trench 23 may be the same or different; the depth of the first trench 12 is smaller than the thickness of the epitaxial layer 11 of the first conductivity type, the depth of the second trench 13 is smaller than the thickness of the epitaxial layer 11 of the first conductivity type, and the depth of the third trench 23 is smaller than the thickness of the epitaxial layer 11 of the first conductivity type.

For example, the width of the first trench 12, the width of the second trench 13, and the width of the third trench 23 may be the same or different.

As an example, the number of the first trenches 12 formed in the terminal protection region 102 may be set according to actual needs, wherein the number of the first trenches 12 is three in fig. 4 as an example, and in an actual example, the number of the first trenches 12 is not limited thereto. A plurality of the first trenches 12 extend in a direction from the active region 101 to away from the active region 101.

As an example, the number of the third grooves 23 may be set according to actual needs, and the number of the third grooves 23 may be one or multiple; in fig. 4, the number of the third grooves 23 is taken as an example, and in an actual example, the number of the third grooves 23 is not limited sequentially.

As an example, the distance between the third trench 23 and the second trench 13 adjacent thereto is larger than the distance between the third trench 23 and the first trench 12 adjacent thereto.

In another example, the distance between adjacent first trenches 12 may gradually increase from the active region 101 to a direction away from the active region 101.

In step 4), referring to step S4 in fig. 1 and fig. 5, a first well region 14 of the second conductivity type is formed at the bottom of the first trench 12; the first well regions 14 of the second conductivity type are overlapped between the first trenches 12.

As an example, an ion implantation process may be performed on the epitaxial layer 11 of the first conductivity type at the bottom of the first trench 12 to form a first well region 14 of the second conductivity type. The first well region 14 of the second conductivity type extends from the bottom of the first trench 12 to the periphery of the lower portion of the first trench 12. The ion implantation energy range may be 10 KeV-200 KeV, and the implantation dose range may be 10KeV¹²Per square centimeter to 10¹⁶One per square centimeter.

As an example, the longitudinal cross-sectional shape of the first well region 14 of the first conductivity type may be circular, but of course, in other examples, the longitudinal cross-sectional shape of the first well region 14 of the first conductivity type may also be elliptical, and so on.

As an example, the first well regions 14 of the second conductivity type adjacent to each other partially overlap and coincide between the adjacent first trenches 12, that is, each first well region 14 of the second conductivity type partially overlaps and coincides with the first well region 14 of the second conductivity type adjacent to the first well region 14 of the second conductivity type, and the overlapping and coinciding region is located between the adjacent first trenches 12.

As an example, the second well region 22 of the second conductivity type is also arranged within the epitaxial layer 11 of the first conductivity type between the first trench 12 and the third trench 23. The second well regions 22 of the second conductivity type are implanted simultaneously with the first well regions 14 of the second conductivity type. The second well region 22 is finally connected to the adjacent source polysilicon 16 to function as a transfer field, laterally extending the field distribution, and alleviating field crowding.

In step 5), referring to step S5 of fig. 1 and fig. 6, a first dielectric layer 15 is formed on the sidewall and the bottom of each of the first trenches 12, and a second dielectric layer 17 is formed on the sidewall and the bottom of each of the second trenches 13.

For example, a third dielectric layer 24 is formed on the sidewall and the bottom of the third trench 23 while the first dielectric layer 15 and the second dielectric layer 17 are formed.

In one example, the first dielectric layer 15 may be formed directly on the sidewall and bottom of the first trench 12, the second dielectric layer 17 may be formed directly on the sidewall and bottom of the second trench 13, and the third dielectric layer 24 may be formed directly on the sidewall and bottom of the third trench 23.

In another example, a dielectric layer may be formed prior to the sidewalls and bottom of the first trench 12, the sidewalls and bottom of the second trench 13, the sidewalls and bottom of the third trench 23, and the upper surface of the epitaxial layer 11 of the first conductivity type; and then, removing the dielectric layer on the upper surface of the epitaxial layer 11 of the first conductivity type by using an etching process or a grinding process to form the first dielectric layer 15 on the sidewall and the bottom of the first trench 12, forming the second dielectric layer 17 on the sidewall and the bottom of the second trench 13, and directly forming the third dielectric layer 24 on the sidewall and the bottom of the third trench 23.

By way of example, the first dielectric layer 15, the second dielectric layer 17, and the third dielectric layer 24 may include, but are not limited to, a silicon oxide layer.

Illustratively, the thickness of the first dielectric layer 15 is less than half of the width of the first trench 12, the thickness of the second dielectric layer 17 is less than half of the width of the second trench 13, and the thickness of the third dielectric layer 24 is less than half of the width of the third trench 23.

In step 6), referring to fig. 7 and 8, a first source polysilicon layer 16 is formed in each of the first trenches 12, and a second source polysilicon layer 18 is formed in each of the second trenches 13; the first source polysilicon layer 16 is located on the surface of the first dielectric layer 15 away from the epitaxial layer 11 of the first conductivity type, and the second source polysilicon layer 18 is located on the surface of the second dielectric layer 17 away from the epitaxial layer 11 of the first conductivity type.

As an example, while the first source polysilicon layer 16 and the second source polysilicon layer 18 are formed, the third source polysilicon layer 25 is further formed in the third trench 23, and the third source polysilicon layer 25 is located on the surface of the third dielectric layer 24 away from the epitaxial layer 11 of the first conductivity type.

In an example, a polysilicon layer may be first deposited directly in the first trench 12, the second trench 13 and the third trench 23, and an upper surface of the polysilicon layer in the first trench 12, the second trench 13 and the third trench 23 is flush with an upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 7; then, part of the third dielectric layer 24 and the polysilicon layer in the third trench 23 are etched and removed, so that the upper surface of the second dielectric layer 17 and the upper surface of the second source polysilicon layer 18 remaining in the second trench 13 are both lower than the upper surface of the first conductive epitaxial layer 11, as shown in fig. 8.

In another example, first, a polysilicon layer is formed in the first trench 12, the second trench 13, the third trench 23 and the upper surface of the epitaxial layer 11 of the first conductivity type; then, removing the polysilicon layer on the upper surface of the first conductive type epitaxial layer 11 by using an etching process or a grinding process, as shown in fig. 7; finally, etching and removing part of the third dielectric layer 24 and the polysilicon layer in the third trench 23, so that the upper surface of the second dielectric layer 17 and the upper surface of the second source polysilicon layer 18 remaining in the second trench 13 are both lower than the upper surface of the first conductive epitaxial layer 11, as shown in fig. 8.

As an example, the first source polysilicon layer 16, the second source polysilicon layer 18, and the third source polysilicon layer 25 may be formed using a physical vapor deposition process or a chemical vapor deposition process; the first source polysilicon layer 16 may fill the first trench 12, and the third source polysilicon layer 25 may fill the third trench 23; it should be noted that the first source polysilicon layer 16, the second source polysilicon layer 18 and the third source polysilicon layer 25 are preferably doped polysilicon layers to ensure the conductivity of the first source polysilicon layer 16, the second source polysilicon layer 18 and the third source polysilicon layer 25.

In step 7), referring to step S7 in fig. 1 and fig. 9 to 10, forming an insulating isolation layer 19, a gate oxide layer 20 and a gate polysilicon layer 21 in each of the second trenches 13; wherein the gate polysilicon layer 21 is located above the second source polysilicon layer 18; the gate oxide layer 20 is located on the side wall of the second trench 13 and between the gate polysilicon layer 21 and the epitaxial layer 11 of the first conductivity type; the insulating spacer 19 is located between the gate polysilicon layer 21 and the second source polysilicon layer 18.

As an example, step 7) may comprise the steps of:

7-1) forming the insulating isolation layer 19 on the upper surface of the second source polysilicon layer 18 and the upper surface of the second dielectric layer 17, as shown in fig. 9;

7-2) forming a gate oxide layer 20 on the upper side wall of the second trench 13, and forming a gate polysilicon layer 21 in the second trench 13, wherein the gate polysilicon layer 21 is located on the insulation isolation layer 19, as shown in fig. 10.

As an example, in step 7-1), the insulating isolation layer 19 may be formed by using a physical vapor deposition process or a chemical vapor deposition process; the insulating spacer layer 19 at least completely covers the second source polysilicon layer 18.

As an example, the material of the insulating isolation layer 19 may be the same as the material of the second dielectric layer 17, and preferably, in this embodiment, the material of the insulating isolation layer 19 may include, but is not limited to, a silicon oxide layer.

As an example, step 7-2) may comprise the steps of:

7-2-1) forming said gate oxide layer 20 on the upper sidewall of said second trench 13, on the upper surface of said insulating isolation layer 19 and on the upper surface of said epitaxial layer 11 of the first conductivity type;

7-2-2) forming the gate polysilicon layer 21 on the upper surface of the gate oxide layer 20, wherein the gate polysilicon layer 21 fills the second trench 13 and is partially located on the epitaxial layer 11 of the first conductivity type;

7-2-3) removing said gate polysilicon layer 21 on said epitaxial layer 11 of the first conductivity type and said gate oxide layer 20 on said epitaxial layer 11 of the first conductivity type.

As an example, in step 7-2 — 1), a physical vapor deposition process, a chemical vapor deposition process, or a thermal oxidation process may be used to form the gate oxide layer 20, where the thickness of the gate oxide layer 20 is less than half of the width of the second trench 13, so as to ensure that a space of the gate polysilicon layer 21 is reserved in the second trench 13 after the gate oxide layer 20 is formed. The gate oxide layer 20 may include, but is not limited to, a silicon oxide layer, and the thickness of the gate oxide layer 20 is smaller than that of the first dielectric layer 15.

As an example, in step 7-2-2), the gate polysilicon layer 21 may be formed by a physical vapor deposition process or a chemical vapor deposition process; it should be noted that the gate polysilicon layer 21 is preferably a doped polysilicon layer to ensure the conductivity of the gate polysilicon layer 21.

As an example, in step 7-2-3), the gate polysilicon layer 21 on the first conductivity type epitaxial layer 11 and the gate oxide layer 20 on the first conductivity type epitaxial layer 11 may be removed by an etching process or a chemical mechanical polishing process.

As an example, step 7) is followed by the following steps:

8) forming a body region 26 of the second conductivity type on the upper portion of the epitaxial layer 11 of the first conductivity type, where the body region 26 of the second conductivity type is located in the active region 101 and at the periphery of the second trench 13, as shown in fig. 11;

9) forming a first conductive source region 27 in the first conductive epitaxial layer 11, where the first conductive source region 27 is located above the second conductive body region 11 and at the periphery of the second trench 13, as shown in fig. 11;

10) forming a source electrode 28, a gate electrode (not shown) and a plurality of floating electrodes on the epitaxial layer 11 of the first conductivity type, and forming a drain electrode 29 on the lower surface of the substrate 10 of the first conductivity type, as shown in fig. 12; the source electrode 28 is connected to the body region 26 of the second conductivity type and the second source polysilicon layer 18, and the gate electrode is connected to the gate polysilicon layer 21. Each floating electrode is formed by connecting the first source polysilicon layer 16 to the surface of its adjacent well region, and each floating electrode is not connected, i.e. each floating electrode is an independent electrode and is not electrically connected to other floating electrodes. Specifically, the first source polysilicon layer 16 may be connected inward to a surface of the second well region 22 adjacent to the active region 101, or may be connected outward to a surface of the second well region 22 adjacent to the second conductivity type, which is far from the active region 101, as shown in fig. 12. As an example, in step 8), ion implantation and diffusion of the second conductivity type may be performed from above the epitaxial layer 11 of the first conductivity type using an ion implantation process to form the body region 26 of the second conductivity type.

As an example, the implantation of the ions of the first conductivity type may be performed in the formed body region 26 of the second conductivity type, so as to form the source region 27 of the first conductivity type on the upper surface of the body region 26 of the second conductivity type.

In one example, the source electrode 28 and the gate electrode (not shown) may be formed on the epitaxial layer 11 of the first conductivity type, and the drain electrode 29 may be formed on the lower surface of the substrate 10 of the first conductivity type.

In another example, the drain electrode 29 may be formed on the lower surface of the first conductive type substrate 10, and the source electrode 28 and the gate electrode may be formed on the first conductive type epitaxial layer 11.

By way of example, the source electrode 28, the gate electrode, and the drain electrode 29 may each include a metal electrode, such as a copper electrode, an aluminum electrode, a gold electrode, a silver electrode, a nickel electrode, or the like.

As an example, when the deep trench MOSFET terminal structure includes the second well region 22 of the second conductivity type and the third source polysilicon layer 25, the source electrode 28 electrically connects the body region 26 of the second conductivity type with the third source polysilicon layer 25, and the source electrode 28 electrically connects the first source polysilicon layer 16 with the second well region 22 of the second conductivity type adjacent thereto and on the side thereof away from the active region 101.

In an example, the first conductive type in each of the above steps may include an N type, and at this time, the second conductive type may include a P type.

In another example, the first conductive type in each of the above steps may include a P type, and in this case, the second conductive type may include an N type.

The utility model discloses a preparation method preparation of deep groove MOSFET terminal structure the deep groove MOSFET terminal structure through be in terminal protection area 102 the bottom of first slot 12 sets up the first well region 14 of second conductivity type is as JTE structure, makes the electric field of the bottom of first slot 12 can disperse, and vertical electric field is in terminal protection area 102 can transversely extend, improves the field effect of gathering, has improved deep groove MOSFET terminal structure's withstand voltage characteristic effectively, the withstand voltage of terminal protection area 102 is higher than the withstand voltage of active area 101, does not receive the withstand voltage restriction of active area 101, can effectively carry out the terminal protection; the thicknesses of the first dielectric layer 15 in the first trench 12, the second dielectric layer 17 in the second trench 13, and the third dielectric layer 24 in the third trench 23 can be made thinner, so that the design of the epitaxial layer 11 of the first conductivity type can be optimized, and the on-resistance of the terminal structure of the deep trench MOSFET can be effectively improved; the depths of the first trench 12, the second trench 13 and the third trench 13 do not need to be increased along with the increase of voltage, so that the process difficulty is reduced; the longitudinal cross section of the first well region 14 of the first conductivity type is circular, which can effectively reduce the width of the terminal protection region 102, thereby saving the chip area; the implantation concentration of the first well region 14 of the first conductivity type is small, so that the cost is saved; the distance between every two grooves is small, so that the area of a chip is saved; the utility model discloses a preparation method of deep groove MOSFET terminal structure is compatible in current technology, does not need extra thermal annealing, and is with low costs, and application scope is wide, safe and reliable.

Example two

With reference to fig. 12 with reference to fig. 2 to fig. 11, the present invention further provides a deep trench MOSFET terminal structure, which includes: a substrate 10 of a first conductivity type, the substrate 10 of the first conductivity type including an active region 101 and a terminal protection region 102 located at a periphery of the active region 101; an epitaxial layer 11 of the first conductivity type, the epitaxial layer 11 of the first conductivity type being located on the upper surface of the substrate 10 of the first conductivity type and covering the active region 101 and the terminal protection region 102; a plurality of first trenches 12, said first trenches 12 being located within said epitaxial layer 11 of said first conductivity type and within said termination protection region 102; a plurality of the first trenches 12 are arranged at intervals in the terminal protection region 102; the distance between the adjacent first trenches 12 is the same, or gradually increases from the active region 102 to the direction away from the active region 102; the first dielectric layer 15 covers the side wall and the bottom of each first groove 12; a first source polysilicon layer 16, wherein the first source polysilicon layer 16 is located in each first trench 12 and on the surface of the first dielectric layer 15 away from the epitaxial layer 11 of the first conductivity type; a plurality of first well regions 14 of a second conductivity type, said first well regions 14 of a second conductivity type being located within said epitaxial layer 11 of a first conductivity type and at the bottom of said first trenches 12; the first well regions 14 of the second conductivity type are overlapped and overlapped between the adjacent first trenches 12; a plurality of second trenches 13, the second trenches 13 being located within the epitaxial layer 11 of the first conductivity type and within the active region 101; the second trenches 13 are arranged at intervals in the active region 102, and the intervals between adjacent first trenches 12 are the same, and the intervals between adjacent second trenches 13 are the same as the intervals between adjacent first trenches 12; the second dielectric layers 17 are positioned on the side walls and the bottoms of the second grooves 13; a second source polysilicon layer 18, wherein the second source polysilicon layer 18 is located in each second trench 13 and is located on the surface of the second dielectric layer 17 away from the epitaxial layer 11 of the first conductivity type; a gate polysilicon layer 21, the gate polysilicon layer 21 being located in the second trench 13 and above the second source polysilicon layer 18; the gate oxide layer 20 is positioned on the side wall of each second groove 13, and is positioned between the gate polycrystalline silicon layer 20 and the epitaxial layer 11 of the first conductivity type; an insulating isolation layer 19, said insulating isolation layer 19 being located within each of said second trenches 13 and between said gate polysilicon layer 21 and said second source polysilicon layer 18.

As an example, the deep trench MOSFET termination structure further comprises at least one third trench 23, the third trench 23 being located within the epitaxial layer 11 of the first conductivity type and at the interface of the active region 101 and the termination protection region 102.

As an example, the number of the first trenches 12 formed in the terminal protection region 102 may be set according to actual needs; in fig. 4, the number of the first grooves 12 is three as an example, and in an actual example, the number of the first grooves 12 is not limited thereto. A plurality of the first trenches 12 extend in a direction from the active region 101 to away from the active region 101.

As an example, the number of the second trenches 13 formed in the active region 101 may be set according to actual needs; in fig. 4, the number of the second grooves 13 is taken as an example, and in an actual example, the number of the second grooves 13 is not limited thereto.

As an example, the number of the third grooves 23 may be set according to actual needs; in fig. 4, the number of the third grooves 23 is taken as an example, and in an actual example, the number of the third grooves 23 is not limited sequentially.

As an example, the longitudinal cross-sectional shape of the first well region 14 of the first conductivity type may be circular, but in other examples, the longitudinal cross-sectional shape of the first well region 14 of the first conductivity type may also be elliptical, and so on.

As an example, the first well regions 14 of the second conductivity type adjacent to the first trenches 12 overlap with each other, that is, each first well region 14 of the second conductivity type overlaps with the first well region 14 of the second conductivity type adjacent to it, and the overlapping area is located between the adjacent first trenches 12.

As an example, the deep trench MOSFET termination structure further comprises a second well region 22 of the second conductivity type, the second well region 22 of the second conductivity type being located within the epitaxial layer 11 of the first conductivity type and between adjacent ones of the first trenches 12.

As an example, the second well region 22 of the second conductivity type is also located within the epitaxial layer 11 of the first conductivity type between the first trench 12 and the third trench 23.

As an example, the first well region 14 of the second conductivity type and the second well region 22 of the second conductivity type may be formed by using the same ion implantation process, in the ion implantation process, the implantation energy may range from 10KeV to 200KeV, and the implantation dose may range from 10KeV to 200KeV¹²Per square centimeter to 10¹⁶One per square centimeter.

Illustratively, the deep trench MOSFET terminal structure further comprises a third dielectric layer 24, wherein the third dielectric layer 24 covers the sidewall and the bottom of the third trench 23.

Illustratively, the first dielectric layer 15 is located in each of the first trenches 12, the second dielectric layer 17 is located in each of the second trenches 13, and the third dielectric layer 24 is located in each of the third trenches 23.

As an example, the deep trench MOSFET terminal structure further includes a third source polysilicon layer 25, and the third source polysilicon layer 25 is located in the third trench 23 and on the surface of the third dielectric layer 24 away from the epitaxial layer 11 of the first conductivity type.

As an example, the first source polysilicon layer 16, the second source polysilicon layer 18, and the third source polysilicon layer 25 are preferably doped polysilicon layers to ensure the conductivity of the first source polysilicon layer 16, the second source polysilicon layer 18, and the third source polysilicon layer 25.

Illustratively, the first source polysilicon layer 16 is located in each of the first trenches 12, the second source polysilicon layer 18 is located in each of the second trenches 13, and the third source polysilicon layer 25 is located in each of the third trenches 23.

As an example, the insulating isolation layer 19 covers at least the second source polysilicon layer 18 completely.

As an example, the gate polysilicon layer 21 is preferably a doped polysilicon layer to ensure conductivity of the gate polysilicon layer 21.

As an example, the deep trench MOSFET termination structure further comprises: a body region 26 of a second conductivity type, said body region 26 of a second conductivity type being located within said epitaxial layer 11 of a first conductivity type and being located at the periphery of said gate oxide layer 20; a source region 27 of the first conductivity type, said source region 27 of the first conductivity type being located within said epitaxial layer 11 of the first conductivity type and at the periphery of said gate oxide layer 20 and above said body region 26 of the second conductivity type; a gate electrode (not shown) connected to the gate polysilicon layer 21; a source electrode 28, the source electrode 28 being connected to the body region 26 of the second conductivity type and the second source polysilicon layer 18; a drain electrode 29, the drain electrode 29 being located on a lower surface of the first conductive type substrate 10.

In an example, the first conductive type may include an N-type, and at this time, the second conductive type may include a P-type.

In another example, the first conductive type described above may include a P type, and at this time, the second conductive type may include an N type.

The utility model discloses a deep trench MOSFET terminal structure through be in terminal protection area 102 the bottom of first slot 12 sets up the first well region 14 of second conductivity type is as JTE structure, makes the electric field of the bottom of first slot 12 can disperse, and vertical electric field is in terminal protection area 102 can transversely extend, has improved deep trench MOSFET terminal structure's withstand voltage characteristic effectively, the withstand voltage of terminal protection area 102 is higher than the withstand voltage of active area 101, does not receive the withstand voltage restriction of active area 101, can effectively carry out the terminal protection; the thicknesses of the first dielectric layer 15 in the first trench 12, the second dielectric layer 17 in the second trench 13, and the third dielectric layer 24 in the third trench 23 can be made thinner, so that the design of the epitaxial layer 11 of the first conductivity type can be optimized, and the on-resistance of the terminal structure of the deep trench MOSFET can be effectively improved; the depths of the first trench 12, the second trench 13 and the third trench 13 do not need to be increased along with the increase of voltage, so that the process difficulty is reduced; the longitudinal cross section of the first well region 14 of the first conductivity type is circular, which can effectively reduce the width of the terminal protection region 102, thereby saving the chip area; the implantation concentration of the first well region 14 of the first conductivity type is small, so that the cost is saved; the distance between every two grooves is small, so that the area of a chip is saved; the utility model discloses a preparation method of deep groove MOSFET terminal structure is compatible in current technology, does not need extra thermal annealing, and is with low costs, and application scope is wide, safe and reliable.

EXAMPLE III

Referring to fig. 13 to 17 in conjunction with fig. 1 to 12, the present invention further provides a method for manufacturing a deep trench MOSFET terminal structure, the method for manufacturing the deep trench MOSFET terminal structure in this embodiment is substantially the same as the method for manufacturing the deep trench MOSFET terminal structure in the first embodiment, and the difference between the steps is the difference between step 6) and step 7), specifically: in the first embodiment, both the upper surface of the second dielectric layer 17 obtained in step 6) and the upper surface of the second source polysilicon layer 18 are lower than the upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 8, while the upper surface of the second dielectric layer 17 obtained in step 6) in this embodiment is lower than the upper surface of the epitaxial layer 11 of the first conductivity type, and the upper surface of the second source polysilicon layer 18 is flush with the upper surface of the epitaxial layer 11 of the first conductivity type, as shown in fig. 13; the gate polysilicon layer 21, the gate oxide layer 20 and the insulating isolation layer 19 obtained in step 7) of the first embodiment are all located above the second source polysilicon layer 18, as shown in fig. 10, while the gate polysilicon layer 21, the gate oxide layer 20 and the insulating isolation layer 19 obtained in step 7) of the present embodiment are all located on the upper periphery of the second source polysilicon layer 18, as shown in fig. 15.

As an example, steps 1) to 5) of the method for manufacturing a deep trench MOSFET terminal structure in the present embodiment are the same as steps 1) to 5) of the method for manufacturing a deep trench MOSFET terminal structure in the first embodiment, and will not be described again here; a schematic cross-sectional structure of the structure obtained in step 8) and step 9) of the method for manufacturing a deep trench MOSFET terminal structure in the present embodiment is shown in fig. 16, and a schematic cross-sectional structure of the structure obtained in step 10) of the method for manufacturing a deep trench MOSFET terminal structure in the present embodiment is shown in fig. 17; steps 8) to 10) of the method for fabricating a deep trench MOSFET terminal structure in this embodiment are the same as steps 8) to 10) of the method for fabricating a deep trench MOSFET terminal structure in the first embodiment, and will not be described in detail herein.

Example four

With reference to fig. 17 with reference to fig. 2 to fig. 12, the present invention further provides a deep trench MOSFET terminal structure, the deep trench MOSFET terminal structure in the present embodiment is substantially the same as the deep trench MOSFET terminal structure in the second embodiment, and the difference between the two structures is: in the first embodiment, the upper surface of the second dielectric layer 17 and the upper surface of the second source polysilicon layer 18 are lower than the upper surface of the epitaxial layer 11 of the first conductivity type, and the gate polysilicon layer 21, the gate oxide layer 20 and the insulating isolation layer 19 are all located above the second source polysilicon layer 18, as shown in fig. 12; in this embodiment, the upper surface of the second dielectric layer 17 is lower than the upper surface of the first conductive epitaxial layer 11, the upper surface of the second source polysilicon layer 18 is flush with the upper surface of the first conductive epitaxial layer 11, and the gate polysilicon layer 21, the gate oxide layer 20 and the insulating isolation layer 19 are all located on the upper periphery of the second source polysilicon layer 18, as shown in fig. 17.

EXAMPLE five

Referring to fig. 18 to 20 in conjunction with fig. 1 to 12, the present invention further provides a method for manufacturing a deep trench MOSFET terminal structure, the method for manufacturing the deep trench MOSFET terminal structure in this embodiment is substantially the same as the method for manufacturing the deep trench MOSFET terminal structure in the first embodiment, and the difference between the two methods is: in the first embodiment, in each of the first well regions 14 of the second conductivity type formed in step 4), the adjacent first well regions 14 of the second conductivity type overlap and coincide with the adjacent first trenches 12; in this embodiment, in each of the first well regions 14 of the second conductivity type formed in step 4), the first well region 14 of the second conductivity type at the bottom of the first trench 12 farthest from the active region 101 has a spacing with the first well region 14 of the second conductivity type adjacent thereto, and the rest of the first well regions 14 of the second conductivity type adjacent to the first trench 12 partially overlap with each other, and in this embodiment, not all the first well regions 14 of the second conductivity type partially overlap with the first well regions 14 of the second conductivity type adjacent thereto.

EXAMPLE six

Referring to fig. 20 in conjunction with fig. 12, the present invention further provides a deep trench MOSFET terminal structure, the deep trench MOSFET terminal structure in this embodiment is substantially the same as the deep trench MOSFET terminal structure in the second embodiment, and the difference between the two is as follows: in the first embodiment, in each first well region 14 of the second conductivity type, the adjacent first well regions 14 of the second conductivity type are overlapped with the adjacent first trenches 12; in this embodiment, in each of the first well regions 14 of the second conductivity type, the first well region 14 of the second conductivity type at the bottom of the first trench 12 farthest from the active region 101 has a spacing with the adjacent first well regions 14 of the second conductivity type, and the rest of the adjacent first well regions 14 of the second conductivity type partially overlap with the adjacent first trenches 12, or in this embodiment, not all of the first well regions 14 of the second conductivity type partially overlap with the adjacent first well regions 14 of the second conductivity type.

EXAMPLE seven

Referring to fig. 17 and fig. 21, the present invention further provides a method for manufacturing a deep trench MOSFET terminal structure, where the method for manufacturing the deep trench MOSFET terminal structure in this embodiment is substantially the same as the method for manufacturing the deep trench MOSFET terminal structure in the third embodiment, and the difference between the two methods is as follows: in the third embodiment, in each of the second conductivity-type first well regions 14 formed in step 4), the adjacent second conductivity-type first well regions 14 and the adjacent first trenches 12 are overlapped and overlapped partially; in this embodiment, in each of the first well regions 14 of the second conductivity type formed in step 4), the first well region 14 of the second conductivity type at the bottom of the first trench 12 farthest from the active region 101 has a spacing with the first well region 14 of the second conductivity type adjacent thereto, and the rest of the first well regions 14 of the second conductivity type adjacent to the first trench 12 partially overlap with each other, and in this embodiment, not all the first well regions 14 of the second conductivity type partially overlap with the first well regions 14 of the second conductivity type adjacent thereto.

Example eight

Referring to fig. 17 and fig. 21, the present invention further provides a deep trench MOSFET terminal structure, the deep trench MOSFET terminal structure in this embodiment is substantially the same as the deep trench MOSFET terminal structure in the fourth embodiment, and the difference between the terminal structures is as follows: in the fourth embodiment, in each of the first well regions 14 of the second conductivity type, the adjacent first well regions 14 of the second conductivity type are overlapped with the adjacent first trenches 12; in this embodiment, in each of the first well regions 14 of the second conductivity type, the first well region 14 of the second conductivity type at the bottom of the first trench 12 farthest from the active region 101 has a spacing with the adjacent first well regions 14 of the second conductivity type, and the rest of the adjacent first well regions 14 of the second conductivity type partially overlap with the adjacent first trenches 12, or in this embodiment, not all of the first well regions 14 of the second conductivity type partially overlap with the adjacent first well regions 14 of the second conductivity type.

To sum up, the utility model provides a deep groove MOSFET terminal structure and preparation method thereof, deep groove MOSFET terminal structure includes: the semiconductor device comprises a substrate of a first conduction type, a first electrode and a second electrode, wherein the substrate of the first conduction type comprises an active area and a terminal protection area positioned on the periphery of the active area; the epitaxial layer of the first conduction type is positioned on the upper surface of the substrate of the first conduction type and covers the active region and the terminal protection region; the first groove is positioned in the epitaxial layer of the first conduction type and positioned in the terminal protection area; the first dielectric layer covers the side wall and the bottom of the first groove; the first source electrode polycrystalline silicon layer is positioned in the first groove and positioned on the surface of the first dielectric layer far away from the epitaxial layer of the first conduction type; the first well region of the second conduction type is positioned in the epitaxial layer of the first conduction type and positioned at the bottom of the first groove; a second trench located within the epitaxial layer of the first conductivity type and within the active region; the second dielectric layer is positioned on the side wall and the bottom of the second groove; the second source electrode polycrystalline silicon layer is positioned in the second groove and positioned on the surface, far away from the first conductive type epitaxial layer, of the second dielectric layer; the grid polycrystalline silicon layer is positioned in the second groove and positioned above the second source polycrystalline silicon layer or positioned on the periphery of the upper part of the second source polycrystalline silicon layer; the gate oxide layer is positioned on the side wall of the second groove and is positioned between the gate polycrystalline silicon layer and the epitaxial layer of the first conduction type; and the insulation isolation layer is positioned in the second groove and is positioned between the grid polycrystalline silicon layer and the second source polycrystalline silicon layer. The utility model discloses a deep groove MOSFET terminal structure is through setting up the first well region of second conductivity type as JTE structure in the first trench bottom of terminal protection area for the electric field of first trench bottom can disperse, and the vertical electric field can transversely extend at the terminal protection area, has improved deep groove MOSFET terminal structure's withstand voltage characteristic effectively, and the withstand voltage of terminal protection area is higher than the withstand voltage of active area, does not receive the withstand voltage restriction in active area, can effectively carry out terminal protection; the utility model discloses a thickness of the first dielectric layer that is arranged in the first slot, the second dielectric layer that is arranged in the second slot and the third dielectric layer that is arranged in the third slot in the deep trench MOSFET terminal structure can be made thinner, thereby optimizing the design of the epitaxial layer of the first conductivity type and effectively improving the on-resistance of the deep trench MOSFET terminal structure; the depth of the first groove, the second groove and the third groove in the deep groove MOSFET terminal structure of the utility model is not required to be increased along with the rise of voltage, thereby reducing the process difficulty; the longitudinal section of the first well region of the first conduction type in the deep groove MOSFET terminal structure is circular, so that the width of a terminal protection region can be effectively reduced, and the chip area is saved; in the deep trench MOSFET terminal structure of the utility model, the injection concentration of the first well region of the first conductive type is smaller, thereby saving the cost; the distance between every two grooves is small, so that the area of a chip is saved; the utility model discloses a preparation method of deep groove MOSFET terminal structure is compatible in current technology, does not need extra thermal annealing, and is with low costs, and application scope is wide, safe and reliable.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A deep trench MOSFET terminal structure comprising:

2. The deep trench MOSFET termination structure of claim 1, wherein: the first well region of the second conduction type at the bottom of the first trench farthest from the active region has a spacing with the first well region of the second conduction type adjacent to the first well region of the second conduction type, and the rest of the first well regions of the second conduction type adjacent to the first trench are overlapped and overlapped partially.

3. The deep trench MOSFET termination structure of claim 1, wherein: the deep trench MOSFET terminal structure further comprises a second well region of a second conductivity type, wherein the second well region of the second conductivity type is located in the epitaxial layer of the first conductivity type and located between the adjacent first trenches.

4. The deep trench MOSFET termination structure of claim 1, wherein: the deep trench MOSFET terminal structure further comprises:

5. The deep trench MOSFET termination structure of claim 1, wherein: the longitudinal cross-sectional shape of the first well region of the second conductivity type includes a circular shape.

6. The deep trench MOSFET termination structure of claim 1, wherein: the first conductivity type comprises an N-type and the second conductivity type comprises a P-type, or the first conductivity type comprises a P-type and the second conductivity type comprises an N-type.