CN104576730A - Superjunction device and manufacturing method thereof - Google Patents

Superjunction device and manufacturing method thereof Download PDF

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Publication number
CN104576730A
CN104576730A CN201310484725.8A CN201310484725A CN104576730A CN 104576730 A CN104576730 A CN 104576730A CN 201310484725 A CN201310484725 A CN 201310484725A CN 104576730 A CN104576730 A CN 104576730A
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thin layer
type thin
type
layer
resistivity
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CN104576730B (en
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肖胜安
雷海波
姚亮
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

Abstract

The invention discloses a superjunction device. A current flowing area comprises a plurality of N type thin layers and P type thin layers, the N type thin layers and the P type thin layers are alternately arranged, a plurality of grooves are formed in a silicon substrate, and each N type thin layer comprises a first N type thin layer and a second N type thin layer; each first N type thin layer comprises a silicon substrate bottom thin layer between adjacent grooves, each second N type thin layer has lower electrical resistivity, electric charges of at least the second N type thin layers and the adjacent P type thin layers are balanced, electric charges of at least part of N type thin layers and the adjacent P type thin layers are not balanced, and N type areas comprising back ion injection areas are formed at bottoms of the N type thin layers and P type thin layers. The invention further discloses a manufacturing method of the superjunction device. According to the superjunction device and the manufacturing method of the superjunction device, the manufacturing cost can be minimized, and meanwhile, specific on-state resistance of the device and softness coefficient of reverse recovery of the device in a turn-off process can be optimized.

Description

Super-junction device and manufacture method thereof
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of super-junction device; The invention still further relates to a kind of manufacture method of super-junction device.
Background technology
Super junction MOSFET adopts new structure of voltage-sustaining layer, the a series of P type semiconductor thin layer that is alternately arranged and N type semiconductor thin layer is utilized to come just described P type semiconductor thin layer and N type semiconductor thin layer to be exhausted at the lower voltage in the off state, realize electric charge mutually to compensate, thus make P type semiconductor thin layer and N type semiconductor thin layer can realize high puncture voltage under high-dopant concentration, thus obtain low on-resistance and high-breakdown-voltage simultaneously, break traditions power MOSFET theoretical limit.In US Patent No. 5216275, the above P type semiconductor thin layer be alternately arranged is connected with N+ substrate with N type semiconductor thin layer; In US Patent No. 6630698B1, middle P type semiconductor thin layer and N type semiconductor thin layer and N+ substrate can have the interval being greater than 0.
In prior art, the formation one of P type semiconductor thin layer and N type semiconductor thin layer then carries out photoetching and injection by epitaxial growth, repeatedly this process obtains P type semiconductor thin layer and the N type semiconductor thin layer of the thickness needed repeatedly, this technique is in the MOSFET of more than 600V, generally need repetition more than 5 times, production cost and the production cycle long.Another kind be by a kind of type of a secondary growth need the extension of thickness after, carry out the etching of groove, insert the silicon of opposite types afterwards in the trench; Although this method difficulty is large, there is simplification of flowsheet, improve the effect of stability; After adopting groove structure, namely in the P type semiconductor thin layer be alternately arranged due to P/N thin layer and N type semiconductor thin layer, P type semiconductor thin layer and the doping content of N type semiconductor thin layer on longitudinal direction are easy to control, and in the thin layer not having repeatedly epitaxy technique to cause, P type semiconductor thin layer and N type semiconductor thin layer or the doping content of one of them change in the vertical thus bring additional longitudinal electric field, ensure that the leakage current characteristic that device can obtain and high puncture voltage.
In super junction technique, owing to have employed P/N thin layer alternately, in the body of super-junction device, diode and diode such as 50 volts of Vds under lower reversed bias voltage of being formed between P type semiconductor thin layer and N type semiconductor thin layer will exhaust P type semiconductor thin layer and N type semiconductor thin layer fall completely, this makes this diode have very hard reverse recovery characteristic, this hard reverse recovery characteristic causes the restoring current of device sharply to change, in Reverse recovery, fluctuation is violent, cause the magnetotelluric noise (EMI NOISE) in circuit, impact is brought on the work of other device in circuit, in this, super-junction device is not as conventional MOSFET element, because exhausting of the MOSFET element N-drift region of routine expands along with the increase of voltage (Vds) always, reverse recovery characteristic is softer.
In process choice, repeatedly epitaxial growth and photoetching, injection technology have complexity, the manufacturing cycle is long and cost is high problem, in trench fill process, to need before trench process deposition thickness on the substrate of high-concentration dopant to reach the epitaxial loayer of some tens of pm, too increase the cost of technique.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of super-junction device, and manufacturing cost can be made to minimize, simultaneously can also the conduction resistance of optimised devices and the softness coefficient (SOFTNESS) of the Reverse recovery of device in turn off process.For this reason, the present invention also provides a kind of manufacture method of super-junction device.
For solving the problems of the technologies described above, super-junction device provided by the invention is formed in N-type silicon substrate, and the zone line of described super-junction device is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer.
Described silicon substrate is formed with multiple groove, and each described N-type thin layer is made up of the first N-type thin layer and the second N-type thin layer all respectively; Described first N-type thin layer is made up of the silicon substrate thin layer between described groove, described second N-type thin layer forms by be filled in described groove and to be positioned at described first N-type thin layer both sides first N-type silicon epitaxy layer, described P type thin layer is made up of the second P-type silicon epitaxial loayer be filled in described groove, and the described second N-type thin layer of each described P type thin layer and its both sides contacts and filled completely by the described groove of correspondence.
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms.
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer.
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer.
The N-type region be made up of backside particulate injection region is formed bottom described N-type thin layer and described P type thin layer.
Further improvement is, described in described current flowing district, the width of N-type thin layer is all identical, and all comprises described high-resistivity portions in the described first N-type thin layer of whole described N-type thin layer.
Or, described N-type thin layer in described current flowing district comprises two or more width, the described N-type thin layer of Breadth Maximum comprises described high-resistivity portions, and the described N-type thin layer that width is less than described Breadth Maximum comprises or do not comprise described high-resistivity portions; The described N-type thin layer not comprising described high-resistivity portions has feature: diffuse into the N-type impurity described first N-type thin layer from described second N-type thin layer and spread all in the width range of whole described first N-type thin layer, and the resistivity of described first N-type thin layer zone line is lower than the resistivity of described silicon substrate.
Further improvement is, described N-type region is made up of ground floor N-type region and second layer N-type region, described ground floor N-type region is bottom described N-type thin layer and described P type thin layer, described second layer N-type region is near the back side of described silicon substrate, the doping content of described second layer N-type region is greater than the doping content of described ground floor N-type region, the metal at the back side that the doping content of described second layer N-type region meets and is formed at described silicon substrate forms the condition of ohmic contact, and described first N-type region is as the resilient coating of described super-junction device.
Further improvement is, the thickness of described N-type region is 0.5 micron ~ 5 microns.
Further improvement is, the thickness of described ground floor N-type region is 3 microns ~ 50 microns, and the thickness of described second layer N-type region is 0.5 micron ~ 3 microns.
Further improvement is, is also formed with the p type island region be made up of backside particulate injection region at the back side of described N-type region.
Further improvement is, the described N-type thin layer comprising described high-resistivity portions in described current flowing district is distributed in one or more regions in described current flowing district.
Further improvement is, the distributed areas of described N-type thin layer comprising described high-resistivity portions in described current flowing district and the region of described terminal protection structure do not adjoin.
Further improvement is, the region comprising the distributed areas of the described N-type thin layer of described high-resistivity portions and the grid metal electrode figure of described super-junction device in described current flowing district does not adjoin.
For solving the problems of the technologies described above, the described super-junction device of the manufacture method of super-junction device provided by the invention is super junction trench gate mosfet device, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively.
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains.
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding.
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms.
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer.
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer.
Step 5, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district.
Step 6, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside.
Step 7, form P trap at the top of described N-type thin layer and described P type thin layer; The degree of depth of described gate groove is greater than the degree of depth of described P trap, described polysilicon gate cover described P trap from the side and the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel.
Step 8, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region.
Step 9, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact.
Step 10, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively.
Step 11, carry out thinning from the back side to described silicon substrate.
Step 12, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer.
Step 13, the ion of described N-type region to be activated.
Step 14, carry out back face metalization formed drain electrode.
Further improvement is, the distance of the described trench bottom surfaces formed in the backside surface of the described silicon substrate after step 11 is thinning and step 2 is 0.5 micron ~ 40 microns.
Further improvement is, at least comprises a laser annealing in the activation technology in step 13.
Further improvement is, carries out before the first silicon dioxide layer described in the deposit that the technique of the described P trap of the formation in step 7 advances to step one.
For solving the problems of the technologies described above, the described super-junction device of the manufacture method of super-junction device provided by the invention is super junction flat-grid MOSFET component, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively.
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains.
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding.
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms.
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer.
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer.
Step 5, form P trap at the top of each described P type thin layer, each described P trap also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap is N-type conducting district.
Step 6, successively deposit gate dielectric layer and polysilicon gate, adopt lithographic etch process to etch described polysilicon gate and described gate dielectric layer successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer after etching and described polysilicon gate; Described polysilicon gate cover described N-type thin layer and part described P trap from top and the described P trap that covers by described polysilicon gate for the formation of lateral channel.
Step 7, carry out N+ ion implantation formed source region; Described source region is formed at described P trap top and and described polysilicon gate autoregistration.
Step 8, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact.
Step 9, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively.
Step 10, carry out thinning from the back side to described silicon substrate.
Step 11, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer.
Step 12, the ion of described N-type region to be activated.
Step 13, carry out back face metalization formed drain electrode.
Further improvement is, the distance of the described trench bottom surfaces formed in the backside surface of the described silicon substrate after step 10 is thinning and step 2 is 0.5 micron ~ 40 microns.
Further improvement is, at least comprises a laser annealing in the activation technology in step 12.
Further improvement is, carries out before the first silicon dioxide layer described in the deposit that the technique of the described P trap of the formation in step 5 advances to step one.
Further improvement is, after the described P trap of step 5 is formed, before the described gate dielectric layer deposit of step 6, is also included in the step of carrying out N-type ion implantation in described N-type conducting district.
For solving the problems of the technologies described above, the described super-junction device of the manufacture method of super-junction device provided by the invention is super junction trench gate IGBT device, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively.
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains.
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding.
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms.
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer.
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, the charge balance of described N-type thin layer and its contiguous described P type thin layer or imbalance, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, the first N-type thin layer of the complete having lateral depletion of whole described N-type thin layer or described N-type thin layer is not by the complete having lateral depletion of described P type thin layer.
Step 5, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district.
Step 6, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside.
Step 7, form P trap at the top of described N-type thin layer and described P type thin layer; The degree of depth of described gate groove is greater than the degree of depth of described P trap, described polysilicon gate cover described P trap from the side and the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel.
Step 8, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region.
Step 9, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact.
Step 10, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively.
Step 11, carry out thinning from the back side to described silicon substrate.
Step 12, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer; Carry out the formation p type island region, the back side that backside particulate is infused in described N-type region.
Step 13, the ion of described N-type region and described p type island region to be activated.
Step 14, carry out back face metalization formed drain electrode.
For solving the problems of the technologies described above, the described super-junction device of the manufacture method of super-junction device provided by the invention is super junction flat-grid MOSFET component, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively.
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains.
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding.
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms.
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer.
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer.
Step 5, form P trap at the top of each described P type thin layer, each described P trap also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap is N-type conducting district.
Step 6, successively deposit gate dielectric layer and polysilicon gate, adopt lithographic etch process to etch described polysilicon gate and described gate dielectric layer successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer after etching and described polysilicon gate; Described polysilicon gate cover described N-type thin layer and part described P trap from top and the described P trap that covers by described polysilicon gate for the formation of lateral channel.
Step 7, carry out N+ ion implantation formed source region; Described source region is formed at described P trap top and and described polysilicon gate autoregistration.
Step 8, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact.
Step 9, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively.
Step 10, carry out thinning from the back side to described silicon substrate.
Step 11, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer; Carry out the formation p type island region, the back side that backside particulate is infused in described N-type region.
Step 12, the ion of described N-type region and described p type island region to be activated.
Step 13, carry out back face metalization formed drain electrode.
The groove of the P/N thin layer of super-junction device of the present invention is formed directly on silicon substrate, does not need on a silicon substrate to form epitaxial loayer, so the present invention can make minimizing of the manufacturing cost of device.Super-junction device of the present invention, by adopting thinner silicon substrate film, forms very thin N-type region in the bottom of P/N thin layer simultaneously, can reduce the conduction resistance of device and reduce device thermal resistance, improves reliability.The N-type thin layer of the P/N thin layer of super-junction device of the present invention is made up of silicon substrate coating portion i.e. the first N-type thin layer and extension filling part i.e. second N-type thin layer two parts, wherein silicon substrate coating portion has higher resistivity, extension filling part has lower resistivity, silicon substrate coating portion can not by the complete having lateral depletion of P type thin layer when reverse bias, like this when reversed bias voltage increases, longitudinally can be exhausted silicon substrate coating portion by the P trap that is positioned at N-type thin layer top and the degree of depth of longitudinal depletion region increases with the increase of reverse biased, so hard reverse recovery characteristic deliquescing that can make device, thus the reverse recovery characteristic of device can be improved, reduce restoring current to impact.So the present invention can better optimize low conduction resistance and the SOFTNESS of device in turn off process, the optimum balance of conduction resistance and resistance to rush of current can be realized.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing super-junction device vertical view one;
Fig. 2 is existing super-junction device vertical view two;
Fig. 3 is the vertical view in the current flowing district of the embodiment of the present invention one super-junction device;
Fig. 4 is the profile of the embodiment of the present invention one super-junction device;
Fig. 5-Fig. 9 is the device profile map in each step of manufacture method of the embodiment of the present invention one super-junction device;
Figure 10 A-Figure 10 B is the genesis analysis figure of the impurity concentration of the N-type region of the embodiment of the present invention one super-junction device;
Figure 11 is the profile of the embodiment of the present invention two super-junction device;
Figure 12 A-Figure 12 C is the genesis analysis figure of the impurity concentration of the N-type region of the embodiment of the present invention two super-junction device;
Figure 13 is the profile of the embodiment of the present invention three super-junction device;
Figure 14 be the embodiment of the present invention three super-junction device P/N thin layer bottom to the genesis analysis figure of impurity concentration at the silicon substrate back side;
Figure 15 is the vertical view in the current flowing district of the embodiment of the present invention four super-junction device;
Figure 16 is the profile of the embodiment of the present invention four super-junction device;
Figure 17 is the profile of the embodiment of the present invention five super-junction device;
Figure 18 is the vertical view in the current flowing district of the embodiment of the present invention six super-junction device;
Figure 19 is the profile of the embodiment of the present invention seven super-junction device.
Embodiment
As shown in Figure 1, be the vertical view one of existing super-junction device.On vertical view, the embodiment of the present invention can be divided into 1st district, 2nd district and 3rd district.1st district is the zone line of super-junction device is current flowing district, described current flowing district comprises the territory, p type island region 25 and N-type region territory that are alternately arranged, and namely territory, described p type island region 25 is also formed at the P type thin layer in described current flowing district, namely described N-type region territory is also formed at N-type thin layer in described current flowing district; Can arrive drain electrode by source electrode through raceway groove by N-type region territory at described current flowing district electric current, and territory, described p type island region 25 bears voltage under reverse blocking state together with formation depletion region, described N-type region territory.2nd district and 3rd district are the terminal protection structure region of described super-junction device; when break-over of device, described terminal protection structure does not provide electric current, reverse-biased for this voltage of voltage born from the surface in 1 periphery, district unit and territory, p type island region, periphery 25 to device outer-most end surface substrate be lateral voltage and from 1 periphery, district cell surface to this voltage of voltage of substrate be longitudinal voliage.Having in 2nd district at least one P type ring 24, Fig. 1 is a P type ring 24, and the general P type backgate with 1st district of this P type ring 24 and P trap link together; There is the field plate dielectric film with certain inclination angle in 2nd district, also having in 2nd district for slowing down surface field polycrystalline field plate jumpy sheet and Metal field plate, and P type post 23; In 2nd district, also described Metal field plate can not be set.3rd district bear district by P type post 23 and the voltage that the N-type post be made up of N-type silicon epitaxy layer is alternately formed, it there is deielectric-coating, namely described P type post 23 is also formed at the P type thin layer in described terminal protection structure, namely described N-type post is also formed at N-type thin layer in described terminal protection structure; There is Metal field plate in 3rd district, in 3rd district, also described Metal field plate can not be set; P type ring 24 can be had in 3rd district also can not have, have the P type ring at this place during P type ring 24 to be not connected with the P type backgate in current flowing district (suspension) that be connected; Have channel cutoff ring 21 in the outermost end in 3rd district, described channel cutoff ring 21 adds medium formed thereon again by N+ injection region or N+ injection region or medium adds that metal is formed; Additional little P type post 22 can be had at four angles place, in order to better to realize charge balance at described P type post 23.As seen from Figure 1, the cellular construction in described current flowing district and territory, described p type island region 25 and N-type region territory are all strip structure; Described terminal protection structure is surrounded on the periphery in described current flowing district and described P type ring 24, described P type post 23 and described channel cutoff ring 21 are all tetragonal circulus, also can have the circulus of circular arc in tetragonal corner.
As shown in Figure 2, it is the vertical view two of existing super-junction device, structure difference is as shown in Figure 1, cellular construction in described current flowing district and territory, described p type island region 25 and N-type region territory are all tetragonal structure, namely by territory, tetragonal described p type island region 25 and N-type region territory in the two-dimensional direction proper alignment form the cell array in described current flowing district.Territory, described p type island region 25 and N-type region territory also can be hexagon, octagon and other shape, and the arrangement mode in territory, described p type island region 25 and N-type region territory also can at X, and Y-direction carries out certain dislocation; As long as ensure that whole arrangement is by certain rule, carry out repeating just passable.
The additional little P type post 22 of corner in Fig. 1 and Fig. 2, can design according to the optimized requirement of local charge balance, if the width of described P type post 23 is a, distance between described P type post 23 and described P type post 23 is also a, and so described little P type post 22 can adopt the length of side to be the square P nibs of 0.3 ~ 0.5a.
In existing super junction MOSFET element; MOSFET element unit is all formed above the N-type thin layer in current flowing district; the N-type thin layer in current flowing district, P type thin layer and MOSFET element unit repeat completely; the device being such as 600V and BVds-600V to a puncture voltage is example: the N+ silicon substrate of device is uniform; resistivity is 0.001-0.003 ohmcm; on N+ substrate, deposition thickness is 45 microns, and resistivity is the N-type silicon epitaxial layers of the Uniform Doped of 1 ohmcm ~ 5 ohmcm or the N-type silicon epitaxial layers of longitudinally impurity concentration change; Form groove afterwards, fill P type silicon epitaxial layers in the trench, P type silicon epitaxial layers can be longitudinally Uniform Doped, also can be longitudinally change doping, the P type thin layer leaving N-type thin layer and extension filling after such etching groove just constitutes the P-N thin layer replaced of super-junction device by P type thin layer and N-type thin layer; In current flowing district, except the region close to device terminal, may because Terminal Design and technique cause outside some differences, all device cells are consistent, and in the horizontal, the structure of P-N thin layer repeats completely.
As shown in Figure 3, be the vertical view in current flowing district of the embodiment of the present invention one super-junction device; As shown in Figure 4, be the profile of the embodiment of the present invention one super-junction device.The embodiment of the present invention one super-junction device is formed in N-type silicon substrate 1, and the zone line of described super-junction device is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer 4.As can be seen from Figure 3, described P type thin layer 4 corresponds to the thin layer between B1B2, B3B4, B5B6, B7B8 etc., described N-type thin layer corresponds to the thin layer between B0B1, B2B3, B4B5, B6B7, B8B9 etc., can find out that described P type thin layer 4 and described N-type thin layer are all strip structure and are alternately arranged.
Described silicon substrate 1 adopts the N-type doped substrate of higher electric resistivity.
Described silicon substrate 1 is formed with multiple groove.
Each described N-type thin layer is made up of the first N-type thin layer 3 and the second N-type thin layer 3a all respectively; Described first N-type thin layer 3 is made up of the silicon substrate thin layer between described groove, described second N-type thin layer 3a forms by be filled in described groove and to be positioned at described first N-type thin layer 3 both sides first N-type silicon epitaxy layer, described P type thin layer 4 is made up of the second P-type silicon epitaxial loayer be filled in described groove, and the described second N-type thin layer 3a of each described P type thin layer 4 and its both sides contacts and filled completely by the described groove of correspondence.
The resistivity of described second N-type thin layer 3a is lower than the resistivity of described silicon substrate 1, by the N-type impurity of of described silicon substrate 1 itself, the N-type doping of described first N-type thin layer 3 adds that the N-type impurity diffused into from described second N-type thin layer 3a forms.
The described first N-type thin layer 3 of part or all of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer 3 from the described second N-type thin layer 3a N-type impurity diffused into described first N-type thin layer 3, the resistivity of described silicon substrate 1 is more than 10 times of the resistivity of described second N-type thin layer 3a, the resistivity of the zone line of described first N-type thin layer 3 equals the resistivity of described silicon substrate 1, and form described high-resistivity portions by the zone line of described first N-type thin layer 3.
Be preferably, described in described current flowing district, the width of N-type thin layer is all identical, and all comprises described high-resistivity portions in the described first N-type thin layer 3 of whole described N-type thin layer.Or, described N-type thin layer in described current flowing district comprises two or more width, the described N-type thin layer of Breadth Maximum comprises described high-resistivity portions, and the described N-type thin layer that width is less than described Breadth Maximum comprises or do not comprise described high-resistivity portions; The described N-type thin layer not comprising described high-resistivity portions has feature: diffuse into the N-type impurity described first N-type thin layer 3 from described second N-type thin layer 3a and spread all in the width range of whole described first N-type thin layer 3, and the resistivity of described first N-type thin layer 3 zone line is lower than the resistivity of described silicon substrate 1.
The charge balance of at least described second N-type thin layer 3a and its contiguous described P type thin layer 4, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer 4, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer 4.And for not comprising the described N-type thin layer of described high-resistivity portions, this part N-type thin layer can balance with its contiguous described P type thin layer 4, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, the described N-type thin layer not comprising described high-resistivity portions can by the complete having lateral depletion of described P type thin layer 4.
The N-type region 2 be made up of backside particulate injection region is formed bottom described N-type thin layer and described P type thin layer 4.
During the break-over of device of the embodiment of the present invention one, described N-type thin layer and described first N-type thin layer 3 and described second N-type thin layer 3a provide the current flowing district of device; When device is in cut-off state, the N-type partial impurities in described N-type thin layer is all exhausted by the impurity in described P type thin layer 4; Or the N-type partial impurities at least described second N-type thin layer 3a is all exhausted by the impurity in described P type thin layer 4, the absolute value of the difference of the N-type partial impurities sum in the described second N-type thin layer 3a of described first N-type thin layer 3 both sides and the impurity sum in described P type thin layer 4 can not be greater than wherein any one and 20%.
In the embodiment of the present invention one, being formed with a thickness in the bottom of described groove is the N-type layer of t1, also namely below described P type thin layer 4, the N-type layer that thickness is t1 is formed with, this N-type layer when device ends can not exhaust by the p type impurity of described P type thin layer 4, the turn-off characteristic of device can be improved like this.
The embodiment of the present invention one super-junction device is super junction trench gate mosfet device, a MOSFET element unit is all formed at each described N-type thin layer top, the gate groove of P trap 7 is formed through at the top of each described N-type thin layer, be formed with gate dielectric layer 5 in the lower surface of described gate groove and side, be formed with the polysilicon gate 6 of filling described gate groove on gate dielectric layer 5 surface, described gate dielectric layer 5 is gate oxide.Described P trap 7 side that covers by described polysilicon gate 6 for the formation of longitudinal channel.Described P trap 7 top of the both sides of the described gate groove at described N-type thin layer top is all formed with the source region 8 be made up of N+ district.
Interlayer film 10 is formed in described silicon substrate 1 front; Contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Bottom the described contact hole 11 at top, described source region 8, be formed with the P trap draw-out area 9 be made up of P+ district, described P trap draw-out area 9 and described P trap 7 contact.
Be formed with front metal 12 in described silicon substrate 1 front, described front metal 12 draws source electrode and grid respectively.Be formed with back metal 13 at described silicon substrate 1 back side, described back metal 13 draws drain electrode respectively.
The further improvement of the embodiment of the present invention one has: described gash depth is 40 microns ~ 50 microns, and the width of described groove is 6 microns, and the spacing between each adjacent described groove is 1 micron.
The resistivity of described silicon substrate 1 is 20 ohmcm ~ 40 ohmcms.The resistivity of described second N-type thin layer 3a is 0.97 ohmcm, and impurity concentration is 5e15cm -3, the width being positioned at two described second N-type thin layer 3a of each described first N-type thin layer 3 both sides is all respectively 1.5 microns.The resistivity of described P type thin layer 4 is 2.74 ohmcms, and impurity concentration is 5e15cm -3; The width of described P type thin layer 4 is 3 microns, be by two width be 1.5 microns described second P-type silicon epitaxial loayer in the trench between engage after formed.
The impurity of described N-type region 2 needs to activate, as laser annealing, and furnace anneal, or the combination of laser annealing and furnace anneal activates; The thickness of described N-type region 2 is 0.5 micron ~ 5 microns, this thickness is that the thickness of thinning back side by controlling described silicon substrate 1 obtains, in double arrowed line EDC in Fig. 4, border E, D are respectively the back side of described N-type region 2 and upper bounds, border C are in described N-type thin layer, because the thickness of described N-type region 2 is less, the doping of described N-type region 2 adopts primary ions to inject and realizes as injected phosphorus, and Implantation Energy is 50-500KEV, and dosage is higher than 5E14CM -2, as shown in Figure 10 a, be the first genesis analysis figure of the impurity concentration of the N-type region 2 of the embodiment of the present invention one super-junction device, the impurity of described N-type region 2 is diffused into the upper bounds place of border D and described N-type region 2; As shown in fig. lob, the second genesis analysis figure of the impurity concentration of the N-type region 2 of the embodiment of the present invention one super-junction device, the impurity of described N-type region 2 is not diffused into the upper bounds place of border D and described N-type region 2, namely also comprise one section of resistivity region identical with described silicon substrate 1 in described beneath trenches, the first genesis analysis as described in Figure 10 a can obtain lower conduction resistance.
As shown in Figures 5 to 9, be the embodiment of the present invention one super-junction device each step of manufacture method in device profile map; The described super-junction device of the manufacture method of the embodiment of the present invention one super-junction device is super junction trench gate mosfet device, comprises the steps:
Step one, as shown in Figure 5, at N-type silicon substrate 1 surface of higher electric resistivity successively deposit first silicon dioxide layer 31, second silicon nitride layer 32 and the 3rd silicon dioxide layer 33; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer 33, described second silicon nitride layer 32 and described first silicon dioxide layer 31 successively.Be preferably, the resistivity of described silicon substrate 1 is 20 ohmcm ~ 40 ohmcms, and the thickness for the described silicon substrate 1 of 8 inches is 700 microns ~ 725 microns.
Step 2, as shown in Figure 6, forms multiple groove with described groove figure mask for mask carries out etching to described silicon substrate 1; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate 1 between each described groove is laminate structure and forms the first N-type thin layer 3 by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer 33 of described groove figure mask and described second silicon nitride layer 32 are removed successively, described first silicon dioxide layer 31 retains.Be preferably, described gash depth is 40 microns ~ 50 microns, and the width of described groove is 6 microns, and the spacing between each adjacent described groove is 1 micron.
Step 3, as shown in Figure 7, form the first N-type silicon epitaxy layer in described silicon substrate 1 front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer 3a by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer 3 both sides, each described first N-type thin layer 3 adds that the described second N-type thin layer 3a of its both sides forms corresponding each N-type thin layer.
The resistivity of described second N-type thin layer 3a is lower than the resistivity of described silicon substrate 1, by the N-type impurity of of described silicon substrate 1 itself, the N-type doping of described first N-type thin layer 3 adds that the N-type impurity diffused into from described second N-type thin layer 3a forms.
The described first N-type thin layer 3 of part or all of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer 3 from the described second N-type thin layer 3a N-type impurity diffused into described first N-type thin layer 3, the resistivity of described silicon substrate 1 is more than 10 times of the resistivity of described second N-type thin layer 3a, the resistivity of the zone line of described first N-type thin layer 3 equals the resistivity of described silicon substrate 1, and form described high-resistivity portions by the zone line of described first N-type thin layer 3.
Be preferably, described in described current flowing district, the width of N-type thin layer is all identical, and all comprises described high-resistivity portions in the described first N-type thin layer 3 of whole described N-type thin layer.Or, described N-type thin layer in described current flowing district comprises two or more width, the described N-type thin layer of Breadth Maximum comprises described high-resistivity portions, and the described N-type thin layer that width is less than described Breadth Maximum comprises or do not comprise described high-resistivity portions; The described N-type thin layer not comprising described high-resistivity portions has feature: diffuse into the N-type impurity described first N-type thin layer 3 from described second N-type thin layer 3a and spread all in the width range of whole described first N-type thin layer 3, and the resistivity of described first N-type thin layer 3 zone line is lower than the resistivity of described silicon substrate 1.
Be preferably, the resistivity of described second N-type thin layer 3a is 0.97 ohmcm, and impurity concentration is 5e15cm -3, the width being positioned at two described second N-type thin layer 3a of each described first N-type thin layer 3 both sides is all respectively 1.5 microns.
Step 4, as shown in Figure 7, form the second P-type silicon epitaxial loayer in described silicon substrate 1 front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer 4 by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer 4 in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of at least described second N-type thin layer 3a and its contiguous described P type thin layer 4, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer 4, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer 4.And for not comprising the described N-type thin layer of described high-resistivity portions, this part N-type thin layer can balance with its contiguous described P type thin layer 4, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, the described N-type thin layer not comprising described high-resistivity portions can by the complete having lateral depletion of described P type thin layer 4.
During the break-over of device of the embodiment of the present invention one, described N-type thin layer and described first N-type thin layer 3 and described second N-type thin layer 3a provide the current flowing district of device; When device is in cut-off state, the N-type partial impurities in described N-type thin layer is all exhausted by the impurity in described P type thin layer 4; Or the N-type partial impurities at least described second N-type thin layer 3a is all exhausted by the impurity in described P type thin layer 4, the absolute value of the difference of the N-type partial impurities sum in the described second N-type thin layer 3a of described first N-type thin layer 3 both sides and the impurity sum in described P type thin layer 4 can not be greater than wherein any one and 20%.
Be preferably, the resistivity of described P type thin layer 4 is 2.74 ohmcms, and impurity concentration is 5e15cm -3; The width of described P type thin layer 4 is 3 microns, be by two width be 1.5 microns described second P-type silicon epitaxial loayer in the trench between engage after formed.
Step 5, as shown in Figure 8, adopts lithographic etch process to form gate groove at the top of the described N-type thin layer in described current flowing district.
Step 6, as shown in Figure 8, deposit gate dielectric layer 5 and polysilicon gate 6, be preferably successively, and described gate dielectric layer 5 is gate oxide.Described gate dielectric layer 5 covers the lower surface of described gate groove and side and outside, described polysilicon gate 6 is formed at described gate dielectric layer 5 surface and is filled completely by described gate groove, remove described gate dielectric layer 5 and the described polysilicon gate 6 of described gate groove outside, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer 5 and described polysilicon gate 6 that are filled in described gate groove inside.
Step 7, as shown in Figure 8, forms P trap 7 at the top of described N-type thin layer and described P type thin layer 4; The degree of depth of described gate groove is greater than the degree of depth of described P trap 7, described polysilicon gate 6 cover described P trap 7 from the side and described P trap 7 side that covers by described polysilicon gate 6 for the formation of longitudinal channel.
Step 8, as shown in Figure 8, carries out N+ ion implantation and forms source region 8; Described P trap 7 top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region 8.
Step 9, as shown in Figure 8, forms interlayer film 10 in described silicon substrate 1 front defining described source region 8; Adopt lithographic etch process to form contact hole 11, described contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Carry out P+ ion implantation and form P trap draw-out area 9, described P trap draw-out area 9 is positioned at bottom the described contact hole 11 that contacts with described source region 8, and described P trap draw-out area 9 and described P trap 7 contact.
Step 10, as shown in Figure 9, deposit front metal 12 also carries out chemical wet etching to described front metal 12 and forms source electrode and grid respectively;
Step 11, as shown in Figure 4, carry out thinning from the back side to described silicon substrate 1.
Step 12, as shown in Figure 4, carry out backside particulate and inject and form N-type region 2, described N-type region 2 is positioned at bottom described N-type thin layer and described P type thin layer 4.Be preferably, the thickness of described N-type region 2 is 0.5 micron ~ 5 microns, this thickness is that the thickness of thinning back side by controlling described silicon substrate 1 obtains, and in the double arrowed line EDC in Fig. 4, border E, D are respectively the back side of described N-type region 2 and upper bounds, border C are in described N-type thin layer.Because the thickness of described N-type region 2 is less, the doping of described N-type region 2 adopts primary ions to inject and realizes as injected phosphorus, and Implantation Energy is 50KEV ~ 500KEV, and dosage is higher than 5E14CM -2.
Step 13, as shown in Figure 4, the ion of described N-type region 2 to be activated.Be preferably, the activation of the impurity of described N-type region 2 adopts a laser annealing, a furnace anneal, or the combination of a laser annealing and a furnace anneal activates.After activation, the genesis analysis of the impurity concentration of described N-type region 2 as as-shown-in figures 10 a and 10b.
Step 14, as shown in Figure 4, carries out back face metalization and forms drain electrode 13.
In the embodiment of the present invention one method, the technique forming described P trap 7 in step 7 is before can advanceing to step one namely before groove formation process.Such energy reduces because the thermal process pushing away trap technique needs in described P trap 7 forming process is on the impact of Impurity Diffusion in P-N thin layer, improves the conduction resistance of device.
As shown in figure 11, be the profile of the embodiment of the present invention two super-junction device, the difference part of the embodiment of the present invention two super-junction device and the embodiment of the present invention one super-junction device is: described N-type region 2 is made up of ground floor N-type region 21 and second layer N-type region 22, described ground floor N-type region 21 is bottom described N-type thin layer and described P type thin layer 4, described second layer N-type region 22 is near the back side of described silicon substrate 1, the doping content of described second layer N-type region 22 is greater than the doping content of described ground floor N-type region 21, the doping content of described second layer N-type region 22 meets and the back metal 13 that is formed at described silicon substrate 1 forms the condition of ohmic contact, the injection ion of described first N-type region 21 wider respectively as the resilient coating of described super-junction device.The thickness of the described N-type region 2 of the embodiment of the present invention two will thick compared with the embodiment of the present invention one, be preferably, the thickness of described N-type region 2 is 3 microns ~ 50 microns, and the thickness of described ground floor N-type region 21 is 3 microns ~ 50 microns, and the thickness of described second layer N-type region 22 is 0.5 micron ~ 3 microns.
Be preferably, the genesis analysis of the impurity concentration of described N-type region 2 comprises 3 kinds of situations:
Figure 12 A is the genesis analysis figure of the first impurity concentration of the N-type region 2 of the embodiment of the present invention two super-junction device; In the situation of the genesis analysis of this first impurity concentration, the thickness of described N-type region 2 is 3 microns ~ 5 microns, adopts twice backside particulate to inject and can obtain described first N-type region 21 and described second layer N-type region 22 respectively.First time, the implanted dopant of backside particulate injection was phosphorus, and Implantation Energy is 1000KEV ~ 4000KEV, and dosage is higher than 5E13CM -2; The implanted dopant that second time backside particulate injects is phosphorus, and arsenic etc., energy is less than 80KEV, and dosage is greater than 1e15cm -2, as illustrated in fig. 12, closest to backside surface, place is dense for the N-type impurity CONCENTRATION DISTRIBUTION between border D and E obtained like this, obtains the contact resistance of very Di N+ district and metal; Thereafter activation can adopt temperature lower than the furnace anneal of 500 DEG C, or adopts laser annealing.
Figure 12 B is the genesis analysis figure of the second impurity concentration of the N-type region 2 of the embodiment of the present invention two super-junction device; In the situation of the genesis analysis of this second impurity concentration, the thickness of described N-type region 2 is 3 microns ~ 50 microns, adopts twice backside particulate to inject and can obtain described first N-type region 21 and described second layer N-type region 22 respectively.First time, the implanted dopant of backside particulate injection was H+, and Implantation Energy is 50KEV ~ 4000KEV, and dosage is higher than 5E13CM -2; The implanted dopant that second time backside particulate injects is phosphorus, and arsenic etc., energy is less than 80KEV, and dosage is greater than 1e15cm -2, activation thereafter can adopt temperature lower than the furnace anneal of 500 DEG C.In the situation of the genesis analysis of this second impurity concentration, the implantation dosage of backside particulate injection is for the first time higher, the impurity concentration activating rear interface D place N-type region 2 is greater than the impurity concentration of described N-type thin layer or described P type thin layer 4, and the N-type impurity CONCENTRATION DISTRIBUTION between border D and E obtained so as shown in Figure 12 B.
Figure 12 C is the genesis analysis figure of the third impurity concentration of the N-type region 2 of the embodiment of the present invention two super-junction device; The difference of the situation of the situation of the genesis analysis of this third impurity concentration and the genesis analysis of the third impurity concentration shown in Figure 12 B is, in the situation of the genesis analysis of this third impurity concentration, the implantation dosage of backside particulate injection is for the first time lower, the impurity concentration activating rear interface D place N-type region 2 is less than the impurity concentration of described N-type thin layer or described P type thin layer 4, and the N-type impurity CONCENTRATION DISTRIBUTION between border D and E obtained so as indicated in fig. 12 c.
The difference of the manufacture method of the embodiment of the present invention two super-junction device and the manufacture method of the embodiment of the present invention one super-junction device is: carry out thinning technique from the back side to described silicon substrate 1 in step 11, requires that the thickness of the described N-type region 2 ensureing follow-up formation is 3 microns ~ 50 microns.Inject at the backside particulate that carries out of step 12 the technique forming N-type region 2, the embodiment of the present invention two method includes twice backside particulate and injects and form described first N-type region 21 and described second layer N-type region 22 respectively.Be preferably, the impurity concentration of described first N-type region 21 and described second layer N-type region 22 can have 3 kinds of genesis analysis situations:
The genesis analysis of the first impurity concentration corresponds to shown in Figure 12 A, and the thickness of described N-type region 2 is 3 microns ~ 5 microns, and the implanted dopant that backside particulate injects for the first time is phosphorus, and Implantation Energy is 1000KEV ~ 4000KEV, and dosage is higher than 5E13CM -2; The implanted dopant that second time backside particulate injects is phosphorus, and arsenic etc., energy is less than 80KEV, and dosage is greater than 1e15cm -2; Now adopt temperature lower than the furnace anneal of 500 DEG C to the activation of the ion of described N-type region 2 in step 13 thereafter, or adopt laser annealing.
The genesis analysis of the second impurity concentration corresponds to shown in Figure 12 B, in the situation of the genesis analysis of this second impurity concentration, the thickness of described N-type region 2 is 3 microns ~ 50 microns, and the implanted dopant that backside particulate injects for the first time is H+, Implantation Energy is 50KEV ~ 4000KEV, and dosage is higher than 5E13CM -2; The implanted dopant that second time backside particulate injects is phosphorus, and arsenic etc., energy is less than 80KEV, and dosage is greater than 1e15cm -2, the activation now in step 13 thereafter can adopt temperature lower than the furnace anneal of 500 DEG C.In the situation of the genesis analysis of this second impurity concentration, the implantation dosage of backside particulate injection is for the first time higher, and the impurity concentration activating rear interface D place N-type region 2 is greater than the impurity concentration of described N-type thin layer or described P type thin layer 4.
The genesis analysis of the second impurity concentration corresponds to shown in Figure 12 C, the difference of the situation of the situation of the genesis analysis of this third impurity concentration and the genesis analysis of the third impurity concentration shown in Figure 12 B is, in the situation of the genesis analysis of this third impurity concentration, first time, the implantation dosage of backside particulate injection was lower, and the impurity concentration activating rear interface D place N-type region 2 is less than the impurity concentration of described N-type thin layer or described P type thin layer 4.
As shown in figure 13, be the profile of the embodiment of the present invention three super-junction device; The difference part of the embodiment of the present invention three super-junction device and the embodiment of the present invention one super-junction device is: the embodiment of the present invention three super-junction device is super junction trench gate IGBT device, also be formed with p type island region 14 in the bottom of described N-type region 2, described p type island region 14 is injected by employing backside particulate the P+ district formed and is formed.Described N-type region 2 becomes a field cutoff layer, and described p type island region 14 becomes the collector region of device; Whole formation IGBT device.As shown in figure 14, be the embodiment of the present invention three super-junction device P/N thin layer bottom to the genesis analysis figure of impurity concentration at silicon substrate 1 back side; Wherein form described p type island region 4 near the P+ district at the back side.
The difference of the manufacture method of the embodiment of the present invention three super-junction device and the manufacture method of the embodiment of the present invention one super-junction device is: in step 12 after carrying out backside particulate and injecting formation N-type region 2, also comprises and adopts backside particulate to inject the described p type island region 14 of formation.The genesis analysis of the doping content of the p type island region 14 formed as shown in figure 14.
As shown in figure 15, be the vertical view in current flowing district of the embodiment of the present invention four super-junction device; As shown in figure 16, be the profile of the embodiment of the present invention four super-junction device.The difference part of the embodiment of the present invention four super-junction device and the embodiment of the present invention one super-junction device is: at least comprise the described N-type thin layer that comprises the first N-type thin layer 3W of wider width in embodiment of the present invention four device, first N-type thin layer 3W described in Figure 15 corresponds to the thin layer between C2D2, and the thin layer between C0D0, C1D1, C3D3 and C4D4 corresponds to described first N-type thin layer 3.Due to the wider width of described first N-type thin layer 3W, do not spread all in the width range of whole described first N-type thin layer 3W from the described second N-type thin layer 3a N-type impurity diffused into described first N-type thin layer 3W, so described first always in the middle of N-type thin layer 3W exists a high-resistivity portions, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, described high-resistivity portions is not by the complete having lateral depletion of described P type thin layer 4; And not by the part of described P type thin layer 4 having lateral depletion, a P-N junction can be formed with described P trap 7, along with the increase of device source drain voltage and Vds, depletion region in described first N-type thin layer 3W expands gradually, this different with described second N-type thin layer 3a with described P type thin layer 4 in low voltage as just completely exhausted under 50V, due to this characteristic of described first N-type thin layer 3W, improve reverse recovery characteristic and the switching characteristic of device.Be preferably, the width of described first N-type thin layer 3W is 50 microns.
The difference of the manufacture method of the embodiment of the present invention four super-junction device and the manufacture method of the embodiment of the present invention one super-junction device is: when forming groove in step 2, and the spacing between the described groove of subregion is set to width needed for described first N-type thin layer 3W.Be preferably, the width of described first N-type thin layer 3W is 50 microns.
As shown in figure 17, it is the profile of the embodiment of the present invention five super-junction device, the difference part of the embodiment of the present invention five super-junction device and embodiment of the present invention four device is: the described N-type region 2 of the embodiment of the present invention five device is made up of the first N-type region 21 and the second N-type region 22, and the first N-type region 21 of the embodiment of the present invention five device and the architectural feature of the second N-type region 22 are identical with the embodiment of the present invention two device.
The difference of the manufacture method of the embodiment of the present invention five super-junction device and the manufacture method of the embodiment of the present invention two super-junction device is: when forming groove in step 2, and the spacing between the described groove of subregion is set to width needed for described first N-type thin layer 3W.Be preferably, the width of described first N-type thin layer 3W is 50 microns.
The difference part of the embodiment of the present invention six super-junction device and embodiment of the present invention four device is: the embodiment of the present invention six super-junction device is super junction trench gate IGBT device, the back side of the described N-type region 2 of the embodiment of the present invention six device is also formed with described p type island region 14, and the architectural feature of described p type island region 14 is identical with the embodiment of the present invention three device as shown in fig. 13 that.
The difference of the manufacture method of the embodiment of the present invention six super-junction device and the manufacture method of the embodiment of the present invention two super-junction device is: when forming groove in step 2, and the spacing between the described groove of subregion is set to width needed for described first N-type thin layer 3W.Be preferably, the width of described first N-type thin layer 3W is 50 microns.
As shown in figure 18, be the vertical view in current flowing district of the embodiment of the present invention seven super-junction device; The difference part of the embodiment of the present invention seven super-junction device and embodiment of the present invention four device is: the described first N-type thin layer 3W of the wider width in embodiment of the present invention device device only exists in subregion, not whole through a device current flow region, and make described first N-type thin layer 3W not with the termination environment of device near, in order to avoid cause in the difference due to neighbour termination environment and cause the conforming difference of device, or add the complexity of Terminal Design.Near the metal pad (PAD) of front metal 12 that simultaneously described first N-type thin layer 3W does not also connect with device gate electrode and polysilicon gate 6, the consistency of device can be improved and reduce the complexity of device layout.
The invention described above embodiment one to seven super-junction device is all trench gate structure device, and the present invention is applicable to planar gate structure device too, only trench gate is transformed into planar gate.
As shown in figure 19, be the profile of the embodiment of the present invention eight super-junction device.The embodiment of the present invention eight super-junction device is super junction flat-grid MOSFET component, the difference part of the embodiment of the present invention eight device and the embodiment of the present invention one device is: described gate dielectric layer 5 and described polysilicon gate 6 are planar structure, P trap 7 described in described polysilicon gate 6 cover part also extends to the top of described N-type thin layer, the side autoregistration of described source region 8 and described polysilicon gate 6, the surface of the described P trap 7 covered by described polysilicon gate 6 is for the formation of the raceway groove connecting described source region 8 and described N-type thin layer.
The manufacture method of the embodiment of the present invention eight super-junction device comprises the steps:
Step one, as shown in Figure 5, at N-type silicon substrate 1 surface of higher electric resistivity successively deposit first silicon dioxide layer 31, second silicon nitride layer 32 and the 3rd silicon dioxide layer 33; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer 33, described second silicon nitride layer 32 and described first silicon dioxide layer 31 successively.Be preferably, the resistivity of described silicon substrate 1 is 20 ohmcm ~ 40 ohmcms, and the thickness for the described silicon substrate 1 of 8 inches is 700 microns ~ 725 microns.
Step 2, as shown in Figure 6, forms multiple groove with described groove figure mask for mask carries out etching to described silicon substrate 1; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate 1 between each described groove is laminate structure and forms the first N-type thin layer 3 by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer 33 of described groove figure mask and described second silicon nitride layer 32 are removed successively, described first silicon dioxide layer 31 retains.Be preferably, described gash depth is 40 microns ~ 50 microns, and the width of described groove is 6 microns, and the spacing between each adjacent described groove is 1 micron.
Step 3, as shown in Figure 7, form the first N-type silicon epitaxy layer in described silicon substrate 1 front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer 3a by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer 3 both sides, each described first N-type thin layer 3 adds that the described second N-type thin layer 3a of its both sides forms corresponding each N-type thin layer.
The resistivity of described second N-type thin layer 3a is lower than the resistivity of described silicon substrate 1, by the N-type impurity of of described silicon substrate 1 itself, the N-type doping of described first N-type thin layer 3 adds that the N-type impurity diffused into from described second N-type thin layer 3a forms.
The described first N-type thin layer 3 of part or all of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer 3 from the described second N-type thin layer 3a N-type impurity diffused into described first N-type thin layer 3, the resistivity of described silicon substrate 1 is more than 10 times of the resistivity of described second N-type thin layer 3a, the resistivity of the zone line of described first N-type thin layer 3 equals the resistivity of described silicon substrate 1, and form described high-resistivity portions by the zone line of described first N-type thin layer 3.
Be preferably, described in described current flowing district, the width of N-type thin layer is all identical, and all comprises described high-resistivity portions in the described first N-type thin layer 3 of whole described N-type thin layer.Or, described N-type thin layer in described current flowing district comprises two or more width, the described N-type thin layer of Breadth Maximum comprises described high-resistivity portions, and the described N-type thin layer that width is less than described Breadth Maximum comprises or do not comprise described high-resistivity portions; The described N-type thin layer not comprising described high-resistivity portions has feature: diffuse into the N-type impurity described first N-type thin layer 3 from described second N-type thin layer 3a and spread all in the width range of whole described first N-type thin layer 3, and the resistivity of described first N-type thin layer 3 zone line is lower than the resistivity of described silicon substrate 1.
Be preferably, the resistivity of described second N-type thin layer 3a is 0.97 ohmcm, and impurity concentration is 5e15cm -3, the width being positioned at two described second N-type thin layer 3a of each described first N-type thin layer 3 both sides is all respectively 1.5 microns.
Step 4, as shown in Figure 7, form the second P-type silicon epitaxial loayer in described silicon substrate 1 front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer 4 by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer 4 in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of at least described second N-type thin layer 3a and its contiguous described P type thin layer 4, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer 4, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer 4.And for not comprising the described N-type thin layer of described high-resistivity portions, this part N-type thin layer can balance with its contiguous described P type thin layer 4, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, the described N-type thin layer not comprising described high-resistivity portions can by the complete having lateral depletion of described P type thin layer 4.
During the break-over of device of the embodiment of the present invention eight, described N-type thin layer and described first N-type thin layer 3 and described second N-type thin layer 3a provide the current flowing district of device; When device is in cut-off state, the N-type partial impurities in described N-type thin layer is all exhausted by the impurity in described P type thin layer 4; Or the N-type partial impurities at least described second N-type thin layer 3a is all exhausted by the impurity in described P type thin layer 4, the absolute value of the difference of the N-type partial impurities sum in the described second N-type thin layer 3a of described first N-type thin layer 3 both sides and the impurity sum in described P type thin layer 4 can not be greater than wherein any one and 20%.
Be preferably, the resistivity of described P type thin layer 4 is 2.74 ohmcms, and impurity concentration is 5e15cm -3; The width of described P type thin layer 4 is 3 microns, be by two width be 1.5 microns described second P-type silicon epitaxial loayer in the trench between engage after formed.
Step 5, as shown in figure 19, form P trap 7 at the top of each described P type thin layer 4, each described P trap 7 also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap 7 is N-type conducting district 16.Be preferably, be also included in the step of carrying out N-type ion implantation in described N-type conducting district 16, this N-type ion implantation can reduce the conduction resistance of device.
Step 6, as shown in figure 19, deposit gate dielectric layer 5 and polysilicon gate 6 successively, adopt lithographic etch process to etch described polysilicon gate 6 and described gate dielectric layer 5 successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer 5 after etching and described polysilicon gate 6; Described polysilicon gate 6 cover described N-type thin layer and part described P trap 7 from top and the described P trap 7 that covers by described polysilicon gate 6 for the formation of lateral channel.
Step 7, as shown in figure 19, carries out N+ ion implantation and forms source region 8; Described source region 8 is formed at described P trap 7 top and and described polysilicon gate 6 autoregistration.
Step 8, as shown in figure 19, forms interlayer film 10 in described silicon substrate 1 front defining described source region 8; Adopt lithographic etch process to form contact hole 11, described contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Carry out P+ ion implantation and form P trap draw-out area 9, described P trap draw-out area 9 is positioned at bottom the described contact hole 11 that contacts with described source region 8, and described P trap draw-out area 9 and described P trap 7 contact.
Step 9, as shown in figure 19, deposit front metal 12 also carries out chemical wet etching to described front metal 12 and forms source electrode and grid respectively;
Step 10, as shown in figure 19, carry out thinning from the back side to described silicon substrate 1.
Step 11, as shown in figure 19, carry out backside particulate and inject and form N-type region 2, described N-type region 2 is positioned at bottom described N-type thin layer and described P type thin layer 4.Be preferably, the thickness of described N-type region 2 is 0.5 micron ~ 5 microns, this thickness is that the thickness of thinning back side by controlling described silicon substrate 1 obtains, and in the double arrowed line EDC in Fig. 4, border E, D are respectively the back side of described N-type region 2 and upper bounds, border C are in described N-type thin layer.Because the thickness of described N-type region 2 is less, the doping of described N-type region 2 adopts primary ions to inject and realizes as injected phosphorus, and Implantation Energy is 50-500KEV, and dosage is higher than 5E14CM -2.
Step 12, as shown in figure 19, the ion of described N-type region 2 to be activated.Be preferably, the activation of the impurity of described N-type region 2 adopts a laser annealing, a furnace anneal, or the combination of a laser annealing and a furnace anneal activates.After activation, the genesis analysis of the impurity concentration of described N-type region 2 as as-shown-in figures 10 a and 10b.
Step 13, as shown in figure 19, carries out back face metalization and forms drain electrode 13.
The difference part of the embodiment of the present invention nine super-junction device and the embodiment of the present invention eight super-junction device is: the embodiment of the present invention nine super-junction device is super junction planar gate IGBT device, also be formed with p type island region in the bottom of described N-type region 2, described p type island region forms by adopting backside particulate to inject the P+ district formed.Described N-type region 2 becomes a field cutoff layer, and described p type island region becomes the collector region of device; Whole formation IGBT device.The architectural feature of the described p type island region 14 of the embodiment of the present invention nine is identical with the described p type island region 4 of the embodiment of the present invention three super-junction device.
The difference of the manufacture method of the embodiment of the present invention nine super-junction device and the manufacture method of the embodiment of the present invention eight super-junction device is: in step 11 after carrying out backside particulate and injecting formation N-type region 2, also comprises and adopts backside particulate to inject the described p type island region of formation.
Only list super junction MOSFET element and IGBT device in above-described embodiment, the P-N laminate structure of the embodiment of the present invention is suitable for equally to be had in the power device of super-junction structures with super junction high-voltage diode etc.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (20)

1. a super-junction device, super-junction device is formed in N-type silicon substrate, and the zone line of described super-junction device is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; It is characterized in that:
Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer;
Described silicon substrate is formed with multiple groove, and each described N-type thin layer is made up of the first N-type thin layer and the second N-type thin layer all respectively; Described first N-type thin layer is made up of the silicon substrate thin layer between described groove, described second N-type thin layer forms by be filled in described groove and to be positioned at described first N-type thin layer both sides first N-type silicon epitaxy layer, described P type thin layer is made up of the second P-type silicon epitaxial loayer be filled in described groove, and the described second N-type thin layer of each described P type thin layer and its both sides contacts and filled completely by the described groove of correspondence;
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;
The N-type region be made up of backside particulate injection region is formed bottom described N-type thin layer and described P type thin layer.
2. super-junction device as claimed in claim 1, is characterized in that: described in described current flowing district, the width of N-type thin layer is all identical, and all comprises described high-resistivity portions in the described first N-type thin layer of whole described N-type thin layer;
Or, described N-type thin layer in described current flowing district comprises two or more width, the described N-type thin layer of Breadth Maximum comprises described high-resistivity portions, and the described N-type thin layer that width is less than described Breadth Maximum comprises or do not comprise described high-resistivity portions; The described N-type thin layer not comprising described high-resistivity portions has feature: diffuse into the N-type impurity described first N-type thin layer from described second N-type thin layer and spread all in the width range of whole described first N-type thin layer, and the resistivity of described first N-type thin layer zone line is lower than the resistivity of described silicon substrate.
3. super-junction device as claimed in claim 1, it is characterized in that: described N-type region is made up of ground floor N-type region and second layer N-type region, described ground floor N-type region is bottom described N-type thin layer and described P type thin layer, described second layer N-type region is near the back side of described silicon substrate, the doping content of described second layer N-type region is greater than the doping content of described ground floor N-type region, the metal at the back side that the doping content of described second layer N-type region meets and is formed at described silicon substrate forms the condition of ohmic contact, and described first N-type region is as the resilient coating of described super-junction device.
4. super-junction device as claimed in claim 1, is characterized in that: the thickness of described N-type region is 0.5 micron ~ 5 microns.
5. super-junction device as claimed in claim 3, it is characterized in that: the thickness of described ground floor N-type region is 3 microns ~ 50 microns, the thickness of described second layer N-type region is 0.5 micron ~ 3 microns.
6. super-junction device as claimed in claim 1, is characterized in that: be also formed with the p type island region be made up of backside particulate injection region at the back side of described N-type region.
7. super-junction device as claimed in claim 1 or 2, is characterized in that: the described N-type thin layer comprising described high-resistivity portions in described current flowing district is distributed in one or more regions in described current flowing district.
8. super-junction device as claimed in claim 2, is characterized in that: the distributed areas of described N-type thin layer comprising described high-resistivity portions in described current flowing district and the region of described terminal protection structure do not adjoin.
9. super-junction device as claimed in claim 2, is characterized in that: the region comprising the distributed areas of the described N-type thin layer of described high-resistivity portions and the grid metal electrode figure of described super-junction device in described current flowing district does not adjoin.
10. a manufacture method for super-junction device, described super-junction device is super junction trench gate mosfet device, it is characterized in that, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;
Step 5, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district;
Step 6, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside;
Step 7, form P trap at the top of described N-type thin layer and described P type thin layer; The degree of depth of described gate groove is greater than the degree of depth of described P trap, described polysilicon gate cover described P trap from the side and the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel;
Step 8, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region;
Step 9, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;
Step 10, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;
Step 11, carry out thinning from the back side to described silicon substrate;
Step 12, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer;
Step 13, the ion of described N-type region to be activated;
Step 14, carry out back face metalization formed drain electrode.
11. methods as claimed in claim 10, is characterized in that: the distance of the described trench bottom surfaces formed in the backside surface of the described silicon substrate after step 11 is thinning and step 2 is 0.5 micron ~ 40 microns.
12. methods as claimed in claim 10, is characterized in that: at least comprise a laser annealing in the activation technology in step 13.
13. methods as claimed in claim 10, is characterized in that: carry out before the first silicon dioxide layer described in the deposit that the technique of the described P trap of the formation in step 7 advances to step one.
The manufacture method of 14. 1 kinds of super-junction devices, described super-junction device is super junction flat-grid MOSFET component, it is characterized in that, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;
Step 5, form P trap at the top of each described P type thin layer, each described P trap also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap is N-type conducting district;
Step 6, successively deposit gate dielectric layer and polysilicon gate, adopt lithographic etch process to etch described polysilicon gate and described gate dielectric layer successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer after etching and described polysilicon gate; Described polysilicon gate cover described N-type thin layer and part described P trap from top and the described P trap that covers by described polysilicon gate for the formation of lateral channel;
Step 7, carry out N+ ion implantation formed source region; Described source region be formed at described P trap top and and described polysilicon gate autoregistration;
Step 8, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;
Step 9, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;
Step 10, carry out thinning from the back side to described silicon substrate;
Step 11, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer;
Step 12, the ion of described N-type region to be activated;
Step 13, carry out back face metalization formed drain electrode.
15. methods as claimed in claim 14, is characterized in that: the distance of the described trench bottom surfaces formed in the backside surface of the described silicon substrate after step 10 is thinning and step 2 is 0.5 micron ~ 40 microns.
16. methods as claimed in claim 14, is characterized in that: at least comprise a laser annealing in the activation technology in step 12.
17. methods as claimed in claim 14, is characterized in that: carry out before the first silicon dioxide layer described in the deposit that the technique of the described P trap of the formation in step 5 advances to step one.
18. methods as claimed in claim 14, is characterized in that: after the described P trap of step 5 is formed, before the described gate dielectric layer deposit of step 6, be also included in the step of carrying out N-type ion implantation in described N-type conducting district.
The manufacture method of 19. 1 kinds of super-junction devices, described super-junction device is super junction trench gate IGBT device, it is characterized in that, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, the charge balance of described N-type thin layer and its contiguous described P type thin layer or imbalance, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, the first N-type thin layer of the complete having lateral depletion of whole described N-type thin layer or described N-type thin layer is not by the complete having lateral depletion of described P type thin layer;
Step 5, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district;
Step 6, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside;
Step 7, form P trap at the top of described N-type thin layer and described P type thin layer; The degree of depth of described gate groove is greater than the degree of depth of described P trap, described polysilicon gate cover described P trap from the side and the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel;
Step 8, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at described N-type thin layer top is all formed with described source region;
Step 9, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;
Step 10, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;
Step 11, carry out thinning from the back side to described silicon substrate;
Step 12, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer; Carry out the formation p type island region, the back side that backside particulate is infused in described N-type region;
Step 13, the ion of described N-type region and described p type island region to be activated;
Step 14, carry out back face metalization formed drain electrode.
The manufacture method of 20. 1 kinds of super-junction devices, described super-junction device is super junction flat-grid MOSFET component, it is characterized in that, comprises the steps:
Step one, at N-type silicon substrate surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;
Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple groove; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, the described silicon substrate between each described groove is laminate structure and forms the first N-type thin layer by the silicon substrate thin layer between each described groove; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;
Step 3, form the first N-type silicon epitaxy layer in described silicon substrate front deposit, described first N-type silicon epitaxy layer is formed at bottom surface and the side of described groove; Form the second N-type thin layer by being positioned at the first N-type silicon epitaxy layer described in described first N-type thin layer both sides, each described first N-type thin layer adds each N-type thin layer that the described second N-type thin layer composition of its both sides is corresponding;
The resistivity of described second N-type thin layer is lower than the resistivity of described silicon substrate, by the N-type impurity of of described silicon substrate itself, the N-type doping of described first N-type thin layer adds that the N-type impurity diffused into from described second N-type thin layer forms;
The described first N-type thin layer of all or part of described N-type thin layer comprises high-resistivity portions, the described N-type thin layer comprising described high-resistivity portions has following feature: do not spread all in the width range of whole described first N-type thin layer from the described second N-type thin layer N-type impurity diffused into described first N-type thin layer, the resistivity of described silicon substrate is more than 10 times of the resistivity of described second N-type thin layer, the resistivity of the zone line of described first N-type thin layer equals the resistivity of described silicon substrate, and form described high-resistivity portions by the zone line of described first N-type thin layer,
Step 4, form the second P-type silicon epitaxial loayer in described silicon substrate front deposit, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;
In described current flowing district, form P type thin layer by the described second P-type silicon epitaxial loayer be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;
The charge balance of at least described second N-type thin layer and its contiguous described P type thin layer, comprise the described N-type thin layer of described high-resistivity portions and the imbalance of its contiguous described P type thin layer, when connecting reversed bias voltage between described N-type thin layer and described P type thin layer, comprise the described high-resistivity portions of the described N-type thin layer of described high-resistivity portions not by the complete having lateral depletion of described P type thin layer;
Step 5, form P trap at the top of each described P type thin layer, each described P trap also extends to part described N-type thin layer top; Described N-type thin layer top area between each described P trap is N-type conducting district;
Step 6, successively deposit gate dielectric layer and polysilicon gate, adopt lithographic etch process to etch described polysilicon gate and described gate dielectric layer successively, be made up of the grid structure of described super junction flat-grid MOSFET component the described gate dielectric layer after etching and described polysilicon gate; Described polysilicon gate cover described N-type thin layer and part described P trap from top and the described P trap that covers by described polysilicon gate for the formation of lateral channel;
Step 7, carry out N+ ion implantation formed source region; Described source region be formed at described P trap top and and described polysilicon gate autoregistration;
Step 8, form interlayer film in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;
Step 9, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively;
Step 10, carry out thinning from the back side to described silicon substrate;
Step 11, carry out backside particulate inject formed N-type region, described N-type region is positioned at bottom described N-type thin layer and described P type thin layer; Carry out the formation p type island region, the back side that backside particulate is infused in described N-type region;
Step 12, the ion of described N-type region and described p type island region to be activated;
Step 13, carry out back face metalization formed drain electrode.
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