CN102386212A - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102386212A CN102386212A CN2010102701008A CN201010270100A CN102386212A CN 102386212 A CN102386212 A CN 102386212A CN 2010102701008 A CN2010102701008 A CN 2010102701008A CN 201010270100 A CN201010270100 A CN 201010270100A CN 102386212 A CN102386212 A CN 102386212A
- Authority
- CN
- China
- Prior art keywords
- epitaxial loayer
- groove
- epitaxial
- semiconductor device
- device structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
The invention discloses a semiconductor device structure, which comprises a plurality of first epitaxial layers in the same columnar shape, a plurality of second epitaxial layers and a plurality of third epitaxial layers. The first epitaxial layers are distributed on the surface of a silicon substrate at preset interval, each second epitaxial layer is formed in a groove between two adjacent first epitaxial layers, and the plurality of third epitaxial layers are respectively formed on the second epitaxial layers. The invention further discloses a manufacturing method of the semiconductor device structure. The semiconductor device structure and the manufacturing method can improve uniformity of distribution of carrier gross of interior extending layers and the epitaxial layers in the longitudinal direction, optimize charge balance capability and improve stability of devices.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly relate to a kind of semiconductor device structure, fill epitaxial loayer in the groove with groove structure; The invention still further relates to the manufacture method of said semiconductor device.
Background technology
Super junction MOSFET has super-junction structures because of it, and P type and the N type silicon epitaxy post layer alternately arranged are promptly arranged on Semiconductor substrate, makes the PN junction generation depletion layer in this device p type island region and N type district under cut-off state, thereby the raising device is withstand voltage.
A kind of manufacturing approach of super junction MOSFET device architecture is: growth has first silicon epitaxy layer (being generally the N type) of first conduction type on highly doped Semiconductor substrate; On first silicon epitaxy layer with a plurality of deep trench of preset distance etching; Second epitaxial loayer that will have second conduction type (being generally the P type) again is filled in groove inside and top, with chemical mechanical milling tech groove is carried out planarization at last.Wherein the deep trench filling is the critical process of this flow process.Because gash depth is darker, generally all more than 30 μ m, so after trench fill, groove inside has filling defects such as cavity easily.In order to reduce the difficulty that deep trench is filled, adopt the method that changes the groove pattern usually, promptly the groove top width is big, and trench bottom width is little, so just can avoid the generation owing to the too fast groove interior void that growth caused in groove top.But the another one problem can appear thus, promptly carry out trench fill with silicon epitaxy after, it generally is uniform that the inner charge carrier of groove distributes.Theoretical according to hyperstructure, when the contained charge carrier total amount of adjacent single P type post layer and N type post layer was close, device just can reach higher puncture voltage.For the single second extension post layer, because upper width is greater than lower width, promptly charge carrier total amount in top is greater than bottom charge carrier total amount; To the single first extension post layer; Upper width is less than lower width; Be top charge carrier total amount less than bottom charge carrier total amount, will cause more serious not the matching on vertically distributing of the first extension post layer and the second extension post layer like this, thereby cause the decline of puncture voltage.
Summary of the invention
The technical problem that the present invention will solve provides a kind of semiconductor device structure, can improve the uniformity on the charge carrier total amount of epitaxial loayer distributes in the vertical in the groove, optimizes the charge balance ability, improves the stability of device; The present invention also will provide a kind of manufacture method of said semiconductor device structure for this reason.
For solving the problems of the technologies described above, semiconductor device structure of the present invention comprises: first epitaxial loayer of a plurality of identical columns, and this first epitaxial loayer is distributed on the silicon substrate with preset space length; A plurality of second epitaxial loayers, each second epitaxial loayer are formed in the groove between two said first epitaxial loayers that face mutually; A plurality of the 3rd epitaxial loayers are formed at respectively on said second epitaxial loayer.
The manufacture method of said semiconductor device structure is following:
Step 1, on silicon substrate, form first epitaxial loayer;
Step 2, on said first epitaxial loayer, form a plurality of identical grooves with preset space length;
Step 3, in said groove inside or groove inside and top form second epitaxial loayer;
Wherein, also comprise:
Step 4, on said second epitaxial loayer, form the 3rd epitaxial loayer;
Step 5, employing cmp carry out planarization to said flute surfaces.
As shown in Figure 1; The gross thickness of second epitaxial loayer is uniform in the vertical in the groove; Carrier concentration also is uniformly, so the charge carrier total amount also is uniform, and the 3rd epitaxial loayer to be intrinsic epitaxial loayer or low-doped epitaxial loayer (have the identical conduction type with second epitaxial loayer; But carrier concentration be less than or equal to second epitaxial loayer 10%); So the average doping content of the epitaxial loayer (comprising second epitaxial loayer and the 3rd epitaxial loayer) that groove is inner is skewness in the vertical, i.e. top doping is lighter, and the bottom is mixed denseer; Just opposite with the distribution of groove width, the charge carrier total amount that can make the epitaxial loayer in the groove is uniformly on vertically distributing or approaches uniformly.(the epitaxial loayer carrier concentration profile in the groove is uniform to one step of groove fill process before the contrast; But thickness is uneven; So the charge carrier total amount is uneven in the vertical, and opposite with the first epitaxial loayer carrier concentration distribution in the vertical), the uniformity on the charge carrier total amount that the present invention can improve the interior epitaxial loayer of groove distributes in the vertical; Optimize the charge balance ability, improve the stability of device; Can improve the charge carrier coupling in the vertical of P type and N type post, thereby improve the puncture voltage of device.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is a semiconductor device structure schematic cross-section of the present invention;
Fig. 2 is that first epitaxial loayer and the second epitaxial loayer concentration of dopant concern sketch map;
Fig. 3-the 7th, the control flow sketch map of the embodiment of the invention one;
Fig. 8-the 14th, the control flow sketch map of the embodiment of the invention two;
Figure 15-17 second epitaxial loayer inside carrier concentration profile sketch map in the horizontal direction.
Embodiment
As shown in Figure 1; Said in one embodiment conductor device structure (super junction MOSFET device architecture) comprises having highly doped semiconductor silicon substrate 14 (having first conduction type), alternately arranging first epitaxial loayer (silicon epitaxy post layer) 11 that has first conduction type respectively and second epitaxial loayer (silicon epitaxy post layer) the 12 and the 3rd epitaxial loayer (intrinsic extension post layer) 13 with second conduction type on this silicon substrate 14.Wherein second epitaxial loayer 12 is surrounded by first epitaxial loayer 11, and the 3rd epitaxial loayer 13 is surrounded by second epitaxial loayer 12.
As shown in Figure 1, the top width t of said groove 15 bottom width d1, groove 15 top width d2, the 3rd epitaxial loayer 13 satisfies relational expression: t≤d2-d1.The average doping content of the inner epitaxial loayer of groove skewness in the vertical like this; Be that top is mixed lighter; The bottom is mixed denseer, just opposite with the distribution of groove width, and the charge carrier total amount that can make the epitaxial loayer in the groove is uniformly on vertically distributing or approaches uniformly.
As shown in Figure 2, the mean breadth sum of said first epitaxial loayer, 11 mean breadth L1 (μ m), second epitaxial loayer 12 and the 3rd epitaxial loayer 13 is the charge carrier mean concentration C1 (atoms/cm of L2 (μ m), first epitaxial loayer 11
3), the charge carrier mean concentration C2 (atoms/cm of second epitaxial loayer 12 and the 3rd epitaxial loayer 13
3) satisfy following relational expression:
(C1×L1-C2×L2)/(C1×L1+C2×L2)＜30％。
First epitaxial loayer is equally divided into three parts on the direction perpendicular to Semiconductor substrate: top, middle part and bottom.At the top of first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer charge carrier total amount Q2t satisfy relational expression in the interior charge carrier total amount Q1t of each first epitaxial loayer and that be adjacent and groove parallel position: 0.8Q2t≤Q1t≤1.0Q2t; At the middle part of first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer charge carrier total amount Q2t satisfy relational expression in the interior charge carrier total amount Q1t of each first epitaxial loayer and that be adjacent and groove parallel position: 0.9Q2t≤Q1t≤1.1Q2t; In the bottom of first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer charge carrier total amount Q2t satisfy relational expression in the interior charge carrier total amount Q1t of each first epitaxial loayer and that be adjacent and groove parallel position: 1.0Q2t≤Q1t≤1.2Q2t.
Second epitaxial loayer, 12 inner carrier concentrations can be uniform (combining shown in Figure 17) in the horizontal direction; Also can change; Promptly can be to become greatly or gradually diminish (combining shown in Figure 15) gradually; Also can be big or stepped the diminishing (combining shown in Figure 16) of stepped change, the variation of above-mentioned carrier concentration can realize through the flow that changes impurity gas.
It is big that the width of said first epitaxial loayer 11 becomes from top to bottom gradually, and the overall width of said second epitaxial loayer 12 and the 3rd epitaxial loayer 13 diminishes from top to bottom gradually.
Specify the manufacture method of said conductor device structure below in conjunction with embodiment.
Embodiment 1
Step 1, referring to shown in Figure 3, on semiconductor silicon substrate 14 growth first epitaxial loayer 11, this epitaxial loayer 11 has first conduction type, like the N type.The thickness of first epitaxial loayer 11 is 1.0-100.0 μ m, as 50 microns.
Step 2, referring to shown in Figure 4, in epitaxial loayer 11, utilize photoetching and etching to form deep trench 15, the width at said groove 15 tops is 0.2-10.0 μ m (like 5 μ m), and the groove top width is greater than trench bottom width; The degree of depth is 0.8-100.0 μ m (like 45 μ m), and groove pitch is 0.2-20 μ m (like 15 μ m).The etching of deep trench 15 can be used the anisotropic dry etching method, and the mask of etching can be a photoresist, can be dielectric film also, like silica, can also be the two the combination of photoresist and dielectric film.
Step 3, referring to shown in Figure 5; After deep trench 15 etchings; Mask is removed, and is 500-1300 ℃ in temperature, and pressure is under the condition of 0.01-760 holder; Adopt the mist of silicon source gas and halide gas, hydrogen and impurity gas to carry out growing silicon epitaxy layer, form second epitaxial loayer 12 and make it fill deep trench 15.
Step 4, combine Fig. 5, shown in 6; When said second epitaxial loayer 12 at the growth thickness s of groove 15 sidewalls more than or equal to the half the of trench bottom width d1 but less than the half of groove top width d2; Turn off impurity gas; Adopt the mist of silicon source gas and halide gas and hydrogen to carry out the second step epitaxial growth, form the 3rd epitaxial loayer 13 until complete filling groove 15.
Can know according to above description, adopt growing epitaxial silicon filling groove 15 to carry out in two steps among the present invention, but be continuously the mode of growth; Promptly in the epitaxially grown starting stage; Feed impurity gas, be the half the of groove 15 bottom width d1 when second epitaxial loayer 12 at the growth thickness s of groove 15 sidewalls but, turn off impurity gas less than the half of groove top width d2; Carry out the second step epitaxial growth, until the complete filling groove.Epitaxially grown temperature, pressure and growth rate are regulated according to the width and the different of depth-to-width ratio of groove, and the groove that wherein depth-to-width ratio is big adopts lower growth rate growth, and the groove that depth-to-width ratio is little can be used growth rate growth faster.
Said silicon source gas is at least a in a chlorine hydrogen silicon, dichloro-dihydro silicon, trichlorosilane, the tetrachloro hydrogen silicon.Said halide gas is at least a in hydrogen chloride and the hydrogen fluoride.Said impurity gas is a kind of in roc alkane, phosphine or the arsine.Being grown in same board and the same cavity of said second epitaxial loayer 12 and the 3rd epitaxial loayer 13 once accomplished, and promptly behind second epitaxial loayer, 12 growth endings, turns off impurity gas and continues epitaxial growth, to form the 3rd epitaxial loayer 13.
Step 5, combine shown in Figure 7ly, adopt the method for cmp that planarization is carried out at groove 15 tops, form the final devices structure.
Embodiment 2
Step 1, referring to shown in Figure 8, growth first epitaxial loayer 11 on semiconductor silicon substrate 14, this epitaxial loayer 11 has first conduction type, like the N type, thickness can be that several micron is to tens microns, as 50 microns.
Step 2, referring to shown in Figure 9, on said first epitaxial loayer 11, form one deck hard mask layer 16, the mask during as selective epitaxial growth.
Step 3, referring to shown in Figure 10, said first epitaxial loayer 11 is carried out photoetching and etching, form a plurality of equally spaced deep trench 15.The top width of deep trench 15 is several thousand dusts to tens micron, as 5 microns; The degree of depth of deep trench 15 is that several microns are to tens microns, as 45 microns; The spacing of deep trench 15 is several thousand dusts to tens micron, as 15 microns.The etching of deep trench 15 can be used the anisotropic dry etching method, and the mask of etching can be that dielectric film also can be dielectric film and photoresist; After deep trench 15 etchings, photoresist is removed, and dielectric film keeps or part keeps.
Step 4, referring to shown in Figure 11; In temperature is 500-1300 ℃; Pressure is under the condition of 0.01-760 holder, adopts the mist of silicon source gas and halide gas, hydrogen and impurity gas to carry out growing silicon epitaxy layer, forms second epitaxial loayer 12 and makes it fill deep trench 15.
Step 5, combine Figure 11, shown in 12; When said second epitaxial loayer 12 at the growth thickness s of groove 15 sidewalls more than or equal to the half the of trench bottom width d1 but less than the half of groove top width d2; Turn off impurity gas; Adopt the mist of silicon source gas and halide gas and hydrogen to carry out the second step epitaxial growth, form the 3rd epitaxial loayer 13 until complete filling groove 15.
Can know according to above description, adopt growing epitaxial silicon filling groove 15 to carry out in two steps among the present invention, but be continuously the mode of growth.Through the flow-rate ratio of adjusting silicon mist, and temperature and pressure, accomplish the selective growth of silicon epitaxy on dielectric film and silicon single crystal, can avoid groove 15 tops owing to too fast growth is sealed like this.
Step 6, referring to shown in Figure 13, adopt the method for cmp that planarization is carried out at groove 15 tops, remove hard mask layer 16 (combining shown in Figure 14) with wet etching again.
More than through embodiment and embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (20)
1. semiconductor device structure comprises: first epitaxial loayer of a plurality of identical columns, and this first epitaxial loayer is distributed on the surface of silicon substrate with preset space length; A plurality of second epitaxial loayers, each second epitaxial loayer are formed in the groove between two said first epitaxial loayers that face mutually; It is characterized in that: also comprise a plurality of the 3rd epitaxial loayers, be formed at respectively on said second epitaxial loayer.
2. semiconductor device structure according to claim 1 is characterized in that: said first epitaxial loayer has first conduction type, and second epitaxial loayer has second conduction type; The 3rd epitaxial loayer is the intrinsic epitaxial loayer, or has the conduction type the same with second epitaxial loayer, but its carrier concentration is less than or equal to 10% of the second epitaxial loayer carrier concentration.
3. semiconductor device structure according to claim 1 is characterized in that: the bottom width d1 of said groove and top width d2, and satisfy following relational expression: t≤d2-d1 between the top width t of the 3rd epitaxial loayer.
4. semiconductor device structure according to claim 1 is characterized in that: the width of said first epitaxial loayer becomes big from top to bottom gradually, and the overall width of said second epitaxial loayer and the 3rd epitaxial loayer diminishes from top to bottom gradually.
5. semiconductor device structure according to claim 1; It is characterized in that: the inner carrier concentration of the above second epitaxial loayer can be uniform in the horizontal direction; Also can change; Promptly inner from the trenched side-wall to the groove, the inner carrier concentration of second epitaxial loayer can be uniformly, also can change; Inner from the trenched side-wall to the groove, the inner carrier concentration of second epitaxial loayer can be to become big gradually, and is also can stepped change big, can also be to diminish gradually, or stepped diminishing.
6. semiconductor device structure according to claim 1; It is characterized in that: the charge carrier mean concentration C2 of charge carrier mean concentration C1, second epitaxial loayer and the 3rd epitaxial loayer of the mean breadth L2 of the mean breadth L1 of said first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer, first epitaxial loayer satisfies relational expression: (C1 * L1-C2 * L2)/(C1 * L1+C2 * L2)＜30%; Wherein, The unit of L1, L2 is μ m, and the unit of C1, C2 is atoms/cm
3
7. semiconductor device structure according to claim 1 is characterized in that: first epitaxial loayer is equally divided into three parts, top, middle part and bottom on the direction perpendicular to Semiconductor substrate; At the top of first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer charge carrier total amount Q2t satisfy relational expression in the interior charge carrier total amount Q1t of each first epitaxial loayer and that be adjacent and groove parallel position: 0.8Q2t≤Q1t≤1.0Q2t; At the middle part of first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer charge carrier total amount Q2t satisfy relational expression in the interior charge carrier total amount Q1t of each first epitaxial loayer and that be adjacent and groove parallel position: 0.9Q2t≤Q1t≤1.1Q2t; In the bottom of first epitaxial loayer, second epitaxial loayer and the 3rd epitaxial loayer charge carrier total amount Q2t satisfy relational expression in the interior charge carrier total amount Q1t of each first epitaxial loayer and that be adjacent and groove parallel position: 1.0Q2t≤Q1t≤1.2Q2t.
8. the manufacture method of a semiconductor device structure may further comprise the steps:
Step 1, on silicon substrate, form first epitaxial loayer;
Step 2, on said first epitaxial loayer, form a plurality of identical grooves with preset space length;
Step 3, in said groove inside or groove inside and top form second epitaxial loayer;
It is characterized in that, also comprise:
Step 4, on said second epitaxial loayer, form the 3rd epitaxial loayer;
Step 5, employing cmp carry out planarization to said flute surfaces.
9. manufacture method as claimed in claim 8 is characterized in that: the thickness of first epitaxial loayer described in the step 1 is 1.0-100.0 μ m, and has first conduction type.
10. manufacture method as claimed in claim 8 is characterized in that: the width at the top of groove described in the step 2 is 0.2-10.0 μ m, and the groove top width is greater than trench bottom width; The degree of depth is 0.8-100.0 μ m, groove pitch 0.2-20 μ m.
11. manufacture method as claimed in claim 8 is characterized in that: second epitaxial loayer has second conduction type described in the step 3.
12. manufacture method as claimed in claim 8; It is characterized in that: the 3rd epitaxial loayer described in the step 4 is the intrinsic epitaxial loayer or has the conduction type the same with second epitaxial loayer, but its carrier concentration is less than or equal to 10% of the second epitaxial loayer carrier concentration.
13. manufacture method as claimed in claim 8 is characterized in that: the temperature during the 3rd outer layer growth described in second outer layer growth and the step 4 described in the step 3 is 500-1300 degree centigrade, and pressure is the 0.01-760 holder.
14. manufacture method as claimed in claim 8 is characterized in that: adopt the mist of silicon source gas, halide gas, hydrogen and impurity gas to carry out the growth of second epitaxial loayer described in the step 3.
15. manufacture method as claimed in claim 8 is characterized in that: adopt the mist of silicon source gas, halide gas and hydrogen to carry out the growth of the 3rd epitaxial loayer described in the step 4.
16. like claim 14 or 15 described manufacture methods, it is characterized in that: said silicon source gas is at least a in a chlorine hydrogen silicon, dichloro-dihydro silicon, trichlorosilane, the tetrachloro hydrogen silicon.
17. like claim 14 or 15 described manufacture methods, it is characterized in that: said halide gas is at least a in hydrogen chloride and the hydrogen fluoride.
18. manufacture method as claimed in claim 14 is characterized in that: said impurity gas is a kind of in roc alkane, phosphine or the arsine.
19. manufacture method as claimed in claim 8; It is characterized in that: being grown in same board and the same cavity of said second epitaxial loayer and the 3rd epitaxial loayer once accomplished; Promptly after second outer layer growth finishes, turn off impurity gas and continue epitaxial growth, to form the 3rd epitaxial loayer; Said second epitaxial loayer is at half the more than or equal to the half the of trench bottom width d1 but less than groove top width d2 of the growth thickness s of trenched side-wall.
20. manufacture method as claimed in claim 8 is characterized in that: the inner carrier concentration profile of said second epitaxial loayer can be uniform in the horizontal direction; Also can change, promptly can become greatly or gradually gradually and diminish, also can be big or stepped the diminishing of stepped change.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102701008A CN102386212A (en) | 2010-08-31 | 2010-08-31 | Semiconductor device structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102701008A CN102386212A (en) | 2010-08-31 | 2010-08-31 | Semiconductor device structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102386212A true CN102386212A (en) | 2012-03-21 |
Family
ID=45825448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102701008A Pending CN102386212A (en) | 2010-08-31 | 2010-08-31 | Semiconductor device structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102386212A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103837807A (en) * | 2012-11-23 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for measuring carrier concentration distribution in deep trench |
| CN104319284A (en) * | 2014-10-24 | 2015-01-28 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN104347715A (en) * | 2013-07-31 | 2015-02-11 | 英飞凌科技奥地利有限公司 | Semiconductor component with edge end junction |
| CN104425602A (en) * | 2013-08-30 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Super-junction appliance and manufacturing method |
| CN104425600A (en) * | 2013-08-28 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Super-junction device and method for manufacturing same |
| CN104576730A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Superjunction device and manufacturing method thereof |
| CN106229335A (en) * | 2016-08-01 | 2016-12-14 | 上海华虹宏力半导体制造有限公司 | Method for filling deep trench |
| CN106847896A (en) * | 2017-01-04 | 2017-06-13 | 上海华虹宏力半导体制造有限公司 | Groove-shaped super junction and its manufacture method |
| CN107546129A (en) * | 2017-07-21 | 2018-01-05 | 上海华虹宏力半导体制造有限公司 | The manufacture method of super junction |
| CN111403267A (en) * | 2020-04-23 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Trench epitaxial filling method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197152A1 (en) * | 2005-03-01 | 2006-09-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
-
2010
- 2010-08-31 CN CN2010102701008A patent/CN102386212A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197152A1 (en) * | 2005-03-01 | 2006-09-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103837807B (en) * | 2012-11-23 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | The method of measurement deep trench carriers concentration distribution |
| CN103837807A (en) * | 2012-11-23 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for measuring carrier concentration distribution in deep trench |
| CN104347715B (en) * | 2013-07-31 | 2017-08-11 | 英飞凌科技奥地利有限公司 | Semiconductor devices including edge butt joint |
| CN104347715A (en) * | 2013-07-31 | 2015-02-11 | 英飞凌科技奥地利有限公司 | Semiconductor component with edge end junction |
| US9520463B2 (en) | 2013-07-31 | 2016-12-13 | Infineon Technologies Austra AG | Super junction semiconductor device including edge termination |
| CN104425600A (en) * | 2013-08-28 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Super-junction device and method for manufacturing same |
| CN104425602A (en) * | 2013-08-30 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Super-junction appliance and manufacturing method |
| CN104576730A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Superjunction device and manufacturing method thereof |
| CN104576730B (en) * | 2013-10-16 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | Super-junction device and its manufacture method |
| CN104319284A (en) * | 2014-10-24 | 2015-01-28 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN106229335A (en) * | 2016-08-01 | 2016-12-14 | 上海华虹宏力半导体制造有限公司 | Method for filling deep trench |
| CN106847896A (en) * | 2017-01-04 | 2017-06-13 | 上海华虹宏力半导体制造有限公司 | Groove-shaped super junction and its manufacture method |
| CN106847896B (en) * | 2017-01-04 | 2019-10-11 | 上海华虹宏力半导体制造有限公司 | Groove-shaped super junction and its manufacturing method |
| CN107546129A (en) * | 2017-07-21 | 2018-01-05 | 上海华虹宏力半导体制造有限公司 | The manufacture method of super junction |
| CN111403267A (en) * | 2020-04-23 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Trench epitaxial filling method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102386212A (en) | Semiconductor device structure and manufacturing method thereof | |
| CN102254796B (en) | Method for forming alternative arrangement of P-type and N-type semiconductor thin layers | |
| CN103094067B (en) | A kind of manufacture method of semiconductor device | |
| US9034721B2 (en) | Method for manufacturing semiconductor substrate | |
| CN107359118B (en) | A kind of production method of super junction power device Withstand voltage layer | |
| CN103026461B (en) | In filling semiconductor material body deep trench technique and according to the semiconductor device of same process gained | |
| CN108807154A (en) | Silicon carbide epitaxy chip, silicon carbide insulated gate bipolar transistor and manufacturing method | |
| WO2018016201A1 (en) | Semiconductor device and method for manufacturing same | |
| JP6054272B2 (en) | Semiconductor device | |
| CN104347346B (en) | The deep trench flattening method of different structure | |
| CN102208336A (en) | Technical method for forming alternately arranged P type and N type semiconductor thin layers | |
| JP2016139761A (en) | Semiconductor device | |
| CN114512406A (en) | Manufacturing method of super junction device | |
| CN106876463A (en) | A kind of superjunction silicon carbide device and preparation method thereof | |
| WO2010137146A1 (en) | Method for producing diode, and diode | |
| CN109378343A (en) | Super-junction metal oxide field effect transistor and preparation method thereof | |
| CN106816376A (en) | A kind of preparation method of superjunction devices Withstand voltage layer | |
| CN102456715B (en) | Semiconductor device structure and manufacturing method thereof | |
| JP2006352092A (en) | Semiconductor substrate and its method for manufacturing | |
| CN104078354B (en) | Power semiconductor and manufacture method thereof | |
| JP4304034B2 (en) | Superjunction semiconductor device manufacturing method | |
| CN101859699A (en) | Polycrystalline silicon deposition process | |
| DE102016101559A1 (en) | METHOD FOR THE PRODUCTION OF SEMICONDUCTOR DEVICES, INCLUDING A DEPOSITION OF CRYSTALLINE SILICON IN GRAVES | |
| CN111584350B (en) | Filling method of SiC epitaxial trench and trench filling structure prepared by method | |
| CN104201099B (en) | Superjunction devices preparation process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120321 |