CN104425600A - Super-junction device and method for manufacturing same - Google Patents

Super-junction device and method for manufacturing same Download PDF

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CN104425600A
CN104425600A CN201310380359.1A CN201310380359A CN104425600A CN 104425600 A CN104425600 A CN 104425600A CN 201310380359 A CN201310380359 A CN 201310380359A CN 104425600 A CN104425600 A CN 104425600A
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thin layer
type thin
type
resistivity
trap
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CN104425600B (en
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肖胜安
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a super-junction device. A current flow region comprises a plurality of N-type thin layers and P-type thin layers which are arranged alternatively. The N-type thin layers comprise two types, and both the two types of N-type thin layers comprise a high-resistance part in the middle and low-resistance parts at the two sides. The charge of the first type of N-type thin layers and that of the P-type thin layers are in balance. The second type of N-type thin layers has a wider high-resistance part, and the charge of the second type of N-type thin layers and that of the P-type thin layers are not in balance. After the P-type thin layers horizontally deplete the second type of N-type thin layers, a P well on the top of the N-type thin layers vertically depletes the high-resistance parts of the second type of N-type thin layers in a gradually expanding way with the increase of reverse bias voltage. The invention further discloses a method for manufacturing the super-junction device. The reverse recovery characteristic of the device can be improved, and the conduction resistance is low.

Description

Super-junction device and manufacture method
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of super-junction device; The invention still further relates to a kind of manufacture method of super-junction device.
Background technology
Super junction MOSFET adopts new structure of voltage-sustaining layer, the a series of P type semiconductor thin layer that is alternately arranged and N type semiconductor thin layer is utilized to come just described P type semiconductor thin layer and N type semiconductor thin layer to be exhausted at the lower voltage in the off state, realize electric charge mutually to compensate, thus make P type semiconductor thin layer and N type semiconductor thin layer can realize high puncture voltage under high-dopant concentration, thus obtain low on-resistance and high-breakdown-voltage simultaneously, break traditions power MOSFET theoretical limit.In US Patent No. 5216275, the above P type semiconductor thin layer be alternately arranged is connected with N+ substrate with N type semiconductor thin layer; In US Patent No. 6630698B1, middle P type semiconductor thin layer and N type semiconductor thin layer and N+ substrate can have the interval being greater than 0.
In prior art, the formation one of P type semiconductor thin layer and N type semiconductor thin layer then carries out photoetching and injection by epitaxial growth, repeatedly this process obtains P type semiconductor thin layer and the N type semiconductor thin layer of the thickness needed repeatedly, this technique is in the MOSFET of more than 600V, generally need repetition more than 5 times, production cost and the production cycle long.Another kind be by a kind of type of a secondary growth need the extension of thickness after, carry out the etching of groove, insert the silicon of opposite types afterwards in the trench; Although this method difficulty is large, there is simplification of flowsheet, improve the effect of stability; After adopting groove structure, namely in the P type semiconductor thin layer be alternately arranged due to P/N thin layer and N type semiconductor thin layer, P type semiconductor thin layer and the doping content of N type semiconductor thin layer on longitudinal direction are easy to control, and in the thin layer not having repeatedly epitaxy technique to cause, P type semiconductor thin layer and N type semiconductor thin layer or the doping content of one of them change in the vertical thus bring additional longitudinal electric field, ensure that the leakage current characteristic that device can obtain and high puncture voltage.
In super junction technique, owing to have employed P/N thin layer alternately, in the body of super-junction device diode and the diode that formed between P type semiconductor thin layer and N type semiconductor thin layer at lower voltages such as 50 volts of Vds P type semiconductor thin layer and N type semiconductor thin layer will be exhausted completely, this makes this diode have very hard reverse recovery characteristic, this hard reverse recovery characteristic causes the restoring current of device sharply to change, thus causes very high voltage overshoot to bring component failure.Simultaneously because namely sharply changing of electric current and voltage have very high di/dt and dv/dt and can cause electromagnetic interference (EMI-ELEACTROMAGENETIC INTERFERENCE) in circuit, system is brought and affects even EMI and exceed standard, in this, super-junction device is not as conventional MOSFET element, because exhausting of the MOSFET element N-drift region of routine expands along with the increase of voltage (Vds) always, reverse recovery characteristic is softer.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of super-junction device, can improve the reverse recovery characteristic of device, and conduction resistance is lower.For this reason, the present invention also provides a kind of manufacture method of super-junction device.
For solving the problems of the technologies described above, the zone line of super-junction device provided by the invention is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer, is formed with P trap at the top of described N-type thin layer and described P type thin layer.
Described N-type thin layer comprises the first N-type thin layer and the second N-type thin layer.
The first N-type thin layer described comprises the first high-resistivity portions and the first low resistivity portion, described first high-resistivity portions is the mid portion of the first N-type thin layer described, and described first low resistivity portion is positioned at the both sides of described first high-resistivity portions and contacts with contiguous described P type thin layer.
The charge balance of the first N-type thin layer described and its contiguous described P type thin layer, and the difference of the P type carrier number of the N-type carrier number of the first N-type thin layer described and described P type thin layer be less than the N-type carrier number equaling the first N-type thin layer described 10% and be less than or equal to described P type thin layer P type carrier number 10%; When connecting reversed bias voltage between described N-type thin layer and described P type thin layer, can having lateral depletion or non-fully having lateral depletion completely mutually between the first N-type thin layer and its contiguous described P type thin layer, not being no more than 10% of the first N-type thin layer dosage described by the carrier number of having lateral depletion and being no more than 10% of described P type thin layer dosage of the first N-type thin layer described in during non-fully having lateral depletion or described P type thin layer.
Described the second N-type thin layer comprises the second high-resistivity portions and the second low resistivity portion, described second high-resistivity portions is the mid portion of described the second N-type thin layer, and described second low resistivity portion is positioned at the both sides of described second high-resistivity portions and contacts with contiguous described P type thin layer; The ratio of the resistivity of described second high-resistivity portions and described second low resistivity portion is greater than 5:1; Described first high-resistivity portions is identical with the resistivity of described second high-resistivity portions, described first low resistivity portion is identical with the resistivity of described second low resistivity portion, and the width of described second high-resistivity portions is greater than the width of described first high-resistivity portions.
The charge unbalance of described the second N-type thin layer and its contiguous described P type thin layer, under connecting the condition of reversed bias voltage between described N-type thin layer and described P type thin layer, described second low resistivity portion can by the complete having lateral depletion of described P type thin layer be close to, described second high-resistivity portions can not by the complete having lateral depletion of described P type thin layer, and not formed between the part of described P type thin layer having lateral depletion and described P trap of described second high-resistivity portions longitudinally exhausts; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap to described second high-resistivity portions exhausts increases.
Further improvement is, described super-junction device is super junction MOSFET element, the gate groove of described P trap is formed through at the top of each described N-type thin layer, be formed with gate dielectric layer in the lower surface of described gate groove and side, be formed with the polysilicon gate of filling described gate groove on gate dielectric layer surface, the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel, the described N-type thin layer immediately below described longitudinal channel is channel current dispersion area; The described channel current dispersion area of the first N-type thin layer described is positioned at described first low resistivity portion.
The described channel current dispersion area of described the second N-type thin layer is all positioned at described second low resistivity portion; Or the described channel current dispersion area of described the second N-type thin layer is all positioned at described second high-resistivity portions; Or the described channel current dispersion area part of described the second N-type thin layer is positioned at described second high-resistivity portions, part is positioned at described second low resistivity portion.
Further improvement is, the described P trap top of the both sides of the described gate groove at the first N-type thin layer top described is all formed with the source region be made up of N+ district.
The described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is all formed with the source region be made up of N+ district; Or the described P trap top of the side of the described gate groove at described the second N-type thin layer top is formed with the source region be made up of N+ district, the described P trap top of opposite side of described gate groove is not formed with the source region be made up of N+ district; Or the described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is not all formed with the source region be made up of N+ district.
Further improvement is, overlooks on face, and the shape of described the second N-type thin layer is identical or different with the shape of the first N-type thin layer described.
Further improvement is, overlooks on face, and described the second N-type thin layer is evenly distributed or uneven distribution in described current flowing district.
Further improvement is, the distributed areas of described the second N-type thin layer described terminal protection structure of getting along well adjoins.
For solving the problems of the technologies described above, the manufacture method of super-junction device provided by the invention comprises the steps:
Step one, on N+ silicon substrate deposit first N-type silicon epitaxial layers.
Step 2, on described first N-type silicon epitaxial layers deposit form the second N-type silicon epitaxial layers, the resistivity of described second N-type silicon epitaxial layers is greater than the resistivity of described first N-type silicon epitaxial layers; The described thickness of the second N-type silicon epitaxial layers is identical with the thickness of the second high-resistivity portions of the second N-type thin layer with the first high-resistivity portions of the first N-type thin layer in the current flowing district of follow-up formation.
Step 3, on described second N-type silicon epitaxial layers surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively.
Step 4, form multiple groove with described groove figure mask for mask carries out etching to described second N-type silicon epitaxial layers, the bottom of described groove described silicon substrate of getting along well is connected; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, described second N-type silicon epitaxial layers between each described groove is laminate structure and defines described first high-resistivity portions and described second high-resistivity portions respectively, and the width of described second high-resistivity portions is greater than the width of described first high-resistivity portions; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains.
Step 5, the deposit of described silicon substrate front formed the 3rd N-type silicon epitaxial layers, described 3rd N-type silicon epitaxy layer is formed at bottom surface and the side of described groove, and the ratio of the resistivity of described second N-type silicon epitaxial layers and the resistivity of described 3rd N-type silicon epitaxial layers is greater than 5:1; In described current flowing district, the described 3rd N-type silicon epitaxy layer being formed at the two sides of described first high-resistivity portions forms the first low resistivity portion, and described first high-resistivity portions and described first low resistivity portion form the first N-type thin layer; In described current flowing district, the described 3rd N-type silicon epitaxy layer being formed at the two sides of described second high-resistivity portions forms the second low resistivity portion, and described second high-resistivity portions and described second low resistivity portion form the second N-type thin layer; The N-type thin layer in described current flowing district is made up of the first N-type thin layer described and described the second N-type thin layer.
Step 6, the deposit of described silicon substrate front formed the 4th P type silicon epitaxial layers, described 4th P type silicon epitaxial layers contacts with described 3rd N-type silicon epitaxial layers and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer by the described 4th P type silicon epitaxial layers be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of the first N-type thin layer described and its contiguous described P type thin layer, and the difference of the P type carrier number of the N-type carrier number of the first N-type thin layer described and described P type thin layer be less than the N-type carrier number equaling the first N-type thin layer described 10% and be less than or equal to described P type thin layer P type carrier number 10%; When connecting reversed bias voltage between described N-type thin layer and described P type thin layer, can having lateral depletion or non-fully having lateral depletion completely mutually between the first N-type thin layer and its contiguous described P type thin layer, not being no more than 10% of the first N-type thin layer dosage described by the carrier number of having lateral depletion and being no more than 10% of described P type thin layer dosage of the first N-type thin layer described in during non-fully having lateral depletion or described P type thin layer.
The charge unbalance of described the second N-type thin layer and its contiguous described P type thin layer, under connecting the condition of reversed bias voltage between described N-type thin layer and described P type thin layer, described second low resistivity portion can by the complete having lateral depletion of described P type thin layer be close to, and described second high-resistivity portions can not by the complete having lateral depletion of described P type thin layer.
Step 7, formation P trap, described P trap is positioned at the top of described N-type thin layer and described P type thin layer; When connecting reversed bias voltage between described N-type thin layer and described P type thin layer, not formed between the part of described P type thin layer having lateral depletion and described P trap of described second high-resistivity portions longitudinally exhausts; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap to described second high-resistivity portions exhausts increases; The formation process of described P trap be placed on step 2 form described second N-type silicon epitaxial layers after, carry out before the first silicon dioxide layer, described second silicon nitride layer and described 3rd silicon dioxide layer described in step 3 deposit, or the formation process of described P trap is placed on after step 6 forms described P type thin layer and described N-type thin layer and carries out.
Further improvement is, described super-junction device is super junction MOSFET element, also comprises the steps:
Step 8, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district, and described gate groove is through described P trap.
Step 9, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction MOSFET element the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside.
The described P trap side that covers by described polysilicon gate for the formation of longitudinal channel, the described N-type thin layer immediately below described longitudinal channel is channel current dispersion area; The described channel current dispersion area of the first N-type thin layer described is positioned at described first low resistivity portion.
The described channel current dispersion area of described the second N-type thin layer is all positioned at described second low resistivity portion; Or the described channel current dispersion area of described the second N-type thin layer is all positioned at described second high-resistivity portions; Or the described channel current dispersion area part of described the second N-type thin layer is positioned at described second high-resistivity portions, part is positioned at described second low resistivity portion.
Further improvement also comprises the steps:
Step 10, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at the first N-type thin layer top described is all formed with described source region.
The described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is all formed with described source region; Or the described P trap top of the side of the described gate groove at described the second N-type thin layer top is formed with described source region, the described P trap top of opposite side of described gate groove is not formed with described source region; Or the described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is not all formed with described source region.
Step 11, form interlayer film in the described silicon substrate front defining source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact.
Step 12, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively; Carry out thinning from the back side to described silicon substrate, carry out back face metalization and form drain electrode.
The current flowing district of super-junction device of the present invention comprises two kinds of N-type thin layers, two kinds of N-type thin layers all comprise low resistivity portion and high-resistivity portions, regulate the doping of low resistivity portion and width to be easy to obtain lower conduction resistance, under high-resistivity portions energy high tension voltage, provide gradual output capacitance.
In addition, the present invention is by strengthening the width of the second high-resistivity portions of the second N-type thin layer, and make the second high-resistivity portions when reverse bias not by the complete having lateral depletion of P type thin layer, like this when reversed bias voltage increases, can to be exhausted by the longitudinal direction of P trap to the second high-resistivity portions being positioned at N-type thin layer top and the degree of depth of longitudinal depletion region increases with the increase of reverse biased, so hard reverse recovery characteristic deliquescing that can make device, thus the reverse recovery characteristic of device can be improved, reduce restoring current and impact.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing super-junction device vertical view one;
Fig. 2 is existing super-junction device vertical view two;
Fig. 3 is the vertical view in the current flowing district of the embodiment of the present invention one super-junction device;
Fig. 4 is the profile of the embodiment of the present invention one super-junction device;
Fig. 5-Fig. 8 is the device profile map in each step of manufacture method of the embodiment of the present invention one super-junction device;
Fig. 9 be the embodiment of the present invention two super-junction device profile;
Figure 10 be the embodiment of the present invention three super-junction device profile;
Figure 11 be the embodiment of the present invention four super-junction device profile;
Figure 12 is the vertical view in the current flowing district of the embodiment of the present invention five super-junction device;
Figure 13 A is the schematic diagram of Reverse recovery curve;
Figure 13 B is the P type thin layer of the super-junction device of the embodiment of the present invention one and the Reverse recovery curve of N-type thin layer.
Embodiment
As shown in Figure 1, be the vertical view one of existing super-junction device.On vertical view, the embodiment of the present invention can be divided into 1st district, 2nd district and 3rd district.1st district is the zone line of super-junction device is current flowing district, described current flowing district comprises the territory, p type island region 25 and N-type region territory that are alternately arranged, and namely territory, described p type island region 25 is also formed at the P type thin layer in described current flowing district, namely described N-type region territory is also formed at N-type thin layer in described current flowing district; Can arrive drain electrode by source electrode through raceway groove by N-type region territory at described current flowing district electric current, and territory, described p type island region 25 bears voltage under reverse blocking state together with formation depletion region, described N-type region territory.2nd district and 3rd district are the terminal protection structure region of described super-junction device; when break-over of device, described terminal protection structure does not provide electric current, reverse blocking state for this voltage of voltage born from the surface in 1 periphery, district unit and territory, p type island region, periphery 25 to device outer-most end surface substrate be lateral voltage and from 1 periphery, district cell surface to this voltage of voltage of substrate be longitudinal voliage.Having in 2nd district at least one P type ring 24, Fig. 1 is a P type ring 24, and the general P type backgate with 1st district of this P type ring 24 and P trap link together; There is the field plate dielectric film with certain inclination angle in 2nd district, also having in 2nd district for slowing down surface field polycrystalline field plate jumpy sheet and Metal field plate, and P type post 23; In 2nd district, also described Metal field plate can not be set.3rd district bear district by P type post 23 and the voltage that the N-type post be made up of N-type silicon epitaxy layer is alternately formed, it there is deielectric-coating, namely described P type post 23 is also formed at the P type thin layer in described terminal protection structure, namely described N-type post is also formed at N-type thin layer in described terminal protection structure; There is Metal field plate in 3rd district, in 3rd district, also described Metal field plate can not be set; P type ring 24 can be had in 3rd district also can not have, have the P type ring at this place during P type ring 24 to be not connected with the P type backgate in current flowing district (suspension) that be connected; Have channel cutoff ring 21 in the outermost end in 3rd district, described channel cutoff ring 21 adds medium formed thereon again by N+ injection region or N+ injection region or medium adds that metal is formed; Additional little P type post 22 can be had at four angles place, in order to better to realize charge balance at described P type post 23.As seen from Figure 1, the cellular construction in described current flowing district and territory, described p type island region 25 and N-type region territory are all strip structure; Described terminal protection structure is surrounded on the periphery in described current flowing district and described P type ring 24, described P type post 23 and described channel cutoff ring 21 are all tetragonal circulus, also can have the circulus of circular arc in tetragonal corner.
As shown in Figure 2, it is the vertical view two of existing super-junction device, structure difference is as shown in Figure 1, cellular construction in described current flowing district and territory, described p type island region 25 and N-type region territory are all tetragonal structure, namely by territory, tetragonal described p type island region 25 and N-type region territory in the two-dimensional direction proper alignment form the cell array in described current flowing district.Territory, described p type island region 25 and N-type region territory also can be hexagon, octagon and other shape, and the arrangement mode in territory, described p type island region 25 and N-type region territory also can at X, and Y-direction carries out certain dislocation; As long as ensure that whole arrangement is by certain rule, carry out repeating just passable.
The additional little P type post 22 of corner in Fig. 1 and Fig. 2, can design according to the optimized requirement of local charge balance, if the width of described P type post 23 is a, distance between described P type post 23 and described P type post 23 is also a, and so described little P type post 22 can adopt the length of side to be the square P nibs of 0.3 ~ 0.5a.
In existing super junction MOSFET element; MOSFET element unit is all formed above the N-type thin layer in current flowing district; the N-type thin layer in current flowing district, P type thin layer and MOSFET element unit repeat completely; the device being such as 600V and BVds-600V to a puncture voltage is example: the N+ silicon substrate of device is uniform; resistivity is 0.001-0.003 ohmcm; on N+ substrate, deposition thickness is 45 microns, and resistivity is the N-type silicon epitaxial layers of the Uniform Doped of 1 ohmcm ~ 5 ohmcm or the N-type silicon epitaxial layers of longitudinally impurity concentration change; Form groove afterwards, fill P type silicon epitaxial layers in the trench, P type silicon epitaxial layers can be longitudinally Uniform Doped, also can be longitudinally change doping, the P type thin layer leaving N-type thin layer and extension filling after such etching groove just constitutes the P-N thin layer replaced of super-junction device by P type thin layer and N-type thin layer; In current flowing district, except the region close to device terminal, may because Terminal Design and technique cause outside some differences, all device cells are consistent, and in the horizontal, the structure of P-N thin layer repeats completely.
As shown in Figure 3, be the vertical view in current flowing district of the embodiment of the present invention one super-junction device; As shown in Figure 4, be the profile of the embodiment of the present invention one super-junction device.
The zone line of the embodiment of the present invention one super-junction device is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district.
Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer 4, P trap 7 is formed at the top of described N-type thin layer and described P type thin layer 4, described N-type thin layer and described P type thin layer 4 are formed at the top of the first N-type silicon epitaxial layers 2, and described first N-type silicon epitaxial layers 2 is formed on N+ silicon substrate 1.
As can be seen from Figure 3, described P type thin layer 4 corresponds to the thin layer between B1B2, B3B4, B5B6, B7B8 etc., described N-type thin layer corresponds to the thin layer between B0B1, B2B3, B4B5, B6B7, B8B9 etc., can find out that described P type thin layer 4 and described N-type thin layer are all strip structure and are alternately arranged.
Described N-type thin layer comprises the first N-type thin layer and the second N-type thin layer, and the first N-type thin layer corresponds to the narrower thin layer in Fig. 3 between B0B1, B2B3, B6B7, B8B9 etc.; The second N-type thin layer corresponds to the wider thin layer between B4B5 in Fig. 3 etc.
The first N-type thin layer described comprises the first high-resistivity portions 3n and the first low resistivity portion 3a, described first high-resistivity portions 3n is the mid portion of the first N-type thin layer described, and described first low resistivity portion 3a is positioned at the both sides of described first high-resistivity portions 3n and contacts with contiguous described P type thin layer 4.As shown in Figure 3, described first high-resistivity portions 3n is the part between C0D0, C1D1, C3D3 and C4D4 etc.The charge balance of the first N-type thin layer described and its contiguous described P type thin layer 4, be preferably, the difference of the N-type carrier number of the first N-type thin layer described and the P type carrier number of described P type thin layer 4 be less than the N-type carrier number of the first N-type thin layer described 10% and be less than described P type thin layer 4 P type carrier number 10%.When connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, can having lateral depletion or non-fully having lateral depletion completely mutually between the first N-type thin layer and its contiguous described P type thin layer 4, as when reverse biased reaches about 50V or more the first N-type thin layer and its contiguous as described in just having lateral depletion or non-fully having lateral depletion completely mutually between P type thin layer 4; Not being no more than 10% of the first N-type thin layer dosage described by the carrier number of having lateral depletion and being no more than 10% of described P type thin layer 4 dosage of the first N-type thin layer described in during non-fully having lateral depletion or described P type thin layer 4.In the preferred embodiment, the charge balance of the first N-type thin layer described and described these two thin layers of P type thin layer 4 will be realized by their transverse width of adjustment and impurity concentration; The first N-type thin layer described is as the thin layer of super-junction device, charge balance is reached with the described P type thin layer 4 of surrounding, general needs are in the scope that lithographic etch process ability is permitted, the width controlling described first high-resistivity portions 3n is as far as possible little of being less than 0.5 micron, with that be optimized, low conduction resistance.
Described the second N-type thin layer comprises the second high-resistivity portions 3w and the second low resistivity portion 3a, first low resistivity portion 3a described in the embodiment of the present invention one and described second low resistivity portion 3a has identical process structure, therefore adopts identical mark to represent.Described second high-resistivity portions 3w is the mid portion of described the second N-type thin layer, and described second low resistivity portion 3a is positioned at the both sides of described second high-resistivity portions 3w and contacts with contiguous described P type thin layer 4; The ratio of the resistivity of described second high-resistivity portions 3w and described second low resistivity portion 3a is greater than 5:1; Described first high-resistivity portions 3n is identical with the resistivity of described second high-resistivity portions 3w, described first low resistivity portion 3a is identical with the resistivity of described second low resistivity portion 3a, and the width of described second high-resistivity portions 3w is greater than the width of described first high-resistivity portions 3n.In the preferred embodiment, the resistivity of described second high-resistivity portions 3w is 45 ohmcms, and the resistivity of described second low resistivity portion 3a is 1 ohmcm ~ 5 ohmcm.
The charge unbalance of described the second N-type thin layer and its contiguous described P type thin layer 4, under connecting the condition of reversed bias voltage between described N-type thin layer and described P type thin layer 4, described second low resistivity portion 3a can by the complete having lateral depletion of described P type thin layer 4 be close to, described second high-resistivity portions 3w is not by the complete having lateral depletion of described P type thin layer 4, and not formed between the part of described P type thin layer 4 having lateral depletion and described P trap 7 of described second high-resistivity portions 3w longitudinally exhausts; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap 7 to described second high-resistivity portions 3w exhausts increases.
For longitudinal direction, if the thickness of described the second N-type thin layer is enough thick, when can ensure device breakdown, described second high-resistivity portions 3w is completely not depleted; If the thickness low LCL of described the second N-type thin layer is thick, described second high-resistivity portions 3w can be just depleted before puncture voltage reaches, and so will terminate in the region of described first N-type silicon epitaxial layers 2; No matter in which kind of situation, the design in described second high-resistivity portions 3w region, all can improve the reverse recovery characteristic of the diode that body diode and described P type thin layer and described N-type thin layer are formed, thus improve the reverse recovery characteristic of whole device; In above this device, utilize the part of described second high-resistivity portions 3w, improve the reverse recovery characteristic of device; The width of described second high-resistivity portions 3w part is larger, component is larger, and the reverse recovery characteristic of device is softer, but due to described second high-resistivity portions 3w part be high resistivity, along with the accounting of described second high-resistivity portions 3w increases, the conducting resistance of device can improve accordingly.
The described super-junction device of the embodiment of the present invention one is super junction MOSFET element, a MOSFET element unit is all formed at each described N-type thin layer top, the gate groove of described P trap 7 is formed through at the top of each described N-type thin layer, be formed with gate dielectric layer 5 in the lower surface of described gate groove and side, be formed with the polysilicon gate 6 of filling described gate groove on gate dielectric layer 5 surface, described gate dielectric layer 5 is gate oxide.Described P trap 7 side that covers by described polysilicon gate 6 for the formation of longitudinal channel, the described N-type thin layer immediately below described longitudinal channel is channel current dispersion area; The described channel current dispersion area of the first N-type thin layer described is positioned at described first low resistivity portion 3a.
The described channel current dispersion area of described the second N-type thin layer is all positioned at described second high-resistivity portions 3w.
Described P trap 7 top of the both sides of the described gate groove at the first N-type thin layer top described is all formed with the source region 8 be made up of N+ district.
Described P trap 7 top of the both sides of the described gate groove at described the second N-type thin layer top is all formed with the source region 8 be made up of N+ district.
Interlayer film 10 is formed in described silicon substrate 1 front; Contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Bottom the described contact hole 11 at top, described source region 8, be formed with the P trap draw-out area 9 be made up of P+ district, described P trap draw-out area 9 and described P trap 7 contact.
Be formed with front metal 12 in described silicon substrate 1 front, described front metal 12 draws source electrode and grid respectively.Be formed with back metal 13 at described silicon substrate 1 back side, described back metal 13 draws drain electrode respectively.
As shown in Figure 9, be the embodiment of the present invention two super-junction device profile; With being distinguished as of the embodiment of the present invention one super-junction device: the described channel current dispersion area part of described the second N-type thin layer is positioned at described second high-resistivity portions 3w, part is positioned at described second low resistivity portion 3a, and also namely the described channel current dispersion area of the side of described polysilicon gate 6 is positioned at described second high-resistivity portions 3w, the described channel current dispersion area of opposite side is positioned at described second low resistivity portion 3a.
As shown in Figure 10, be the embodiment of the present invention three super-junction device profile; With being distinguished as of the embodiment of the present invention one super-junction device: the described channel current dispersion area of described the second N-type thin layer is all positioned at described second low resistivity portion 3a.
As shown in figure 11, be the embodiment of the present invention four super-junction device profile; With being distinguished as of the embodiment of the present invention one super-junction device: described P trap 7 top of the both sides of the described gate groove at described the second N-type thin layer top is not all formed with the source region 8 be made up of N+ district, and namely the MOSFET element unit at described the second N-type thin layer top does not have channel current.In another embodiment, described P trap 7 top of the side of the described gate groove at described the second N-type thin layer top is formed with the source region 8 be made up of N+ district, described P trap 7 top of opposite side of described gate groove is not formed with the source region 8 be made up of N+ district, and namely the MOSFET element unit at described the second N-type thin layer top only has a channel current.
As shown in figure 12, be the vertical view in current flowing district of the embodiment of the present invention five super-junction device; With being distinguished as of the embodiment of the present invention one super-junction device: the described the second N-type thin layer in the embodiment of the present invention five is not that the length of length described the first the N-type thin layer that be close to horizontal than it of rectangular i.e. described the second N-type thin layer is completely short, is that the length of described the second N-type thin layer is less than the size in the described current flowing district of its length direction yet.Described the second N-type thin layer is the rectangular of part, only occupies a region of device current flow region; Described the second N-type thin layer also can be distributed in multiple region, and centre by the region of the first N-type thin layer described separately; Which increase the flexibility of design; even if get along well in the distributed areas that all described the second N-type thin layers can be arranged in region described the second N-type thin layer of nonterminal, described terminal protection structure adjoins; the difficulty of Terminal Design can be reduced, increase homogeneity and the stability of device.Described the second N-type thin layer can be evenly distributed or uneven distribution in described current flowing district.
In addition, known with reference to figure 2, in other embodiments, the shape of described the second N-type thin layer can be identical with the shape of the first N-type thin layer described, also can be different, needs and determine according to design.
In other embodiments, can there be more than one width in branch at the described second high-resistivity portions 3w of described the second N-type thin layer of zones of different, expand the adjustable of device layout so further, as long as ensure that described second low resistivity portion 3a can be exhausted by the P type thin layer 4 of surrounding before the critical electric field (Ec) lower than described second low resistivity portion 3a region reaches.
With front described technical scheme unlike, the device in flow of charge district, can there be more than one width in branch at the described second high-resistivity portions 3w of described the second N-type thin layer of zones of different, such MOSFET element unit can be arranged in neighbour region, or some regions are all such devices, reverse recovery characteristic can be improved further like this, as long as ensure that described second low resistivity portion 3a can be exhausted by the P type thin layer 4 of surrounding before the critical electric field (Ec) lower than described second low resistivity portion 3a region reaches.
In above-described embodiment, because N-type thin layer and P type thin layer are all carry out deposit in same groove, the susceptibility between the characteristic of device and the degree of depth of groove declines, and further increases homogeneity and the consistency of device.
As shown in FIG. 13A, be the schematic diagram of Reverse recovery curve; In figure, ta is the time increasing to maximum reverse current at device electric current in turn off process from 0, di/dt in this time period determines primarily of the parameter of external circuit, tb is reduced to from maximum reverse current the time that electric current is 0 in recovery process, the di/dt of this time period determines primarily of the characteristic of diode in body, softness coefficient is S=tb/ta, (or hard recovery characteristics) device of low softness coefficient can cause di/dt very high in recovery process, cause the voltage overshoot that device is high, the electromagnetic interference of component failure, system such as to exceed standard at the problem.Shown in Figure 13 B, be the P type thin layer of the super-junction device of the embodiment of the present invention one and the Reverse recovery curve of N-type thin layer.Curve 17 is the Reverse recovery curve of the body diode of the super-junction device of the embodiment of the present invention, curve 18 is reverse recovery characteristics of the body diode of the existing super-junction device not having high resistivity portion, curve 19 is reverse recovery characteristics of the body diode of the high tension apparatus adopting conventional drift region structure, it is larger than not having the softness coefficient of high resistivity region to find out the softness coefficient of the Reverse recovery of the device of the embodiment of the present invention, the reverse recovery characteristic of the body diode of existing super-junction device is improved, but the reverse recovery characteristic of the high tension apparatus lower than employing conventional migration technique plot structure.
The manufacture method of the embodiment of the present invention one super-junction device comprises the steps:
Step one, as shown in Figure 5, deposit first N-type silicon epitaxial layers 2 on N+ silicon substrate 1.
Step 2, as shown in Figure 5, on described first N-type silicon epitaxial layers 2, deposit forms the second N-type silicon epitaxial layers 3, and the resistivity of described second N-type silicon epitaxial layers 3 is greater than the resistivity of described first N-type silicon epitaxial layers 2; Be preferably, the resistivity of described second N-type silicon epitaxial layers 3 is 45 ohmcms.The described thickness of the second N-type silicon epitaxial layers 3 is identical with the thickness of the second high-resistivity portions 3w of the second N-type thin layer with the first high-resistivity portions 3n of the first N-type thin layer in the current flowing district of follow-up formation.
Step 3, as shown in Figure 5, on described second N-type silicon epitaxial layers 3 surface successively deposit first silicon dioxide layer 31, second silicon nitride layer 32 and the 3rd silicon dioxide layer 33; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer 33, described second silicon nitride layer 32 and described first silicon dioxide layer 31 successively.
Step 4, as shown in Figure 6, forms multiple groove with described groove figure mask for mask carries out etching to described second N-type silicon epitaxial layers 3, and the bottom of described groove described silicon substrate 1 of getting along well is connected; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, described second N-type silicon epitaxial layers 3 between each described groove also defines described first high-resistivity portions 3n and described second high-resistivity portions 3w respectively in laminate structure, and the width of described second high-resistivity portions 3w is greater than the width of described first high-resistivity portions 3n; Described 3rd silicon dioxide layer 33 of described groove figure mask and described second silicon nitride layer 32 are removed successively, described first silicon dioxide layer 31 retains.
Step 5, as shown in Figure 7, the 3rd N-type silicon epitaxial layers is formed in the deposit of described silicon substrate 1 front, described 3rd N-type silicon epitaxy layer is formed at bottom surface and the side of described groove, the ratio of the resistivity of described second N-type silicon epitaxial layers 3 and the resistivity of described 3rd N-type silicon epitaxial layers is 5:1, and the resistivity being preferably the resistivity of described 3rd N-type silicon epitaxial layers is 1 ohmcm ~ 5 ohmcm.In described current flowing district, the described 3rd N-type silicon epitaxy layer being formed at the two sides of described first high-resistivity portions 3n forms the first low resistivity portion 3a, and described first high-resistivity portions 3n and described first low resistivity portion 3a forms the first N-type thin layer; In described current flowing district, the described 3rd N-type silicon epitaxy layer being formed at the two sides of described second high-resistivity portions 3w forms the second low resistivity portion 3a, and described second high-resistivity portions 3w and described second low resistivity portion 3a forms the second N-type thin layer; The N-type thin layer in described current flowing district is made up of the first N-type thin layer described and described the second N-type thin layer.
Step 6, as shown in Figure 7, form the 4th P type silicon epitaxial layers in the deposit of described silicon substrate 1 front, described 4th P type silicon epitaxial layers contacts with described 3rd N-type silicon epitaxial layers and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.
In described current flowing district, form P type thin layer 4 by the described 4th P type silicon epitaxial layers be filled in described groove, the described P type thin layer 4 in described current flowing district and described N-type thin layer are arranged alternately structure.
The charge balance of the first N-type thin layer described and its contiguous described P type thin layer 4, be preferably, the difference of the N-type carrier number of the first N-type thin layer described and the P type carrier number of described P type thin layer 4 be less than the N-type carrier number of the first N-type thin layer described 10% and be less than described P type thin layer 4 P type carrier number 10%.When connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, can having lateral depletion or non-fully having lateral depletion completely mutually between the first N-type thin layer and its contiguous described P type thin layer 4, not being no more than 10% of the first N-type thin layer dosage described by the carrier number of having lateral depletion and being no more than 10% of described P type thin layer 4 dosage of the first N-type thin layer described in during non-fully having lateral depletion or described P type thin layer 4.
The charge unbalance of described the second N-type thin layer and its contiguous described P type thin layer 4, under connecting the condition of reversed bias voltage between described N-type thin layer and described P type thin layer 4, described second low resistivity portion 3a can by the complete having lateral depletion of described P type thin layer 4 be close to, and described second high-resistivity portions 3w is not by the complete having lateral depletion of described P type thin layer 4.
Step 7, as shown in Figure 4, forms P trap 7 at the top of described N-type thin layer and described P type thin layer 4.The formation process of described P trap 7 be placed on step 2 form described second N-type silicon epitaxial layers after, carry out before the first silicon dioxide layer, described second silicon nitride layer and described 3rd silicon dioxide layer described in step 3 deposit, or the formation process of described P trap 7 is placed on after step 6 forms described P type thin layer 4 and described N-type thin layer and carries out.
When connecting reversed bias voltage between described N-type thin layer and described P type thin layer 4, not formed between the part of described P type thin layer 4 having lateral depletion and described P trap 7 of described second high-resistivity portions 3w longitudinally exhausts; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap 7 to described second high-resistivity portions 3w exhausts increases.
Step 8, as shown in Figure 4, adopt lithographic etch process to form gate groove at the top of the described N-type thin layer in described current flowing district, described gate groove is through described P trap 7.
Step 9, as shown in Figure 4, deposit gate dielectric layer 5 and polysilicon gate 6 successively, described gate dielectric layer 5 covers the lower surface of described gate groove and side and outside, described polysilicon gate 6 is formed at described gate dielectric layer 5 surface and is filled completely by described gate groove, remove described gate dielectric layer 5 and the described polysilicon gate 6 of described gate groove outside, be made up of the grid structure of described super junction MOSFET element the described gate dielectric layer 5 and described polysilicon gate 6 that are filled in described gate groove inside.
Described P trap 7 side that covers by described polysilicon gate 6 for the formation of longitudinal channel, the described N-type thin layer immediately below described longitudinal channel is channel current dispersion area; The described channel current dispersion area of the first N-type thin layer described is positioned at described first low resistivity portion 3a.
The described channel current dispersion area of described the second N-type thin layer is all positioned at described second high-resistivity portions 3w.
Step 10, as shown in Figure 4, carries out N+ ion implantation and forms source region 8; Described P trap 7 top of the both sides of the described gate groove at the first N-type thin layer top described is all formed with described source region 8.
Described P trap 7 top of the both sides of the described gate groove at described the second N-type thin layer top is all formed with described source region 8.
Step 11, as shown in Figure 4, forms interlayer film 10 in described silicon substrate 1 front defining source region 8; Adopt lithographic etch process to form contact hole 11, described contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Carry out P+ ion implantation and form P trap draw-out area 9, described P trap draw-out area 9 is positioned at bottom the described contact hole 11 that contacts with described source region 8, and described P trap draw-out area 9 and described P trap 7 contact.
Step 12, as shown in Figure 4, deposit front metal 12 also carries out chemical wet etching to described front metal 12 and forms source electrode and grid respectively; Carry out thinning from the back side to described silicon substrate 1, carry out back metal 13 and change formation drain electrode.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (9)

1. a super-junction device, the zone line of super-junction device is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; It is characterized in that:
Current flowing district comprises multiple N-type thin layer of being alternately arranged and P type thin layer, is formed with P trap at the top of described N-type thin layer and described P type thin layer;
Described N-type thin layer comprises the first N-type thin layer and the second N-type thin layer;
The first N-type thin layer described comprises the first high-resistivity portions and the first low resistivity portion, described first high-resistivity portions is the mid portion of the first N-type thin layer described, and described first low resistivity portion is positioned at the both sides of described first high-resistivity portions and contacts with contiguous described P type thin layer;
The charge balance of the first N-type thin layer described and its contiguous described P type thin layer, and the difference of the P type carrier number of the N-type carrier number of the first N-type thin layer described and described P type thin layer be less than the N-type carrier number equaling the first N-type thin layer described 10% and be less than or equal to described P type thin layer P type carrier number 10%; When connecting reversed bias voltage between described N-type thin layer and described P type thin layer, can having lateral depletion or non-fully having lateral depletion completely mutually between the first N-type thin layer and its contiguous described P type thin layer, not being no more than 10% of the first N-type thin layer dosage described by the carrier number of having lateral depletion and being no more than 10% of described P type thin layer dosage of the first N-type thin layer described in during non-fully having lateral depletion or described P type thin layer;
Described the second N-type thin layer comprises the second high-resistivity portions and the second low resistivity portion, described second high-resistivity portions is the mid portion of described the second N-type thin layer, and described second low resistivity portion is positioned at the both sides of described second high-resistivity portions and contacts with contiguous described P type thin layer; The ratio of the resistivity of described second high-resistivity portions and described second low resistivity portion is greater than 5:1; Described first high-resistivity portions is identical with the resistivity of described second high-resistivity portions, described first low resistivity portion is identical with the resistivity of described second low resistivity portion, and the width of described second high-resistivity portions is greater than the width of described first high-resistivity portions;
The charge unbalance of described the second N-type thin layer and its contiguous described P type thin layer, under connecting the condition of reversed bias voltage between described N-type thin layer and described P type thin layer, described second low resistivity portion can by the complete having lateral depletion of described P type thin layer be close to, described second high-resistivity portions can not by the complete having lateral depletion of described P type thin layer, and not formed between the part of described P type thin layer having lateral depletion and described P trap of described second high-resistivity portions longitudinally exhausts; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap to described second high-resistivity portions exhausts increases.
2. super-junction device as claimed in claim 1, it is characterized in that: described super-junction device is super junction MOSFET element, the gate groove of described P trap is formed through at the top of each described N-type thin layer, be formed with gate dielectric layer in the lower surface of described gate groove and side, be formed with the polysilicon gate of filling described gate groove on gate dielectric layer surface, the described P trap side that covers by described polysilicon gate for the formation of longitudinal channel, the described N-type thin layer immediately below described longitudinal channel is channel current dispersion area; The described channel current dispersion area of the first N-type thin layer described is positioned at described first low resistivity portion;
The described channel current dispersion area of described the second N-type thin layer is all positioned at described second low resistivity portion; Or the described channel current dispersion area of described the second N-type thin layer is all positioned at described second high-resistivity portions; Or the described channel current dispersion area part of described the second N-type thin layer is positioned at described second high-resistivity portions, part is positioned at described second low resistivity portion.
3. super-junction device as claimed in claim 2, is characterized in that: the described P trap top of the both sides of the described gate groove at the first N-type thin layer top described is all formed with the source region be made up of N+ district;
The described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is all formed with the source region be made up of N+ district; Or the described P trap top of the side of the described gate groove at described the second N-type thin layer top is formed with the source region be made up of N+ district, the described P trap top of opposite side of described gate groove is not formed with the source region be made up of N+ district; Or the described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is not all formed with the source region be made up of N+ district.
4. super-junction device as claimed in claim 1, it is characterized in that: overlook on face, the shape of described the second N-type thin layer is identical or different with the shape of the first N-type thin layer described.
5. super-junction device as claimed in claim 1, it is characterized in that: overlook on face, described the second N-type thin layer is evenly distributed or uneven distribution in described current flowing district.
6. super-junction device as claimed in claim 1, is characterized in that: the distributed areas of described the second N-type thin layer described terminal protection structure of getting along well adjoins.
7. a manufacture method for super-junction device, is characterized in that, comprises the steps:
Step one, on N+ silicon substrate deposit first N-type silicon epitaxial layers;
Step 2, on described first N-type silicon epitaxial layers deposit form the second N-type silicon epitaxial layers, the resistivity of described second N-type silicon epitaxial layers is greater than the resistivity of described first N-type silicon epitaxial layers; The described thickness of the second N-type silicon epitaxial layers is identical with the thickness of the second high-resistivity portions of the second N-type thin layer with the first high-resistivity portions of the first N-type thin layer in the current flowing district of follow-up formation;
Step 3, on described second N-type silicon epitaxial layers surface successively deposit first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer; Lithographic etch process is utilized to form groove figure mask to described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer successively;
Step 4, form multiple groove with described groove figure mask for mask carries out etching to described second N-type silicon epitaxial layers, the bottom of described groove described silicon substrate of getting along well is connected; The zone line of super-junction device is described current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; In described current flowing district, described second N-type silicon epitaxial layers between each described groove is laminate structure and defines described first high-resistivity portions and described second high-resistivity portions respectively, and the width of described second high-resistivity portions is greater than the width of described first high-resistivity portions; Described 3rd silicon dioxide layer of described groove figure mask and described second silicon nitride layer are removed successively, described first silicon dioxide layer retains;
Step 5, the deposit of described silicon substrate front formed the 3rd N-type silicon epitaxial layers, described 3rd N-type silicon epitaxy layer is formed at bottom surface and the side of described groove, and the ratio of the resistivity of described second N-type silicon epitaxial layers and the resistivity of described 3rd N-type silicon epitaxial layers is greater than 5:1; In described current flowing district, the described 3rd N-type silicon epitaxy layer being formed at the two sides of described first high-resistivity portions forms the first low resistivity portion, and described first high-resistivity portions and described first low resistivity portion form the first N-type thin layer; In described current flowing district, the described 3rd N-type silicon epitaxy layer being formed at the two sides of described second high-resistivity portions forms the second low resistivity portion, and described second high-resistivity portions and described second low resistivity portion form the second N-type thin layer; The N-type thin layer in described current flowing district is made up of the first N-type thin layer described and described the second N-type thin layer;
Step 6, the deposit of described silicon substrate front formed the 4th P type silicon epitaxial layers, described 4th P type silicon epitaxial layers contacts with described 3rd N-type silicon epitaxial layers and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;
In described current flowing district, form P type thin layer by the described 4th P type silicon epitaxial layers be filled in described groove, the described P type thin layer in described current flowing district and described N-type thin layer are arranged alternately structure;
The charge balance of the first N-type thin layer described and its contiguous described P type thin layer, and the difference of the P type carrier number of the N-type carrier number of the first N-type thin layer described and described P type thin layer be less than the N-type carrier number equaling the first N-type thin layer described 10% and be less than or equal to described P type thin layer P type carrier number 10%; When connecting reversed bias voltage between described N-type thin layer and described P type thin layer, can having lateral depletion or non-fully having lateral depletion completely mutually between the first N-type thin layer and its contiguous described P type thin layer, not being no more than 10% of the first N-type thin layer dosage described by the carrier number of having lateral depletion and being no more than 10% of described P type thin layer dosage of the first N-type thin layer described in during non-fully having lateral depletion or described P type thin layer;
The charge unbalance of described the second N-type thin layer and its contiguous described P type thin layer, under connecting the condition of reversed bias voltage between described N-type thin layer and described P type thin layer, described second low resistivity portion can by the complete having lateral depletion of described P type thin layer be close to, and described second high-resistivity portions can not by the complete having lateral depletion of described P type thin layer;
Step 7, formation P trap, described P trap is positioned at the top of described N-type thin layer and described P type thin layer; When connecting reversed bias voltage between described N-type thin layer and described P type thin layer, not formed between the part of described P type thin layer having lateral depletion and described P trap of described second high-resistivity portions longitudinally exhausts; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap to described second high-resistivity portions exhausts increases; The formation process of described P trap be placed on step 2 form described second N-type silicon epitaxial layers after, carry out before the first silicon dioxide layer, described second silicon nitride layer and described 3rd silicon dioxide layer described in step 3 deposit, or the formation process of described P trap is placed on after step 6 forms described P type thin layer and described N-type thin layer and carries out.
8. method as claimed in claim 7, it is characterized in that, described super-junction device is super junction MOSFET element, also comprises the steps:
Step 8, employing lithographic etch process form gate groove at the top of the described N-type thin layer in described current flowing district, and described gate groove is through described P trap;
Step 9, successively deposit gate dielectric layer and polysilicon gate, described gate dielectric layer covers the lower surface of described gate groove and side and outside, described polysilicon gate is formed at described gate dielectric layer surface and is filled completely by described gate groove, remove the described gate dielectric layer of described gate groove outside and described polysilicon gate, be made up of the grid structure of described super junction MOSFET element the described gate dielectric layer and described polysilicon gate that are filled in described gate groove inside;
The described P trap side that covers by described polysilicon gate for the formation of longitudinal channel, the described N-type thin layer immediately below described longitudinal channel is channel current dispersion area; The described channel current dispersion area of the first N-type thin layer described is positioned at described first low resistivity portion;
The described channel current dispersion area of described the second N-type thin layer is all positioned at described second low resistivity portion; Or the described channel current dispersion area of described the second N-type thin layer is all positioned at described second high-resistivity portions; Or the described channel current dispersion area part of described the second N-type thin layer is positioned at described second high-resistivity portions, part is positioned at described second low resistivity portion.
9. method as claimed in claim 8, is characterized in that, also comprise the steps:
Step 10, carry out N+ ion implantation formed source region; The described P trap top of the both sides of the described gate groove at the first N-type thin layer top described is all formed with described source region;
The described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is all formed with described source region; Or the described P trap top of the side of the described gate groove at described the second N-type thin layer top is formed with described source region, the described P trap top of opposite side of described gate groove is not formed with described source region; Or the described P trap top of the both sides of the described gate groove at described the second N-type thin layer top is not all formed with described source region;
Step 11, form interlayer film in the described silicon substrate front defining source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact;
Step 12, deposit front metal chemical wet etching is carried out to described front metal form source electrode and grid respectively; Carry out thinning from the back side to described silicon substrate, carry out back face metalization and form drain electrode.
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US20080211020A1 (en) * 2007-01-25 2008-09-04 Kabushi Kaisha Toshiba Semiconductor apparatus
CN102386212A (en) * 2010-08-31 2012-03-21 上海华虹Nec电子有限公司 Semiconductor device structure and manufacturing method thereof
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CN101013724A (en) * 2006-01-31 2007-08-08 株式会社电装 Semiconductor device having super junction structure and method for manufacturing the same
US20080211020A1 (en) * 2007-01-25 2008-09-04 Kabushi Kaisha Toshiba Semiconductor apparatus
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