CN104425600B - Super-junction device and manufacture method - Google Patents
Super-junction device and manufacture method Download PDFInfo
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- CN104425600B CN104425600B CN201310380359.1A CN201310380359A CN104425600B CN 104425600 B CN104425600 B CN 104425600B CN 201310380359 A CN201310380359 A CN 201310380359A CN 104425600 B CN104425600 B CN 104425600B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 26
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
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- 238000005530 etching Methods 0.000 claims description 5
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a kind of super-junction device, electric current flowing area includes multiple N-type thin layers and p-type thin layer being alternately arranged, N-type thin layer includes two kinds, and two kinds of N-type thin layers all include the charge balance of the high resistance portion of centre and the low resistance part of both sides, the first N-type thin layer and p-type thin layer；The high-resistivity portions of second N-type thin layer are wider, and second N-type thin layer and p-type thin layer charge unbalance.After p-type thin layer is to second N-type thin layer having lateral depletion, as the p-well at the top of the increase N-type thin layer of reverse biased exhausts to the longitudinal direction that the high-resistivity portions of second N-type thin layer are gradually extended.The invention also discloses a kind of manufacture method of super-junction device.The present invention can improve the reverse recovery characteristic of device, and more relatively low than conducting resistance.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacture field, more particularly to a kind of super-junction device；The present invention is also related to
And a kind of manufacture method of super-junction device.
Background technology
Super junction MOSFET uses new structure of voltage-sustaining layer, using a series of P-type semiconductor thin layer and N being alternately arranged
Type semiconductor lamella in the off state at the lower voltage just consumes the P-type semiconductor thin layer and N-type semiconductor thin layer
To the greatest extent, realize that electric charge is mutually compensated for, so that P-type semiconductor thin layer and N-type semiconductor thin layer can realize height under high-dopant concentration
Breakdown voltage so that simultaneously obtain low on-resistance and high-breakdown-voltage, break traditions power MOSFET theoretical limits.In U.S.
In state patent US5216275, the P-type semiconductor thin layer being alternately arranged and N-type semiconductor thin layer of the above are connected with N+ substrates
's；In United States Patent (USP) US6630698B1, middle P-type semiconductor thin layer and N-type semiconductor thin layer can have greatly with N+ substrates
In 0 interval.
In the prior art, formation one kind of P-type semiconductor thin layer and N-type semiconductor thin layer is by epitaxial growth and then enters
Row photoetching and injection, repeatedly the P-type semiconductor thin layer and N-type semiconductor thin layer of the thickness that the process is needed repeatedly, this
Technique is generally required and is repeated 5 times the above in the MOSFET of more than 600V, and production cost and production cycle are long.Another kind is logical
Cross after a type of extension for needing thickness of a secondary growth, carry out the etching of groove, insert opposite class in the trench afterwards
The silicon of type；Although this method difficulty is big, with simplification of flowsheet, the effect of stability is improved；Using groove structure it
Afterwards, because P/N thin layers are P-type semiconductor thin layer and N-type half in the P-type semiconductor thin layer and N-type semiconductor thin layer being alternately arranged
Doping concentration of the conductor thin layer on longitudinal direction is easily controllable, and p-type is partly led in the thin layer caused without multiple epitaxy technique
Body thin layer and N-type semiconductor thin layer or the doping concentration of one of them change so as to bring additional longitudinal direction electricity in the vertical
, it is ensured that leakage current characteristic and breakdown voltage high that device can be obtained.
In super junction technique, as a result of alternate P/N thin layers, the internal diode of super-junction device is p-type half
Such as 50 volts Vds will partly lead p-type the diode formed between conductor thin layer and N-type semiconductor thin layer at lower voltages
Body thin layer and N-type semiconductor thin layer it is completely depleted fall, this cause the diode have very hard reverse recovery characteristic, this is hard
Reverse recovery characteristic causes the restoring current of device drastically to change, so as to cause voltage overshoot very high that device may be brought to lose
Effect.Simultaneously because the drastically change of electric current and voltage can cause the electromagnetic interference in circuit with di/dt and dv/dt very high
（EMI-ELEACTROMAGENETIC INTERFERENCE）, bring influence even EMI exceeded on system, it is at this point, super
Junction device is not as conventional MOSFET element, because exhausting for the MOSFET element N- drift regions of routine is always with voltage
(Vds) increase and extend, reverse recovery characteristic is softer.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of super-junction device, and the Reverse recovery that can improve device is special
Property, and it is more relatively low than conducting resistance.Therefore, the present invention also provides a kind of manufacture method of super-junction device.
In order to solve the above technical problems, the zone line of the super-junction device of present invention offer is electric current flowing area, terminal
Protection structure is surrounded on the periphery in the electric current flowing area；Electric current flowing area includes that multiple N-type thin layers being alternately arranged and p-type are thin
Layer, p-well is formed with the top of the N-type thin layer and the p-type thin layer.
The N-type thin layer includes the first N-type thin layer and second N-type thin layer.
Described the first N-type thin layer includes the first high-resistivity portions and the first low resistivity portion, the described first electricity high
Resistance commands troops to be divided into the center section of the first N-type thin layer, and first low resistivity portion is located at first high resistance
The both sides of rate part and it is in contact with the neighbouring p-type thin layer.
The charge balance of described the first N-type thin layer and its neighbouring p-type thin layer, and described the first N-type thin layer
N-type carrier number and the difference of p-type carrier number of the p-type thin layer be less than N-type equal to the first N-type thin layer
The 10% of carrier number and 10% of the p-type carrier number less than or equal to the p-type thin layer；The N-type thin layer and the p-type
When connecting reversed bias voltage between thin layer, can entirely laterally be consumed mutually between the first N-type thin layer and its neighbouring described p-type thin layer
To the greatest extent or non-fully having lateral depletion, non-fully during having lateral depletion described in the first N-type thin layer or the p-type thin layer do not consumed laterally
Most carrier number is no more than the 10% and no more than the p-type thin layer dosage 10% of the first the N-type thin layer dosage.
Second N-type thin layer includes the second high-resistivity portions and the second low resistivity portion, the described second electricity high
Resistance commands troops to be divided into the center section of second N-type thin layer, and second low resistivity portion is located at second high resistance
The both sides of rate part and it is in contact with the neighbouring p-type thin layer；Second high-resistivity portions and second low resistance
The ratio between resistivity of rate part is more than 5:1；The resistivity of first high-resistivity portions and second high-resistivity portions
Identical, first low resistivity portion is identical with the resistivity of second low resistivity portion, second high resistivity
Width of the partial width more than first high-resistivity portions.
The charge unbalance of second N-type thin layer and its neighbouring p-type thin layer, the N-type thin layer and the P
Between type thin layer connect reversed bias voltage under conditions of, second low resistivity portion can be complete by the neighbouring p-type thin layer
Having lateral depletion, second high-resistivity portions can not entirely laterally be exhausted by the p-type thin layer, and second high resistance is commanded troops
That divides is not formed longitudinal exhausting between the part of the p-type thin layer having lateral depletion and the p-well；When reversed bias voltage increases,
The depth that the p-well exhausts to the longitudinal direction of second high-resistivity portions increases.
Further improvement is that the super-junction device is super junction MOSFET element, at the top of each N-type thin layer
The gate groove of the p-well is formed through, gate dielectric layer is formed with the lower surface of the gate groove and side, in gate medium
Layer surface is formed with the polysilicon gate for filling the gate groove, and the p-well side covered by the polysilicon gate is used for shape
Into longitudinal channel, the N-type thin layer of the underface of the longitudinal channel is channel current dispersion area；Described the first N-type is thin
The channel current dispersion area of layer is located at first low resistivity portion.
The channel current dispersion area of second N-type thin layer is all located at second low resistivity portion；Or
The channel current dispersion area of second N-type thin layer is all located at second high-resistivity portions；Or described second
It is low that the channel current dispersion area part of kind N-type thin layer is located at described second positioned at second high-resistivity portions, partly
Resistivity portion.
Further improvement is, at the top of the p-well of the both sides of the gate groove at the top of described the first N-type thin layer
All be formed with by N+ district's groups into source region.
All it is formed with by N+ areas at the top of the p-well of the both sides of the gate groove at the top of second N-type thin layer
The source region of composition；Or, it is formed with the top of the p-well of the side of the gate groove at the top of second N-type thin layer
By N+ district's groups into source region, the p-well of the opposite side of the gate groove top be formed without by N+ district's groups into source region；Or
Person, be all formed without at the top of the p-well of the both sides of the gate groove at the top of second N-type thin layer by N+ district's groups into
Source region.
Further improvement is, on vertical view face, the shape of second N-type thin layer and described the first N-type thin layer
Shape is identical or difference.
Further improvement is, on vertical view face, second N-type thin layer is in the electric current flowing area in uniform point
Cloth or uneven distribution.
Further improvement is that the distributed areas discord terminal protection structure of second N-type thin layer is abutted.
In order to solve the above technical problems, the manufacture method of the super-junction device of present invention offer comprises the following steps：
Step one, the first N-type silicon epitaxial layers are deposited on N+ silicon substrates.
Step 2, the second N-type silicon epitaxial layers of deposit formation, the second N-type extension on the first N-type silicon epitaxial layers
Resistivity of the resistivity of silicon layer more than the first N-type silicon epitaxial layers；The thickness and follow-up shape of the second N-type silicon epitaxial layers
Into electric current flowing area the first N-type thin layer the first high-resistivity portions and second second high resistivity of N-type thin layer
Partial thickness is identical.
Step 3, the second N-type silicon epitaxial layers surface deposit successively the first silicon dioxide layer, the second silicon nitride layer and
3rd silicon dioxide layer；Using lithographic etch process successively to the 3rd silicon dioxide layer, second silicon nitride layer and institute
State the first silicon dioxide layer and form groove figure mask.
Step 4, the second N-type silicon epitaxial layers are performed etching to form multiple by mask of the groove figure mask
Groove, the bottom discord silicon substrate of the groove is connected；The zone line of super-junction device is the electric current flowing area,
Terminal protection structure is surrounded on the periphery in the electric current flowing area；In the electric current flowing area, the institute between each groove
The second N-type silicon epitaxial layers are stated in laminate structure and first high-resistivity portions and second high resistivity is defined respectively
Part, the width of the width more than first high-resistivity portions of second high-resistivity portions；Successively by the groove
3rd silicon dioxide layer of pattern mask and second silicon nitride layer are removed, and first silicon dioxide layer retains.
Step 5, deposit to form the 3rd N-type silicon epitaxial layers in the silicon substrate front, the 3rd N-type silicon epitaxy layer shape
The electricity of the bottom surface and side of groove described in Cheng Yu, the resistivity of the second N-type silicon epitaxial layers and the 3rd N-type silicon epitaxial layers
The ratio between resistance rate is more than 5:1；In the electric current flowing area, described the of the two sides of first high-resistivity portions is formed at
Three N-type silicon epitaxy layers constitute the first low resistivity portion, first high-resistivity portions and first low resistivity portion
Constitute the first N-type thin layer；In the electric current flowing area, be formed at second high-resistivity portions two sides it is described
3rd N-type silicon epitaxy layer constitutes the second low resistivity portion, and second high-resistivity portions and second low resistance are commanded troops
It is grouped into second N-type thin layer；The electric current flowing area is constituted by described the first N-type thin layer and second N-type thin layer
N-type thin layer.
Step 6, deposit to form the 4th p-type silicon epitaxial layers in the silicon substrate front, the 4th p-type silicon epitaxial layers and
Simultaneously be fully filled with for the groove by the 3rd N-type silicon epitaxial layers contact；By the silicon and silica of the groove top surface all
Removal.
In the electric current flowing area, p-type is constituted by the 4th p-type silicon epitaxial layers being filled in the groove thin
Layer, the p-type thin layer and the N-type thin layer in the electric current flowing area are arranged alternately structure.
The charge balance of described the first N-type thin layer and its neighbouring p-type thin layer, and described the first N-type thin layer
N-type carrier number and the difference of p-type carrier number of the p-type thin layer be less than N-type equal to the first N-type thin layer
The 10% of carrier number and 10% of the p-type carrier number less than or equal to the p-type thin layer；The N-type thin layer and the p-type
When connecting reversed bias voltage between thin layer, can entirely laterally be consumed mutually between the first N-type thin layer and its neighbouring described p-type thin layer
To the greatest extent or non-fully having lateral depletion, non-fully during having lateral depletion described in the first N-type thin layer or the p-type thin layer do not consumed laterally
Most carrier number is no more than the 10% and no more than the p-type thin layer dosage 10% of the first the N-type thin layer dosage.
The charge unbalance of second N-type thin layer and its neighbouring p-type thin layer, the N-type thin layer and the P
Between type thin layer connect reversed bias voltage under conditions of, second low resistivity portion can be complete by the neighbouring p-type thin layer
Having lateral depletion, second high-resistivity portions can not entirely laterally be exhausted by the p-type thin layer.
Step 7, the p-well that formed, the p-well are located at the top of the N-type thin layer and the p-type thin layer；The N-type thin layer
And the p-type thin layer between connect reversed bias voltage when, second high-resistivity portions not by the p-type thin layer having lateral depletion
Part and the p-well between formed longitudinal direction exhaust；When reversed bias voltage increases, the p-well is commanded troops to second high resistance
The depth that the longitudinal direction divided exhausts increases；The formation process of the p-well be placed on step 2 formed the second N-type silicon epitaxial layers it
Afterwards, step 3 is carried out before depositing first silicon dioxide layer, second silicon nitride layer and the 3rd silicon dioxide layer,
Or the formation process of the p-well is placed on after step 6 forms the p-type thin layer and the N-type thin layer and carries out.
Further improvement is that the super-junction device is super junction MOSFET element, is also comprised the following steps：
Step 8, using lithographic etch process the N-type thin layer in the electric current flowing area top formed gate groove,
The gate groove passes through the p-well.
Step 9, successively deposit gate dielectric layer and polysilicon gate, the gate dielectric layer are covered in the bottom of the gate groove
Surface and side and outside, the polysilicon gate are formed at the gate dielectric layer surface and are filled up completely with the gate groove,
The gate dielectric layer and the polysilicon gate outside the gate groove are removed, by the grid being filled in inside the gate groove
Dielectric layer and the polysilicon gate constitute the grid structure of the super junction MOSFET element.
The p-well side covered by the polysilicon gate is used to form longitudinal channel, the longitudinal channel just under
The N-type thin layer of side is channel current dispersion area；The channel current dispersion area of the first N-type thin layer is located at described
First low resistivity portion.
The channel current dispersion area of second N-type thin layer is all located at second low resistivity portion；Or
The channel current dispersion area of second N-type thin layer is all located at second high-resistivity portions；Or described second
It is low that the channel current dispersion area part of kind N-type thin layer is located at described second positioned at second high-resistivity portions, partly
Resistivity portion.
Further improvement is also to comprise the following steps：
Step 10, carry out N+ ion implantings formed source region；Two of the gate groove at the top of described the first N-type thin layer
The p-well top of side is all formed with the source region.
The source is all formed with the top of the p-well of the both sides of the gate groove at the top of second N-type thin layer
Area；Or, be formed with the top of the p-well of the side of the gate groove at the top of second N-type thin layer the source region,
The p-well top of the opposite side of the gate groove is formed without the source region；Or, at the top of second N-type thin layer
The gate groove both sides the p-well top be all formed without the source region.
Step 11, foring source region the silicon substrate front formed interlayer film；Formed using lithographic etch process
Contact hole, the contact hole is contacted through the interlayer film and with the source region or the polysilicon gate；Carry out P+ ion implantings
Form p-well draw-out area, the contact hole bottom that the p-well draw-out area is located at and the source region is in contact, the p-well draw-out area
It is in contact with the p-well.
Step 12, deposit front metal simultaneously carry out chemical wet etching and form source electrode and grid respectively to the front metal；
The silicon substrate is carried out from the back side it is thinning, carry out back face metalization formed drain electrode.
The electric current flowing area of super-junction device of the present invention includes two kinds of N-type thin layers, and two kinds of N-type thin layers all include low-resistivity
Part and high-resistivity portions, the doping and width for adjusting low resistivity portion are readily available relatively low ratio conducting resistance, high
Gradual output capacitance is provided under resistivity portion energy high tension voltage.
In addition, the present invention is increased by by the width of second second high-resistivity portions of N-type thin layer, and make second high
Resistivity portion is not exhausted entirely laterally in reverse bias by p-type thin layer, so when reversed bias voltage increases, can be by position
P-well at the top of N-type thin layer exhausts the depth of simultaneously longitudinal depletion region to the longitudinal direction of the second high-resistivity portions with reverse biased
Increase and increase, the hard reverse recovery characteristic of device is softened, so as to improve the reverse recovery characteristic of device, reduce
Restoring current impacts.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is existing super-junction device top view one；
Fig. 2 is existing super-junction device top view two；
Fig. 3 is the top view in the electric current flowing area of the super-junction device of the embodiment of the present invention one；
Fig. 4 is the profile of the super-junction device of the embodiment of the present invention one；
Fig. 5-Fig. 8 is the device profile map in each step of manufacture method of the super-junction device of the embodiment of the present invention one；
Fig. 9 is the profile of the super-junction device of the embodiment of the present invention two；
Figure 10 is the profile of the super-junction device of the embodiment of the present invention three；
Figure 11 is the profile of the super-junction device of the embodiment of the present invention four；
Figure 12 is the top view in the electric current flowing area of the super-junction device of the embodiment of the present invention five；
Figure 13 A are the schematic diagrams of Reverse recovery curve；
Figure 13 B are the p-type thin layer of the super-junction device of the embodiment of the present invention one and the Reverse recovery curve of N-type thin layer.
Specific embodiment
As shown in figure 1, being the top view one of existing super-junction device.On top view, the embodiment of the present invention can be divided into 1
Area, 2nd area and 3rd area.1st area is electric current flowing area for the zone line of super-junction device, and the electric current flowing area includes and is alternately arranged
P type island region domain 25 and N-type region domain, the p type island region domain 25 namely the p-type thin layer being formed in the electric current flowing area, the N-type
Region namely the N-type thin layer being formed in the electric current flowing area；In the electric current flowing area, electric current can be by N-type region domain by source
Pole reaches by raceway groove and drains, and the p type island region domain 25 is to form depletion region one with the N-type region domain under reverse blocking state
Rise and bear voltage.2nd area and the terminal protection structure region that 3rd area are the super-junction device, in break-over of device, the terminal is protected
Protection structure does not provide electric current, is used to undertake from the 1 area periphery unit i.e. surface in periphery p type island region domain 25 to device in reverse blocking state
The voltage of the part outer-most end surface substrate voltage is lateral voltage and the voltage voltage from 1 area periphery cell surface to substrate is
Longitudinal voliage.There is at least one p-type ring 24 in 2nd area, be a p-type ring 24 in Fig. 1, the p-type ring 24 is typically carried on the back with the p-type in 1st area
Grid are that p-well links together；There is the field plate dielectric film with certain inclination angle in 2nd area, also have for slowing down surface in 2nd area
Electric field polycrystalline field plate piece jumpy and Metal field plate, and p-type post 23；The Metal field plate can also be not provided with 2nd area.
3rd area undertake area by the voltage that p-type post 23 is alternatively formed with the N-type post being made up of N-type silicon epitaxy layer, have deielectric-coating thereon, institute
State p-type post 23 namely be formed in the terminal protection structure p-type thin layer, the N-type post namely be formed at the terminal and protect
N-type thin layer in protection structure；There is Metal field plate in 3rd area, the Metal field plate can also be not provided with 3rd area；There can be P in 3rd area
Type ring 24 can also not have, and p-type ring when having p-type ring 24 at this is not to be connected with the p-type back-gate connection in electric current flowing area（It is outstanding
Floating）；Outermost end in 3rd area has channel cutoff ring 21, and the channel cutoff ring 21 adds shape again by N+ injection regions or N+ injection regions
Constituted plus metal into medium thereon or medium；There can be additional small p-type post at four angles in the p-type post 23
22, preferably to realize charge balance.As seen from Figure 1, the cellular construction in the electric current flowing area is the p type island region domain
25 and N-type region domain all be strip structure；The terminal protection structure is surrounded on the periphery in the electric current flowing area and the p-type ring
24th, the p-type post 23 and the channel cutoff ring 21 are all in the cyclic structure of square, it is also possible to which there is circle the corner in square
The cyclic structure of arc.
As shown in Fig. 2 be the top view two of existing super-junction device, and structure difference as shown in Figure 1 is,
The cellular construction in the electric current flowing area is that the p type island region domain 25 and N-type region domain are all tetragonal structure, i.e., by the institute of square
Proper alignment constitutes the cell array in the electric current flowing area in the two-dimensional direction to state p type island region domain 25 and N-type region domain.The p-type
Region 25 and N-type region domain also can be the arrangement mode of hexagon, octagon and other shapes, the p type island region domain 25 and N-type region domain
Also certain dislocation can be carried out in X, and Y-direction；As long as ensureing that whole arrangement is that, by certain rule, repeat can
With.
The additional small p-type post 22 of corner in Fig. 1 and Fig. 2, can design according to the optimized requirement of local charge balance,
If the width of the p-type post 23 is a, the distance between the p-type post 23 and the p-type post 23 are also a, then the small P
It is the square p-type hole of 0.3~0.5a that type post 22 can use the length of side.
In existing super junction MOSFET element, MOSFET element list is all formed with above the N-type thin layer in electric current flowing area
Unit, the N-type thin layer in electric current flowing area, p-type thin layer and MOSFET element unit are repeated completely, for example, be to a breakdown voltage
As a example by 600V is the device of BVds-600V：The N+ silicon substrates of device are uniform, and resistivity is 0.001-0.003 ohm li
Rice, deposition thickness is 45 microns on N+ substrates, and resistivity is the N-type of the Uniform Doped of 1 ohmcm~5 ohmcm
Silicon epitaxial layers or the N-type silicon epitaxial layers changed along longitudinal impurity concentration;Groove is formed afterwards, and p-type epitaxial silicon is filled in the trench
Layer, p-type silicon epitaxial layers can be along longitudinal Uniform Doped, or along longitudinally varying doping, after such etching groove
The p-type thin layer for leaving N-type thin layer and extension filling just constitutes the alternate P-N thin layers of super-junction device by p-type thin layer and N-type
Thin layer；In electric current flowing area, except close to the region of device terminal, probably due to Terminal Design and technique cause some different
Outward, all of device cell is consistent, and in the horizontal, the structure of P-N thin layers is to repeat completely.
As shown in figure 3, being the top view in the electric current flowing area of the super-junction device of the embodiment of the present invention one；As shown in figure 4, being
The profile of the super-junction device of the embodiment of the present invention one.
The zone line of the super-junction device of the embodiment of the present invention one is electric current flowing area, and terminal protection structure is surrounded on described
The periphery in electric current flowing area.
Electric current flowing area includes multiple N-type thin layers and p-type thin layer 4 being alternately arranged, in the N-type thin layer and the p-type
The top of thin layer 4 is formed with p-well 7, and the N-type thin layer and the p-type thin layer 4 are formed at the top of the first N-type silicon epitaxial layers 2,
The first N-type silicon epitaxial layers 2 are formed on N+ silicon substrates 1.
From figure 3, it can be seen that the p-type thin layer 4 corresponds to the thin layer between B1B2, B3B4, B5B6, B7B8 etc., the N
Type thin layer corresponds to the thin layer between B0B1, B2B3, B4B5, B6B7, B8B9 etc., it can be seen that the p-type thin layer 4 and the N
Type thin layer all for strip structure and is alternately arranged.
The N-type thin layer includes the first N-type thin layer and second N-type thin layer, and the first N-type thin layer corresponds in Fig. 3
Narrower thin layer between B0B1, B2B3, B6B7, B8B9 etc.；Second N-type thin layer is corresponding to wider between B4B5 in Fig. 3 etc.
Thin layer.
Described the first N-type thin layer includes the first high-resistivity portions 3n and the first low resistivity portion 3a, described first
High-resistivity portions 3n is the center section of the first N-type thin layer, and the first low resistivity portion 3a is located at described the
The both sides of one high-resistivity portions 3n and it is in contact with the neighbouring p-type thin layer 4.As shown in figure 3, first high resistivity
Part 3n is the part between C0D0, C1D1, C3D3 and C4D4 etc..Described the first N-type thin layer and its neighbouring described p-type are thin
The charge balance of layer 4, preferably, the p-type carrier of the N-type carrier number of the first N-type thin layer and the p-type thin layer 4
Several differences is less than the 10% of the N-type carrier number of the first N-type thin layer and is carried less than the p-type of the p-type thin layer 4
The 10% of stream subnumber.When connecting reversed bias voltage between the N-type thin layer and the p-type thin layer 4, the first N-type thin layer is neighbouring with its
The p-type thin layer 4 between can entirely laterally exhaust mutually or non-fully having lateral depletion, such as reach 50V or so in reverse biased
Or more when between the first N-type thin layer and its neighbouring described p-type thin layer 4 just mutually entirely laterally exhaust or non-fully laterally
Exhaust；Non-fully during having lateral depletion described in the first N-type thin layer or the p-type thin layer 4 not by the carrier number of having lateral depletion
No more than the first the N-type thin layer dosage 10% and no more than the dosage of p-type thin layer 4 10%.In preferred embodiment
In, the charge balance of described the first N-type thin layer and the two thin layers of p-type thin layer 4 will be by adjusting their laterally wide
Degree and impurity concentration are realized；Described the first N-type thin layer as super-junction device thin layer, the p-type thin layer 4 with surrounding reaches
To charge balance, generally require in the range of the license of lithographic etch process ability, control the first high-resistivity portions 3n
Width try one's best it is small such as less than 0.5 micron, with ratio conducting resistance optimized, low.
Second N-type thin layer includes the second high-resistivity portions 3w and the second low resistivity portion 3a, and the present invention is real
Applying the first low resistivity portion 3a described in example one and the second low resistivity portion 3a has identical process structure, therefore adopts
Marked with identical and represented.The second high-resistivity portions 3w is the center section of second N-type thin layer, described second
Low resistivity portion 3a is located at the both sides of the second high-resistivity portions 3w and is in contact with the neighbouring p-type thin layer 4；Institute
The ratio between resistivity of the second high-resistivity portions 3w and the second low resistivity portion 3a is stated more than 5:1；Described first electricity high
Resistance rate part 3n is identical with the resistivity of the second high-resistivity portions 3w, the first low resistivity portion 3a and described
The resistivity of two low resistivity portion 3a is identical, and the width of the second high-resistivity portions 3w is more than first high resistivity
The width of part 3n.In the preferred embodiment, the resistivity of the second high-resistivity portions 3w is 45 ohmcms, described
The resistivity of the second low resistivity portion 3a is 1 ohmcm~5 ohmcm.
The charge unbalance of second N-type thin layer and its neighbouring p-type thin layer 4, the N-type thin layer and described
Connected between p-type thin layer 4 under conditions of reversed bias voltage, the second low resistivity portion 3a can be by the neighbouring p-type thin layer 4
Entirely laterally exhaust, the second high-resistivity portions 3w is not exhausted entirely laterally by the p-type thin layer 4, the described second electricity high
Resistance rate part 3w's is not formed longitudinal exhausting between the part of the having lateral depletion of p-type thin layer 4 and the p-well 7；In reverse-biased electricity
When pressure increases, the depth that the longitudinal direction of the second high-resistivity portions 3w of the p-well 7 pairs exhausts increases.
For longitudinal direction, if the thickness of second N-type thin layer is sufficiently thick, it is ensured that during device breakdown, institute
The second high-resistivity portions 3w is stated not to be depleted completely；If the thickness low LCL of second N-type thin layer is thick, described the
Two high-resistivity portions 3w can just be depleted before breakdown voltage reaches, then will terminate in the first N-type epitaxial silicon
The region of layer 2；No matter in which kind of situation, the design in the second high-resistivity portions 3w regions all can improve body diode i.e.
The reverse recovery characteristic of the diode that the p-type thin layer and the N-type thin layer are formed, so as to improve the Reverse recovery of whole device
Characteristic；More than in this device, using the part of the second high-resistivity portions 3w, the Reverse recovery for improving device is special
Property；The width of the second high-resistivity portions 3w parts is bigger, and component is bigger, and the reverse recovery characteristic of device is softer, but by
It is high resistivity in the second high-resistivity portions 3w parts, the accounting with the second high-resistivity portions 3w increases,
The conducting resistance of device can be correspondingly improved.
The super-junction device of the embodiment of the present invention one is super junction MOSFET element, at the top of each N-type thin layer
A MOSFET element unit is all formed with, the gate groove of the p-well 7 is formed through at the top of each N-type thin layer,
The lower surface of the gate groove and side are formed with gate dielectric layer 5, are formed with the filling gate groove on the surface of gate dielectric layer 5
Polysilicon gate 6, the gate dielectric layer 5 be gate oxide.The side of the p-well 7 covered by the polysilicon gate 6 is used for shape
Into longitudinal channel, the N-type thin layer of the underface of the longitudinal channel is channel current dispersion area；Described the first N-type is thin
The channel current dispersion area of layer is located at the first low resistivity portion 3a.
The channel current dispersion area of second N-type thin layer is all located at the second high-resistivity portions 3w.
The top of the p-well 7 of the both sides of the gate groove at the top of described the first N-type thin layer is all formed with by N+ areas
The source region 8 of composition.
The top of the p-well 7 of the both sides of the gate groove at the top of second N-type thin layer is all formed with by N+ areas
The source region 8 of composition.
Interlayer film 10 is formed with the front of the silicon substrate 1；Contact hole 11 passes through the interlayer film 10 and and the source region 8
Or the polysilicon gate 6 is contacted；The bottom of the contact hole 11 at the top of the source region 8 be formed with by P+ district's groups into p-well draw
Go out area 9, the p-well draw-out area 9 and the p-well 7 are in contact.
Front metal 12 is formed with the front of the silicon substrate 1, the front metal 12 draws source electrode and grid respectively.
The back side of the silicon substrate 1 is formed with back metal 13, and the back metal 13 draws drain electrode respectively.
As shown in figure 9, being the profile of the super-junction device of the embodiment of the present invention two；With the super junction of the embodiment of the present invention one
Device is distinguished as：Commanded troops positioned at second high resistance channel current dispersion area part of second N-type thin layer
Divide 3w, be partly located at the second low resistivity portion 3a, namely the channel current of the side of the polysilicon gate 6 disperses
Area is located at the second high-resistivity portions 3w, the channel current dispersion area of opposite side and is commanded troops positioned at second low resistance
Divide 3a.
As shown in Figure 10, it is the profile of the super-junction device of the embodiment of the present invention three；It is super with the embodiment of the present invention one
Junction device is distinguished as：The channel current dispersion area of second N-type thin layer is all located at second low resistance and commands troops
Divide 3a.
As shown in figure 11, it is the profile of the super-junction device of the embodiment of the present invention four；It is super with the embodiment of the present invention one
Junction device is distinguished as：The all non-shape in the top of the p-well 7 of the both sides of the gate groove at the top of second N-type thin layer
Into have by N+ district's groups into source region 8, i.e., the MOSFET element unit at the top of described second N-type thin layer do not have channel current.
In another embodiment, the top of the p-well 7 of the side of the gate groove at the top of second N-type thin layer is formed with by N
+ district's groups into source region 8, the top of the p-well of the opposite side of the gate groove 7 be formed without by N+ district's groups into source region 8, i.e. institute
State the MOSFET element unit only one of which channel current at the top of second N-type thin layer.
As shown in figure 12, be the super-junction device of the embodiment of the present invention five electric current flowing area top view；With reality of the present invention
Apply being distinguished as the super-junction device of example one：Second N-type thin layer in the embodiment of the present invention five is not complete one long
Bar is that the length of second N-type thin layer is shorter than the length of its first N-type thin layer laterally adjacent to described in, namely described
Two kinds of length of N-type thin layer are smaller than the size in the electric current flowing area of its length direction.Second N-type thin layer is portion
The strip divided, only occupies a region of device current flow region；Second N-type thin layer can also be distributed in multiple regions,
Centre is separated by the region of the first N-type thin layer；The flexibility of design is which increased, can be by all of described second
Even if N-type thin layer is arranged in the distributed areas discord terminal protection structure of region second N-type thin layer of nonterminal
It is adjacent, it is possible to reduce the difficulty of Terminal Design, increase the homogeneity and stability of device.Second N-type thin layer is described
Can be evenly distributed or uneven distribution in electric current flowing area.
In addition, understanding, in other embodiments, the shape of second N-type thin layer and described the first N with reference to Fig. 2
The shape of type thin layer can be identical, also can be different, is needed according to design and determined.
In other embodiments, branch commands troops in second high resistance of second N-type thin layer of different zones
Dividing 3w can have more than one width, so further expand the adjustable of device design, as long as ensureing that described second is low
Resistivity portion 3a can be by the p-type thin layer 4 of surrounding in the critical electric field less than the second low resistivity portion 3a regions
（Ec）Exhaust before reaching.
From unlike the preceding technical scheme, the device of electric charge flow region, second N of the branch in different zones
The second high-resistivity portions 3w of type thin layer can have more than one width, and such MOSFET element unit can arrange
In neighbour region, or some region is entirely such device, so can further improve reverse recovery characteristic, as long as
Ensure that the second low resistivity portion 3a can be by the p-type thin layer 4 of surrounding less than the second low resistivity portion 3a areas
The critical electric field in domain（Ec）Exhaust before reaching.
In above-described embodiment, because N-type thin layer and p-type thin layer are deposited in same groove, the characteristic of device
The susceptibility and depth of groove between declines, and further increases the homogeneity and uniformity of device.
As shown in FIG. 13A, it is the schematic diagram of Reverse recovery curve；In figure ta be device in turn off process electric current from 0
The time of maximum reverse current is increased to, the di/dt in the time period is mainly determined that tb is to recover by the parameter of external circuit
The time that electric current is 0 is reduced to from maximum reverse current in journey, the di/dt of the time period is mainly determined by the characteristic of internal diode
Fixed, softness coefficient is S=tb/ta, low softness coefficient（Or hard recovery characteristics）Device can cause very high in recovery process
Di/dt, causes the voltage overshoot that device is high, component failure, system electromagnetic interference it is exceeded the problems such as.It is this hair shown in Figure 13 B
The p-type thin layer of the super-junction device of bright embodiment one and the Reverse recovery curve of N-type thin layer.Curve 17 is the embodiment of the present invention
The Reverse recovery curve of the body diode of super-junction device, curve 18 is the existing super-junction device of no high resistivity portion
The reverse recovery characteristic of body diode, curve 19 is the reverse extensive of the body diode of the high tension apparatus using conventional drift region structure
Multiple characteristic, it can be seen that the softness coefficient of the Reverse recovery of the device of the embodiment of the present invention is than the softness system without high resistivity region
Number is big, and the reverse recovery characteristic to the body diode of existing super-junction device is improved, but less than using conventional migration technique
The reverse recovery characteristic of the high tension apparatus of plot structure.
The manufacture method of the super-junction device of the embodiment of the present invention one comprises the following steps：
Step one, as shown in figure 5, depositing the first N-type silicon epitaxial layers 2 on N+ silicon substrates 1.
Step 2, as shown in figure 5, on the first N-type silicon epitaxial layers 2 deposit formed the second N-type silicon epitaxial layers 3, institute
State the resistivity of the resistivity more than the first N-type silicon epitaxial layers 2 of the second N-type silicon epitaxial layers 3；Preferably, second N-type
The resistivity of silicon epitaxial layers 3 is 45 ohmcms.The thickness of the second N-type silicon epitaxial layers 3 and the electric current stream being subsequently formed
First high-resistivity portions 3n's of the first N-type thin layer in dynamic area and second second high-resistivity portions 3w of N-type thin layer
Thickness is identical.
Step 3, as shown in figure 5, the surface of the second N-type silicon epitaxial layers 3 deposit successively the first silicon dioxide layer 31,
Second silicon nitride layer 32 and the 3rd silicon dioxide layer 33；Using lithographic etch process successively to the 3rd silicon dioxide layer 33,
Second silicon nitride layer 32 and first silicon dioxide layer 31 form groove figure mask.
Step 4, as shown in fig. 6, being carved to the second N-type silicon epitaxial layers 3 by mask of the groove figure mask
Erosion forms multiple grooves, and the bottom discord silicon substrate 1 of the groove is connected；The zone line of super-junction device is described
Electric current flowing area, terminal protection structure is surrounded on the periphery in the electric current flowing area；In the electric current flowing area, each ditch
The second N-type silicon epitaxial layers 3 between groove are in laminate structure and define the first high-resistivity portions 3n and institute respectively
The width for stating the second high-resistivity portions 3w, the second high-resistivity portions 3w is more than the first high-resistivity portions 3n's
Width；The 3rd silicon dioxide layer 33 of the groove figure mask and second silicon nitride layer 32 are removed successively, institute
The first silicon dioxide layer 31 is stated to retain.
Step 5, as shown in fig. 7, depositing to form the 3rd N-type silicon epitaxial layers in the front of the silicon substrate 1, the 3rd N-type
Silicon epitaxy layer is formed at the bottom surface and side of the groove, the resistivity and the 3rd N-type of the second N-type silicon epitaxial layers 3
The ratio between resistivity of silicon epitaxial layers is 5:1, the resistivity of the resistivity of preferably described 3rd N-type silicon epitaxial layers is 1 ohm
Centimetre~5 ohmcms.In the electric current flowing area, the institute of the two sides of the first high-resistivity portions 3n is formed at
State the 3rd N-type silicon epitaxy layer and constitute the first low resistivity portion 3a, the first high-resistivity portions 3n and the first low electricity
Resistance rate part 3a constitutes the first N-type thin layer；In the electric current flowing area, it is formed at the second high-resistivity portions 3w's
The 3rd N-type silicon epitaxy layer of two sides constitutes the second low resistivity portion 3a, the second high-resistivity portions 3w and institute
State the second low resistivity portion 3a and constitute second N-type thin layer；By described the first N-type thin layer and second N-type thin layer
Constitute the N-type thin layer in the electric current flowing area.
Step 6, as shown in fig. 7, depositing to form the 4th p-type silicon epitaxial layers in the front of the silicon substrate 1, the 4th p-type
Silicon epitaxial layers and the 3rd N-type silicon epitaxial layers are contacted and are fully filled with the groove；By the silicon of the groove top surface
All removed with silica.
In the electric current flowing area, p-type thin layer is constituted by the 4th p-type silicon epitaxial layers being filled in the groove
4, the p-type thin layer 4 and the N-type thin layer in the electric current flowing area are arranged alternately structure.
The charge balance of described the first N-type thin layer and its neighbouring p-type thin layer 4, preferably, described the first N
The difference of the p-type carrier number of the N-type carrier number of type thin layer and the p-type thin layer 4 is less than the first N-type thin layer
The 10% of N-type carrier number and 10% of the p-type carrier number less than the p-type thin layer 4.The N-type thin layer and the p-type
When connecting reversed bias voltage between thin layer 4, can mutually entirely laterally between the first N-type thin layer and its neighbouring described p-type thin layer 4
Exhaust or non-fully having lateral depletion, non-fully during having lateral depletion described in the first N-type thin layer or the p-type thin layer 4 it is not horizontal
The 10% of the first the N-type thin layer dosage is no more than to the carrier number for exhausting and no more than the dosage of p-type thin layer 4
10%。
The charge unbalance of second N-type thin layer and its neighbouring p-type thin layer 4, the N-type thin layer and described
Connected between p-type thin layer 4 under conditions of reversed bias voltage, the second low resistivity portion 3a can be by the neighbouring p-type thin layer 4
Entirely laterally exhaust, the second high-resistivity portions 3w is not exhausted entirely laterally by the p-type thin layer 4.
Step 7, as shown in figure 4, the N-type thin layer and the p-type thin layer 4 top formed p-well 7.The p-well 7
Formation process be placed on step 2 form the second N-type silicon epitaxial layers after, step 3 deposit first silicon dioxide layer, institute
Carried out before stating the second silicon nitride layer and the 3rd silicon dioxide layer, or the formation process of the p-well 7 is placed on step 6
Formed and carry out after the p-type thin layer 4 and the N-type thin layer.
When connecting reversed bias voltage between the N-type thin layer and the p-type thin layer 4, the second high-resistivity portions 3w's
Longitudinal direction is not formed between the part of the having lateral depletion of p-type thin layer 4 and the p-well 7 to exhaust；When reversed bias voltage increases, institute
State the depth increase that the longitudinal direction of the second high-resistivity portions 3w of p-well 7 pairs exhausts.
Step 8, as shown in figure 4, using lithographic etch process at the top of the N-type thin layer in the electric current flowing area
Gate groove is formed, the gate groove passes through the p-well 7.
Step 9, as shown in figure 4, depositing gate dielectric layer 5 and polysilicon gate 6 successively, the gate dielectric layer 5 is covered in described
The lower surface of gate groove and side and outside, the polysilicon gate 6 are formed at the surface of the gate dielectric layer 5 and by the grid
Groove is filled up completely with, and the gate dielectric layer 5 and the polysilicon gate 6 outside the gate groove is removed, by being filled in the grid
The gate dielectric layer 5 and the polysilicon gate 6 of trench interiors constitute the grid structure of the super junction MOSFET element.
The side of the p-well 7 covered by the polysilicon gate 6 is used to form longitudinal channel, and the longitudinal channel is just
The N-type thin layer of lower section is channel current dispersion area；The channel current dispersion area of the first N-type thin layer is located at institute
State the first low resistivity portion 3a.
The channel current dispersion area of second N-type thin layer is all located at the second high-resistivity portions 3w.
Step 10, as shown in figure 4, carry out N+ ion implantings formed source region 8；Institute at the top of described the first N-type thin layer
The top of the p-well 7 for stating the both sides of gate groove is all formed with the source region 8.
The top of the p-well 7 of the both sides of the gate groove at the top of second N-type thin layer is all formed with the source
Area 8.
Step 11, as shown in figure 4, foring source region 8 the front of the silicon substrate 1 formed interlayer film 10；Using light
Carve etching technics and form contact hole 11, the contact hole 11 passes through the interlayer film 10 and and the source region 8 or the polysilicon
Grid 6 are contacted；Carry out P+ ion implantings and form p-well draw-out area 9, the institute that the p-well draw-out area 9 is located at and the source region 8 is in contact
The bottom of contact hole 11 is stated, the p-well draw-out area 9 and the p-well 7 are in contact.
Step 12, as shown in figure 4, deposit front metal 12 and the front metal 12 is carried out chemical wet etching difference shape
Into source electrode and grid；The silicon substrate 1 is carried out from the back side it is thinning, carry out back metal 13 change formed drain electrode.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (9)
1. a kind of super-junction device, the zone line of super-junction device is electric current flowing area, and terminal protection structure is surrounded on described
The periphery in electric current flowing area；It is characterized in that：
Electric current flowing area includes multiple N-type thin layers and p-type thin layer being alternately arranged, in the N-type thin layer and the p-type thin layer
Top is formed with p-well；
The N-type thin layer includes the first N-type thin layer and second N-type thin layer；
Described the first N-type thin layer includes the first high-resistivity portions and the first low resistivity portion, first high resistivity
Part is the center section of the first N-type thin layer, and first low resistivity portion is commanded troops positioned at first high resistance
Point both sides and be in contact with the neighbouring p-type thin layer；
The charge balance of described the first N-type thin layer and its neighbouring p-type thin layer, and the first N-type thin layer N-type
The difference of the p-type carrier number of carrier number and the p-type thin layer is less than the N-type current-carrying equal to the first N-type thin layer
The 10% of subnumber and 10% of the p-type carrier number less than or equal to the p-type thin layer；The N-type thin layer and the p-type thin layer
Between connect reversed bias voltage when, can entirely laterally be exhausted mutually between the first N-type thin layer and its neighbouring described p-type thin layer or
Non-fully having lateral depletion, non-fully during having lateral depletion described in the first N-type thin layer or the p-type thin layer not by having lateral depletion
Carrier number is no more than the 10% and no more than the p-type thin layer dosage 10% of the first the N-type thin layer dosage；
Second N-type thin layer includes the second high-resistivity portions and the second low resistivity portion, second high resistivity
Part is the center section of second N-type thin layer, and second low resistivity portion is commanded troops positioned at second high resistance
Point both sides and be in contact with the neighbouring p-type thin layer；Second high-resistivity portions and second low resistance are commanded troops
The ratio between resistivity divided is more than 5:1；First high-resistivity portions are identical with the resistivity of second high-resistivity portions,
First low resistivity portion is identical with the resistivity of second low resistivity portion, second high-resistivity portions
Width of the width more than first high-resistivity portions；
The charge unbalance of second N-type thin layer and its neighbouring p-type thin layer, the N-type thin layer and the p-type are thin
Layer between connect reversed bias voltage under conditions of, second low resistivity portion can be by the neighbouring p-type thin layer entirely laterally
Exhaust, second high-resistivity portions can not entirely laterally be exhausted by the p-type thin layer, second high-resistivity portions
Longitudinal direction is not formed between the part of the p-type thin layer having lateral depletion and the p-well to exhaust；When reversed bias voltage increases, the P
The depth that trap exhausts to the longitudinal direction of second high-resistivity portions increases.
2. super-junction device as claimed in claim 1, it is characterised in that：The super-junction device is super junction MOSFET devices
Part, is formed through the gate groove of the p-well, lower surface and side in the gate groove at the top of each N-type thin layer
Face is formed with gate dielectric layer, the polysilicon gate for filling the gate groove is formed with gate dielectric layer surface, by the polysilicon gate
The p-well side for being covered is used to form longitudinal channel, and the N-type thin layer of the underface of the longitudinal channel is raceway groove electricity
Stream dispersion area；The channel current dispersion area of the first N-type thin layer is located at first low resistivity portion；
The channel current dispersion area of second N-type thin layer is all located at second low resistivity portion；Or it is described
The channel current dispersion area of second N-type thin layer is all located at second high-resistivity portions；Or second N-type
The channel current dispersion area part of thin layer is located at second high-resistivity portions, is partly located at second low-resistivity
Part.
3. super-junction device as claimed in claim 2, it is characterised in that：The grid at the top of described the first N-type thin layer
The both sides of groove the p-well top be all formed with by N+ district's groups into source region；
All be formed with the top of the p-well of the both sides of the gate groove at the top of second N-type thin layer by N+ district's groups into
Source region；Or, it is formed with by N+ at the top of the p-well of the side of the gate groove at the top of second N-type thin layer
District's groups into source region, the p-well of the opposite side of the gate groove top be formed without by N+ district's groups into source region；Or,
The both sides of the gate groove at the top of second N-type thin layer the p-well top be all formed without by N+ district's groups into source
Area.
4. super-junction device as claimed in claim 1, it is characterised in that：On vertical view face, the shape of second N-type thin layer
Shape is identical with the shape of the first N-type thin layer or difference.
5. super-junction device as claimed in claim 1, it is characterised in that：On vertical view face, second N-type thin layer is in institute
State and be evenly distributed or uneven distribution in electric current flowing area.
6. super-junction device as claimed in claim 1, it is characterised in that：The distributed areas discord of second N-type thin layer
The terminal protection structure adjoining.
7. a kind of manufacture method of super-junction device, it is characterised in that comprise the following steps：
Step one, the first N-type silicon epitaxial layers are deposited on N+ silicon substrates；
Step 2, the second N-type silicon epitaxial layers of deposit formation, the second N-type silicon epitaxial layers on the first N-type silicon epitaxial layers
Resistivity more than the first N-type silicon epitaxial layers resistivity；The thickness of the second N-type silicon epitaxial layers and it is subsequently formed
First high-resistivity portions of the first N-type thin layer in electric current flowing area and second second high-resistivity portions of N-type thin layer
Thickness it is identical；
Step 3, the first silicon dioxide layer, the second silicon nitride layer and the 3rd are deposited successively on the second N-type silicon epitaxial layers surface
Silicon dioxide layer；Using lithographic etch process successively to the 3rd silicon dioxide layer, second silicon nitride layer and described
One silicon dioxide layer forms groove figure mask；
Step 4, the second N-type silicon epitaxial layers are performed etching to form multiple grooves by mask of the groove figure mask,
The bottom discord silicon substrate of the groove is connected；The zone line of super-junction device is the electric current flowing area, terminal
Protection structure is surrounded on the periphery in the electric current flowing area；In the electric current flowing area, between each groove described
Two N-type silicon epitaxial layers are in laminate structure and define first high-resistivity portions respectively and second high resistance is commanded troops
Point, the width of the width more than first high-resistivity portions of second high-resistivity portions；Successively by the groove figure
3rd silicon dioxide layer of shape mask and second silicon nitride layer are removed, and first silicon dioxide layer retains；
Step 5, deposit to form the 3rd N-type silicon epitaxial layers in the silicon substrate front, the 3rd N-type silicon epitaxy layer is formed at
The resistivity of the bottom surface and side of the groove, the resistivity of the second N-type silicon epitaxial layers and the 3rd N-type silicon epitaxial layers
The ratio between be more than 5:1；In the electric current flowing area, the 3rd N of the two sides of first high-resistivity portions is formed at
Type silicon epitaxy layer constitutes the first low resistivity portion, and first high-resistivity portions and first low resistivity portion are constituted
The first N-type thin layer；In the electric current flowing area, the described 3rd of the two sides of second high-resistivity portions the is formed at
N-type silicon epitaxy layer constitutes the second low resistivity portion, second high-resistivity portions and the second low resistivity portion group
Into second N-type thin layer；The N-type in the electric current flowing area is made up of described the first N-type thin layer and second N-type thin layer
Thin layer；
Step 6, deposit to form the 4th p-type silicon epitaxial layers in the silicon substrate front, the 4th p-type silicon epitaxial layers and described
3rd N-type silicon epitaxial layers are contacted and are fully filled with the groove；The silicon and silica of the groove top surface are all removed；
In the electric current flowing area, p-type thin layer is constituted by the 4th p-type silicon epitaxial layers being filled in the groove, institute
The p-type thin layer and the N-type thin layer in electric current flowing area is stated to be arranged alternately structure；
The charge balance of described the first N-type thin layer and its neighbouring p-type thin layer, and the first N-type thin layer N-type
The difference of the p-type carrier number of carrier number and the p-type thin layer is less than the N-type current-carrying equal to the first N-type thin layer
The 10% of subnumber and 10% of the p-type carrier number less than or equal to the p-type thin layer；The N-type thin layer and the p-type thin layer
Between connect reversed bias voltage when, can entirely laterally be exhausted mutually between the first N-type thin layer and its neighbouring described p-type thin layer or
Non-fully having lateral depletion, non-fully during having lateral depletion described in the first N-type thin layer or the p-type thin layer not by having lateral depletion
Carrier number is no more than the 10% and no more than the p-type thin layer dosage 10% of the first the N-type thin layer dosage；
The charge unbalance of second N-type thin layer and its neighbouring p-type thin layer, the N-type thin layer and the p-type are thin
Layer between connect reversed bias voltage under conditions of, second low resistivity portion can be by the neighbouring p-type thin layer entirely laterally
Exhaust, second high-resistivity portions can not entirely laterally be exhausted by the p-type thin layer；
Step 7, the p-well that formed, the p-well are located at the top of the N-type thin layer and the p-type thin layer；The N-type thin layer and institute
State when connecting reversed bias voltage between p-type thin layer, second high-resistivity portions not by the portion of the p-type thin layer having lateral depletion
Divide and longitudinal exhausting is formed and the p-well between；When reversed bias voltage increases, the p-well is to second high-resistivity portions
The depth that longitudinal direction exhausts increases；The formation process of the p-well be placed on step 2 form the second N-type silicon epitaxial layers after, step
Carried out before rapid three deposit first silicon dioxide layer, second silicon nitride layer and the 3rd silicon dioxide layer, or
The formation process of the p-well is placed on after step 6 forms the p-type thin layer and the N-type thin layer and carries out.
8. method as claimed in claim 7, it is characterised in that the super-junction device is super junction MOSFET element, is also wrapped
Include following steps：
Step 8, using lithographic etch process the N-type thin layer in the electric current flowing area top formed gate groove, it is described
Gate groove passes through the p-well；
Step 9, successively deposit gate dielectric layer and polysilicon gate, the gate dielectric layer are covered in the lower surface of the gate groove
With side and outside, the polysilicon gate is formed at the gate dielectric layer surface and is filled up completely with the gate groove, removes
The gate dielectric layer and the polysilicon gate outside the gate groove, by the gate medium being filled in inside the gate groove
Layer and the polysilicon gate constitute the grid structure of the super junction MOSFET element；
The p-well side covered by the polysilicon gate is used to form longitudinal channel, the underface of the longitudinal channel
The N-type thin layer is channel current dispersion area；The channel current dispersion area of the first N-type thin layer is located at described first
Low resistivity portion；
The channel current dispersion area of second N-type thin layer is all located at second low resistivity portion；Or it is described
The channel current dispersion area of second N-type thin layer is all located at second high-resistivity portions；Or second N-type
The channel current dispersion area part of thin layer is located at second high-resistivity portions, is partly located at second low-resistivity
Part.
9. method as claimed in claim 8, it is characterised in that also comprise the following steps：
Step 10, carry out N+ ion implantings formed source region；The both sides of the gate groove at the top of described the first N-type thin layer
The p-well top is all formed with the source region；
The source region is all formed with the top of the p-well of the both sides of the gate groove at the top of second N-type thin layer；Or
Person, is formed with the source region, described at the top of the p-well of the side of the gate groove at the top of second N-type thin layer
The p-well top of the opposite side of gate groove is formed without the source region；Or, the institute at the top of second N-type thin layer
The p-well top for stating the both sides of gate groove is all formed without the source region；
Step 11, foring source region the silicon substrate front formed interlayer film；Formed using lithographic etch process and contacted
Hole, the contact hole is contacted through the interlayer film and with the source region or the polysilicon gate；Carry out P+ ion implantings and form P
Trap draw-out area, the contact hole bottom that the p-well draw-out area is located at and the source region is in contact, the p-well draw-out area and institute
P-well is stated to be in contact；
Step 12, deposit front metal simultaneously carry out chemical wet etching and form source electrode and grid respectively to the front metal；From the back of the body
Carried out in face of the silicon substrate it is thinning, carry out back face metalization formed drain electrode.
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