CN104517855B - Super junction-semiconductor device manufacture method - Google Patents
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- CN104517855B CN104517855B CN201410459207.5A CN201410459207A CN104517855B CN 104517855 B CN104517855 B CN 104517855B CN 201410459207 A CN201410459207 A CN 201410459207A CN 104517855 B CN104517855 B CN 104517855B
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Abstract
The invention discloses a kind of super junction-semiconductor device manufacture method, including step：One silicon chip with N-type silicon epitaxy layer is provided and does substrate；Hard mask layer is formed, chemical wet etching the first photoetching offset plate figure of formation is carried out, etching forms deep trench；P type single crystal silicon is filled in deep trench；CMP removes the p-type polysilicon on hard mask layer surface, and formation constitutes the super-junction structures being alternately arranged by P posts and N-type thin layer；P type impurity injection is carried out by mask of remaining hard mask layer and P-type layer is formed, P-type layer autoregistration forms the PXing Ti areas as super junction-semiconductor device behind the top of each P posts and diffusion.The present invention can reduce light shield level, save process costs；The body diode and dynamic characteristic of superjunction devices can also be optimized.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of super junction-semiconductor device system
Make method.
Background technology
Super junction MOSFET (metal-oxide half field effect transistor) device uses the new a series of alternating of structure of voltage-sustaining layer-utilization
The p-type and N-type semiconductor thin layer of arrangement in the off state at the lower voltage just exhausts p-type N-type region, realizes electric charge phase
Mutually compensation, so that p-type N-type region can realize high breakdown voltage under high-dopant concentration, so as to obtain low on-resistance simultaneously
And high-breakdown-voltage, break traditions power MOSFET theoretical limits.
As shown in figure 1, being the structural representation of existing super junction-semiconductor device；Hyperstructure semiconductor device shown in Fig. 1
Part is illustrated exemplified by a super junction MOSFET element, is that super junction-semiconductor device described in boundary includes electric current with dotted line AA '
Flow region 201 and termination environment 202, the electric current flowing area 201 are active area and are by multiple MOSFET element cellular constructions week
Phase arrangement is formed, the not streaming current and termination environment 202 is centered around the week side of boss in the electric current flowing area 201 and is used for of termination environment 202
The device in the circuit current area 201 is protected.Super-junction structures are formed in N-type silicon epitaxy layer 101, including are alternately arranged
The P posts of row are that p-type thin layer 102 and N-type thin layer 101a, P 102 p type single crystal silicon by being filled in deep trench of post are constituted, and N-type is thin
The N-type silicon epitaxy layers 101 of the layer 101a between P posts 102 is constituted.
In the electric current flowing area 201, a MOSFET element cellular construction include p-well 104, source region 105,
Grid oxygen 106, polysilicon gate 107, N-type cushion 111 and N+ contact layers, the p-well 104 are formed at the N by lithographic definition
Abutted in type thin layer 101a and with the P posts 102, the source region 105 is formed in the p-well 104, the grid oxygen 106 and institute
State polysilicon gate 107 to be sequentially overlapped in the surface of N-type silicon epitaxy layer 101 formation planar gate structure, can also use certainly
Trench gate structure is replaced.The surface of the p-well 104 covered by the polysilicon gate 107 is used to form raceway groove to connect
The source region 105 and N-type thin layer 101a, the p-well 104 are mainly used in adjusting the threshold voltage of super device, i.e., by changing
The doping concentration of the p-well 104 changes the threshold voltage of super-junction device；The N-type cushion 111 is located at the N-type thin layer
The 101a back side；Source electrode 109 is made up of front metal pattern and contacted with the source region 105 and the P posts 102；Drain electrode 112
It is made up of back metal, the N+ contact layers formation is at the N-type cushion 111 and the contact position of drain electrode 112.
In the termination environment 202, also constituted including multiple N-type thin layer 101a being alternately arranged and the P posts 102
Super-junction structures；Dielectric layer 108 is covered in the surface of N-type silicon epitaxy layer 101 of the termination environment 202, and dielectric layer 108 is most interior
The top of the P posts 102 of side is formed with a ledge structure, and covered with being made up of front metal pattern at the ledge structure
Metal field plate 110, Metal field plate 110 also extends to the outside of ledge structure and covers several P posts 102.In the outer part
The top of P posts 102 be linked to be and be formed with PXing Ti areas (body) 103, a connection covering two is included in the lower section of ledge structure
The PXing Ti areas 103 of the individual P posts 102, the PXing Ti areas 103 are required for using photoetching process definition, the PXing Ti areas 103
Current handling capability when device is applied in inductive circuit can be improved.In the termination environment 202 can also the setting it is multiple
Polysilicon field plate 107a, polycrystalline silicon field plate 107a can simultaneously be formed with the polysilicon gate 107.In the termination environment 202
The outermost P posts 102 outside N-type silicon epitaxy layer 101 in be also formed with channel cutoff ring 105a, the raceway groove is cut
Only ring 105a doping condition and the source region 105 are identical.
As shown in Fig. 2A to Fig. 2 C, be the step of super junction is formed in existing super junction-semiconductor device manufacture method in
Device junction composition；The step of super junction is formed in existing super junction-semiconductor device manufacture method includes：
First, as shown in Figure 2 A, etched using lithographic etch process in the N-type silicon epitaxy layer 101 and form deep trench；
Hard mask layer 113 can be used during chemical wet etching, these need first to form hard mask layer on the surface of N-type silicon epitaxy layer 101
113, then chemical wet etching is to be sequentially etched the hard mask layer 113 and the N-type silicon epitaxy layer 101.
Secondly, as shown in Figure 2 A, after the deep trench is formd, progress is epitaxially-formed p type single crystal silicon filling
In the deep trench and form P posts 102, the surface of the hard mask layer 113 of the silicon of epitaxial growth outside the deep trench
For p-type polysilicon 102a.
Then, as shown in Figure 2 B, the p-type polysilicon 102a is removed using cmp (CMP) technique.
Then, as shown in Figure 2 C, the hard mask layer 113 is removed.Form the p-type 102 and N-type thin layer 101a is alternately arranged
The super-junction structures of row.
As shown in figure 1, in existing super junction-semiconductor device manufacture method, after the super-junction structures are formed,
The forming region position for using photoetching process to define the PXing Ti areas 103 is needed, photoetching is not only increased using photoetching process
Level, so that cause cost higher, moreover, the PXing Ti areas 103 that photoetching process is defined can not be aligned with the P posts 102 completely,
The limited precision being aligned.For the MOSFET element of existing super junction planar gate structure, existing method at least needs to use 10
Block light shield is lithography mask version, is respectively：
1st, JFET mask plate is formed, in planar gate super-junction device, planar gate covers the He of p-well 104 from top
The N-type thin layer 101a, can form a JFET back-gate effects, it is necessary to carry out the JFET definition regulation JFET back ofs the body using JFET mask plates
Matrix effect；And in trench gate super-junction device, trench gate covers p-well from side, in the absence of JFET back-gate effects, therefore trench gate
Super-junction device need not carry out JFET injections, it is not required that use JFET mask plates.2nd, the mask plate in body area is formed；Body area shape
Into in the termination environment of super-junction device, because termination environment is the week side of boss that is looped around active area, GuPXing Ti areas are also referred to as p-type ring.3rd, shape
Into the mask plate of the deep trench of hyperstructure, the deep trench is the deep trench for defining P posts.4th, the mask plate of active area is defined；
The mask plate that the active area is also referred to as electric current flowing area 201, i.e. active area is used to define the electric current flowing area 201.5th, p-well is defined
Mask plate, the main threshold voltage for being used to define device in active area of the p-well.6th, the mask plate of polysilicon gate is defined.
7th, NP mask plates；NP mask plates are used for the region for defining the N+ ion implantings of source region.8th, the mask plate of contact hole is defined.9th, define
The mask plate of front metal pattern；10th, the mask plate of definition passivation layer pattern.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of super junction-semiconductor device manufacture method, can reduce light shield
Level, saves process costs；The body diode and dynamic characteristic of super-junction device can also be optimized.
In order to solve the above technical problems, the super junction-semiconductor device manufacture method that the present invention is provided comprises the following steps：
Step 1: providing a silicon chip does substrate, N-type silicon epitaxy layer is formed with the silicon chip.
Step 2: hard mask layer is formed on the N-type silicon epitaxy layer surface, using chemical wet etching the first photoresist figure of formation
Shape, the pattern of deep trench is defined by first photoetching offset plate figure；It is mask successively to institute using first photoetching offset plate figure
State hard mask layer and the N-type silicon epitaxy layer performs etching to form the deep trench；Remove first photoetching offset plate figure.
Step 3: filling p type single crystal silicon in the deep trench using selective epitaxial process, epitaxy technique is simultaneously in institute
State hard mask layer surface and form p-type polysilicon.
Step 4: removing p-type polysilicon and the part on the hard mask layer surface using chemical mechanical milling tech method
The hard mask layer；P posts are formed by the p type single crystal silicon being filled in the deep trench；As described between each P posts
N-type silicon epitaxy layer constitutes N-type thin layer, the super-junction structures that the P posts and N-type thin layer composition are alternately arranged.
Step 5: carrying out p type impurity injection by mask of the remaining hard mask layer and forming P-type layer, the P-type layer
Autoregistration is formed at the top of each P posts, and the hard mask layer is removed afterwards；The P-type layer can spread in follow-up thermal process
And extend in the N-type thin layer of both sides of the corresponding P posts, the P-type layer after spreading partly is led as super junction
The PXing Ti areas of the termination environment of body device.
Further improve is, in addition to following front processing step：
Step 6: forming field oxide, grid oxygen, polysilicon gate, P type trap zone, source region, interlayer film, contact hole, front metal
And passivation layer.
Further improve is that the polysilicon gate of the super junction-semiconductor device is trench gate structure, forms the grid
The step of oxygen and the polysilicon gate, includes：
Step 61a, using lithographic etch process the second photoetching offset plate figure of formation, the second photoresist glue pattern defines
The pattern of gate groove；Using second photoetching offset plate figure, the N-type silicon epitaxy layer described in mask performs etching to form the grid ditch
Groove；Remove second photoetching offset plate figure.
Step 62a, lower surface and side formation oxide layer in the gate groove, the oxygen by the side of the gate groove
Change layer and constitute the grid oxygen.
Step 63a, filling polysilicon forms the polysilicon gate in the gate groove for forming the grid oxygen, described many
Crystal silicon grid cover the P type trap zone from side, are used to be formed by the surface of the P type trap zone of polysilicon gate side covering
Connect the raceway groove of the source region and the N-type silicon epitaxy layer.
Further improve is that the polysilicon gate of the super junction-semiconductor device is planar gate structure, forms the grid
The step of oxygen and the polysilicon gate, includes：
Step 61b, on the N-type silicon epitaxy layer surface sequentially form the first oxide layer and the second polysilicon layer.
Step 62b, using lithographic etch process to being carried out successively to second polysilicon layer and first oxide layer
Etching forms planar gate structure described in the grid oxygen and the polysilicon gate and composition；The polysilicon gate is described from top covering
P type trap zone, is used to form the connection source region and the N by the surface of the P type trap zone of covering at the top of the polysilicon gate
The raceway groove of type silicon epitaxy layer.
It is further improve be the N-type silicon epitaxy layer that is formed on the silicon chip for 20 microns~70 microns, resistance
Rate scope is the ohmcm of 0.5 ohmcm~5.
Further improve is that the depth of the deep trench is 30 microns~60 microns.
Further improve is that the hard mask layer is oxide, nitride, the combination of oxide and nitride.
Further improve is that the depth of gate groove described in step 61a is 1 micron~6 microns.
Further improve is that the implantation dosage of the p type impurity injection of P-type layer described in step 5 is 1e12cm-2~
1e15cm-2, Implantation Energy be 10Kev~60Kev, injection element be boron difluoride or boron.
The inventive method, which is utilized, to be formed being used for employed in super-junction structures process and defines the hard mask layer of deep trench and be
Mask, carries out p type impurity after the polysilicon removal at the top of hard mask layer, before hard mask layer removal and injects to form P-type layer, and
Finally by the PXing Ti areas for diffuseing to form super junction-semiconductor device of P-type layer, so the PXing Ti areas of the present invention need not be adopted
It can just be formed with single light shield, so as to save process costs；In addition, the PXing Ti areas of the present invention can also form good with P posts
Good autoregistration, so as to reduce technology difficulty and further reduce process costs；The present invention can also utilize PXing Ti areas
The advantage that p type impurity injection can be adjusted on a large scale, can further optimize the body diode and dynamic characteristic of super-junction device
Such as the dynamic characteristic such as electromagnetic interference (EMI) and pulse avalanche breakdown energy of super junction MOSFET element body diode and MOSFET
Measure (EAS).
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structural representation of existing super junction-semiconductor device；
Fig. 2A-Fig. 2 C be the step of super junction is formed in existing super junction-semiconductor device manufacture method in device architecture
Figure；
Fig. 3 is the method flow diagram of the embodiment of the present invention one；
Fig. 4 A- Fig. 4 D be the step of super junction is formed in the method for the embodiment of the present invention one in device junction composition；
Fig. 5 is the structural representation of the super junction-semiconductor device of the formation of present invention method one.
Embodiment
As shown in figure 3, being the method flow diagram of the embodiment of the present invention one；It is the embodiment of the present invention as shown in Fig. 4 A to Fig. 4 D
Device junction composition in the step of super junction is formed in one method；The super junction-semiconductor device manufacture method bag that the present invention is provided
Include following steps：
Step 1: doing substrate there is provided a silicon chip as shown in Figure 4 A, N-type silicon epitaxy layer 1 is formed with the silicon chip.
The pressure voltage that the thickness of N-type silicon epitaxy layer 1 is designed by device is determined, in the silicon in the embodiment of the present invention one
The N-type silicon epitaxy layer 1 formed on piece is 20 microns~70 microns, and electrical resistivity range is 0.5 ohmcm~5 ohm
Centimetre.
Step 2: as shown in Figure 4 A, forming hard mask layer 13 on the surface of N-type silicon epitaxy layer 1, utilizing first layer light shield
And using chemical wet etching the first photoetching offset plate figure of formation, the pattern of deep trench is defined by first photoetching offset plate figure；With institute
The first photoetching offset plate figure is stated the hard mask layer 13 and the N-type silicon epitaxy layer 1 are performed etching successively for mask to form described
Deep trench；Remove first photoetching offset plate figure.
Preferably, the depth of the deep trench is 30 microns~60 microns.
The hard mask layer 13 is oxide, nitride, the combination of oxide and nitride.
Step 3: as shown in Figure 4 A, filling p type single crystal silicon 2 in the deep trench using selective epitaxial process, outside
Prolong technique and form p-type polysilicon 2a on the surface of hard mask layer 13 simultaneously.
Step 4: as shown in Figure 4 B, the p-type on the surface of hard mask layer 13 is removed using chemical mechanical milling tech method
Polysilicon 2A and the part hard mask layer 13；P posts 2 are formed by the p type single crystal silicon 2 being filled in the deep trench；By
The N-type silicon epitaxy layer 1 composition N-type thin layer 1a between each P posts 2, the P posts 2 and N-type thin layer 1a composition alternatings
The super-junction structures of arrangement.
Step 5: as shown in Figure 4 C, carrying out p type impurity injection for mask with the remaining hard mask layer 13 and forming P
Type layer 3a, the P-type layer 3a autoregistrations are formed at the top of each P posts 2, and the hard mask layer is removed afterwards；The P-type layer
3a can be spread and be extended in follow-up thermal process in the N-type thin layer 1A of the both sides of the corresponding P posts 2, after spreading
The P-type layer 3a as super junction-semiconductor device PXing Ti areas 3.
Preferably, the implantation dosage of the p type impurity injection of the P-type layer 3a is 1e12cm-2~1e15cm-2, Implantation Energy
It is boron difluoride or boron for 10Kev~60Kev, injection element.
The super junction-semiconductor device manufactured by the method for the embodiment of the present invention one is super junction trench gate mosfet device
Part；As shown in figure 5, also including following front processing step：
Step 6: forming field oxide 8, grid oxygen 6, polysilicon gate 7, P type trap zone 4, source region 5, interlayer film 8a, contact hole
9a, front metal and passivation layer.
The step of wherein forming field oxide 8 includes：Growing a layer thickness using thermal oxidation technology is Silica membrane；Active area i.e. electric current flowing area 301 is defined using second layer light shield, electric current flowing area 301 is
The cellular construction of device is formed with Fig. 5 dotted line BB ' left field, electric current flowing area 301；Dotted line BB ' right side areas are
Termination environment 302, the termination environment 302 is centered around the week side of boss in the electric current flowing area 301 and for the electric current flowing area 301
Protected.Afterwards, it is using dry or wet etch technique that the silica in the region of electric current flowing area 301 is thin
Film removes and formed the field oxide 8 for only covering the termination environment 302.It is formed with the most inner side of the field oxide 8
Between one step, the outermost polysilicon gate 7 of the step and electric current flowing area 301 can between be separated with 2 to 3 P posts
2。
The grid structure being wherein made up of the grid oxygen 6 and the polysilicon gate 7 is trench gate structure, forms the grid oxygen
6 and include the step of the polysilicon gate 7：
Step 61a, using third layer light shield, using lithographic etch process the second photoetching offset plate figure of formation, second light
Photoresist glue pattern defines the pattern of gate groove；Using second photoetching offset plate figure, the N-type silicon epitaxy layer 1 described in mask is carried out
Etching forms the gate groove；Remove second photoetching offset plate figure.
The gate groove is between two P post 2.Preferably, the depth of the gate groove is 1 micron~6 microns.
Step 62a, lower surface and side formation oxide layer in the gate groove, the oxygen by the side of the gate groove
Change layer and constitute the grid oxygen 6.Preferably, the thickness of the grid oxygen 6 is。
Step 63a, filling polysilicon forms the polysilicon gate 7 in the gate groove for forming the grid oxygen 6, described
Polysilicon gate 7 covers the P type trap zone 4 from side, and the surface of the P type trap zone 4 covered sideways by the polysilicon gate 7 is used
In the raceway groove for forming the connection source region 5 and the N-type silicon epitaxy layer 1.
Afterwards, formed the P type trap zone 4, the source region 5, the interlayer film, the contact hole, the front metal and
The technique of the passivation layer is as follows：
Carry out the P type trap zone 4 to inject and knot, the knot junction depth of P type trap zone 4 is adjusted according to gate groove depth, institute
The implantation dosage of P type trap zone 4 is stated to be adjusted according to threshold voltage requirements.The P type trap zone 4 is formed using injection comprehensively, it is not necessary to adopted
Use mask plate.After the formation of P type trap zone 4, the polysilicon gate 7 can cover the surface of the P type trap zone 4 from side and be used for
The surface is set to form the N-type thin layer 1A of the connection source region 5 and bottom raceway groove.And in the step of the field oxide 8
Between the outermost polysilicon gate 7 in electric current flowing area 301, the P type trap zone 4 and the PXing Ti areas 3 superposition connection shape
Into a PXing Ti areas 3b for covering 2 to 3 P posts 2.
Carry out ion implanting and form the source region 5；The source region 5 is located in the P type trap zone 4.Simultaneously in the terminal
The surface of the N-type silicon epitaxy layer 1 of the outermost P posts 2 in area 302 forms channel cutoff ring 5a.The source region 5 is used
Injection is formed comprehensively, it is not necessary to use mask plate.
Isolating oxide layer 8a (ILD) namely interlayer film 8a deposits, isolating oxide layer 8a uses one or more layers oxide-film, should
Oxide-film can be undope silica (SiO2), phosphorosilicate glass (PSG), Pyrex (BSG) or boron-phosphorosilicate glass
(BPSG), ILD gross thickness。
Contact hole (Contact) area's (Fig. 5 is not shown) is defined using the 4th floor light shield, carry out contact hole 9a dry etchings or
Dry and wet combine etching, and the contact hole 9a is contacted through the interlayer film 8a and the silicon of bottom.
Direct evaporation deposition aluminium or first deposition tungsten fill the contact hole 9a, CMP formation tungsten plugs in deposit aluminium.Afterwards again
Deposit aluminium formation front metal.
The etched area of front metal is defined using layer 5 light shield, source electrode (Source) 9 and grid (Gate) is formed and whole
Hold field plate region 10.Wherein source electrode 9 and the source region 5 and the P type trap zone 4 are contacted.The grid and the polysilicon gate 7 connect
Touch.The termination field plate area 10 is Metal field plate, covered with a terminal at the stepped locations of the field oxide 8
The termination field plate area 10 is contacted by the contact hole 9a and PXing Ti areas 3b of bottom in plate area 10, the embodiment of the present invention.
The termination field plate area 10 can also be set at other positions.
In addition, can also form polysilicon field plate in the termination environment 302.
Afterwards, passivation layer region (this step can be omitted) is determined using layer 6 light shield.
The method of the embodiment of the present invention one also includes following back process step：
Step 7: the thickness that the N-type silicon epitaxy layer 1 of the thinning back side after being thinned is carried out to the silicon chip reaches work
Skill requirement, the N-type silicon epitaxy layer 1 after being such as thinned is 20 microns~70 microns.
Inject to form N-type cushion 11 Step 8: carrying out backside particulate.
Inject to form N+ contact layers Step 9: carrying out backside particulate.
Step 10: carrying out annealing activation to the N-type cushion 11 and the N+ contact layers.
Step 11: forming back metal 12.The back metal 12 as device drain electrode.
From the foregoing, it will be observed that six layers of light shield are only needed in the method for the embodiment of the present invention one altogether, and ten layers i.e. ten pieces of prior art
Light shield is compared, and the method for the embodiment of the present invention one eliminates following four layers of light shield in existing method：JFET mask plate is formed, is formed
The mask plate in body area, defines the mask plate of p-well, NP mask plates.Wherein, due to described in manufactured by the method for the embodiment of the present invention one
Super junction-semiconductor device is super junction trench gate mosfet device, and trench gate mosfet device need not carry out JFET note
Enter, therefore JFET mask plates can be omitted；And in the method for the embodiment of the present invention one, injected all using the N+ of p-well during trench gate and source region
It can be formed using comprehensive injection technology, therefore p-well and NP mask plates can be omitted；It is being using the institute for defining deep trench plus body area
State hard mask layer 13 to define, it is not necessary to use extra body region mask board, therefore the mask plate in body area can be omitted.So the present invention is real
Applying the method for example one can just be formed using six pieces of mask plates altogether, can save process costs.
It is in place of the difference of the method for the embodiment of the present invention two and the method for the embodiment of the present invention one, the super-junction semiconductor device
The polysilicon gate 7 of part is planar gate structure, and the step of forming the grid oxygen 6 and the polysilicon gate 7 includes：
Step 61b, on the surface of N-type silicon epitaxy layer 1 sequentially form the first oxide layer and the second polysilicon layer.
Step 62b, using lithographic etch process to being carried out successively to second polysilicon layer and first oxide layer
Etching forms the grid oxygen 6 and the polysilicon gate 7 and constitutes the planar gate structure；The polysilicon gate 7 is covered from top
The P type trap zone 4, is used to form the connection source region 5 by the surface of the P type trap zone 4 of the top of polysilicon gate 7 covering
With the raceway groove of the N-type silicon epitaxy layer 1.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (9)
1. a kind of super junction-semiconductor device manufacture method, it is characterised in that comprise the following steps：
Step 1: providing a silicon chip does substrate, N-type silicon epitaxy layer is formed with the silicon chip；
Step 2: hard mask layer is formed on the N-type silicon epitaxy layer surface, using chemical wet etching the first photoetching offset plate figure of formation,
The pattern of deep trench is defined by first photoetching offset plate figure；It is mask successively to described hard using first photoetching offset plate figure
Mask layer and the N-type silicon epitaxy layer perform etching to form the deep trench；Remove first photoetching offset plate figure；
Step 3: filling p type single crystal silicon in the deep trench using selective epitaxial process, epitaxy technique is simultaneously described hard
Mask layer surface formation p-type polysilicon；
Step 4: being removed using chemical mechanical milling tech method described in p-type polysilicon and the part on the hard mask layer surface
Hard mask layer；P posts are formed by the p type single crystal silicon being filled in the deep trench；The N-type between each P posts
Silicon epitaxy layer constitutes N-type thin layer, the super-junction structures that the P posts and N-type thin layer composition are alternately arranged；
Step 5: carry out p type impurity injection by mask of the remaining hard mask layer and form P-type layer, the P-type layer is from right
Standard is formed at the top of each P posts, and the hard mask layer is removed afterwards；The P-type layer can spread and prolong in follow-up thermal process
In the N-type thin layer for the both sides for reaching the corresponding P posts, the P-type layer after spreading is used as super-junction semiconductor device
The PXing Ti areas of the termination environment of part.
2. super junction-semiconductor device manufacture method as claimed in claim 1, it is characterised in that also including following positive technique
Step：
Step 6: forming field oxide, grid oxygen, polysilicon gate, P type trap zone, source region, interlayer film, contact hole, front metal and blunt
Change layer.
3. super junction-semiconductor device manufacture method as claimed in claim 2, it is characterised in that the super-junction semiconductor device
The polysilicon gate of part is trench gate structure, and the step of forming the grid oxygen and the polysilicon gate includes：
Step 61a, using lithographic etch process the second photoetching offset plate figure of formation, second photoetching offset plate figure defines gate groove
Pattern；Using second photoetching offset plate figure, the N-type silicon epitaxy layer described in mask, which is performed etching, to form the gate groove；Remove institute
State the second photoetching offset plate figure；
Step 62a, lower surface and side formation oxide layer in the gate groove, the oxide layer by the side of the gate groove
Constitute the grid oxygen；
Step 63a, filling polysilicon forms the polysilicon gate, the polycrystalline in the gate groove for forming the grid oxygen
Si-gate covers the P type trap zone from side, is used for the company of being formed by the surface of the P type trap zone of polysilicon gate side covering
Connect the raceway groove of the source region and the N-type silicon epitaxy layer.
4. super junction-semiconductor device manufacture method as claimed in claim 2, it is characterised in that the super-junction semiconductor device
The polysilicon gate of part is planar gate structure, and the step of forming the grid oxygen and the polysilicon gate includes：
Step 61b, on the N-type silicon epitaxy layer surface sequentially form the first oxide layer and the second polysilicon layer；
Step 62b, using lithographic etch process to being performed etching successively to second polysilicon layer and first oxide layer
Form planar gate structure described in the grid oxygen and the polysilicon gate and composition；The polysilicon gate covers the p-type from top
Well region, is used to form the connection source region and the N-type silicon by the surface of the P type trap zone of covering at the top of the polysilicon gate
The raceway groove of epitaxial layer.
5. super junction-semiconductor device manufacture method as claimed in claim 1, it is characterised in that：Formed on the silicon chip
The N-type silicon epitaxy layer is 20 microns~70 microns, and electrical resistivity range is the ohmcm of 0.5 ohmcm~5.
6. super junction-semiconductor device manufacture method as claimed in claim 1, it is characterised in that：The depth of the deep trench is
30 microns~60 microns.
7. super junction-semiconductor device manufacture method as claimed in claim 1, it is characterised in that：The hard mask layer is oxidation
Thing；Or, the hard mask layer is nitride；Or, the hard mask layer is the combination of oxide and nitride.
8. super junction-semiconductor device manufacture method as claimed in claim 3, it is characterised in that：Grid ditch described in step 61a
The depth of groove is 1 micron~6 microns.
9. super junction-semiconductor device manufacture method as claimed in claim 1, it is characterised in that：P-type layer described in step 5
P type impurity injection implantation dosage be 1e12cm-2~1e15cm-2, Implantation Energy be 10Kev~60Kev, injection element be
Boron difluoride or boron.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410459207.5A CN104517855B (en) | 2014-09-11 | 2014-09-11 | Super junction-semiconductor device manufacture method |
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| CN107346738B (en) * | 2016-05-04 | 2020-03-06 | 北大方正集团有限公司 | Manufacturing method of super junction power device |
| CN106340458A (en) * | 2016-10-11 | 2017-01-18 | 无锡同方微电子有限公司 | Manufacturing method for reducing manufacturing cost of deep-groove type super junction MOSFET |
| CN112002643B (en) * | 2020-08-21 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
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| CN101969068A (en) * | 2010-08-06 | 2011-02-09 | 浙江大学 | Edge terminal structure of high-voltage power semiconductor device |
| CN102760756A (en) * | 2012-06-30 | 2012-10-31 | 东南大学 | Super junction metallic oxide field effect tube terminal structure with floating field plate |
| CN103050539A (en) * | 2012-12-18 | 2013-04-17 | 上海华虹Nec电子有限公司 | Terminal protection structure of super junction device |
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| CN101969068A (en) * | 2010-08-06 | 2011-02-09 | 浙江大学 | Edge terminal structure of high-voltage power semiconductor device |
| CN102760756A (en) * | 2012-06-30 | 2012-10-31 | 东南大学 | Super junction metallic oxide field effect tube terminal structure with floating field plate |
| CN103050539A (en) * | 2012-12-18 | 2013-04-17 | 上海华虹Nec电子有限公司 | Terminal protection structure of super junction device |
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