CN105513971A - Manufacturing method of trench gate power device with shield gate - Google Patents
Manufacturing method of trench gate power device with shield gate Download PDFInfo
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- CN105513971A CN105513971A CN201510992525.2A CN201510992525A CN105513971A CN 105513971 A CN105513971 A CN 105513971A CN 201510992525 A CN201510992525 A CN 201510992525A CN 105513971 A CN105513971 A CN 105513971A
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- hard mask
- polysilicon
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 80
- 229920005591 polysilicon Polymers 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 30
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 91
- 238000000034 method Methods 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000407 epitaxy Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000006396 nitration reaction Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- -1 boron ion Chemical class 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910015900 BF3 Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Abstract
The invention discloses a manufacturing method of a trench gate power device with a shield gate. The manufacturing method comprises the following steps that: a hard mask layer is formed on the surface of a semiconductor substrate, and a gate forming region is defined on the surface of the semiconductor substrate through photoetching; first anisotropic etching is performed on the semiconductor substrate at the gate forming region, so that trenches can be formed, and the width of the trenches is expanded to a width larger than an opening width defined by the hard mask layer through second isotropic etching; a gate dielectric layer and a polysilicon gate are formed; back etching is performed on the polysilicon gate; with the hard mask layer adopted as a mask, third isotropic etching is performed on the semiconductor substrate at the bottoms of the trenches, so that deep trenches can be formed; a first oxide layer is formed at the side surfaces and bottom surfaces of the deep trenches as well as the side surfaces of the polysilicon gate simultaneously; and source polysilicon is grown. With the manufacturing method of the invention adopted, the polysilicon gate of a sidewall polysilicon structure can be formed, and the thickness of a gate and source isolation oxide layer can be improved, and gate and source electric leakage can be decreased.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to the manufacture method that one has the trench-gate power devices of shield grid (ShieldGateTrench, SGT).
Background technology
As shown in Figure 1A to Fig. 1 F, it is the existing device architecture schematic diagram had in each step of manufacture method of the trench-gate power devices of shield grid; This method adopts bottom-to-top method to form the trench gate structure with shield grid, comprises the steps:
Step one, as shown in Figure 1A, provide semi-conductive substrate as silicon substrate 101; Form hard mask layers 102 on the surface of Semiconductor substrate 101, hard mask layers 102 can adopt oxide layer, or adopts oxide layer to add nitration case.Adopt photoetching process to carry out etching to hard mask layers 102 afterwards and define grid forming region, form deep trench 103 with hard mask layers 102 for mask carries out etching to Semiconductor substrate 101 more afterwards.
Step 2, as shown in Figure 1B, forms oxide layer 104 in the side of deep trench 103 and lower surface.
Step 3, as shown in Figure 1 C, in described deep trench 103, fill source polysilicon, this source polysilicon is the polysilicon as shield grid.
Step 4, as shown in figure ip, the oxide layer 104 of deep trench 103 top area to be removed.
Step 5, as referring to figure 1e, forms gate oxide and polysilicon gate 106.Polysilicon gate 106 is trench gate.
Step 6, as shown in fig. 1f, form well region 107, source region 108, well region contact zone 109, interlayer film 110, contact hole 111, front metal layer 112, form source electrode and grid respectively to front metal layer 112 photoetching, wherein source electrode is contacted by the source region 108 of contact hole and bottom, well region contact zone 109 and source polysilicon 105, and grid is contacted with polysilicon gate 106 by contact hole.
Be formed in formation drain region, the back side and the metal layer on back of Semiconductor substrate 101 afterwards.
In existing method, a side of polysilicon gate 106 is isolated by gate oxide and well region 107, and the surface covered by polysilicon gate 106 side of well region 107 is for the formation of raceway groove.Shown in Fig. 1 F, the polysilicon gate 106 that above-mentioned existing method is formed only is positioned at the sidewall at deep trench top, and this vertical power device with sidewall polycrystalline silicon structure can increase operating current; Source polysilicon 105 is filled in whole deep trench simultaneously, and source polysilicon 105 can form good shielding, has less bottom capacitor, thus can reduce the input capacitance of source and drain or grid leak, improves frequency characteristic.But, in above-mentioned existing method, oxide layer and grid source isolating oxide layer and the gate oxide of isolation between another side of polysilicon gate 106 and source polysilicon 105 are formed simultaneously, and this makes grid source isolating oxide layer the same with gate oxide thin, and this can bring larger grid source and drain electricity.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method with the trench-gate power devices of shield grid, can form the polysilicon gate of sidewall polycrystalline silicon structure, can improve the thickness of grid source isolating oxide layer, reduce grid source and drain electricity.
For solving the problems of the technologies described above, the manufacture method with the trench-gate power devices of shield grid provided by the invention, comprises the steps:
Step one, provide semi-conductive substrate, form hard mask layers at described semiconductor substrate surface, adopt photoetching process to define grid forming region, adopt etching technics the described hard mask layers of described grid forming region to be removed.
Step 2, form groove with the described hard mask layers after etching for mask carries out first time anisotropic etching to described Semiconductor substrate, carry out carrying out second time isotropic etching to described Semiconductor substrate after described first time anisotropic etching, the width of described groove is etched into the A/F being greater than described hard mask layers and defining by described second time isotropic etching.
Step 3, form gate dielectric layer and polysilicon gate successively in the side of described groove and lower surface, between the described polysilicon gate of described groove two sides, have spacing, described polysilicon gate also extends to the described hard mask layers surface outside described groove.
Step 4, carry out back carving to described polysilicon gate, the described polysilicon gate on the described hard mask layers surface of described trench bottom surfaces and described groove outside is removed by this time carving technology, and after described time carving technology, the described polysilicon gate of described groove side surface retains.
Step 5, with described hard mask layers for the described Semiconductor substrate of mask to described channel bottom carry out third time anisotropic etching formed deep trench.
Step 6, form the first oxide layer in the side of the side of described deep trench and lower surface and described polysilicon gate simultaneously.
Step 7, carry out source polycrystalline silicon growth, the described deep trench and described groove that are formed with described first oxide layer are filled by described source polysilicon completely.
Further improvement is, the spacing after returning carving technology described in step 4 between the described polysilicon gate of described groove two sides is more than or equal to the A/F that described hard mask layers defines.
Further improvement is, after step 7, also comprises the steps:
Step 8, the described source polysilicon by outside described groove, described first oxide layer and described hard mask layers are all removed and are exposed by described semiconductor substrate surface.
Step 9, carry out ion implantation and thermal annealing and advance technique to form well region in described Semiconductor substrate, described polysilicon gate cover described well region from the side and the described well region surface covered by described polysilicon gate side for the formation of raceway groove.
Step 10, carry out heavily doped source be infused in described well region surface formed source region.
Step 11, form interlayer film, contact hole and front metal layer in described Semiconductor substrate front, chemical wet etching is carried out to described front metal layer and forms source electrode and grid, described source electrode is by contact hole and described source region and described source polysilicon contact, and described grid is contacted with described polysilicon gate by contact hole.
Step 12, carry out thinning to the described Semiconductor substrate back side and form heavily doped drain region, forming metal layer on back as drain electrode at the back side in described drain region.
Further improvement is, described Semiconductor substrate is silicon substrate, is formed with silicon epitaxy layer in described surface of silicon, and described deep trench is positioned at described silicon epitaxy layer.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, described hard mask layers is made up of oxide layer or adds nitration case by oxide layer and forms.
Further improvement is, trench-gate power devices is groove power MOSFET element.
Further improvement is, after the opening of contact hole described in step 11 is formed, metal filled before, the bottom being also included in the contact hole contacted with described source region is carried out heavy doping and is injected the step forming well region contact zone.
The present invention is by top-down technological process, first form the polysilicon gate at top, etching forms deep trench further again, polysilicon gate adopts sidewall polycrystalline silicon structure, like this before the polysilicon of formation source, the first oxide layer can be formed in the side of the side of deep trench and lower surface and polysilicon gate simultaneously, the bottom of the first oxide layer is as the isolating oxide layer between source polysilicon and Semiconductor substrate, the top of the first oxide layer is then as the isolating oxide layer between polysilicon gate and source polysilicon and grid source isolating oxide layer, relative to existing bottom-to-top method, grid source of the present invention isolating oxide layer need not be subject to the restriction of the thickness of thinner gate oxide again, thus the thickness of grid source isolating oxide layer can be improved, reduce grid source and drain electricity.
In addition, the groove at deep trench of the present invention and top is self-alignment structure, namely the present invention is by after increasing by a step isotropic etching broadening to groove, and after quarter is returned to polysilicon gate, still can adopt the hard mask layers definition deep trench of definition groove, namely the present invention does not need to increase other photoetching process to define deep trench, so the present invention adopts lower process costs just can realize yet.
The polysilicon gate that the inventive method is formed has sidewall polycrystalline silicon structure, can increase the operating current of vertical power device.The source polysilicon that the inventive method is formed simultaneously is filled in whole deep trench, has less bottom capacitor, thus can reduce the input capacitance of source and drain or grid leak, improves frequency characteristic.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Figure 1A-Fig. 1 F is the existing device architecture schematic diagram had in each step of manufacture method of the trench-gate power devices of shield grid;
Fig. 2 is embodiment of the present invention method flow diagram;
Fig. 3 A-Fig. 3 N is the device architecture schematic diagram in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 2, be embodiment of the present invention method flow diagram; As shown in Fig. 3 A to Fig. 3 M, it is the device architecture schematic diagram in each step of embodiment of the present invention method.In the embodiment of the present invention for groove 4 grid power device for groove 4 gate power MOSFET device is described, the embodiment of the present invention has the manufacture method of the groove 4 grid power device of shield grid, comprises the steps:
Step one, as shown in Figure 3A, provide semi-conductive substrate 1, form hard mask layers 2 on described Semiconductor substrate 1 surface.Described hard mask layers 2 is made up of oxide layer or adds nitration case by oxide layer and forms.
Described Semiconductor substrate 1 is silicon substrate, and this silicon substrate is the silicon epitaxial wafer that surface is formed with silicon epitaxy layer, and described deep trench 6 is positioned at described silicon epitaxy layer.The conductivity of the silicon epitaxy layer of described silicon substrate is 2 ohmcm ~ 15 ohmcms, and thickness is 2 microns ~ 20 microns, depends on the requirement of chip application puncture voltage, and puncture voltage scope is generally 20 volts ~ 200 volts.
As shown in Figure 3 B, the photoetching offset plate figure 3 adopting photoetching process to be formed defines grid forming region, adopts etching technics the described hard mask layers 2 of described grid forming region to be removed.
Step 2, as shown in Figure 3 C, with the described hard mask layers 2 after etching for mask carries out first time anisotropic etching formation groove 4 to described Semiconductor substrate 1.
In the embodiment of the present invention, the degree of depth of described groove 4 is 0.8 micron ~ 1.5 microns.
As shown in Figure 3 D, carry out carrying out second time isotropic etching to described Semiconductor substrate 1 after described first time anisotropic etching, the width of described groove 4 is etched into the A/F being greater than described hard mask layers 2 and defining by described second time isotropic etching.
Step 3, as shown in FIGURE 3 E, gate dielectric layer is formed successively as gate oxide and polysilicon gate 5 in the side of described groove 4 and lower surface, between the described polysilicon gate 5 of described groove 4 two sides, have spacing, described polysilicon gate 5 also extends to described hard mask layers 2 surface outside described groove 4.
Step 4, as illustrated in Figure 3 F, carry out back carving to described polysilicon gate 5, the described polysilicon gate 5 on described hard mask layers 2 surface of described groove 4 lower surface and described groove 4 outside is removed by this time carving technology, and after described time carving technology, the described polysilicon gate 5 of described groove 4 side retains.Be preferably, the spacing after described time carving technology between the described polysilicon gate 5 of described groove 4 two sides is more than or equal to the A/F that described hard mask layers 2 defines.
Step 5, as shown in Figure 3 G, with described hard mask layers 2, to be mask carry out third time anisotropic etching to the described Semiconductor substrate 1 bottom described groove 4 forms deep trench 6.
In the embodiment of the present invention, the degree of depth of described deep trench 6 is 1 micron ~ 5 microns.
Step 6, as shown in figure 3h, form the first oxide layer 7 in the side of described deep trench 6 and the side of lower surface and described polysilicon gate 5 simultaneously.In the embodiment of the present invention, the thickness of described first oxide layer 7 is 0.3 micron ~ 1.5 microns.
Step 7, as shown in fig. 31, carry out source polysilicon 8 and grow, the described deep trench 6 and described groove 4 that are formed with described first oxide layer 7 are filled by described source polysilicon 8 completely.
Step 8, as shown in figure 3j, the described source polysilicon 8 outside described groove 4, described first oxide layer 7 and described hard mask layers 2 are all removed and described Semiconductor substrate 1 surface is exposed.
Step 9, as shown in Fig. 3 K, carrying out ion implantation and thermal annealing advances technique to form well region 9 in described Semiconductor substrate 1, described polysilicon gate 5 cover described well region 9 from the side and described well region 9 surface covered by described polysilicon gate 5 side for the formation of raceway groove.
For NMOSFET device, the ion implantation of described well region 9 is P type ion implantation, and the ion being preferably injection is boron ion, and implantation dosage is 1E13cm
-2~ 1E13cm
-2.
For PMOSFET device, the ion implantation of described well region 9 is N-type ion implantation, and the ion being preferably injection is phosphonium ion, and implantation dosage is 1E13cm
-2~ 1E13cm
-2.
Step 10, as shown in Fig. 3 K, carry out heavily doped source be infused in described well region 9 surface formed source region 10.
For NMOSFET device, the ion implantation in described source region 10 is N-type ion implantation, and the ion being preferably injection is arsenic or phosphonium ion, and implantation dosage is for being greater than 5E15cm
-2.
For PMOSFET device, the ion implantation in described source region 10 is P type ion implantation, and the ion being preferably injection is boron or boron fluoride ion, and implantation dosage is for being greater than 5E15cm
-2.
Step 11, as shown in figure 3l, forms interlayer film 11 in described Semiconductor substrate 1 front.In the embodiment of the present invention, the thickness of described interlayer film 11 is 3K micron ~ 20K micron.
The photoetching offset plate figure 12 adopting photoetching process to be formed defines the forming region of contact hole 13, adopts etching technics to be removed by the interlayer film 11 of the forming region of contact hole 13 and forms contact hole 13.
Well region contact zone 14 is formed in the bottom of the contact hole 13 of drawing described source region 10 and described well region 9.
For NMOSFET device, the ion implantation of described well region contact zone 14 is P type ion implantation, and the ion being preferably injection is boron or boron fluoride ion, and implantation dosage is for being greater than 5E15cm
-2.
For PMOSFET device, the ion implantation of described well region contact zone 14 is N-type ion implantation, and the ion being preferably injection is arsenic or phosphonium ion, and implantation dosage is for being greater than 5E15cm
-2.
As shown in fig.3m, metal 14 is filled in contact hole 13, form front metal layer 16, chemical wet etching is carried out to described front metal layer 16 and forms source electrode and grid, described source electrode is contacted with described source region 10 and described source polysilicon 8 by the metal 14 of contact hole 13, and described grid is contacted with described polysilicon gate 5 by the metal 14 of contact hole 13.
Step 12, as shown in Fig. 3 N, described Semiconductor substrate 1 back side carried out thinning and formed heavily doped drain region, forming metal layer on back 17 at the back side in described drain region and drain.The thickness of described Semiconductor substrate 1 thinning back side is 100 microns ~ 300 microns.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. there is a manufacture method for the trench-gate power devices of shield grid, it is characterized in that, comprise the steps:
Step one, provide semi-conductive substrate, form hard mask layers at described semiconductor substrate surface, adopt photoetching process to define grid forming region, adopt etching technics the described hard mask layers of described grid forming region to be removed;
Step 2, form groove with the described hard mask layers after etching for mask carries out first time anisotropic etching to described Semiconductor substrate, carry out carrying out second time isotropic etching to described Semiconductor substrate after described first time anisotropic etching, the width of described groove is etched into the A/F being greater than described hard mask layers and defining by described second time isotropic etching;
Step 3, form gate dielectric layer and polysilicon gate successively in the side of described groove and lower surface, between the described polysilicon gate of described groove two sides, have spacing, described polysilicon gate also extends to the described hard mask layers surface outside described groove;
Step 4, carry out back carving to described polysilicon gate, the described polysilicon gate on the described hard mask layers surface of described trench bottom surfaces and described groove outside is removed by this time carving technology, and after described time carving technology, the described polysilicon gate of described groove side surface retains;
Step 5, with described hard mask layers for the described Semiconductor substrate of mask to described channel bottom carry out third time anisotropic etching formed deep trench;
Step 6, form the first oxide layer in the side of the side of described deep trench and lower surface and described polysilicon gate simultaneously;
Step 7, carry out source polycrystalline silicon growth, the described deep trench and described groove that are formed with described first oxide layer are filled by described source polysilicon completely.
2. there is the manufacture method of the trench-gate power devices of shield grid as claimed in claim 1, it is characterized in that: the spacing after returning carving technology described in step 4 between the described polysilicon gate of described groove two sides is more than or equal to the A/F that described hard mask layers defines.
3. there is the manufacture method of the trench-gate power devices of shield grid as claimed in claim 1, it is characterized in that: after step 7, also comprise the steps:
Step 8, the described source polysilicon by outside described groove, described first oxide layer and described hard mask layers are all removed and are exposed by described semiconductor substrate surface;
Step 9, carry out ion implantation and thermal annealing and advance technique to form well region in described Semiconductor substrate, described polysilicon gate cover described well region from the side and the described well region surface covered by described polysilicon gate side for the formation of raceway groove;
Step 10, carry out heavily doped source be infused in described well region surface formed source region;
Step 11, form interlayer film, contact hole and front metal layer in described Semiconductor substrate front, chemical wet etching is carried out to described front metal layer and forms source electrode and grid, described source electrode is by contact hole and described source region and described source polysilicon contact, and described grid is contacted with described polysilicon gate by contact hole;
Step 12, carry out thinning to the described Semiconductor substrate back side and form heavily doped drain region, forming metal layer on back as drain electrode at the back side in described drain region.
4. the manufacture method with the trench-gate power devices of shield grid as described in claim 1 or 3, is characterized in that: described Semiconductor substrate is silicon substrate, is formed with silicon epitaxy layer in described surface of silicon, and described deep trench is positioned at described silicon epitaxy layer.
5. there is the manufacture method of the trench-gate power devices of shield grid as claimed in claim 1, it is characterized in that: described gate dielectric layer is gate oxide.
6. there is the manufacture method of the trench-gate power devices of shield grid as claimed in claim 1, it is characterized in that: described hard mask layers is made up of oxide layer or adds nitration case by oxide layer and forms.
7. there is the manufacture method of the trench-gate power devices of shield grid as claimed in claim 3, it is characterized in that: trench-gate power devices is groove power MOSFET element.
8. there is the manufacture method of the trench-gate power devices of shield grid as claimed in claim 3, it is characterized in that: after the opening of contact hole described in step 11 is formed, metal filled before, the bottom being also included in the contact hole contacted with described source region is carried out heavy doping and is injected the step forming well region contact zone.
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| CN106057675A (en) * | 2016-05-31 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Shield gate trench MOSFET manufacturing method |
| CN112436057A (en) * | 2020-10-15 | 2021-03-02 | 上海芯导电子科技股份有限公司 | Low-on-resistance MOS device and preparation process thereof |
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| CN113866811A (en) * | 2021-08-12 | 2021-12-31 | 中国辐射防护研究院 | Improved processing method of silicon-based micro-dosimeter |
| CN114023648A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing trench gate semiconductor device |
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