CN105895690A

CN105895690A - Super-junction device structure and manufacturing method thereof

Info

Publication number: CN105895690A
Application number: CN201510086221.XA
Authority: CN
Inventors: 肖胜安
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-02-16
Filing date: 2015-02-16
Publication date: 2016-08-24

Abstract

The present invention discloses a super-junction device. A current flow region comprises at least three sections of structures in a vertical direction. The first section is a PN film region layer, the resistivity of an N-type film is lower than that of a silicon substrate, and the resistivity of a P-type film is set to ensure the charge balance of the N-type film and the P-type film in an alternate arrangement. The second section is an N-type drift region layer whose resistivity is equal to that of the silicon substrate. The third section is an ohm contact region layer which comprises a contact region whose resistivity is smaller than or equal to the 1/100 of the resistivity of the silicon substrate. The N-type film in the first section is realized by epitaxial process. Through adjusting the thickness of the first section PN film region layer and the thickness of the second section N-type drift region layer, the balance between the conduction resistance and the switching performance of the device can be adjusted, and the current shock resistance ability of the device can be improved. Through using the back implantation and annealing to form the third section N type region, the switching performance of the device is improved further. The invention also discloses a manufacturing method of the super-junction device.

Description

A kind of super junction device structure and manufacture method thereof

Technical field

The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of super junction metal- MOSFET device architecture；The invention still further relates to the manufacture of a kind of super-junction device Method.

Background technology

Super junction metal-oxide layer semiconductcor field effect transistor, is called for short super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) adopts By new structure of voltage-sustaining layer, a series of alternately arranged P-type semiconductor thin layer and N-type is utilized partly to lead Body thin layer the most described P-type semiconductor thin layer and N-type partly leads Body thin layer exhausts, it is achieved electric charge mutually compensates for, so that P-type semiconductor thin layer and N-type semiconductor are thin Layer can realize high breakdown reverse voltage under high-dopant concentration, thus obtain simultaneously low on-resistance and High-breakdown-voltage, break traditions power MOSFET theoretical limit.In United States Patent (USP) US5216275, Above alternately arranged P-type semiconductor thin layer is connected with N+ substrate with N-type semiconductor thin layer； In United States Patent (USP) US6630698B1, middle P-type semiconductor thin layer and N-type semiconductor thin layer with N+ substrate can have the interval more than 0.

In prior art, the formation one of P-type semiconductor thin layer and N-type semiconductor thin layer is by outward Prolong growth and then carry out photoetching and injection, on high-dopant concentration substrate, epitaxial growth-light is repeated several times The technical process of quarter-ion implanting obtains needing the P-type semiconductor thin layer of thickness and N-type semiconductor thin Layer, this technique, in the MOSFET of more than 600V, it is generally required to be repeated 5 times above, produces into This and production cycle are long.Another kind is a type of by once growing on high-dopant concentration substrate After needing the extension of thickness, carry out the etching of groove, insert the silicon of opposite types the most in the trench； Although this method difficulty is big, but has simplification of flowsheet, improve the effect of stability；Both Manufacture method and corresponding device architecture, be required for the thickest epitaxial layer, such as 600 volts super Node MOSFET device, the thickness of epitaxial layer is about at 45-55 micron, and the epitaxial layer of such thickness brings The problem that manufacturing cost is high, epitaxial layer is the thickest, and manufacture difficulty is the biggest, simultaneously because PN thin layer The change of formation process (such as trench etch process, or ion implantation technology), easily causes PN thin N-type epitaxy layer thickness under Ceng changes, when this N-type epitaxy layer thickness is the thinnest, and may impact The resistance to rush of current ability of device.

Summary of the invention

The technical problem to be solved is to provide a kind of super junction device structure and manufacturer thereof Method, can reduce the difficulty of epitaxial diposition, reduce the cost of epitaxial diposition, be also convenient for adjusting device simultaneously Conducting resistance and the switch performance of device between balance；And the turn-off characteristic of device can be improved, carry The high ability of the resistance to rush of current of device.

For solving above-mentioned technical problem, the super-junction device that the present invention provides is formed at N-type silicon chip substrate On, the zone line of described super-junction device is electric current flow region, and terminal protection structure is surrounded on described The periphery of electric current flow region；Described electric current flow region is vertically including at least three-stage structure, and first Section is PN thin layer region layer, is made up of alternately arranged N-type thin layer and p-type thin layer, N-type thin-layer electric Resistance rate is less than the resistivity of silicon chip substrate, and the setting of p-type sheet resistance rate to ensure alternately arranged N Type thin layer and p-type thin layer realize charge balance, and the N-type thin layer in first paragraph is by epitaxial diposition work Skill realizes；Second segment is N-type drift region layer, and its resistivity is equal to silicon chip substrate resistivity；3rd Section is N-type Ohmic contact region layer, and described N-type ohmic contact regions layer resistivity drifts about less than described N-type The resistivity in district, and comprise the contact less than or equal to the 1/100 of silicon chip substrate resistivity of the resistivity District.

In the PN thin layer region layer of the first paragraph of device, obtained the low-resistivity needed by epitaxial diposition The N thin layer of (high impurity doping concentration), in order to reduce the conducting resistance of device, the height in this section of region The N-type thin layer of impurity doping concentration, to form alternately arranged PN thin with the p-type thin layer formed afterwards Layer region layer, under device is in blocking state, p-type thin layer and N-type thin layer exhaust mutually, suitably Under conditions of charge balance so that the afforded blocking voltage in this section of region is not by impurity in N thin layer The restriction of concentration, such that it is able to obtain high blocking voltage and low conducting resistance simultaneously.

The N-type drift region layer of second segment, its resistivity is equal to silicon chip substrate resistivity, the N of second segment The blocking voltage of the PN thin layer region layer shared device of type drift region layer and first paragraph.Second segment N-type drift region is not owing to having horizontal P thin layer to provide compensation electric charge, and therefore impurity doping concentration has Certain restriction.In Figure 12-2, longitudinal electric field intensity is approximately in the PN thin layer region layer of first paragraph Flat, progressively reduce from the longitudinal electric field intensity of the N-type drift region layer of second segment, this electric-field strength Area under degree distribution, if the area of trapezoidal OEWG is the blocking voltage of undertaken in the case of this, In order to obtain more preferable impact resistance and anti-electromagnetic interference capability, when device designs, general warranty When breakdown voltage occurs, depletion region does not wants broadening to the scope beyond N-type drift region, because if this Time depletion region launch beyond N-type drift region and touched low-resistivity (high impurity doping concentration) N-type Ohmic contact region layer, impact resistance and the anti-electromagnetic interference capability of device are it is possible under Ming Xian Fall.

Owing to the PN thin layer region layer of first paragraph and the N-type drift region layer shared of second segment block electricity Pressure, the thickness of the N-type epitaxy layer deposited the most here is less than epitaxial layer deposition thickness of the prior art (for the device of same breakdown reverse voltage), thus reduce the difficulty of epitaxial layer deposition, minimizing Epitaxial layer manufacturing cost.

The N-type Ohmic contact region layer of the 3rd section, will form Ohmic contact with back metal, and therefore it connects The region touching metal must have higher than 1 × 10¹⁹atoms/cm³Impurity concentration, this N-type ohm connects Tactile region layer can be formed by ion implanting and annealing process, and its ion implanting can be one or many Ion implanting is formed, when using repeatedly ion implanting, by a high-energy and relatively small injectant The technique of amount, can form one and not be very greatly with the impurity concentration difference of N-type drift region layer, have Certain thickness region, improves impact resistance and the anti-electromagnetic interference capability of device further.

For the device of same breakdown reverse voltage, by increasing the thickness of first paragraph PN thin layer region layer, Reduce the thickness of second segment N-type drift region layer, lower conducting resistance can be obtained, but due to P-N The increase of junction area, switching loss has certain increase, thinning due to N-type drift region layer thickness, The resistance to rush of current ability of device can decline.If reducing the thickness of first paragraph PN thin layer region layer, Increasing the thickness of second segment N-type drift region layer, conducting resistance can increase, but due to P-N junction area Reducing, switching loss has certain minimizing, due to thickening of N-type drift region, the resistance to electric current of device Impact capacity can be improved.

Further improve and be, between described N-type Ohmic contact region layer and described N-type drift region layer The thickness of transition region is 0.2-3 micron, when transition region reaches more than 1 micron, will improve device Impact resistance and anti-electromagnetic interference capability, the thickness of this transition region is the biggest, the shock resistance energy of device Power and anti-electromagnetic interference capability are the strongest.

Further improve and be, the p type island region of described PN thin layer region layer can be by ion implanting and Annealing process manufactures, it is also possible to be the technique manufacture by trench fill.By ion implanting and When annealing process manufactures, the thickness of this PN thin layer is typically within 10 microns, but low cost of manufacture； When using trench fill process to manufacture, the thickness in PN thin layer district is not limited.

Further improve and be, in described PN thin layer region layer, the p-type carrier population of p-type thin layer More than the N-type carrier sum of N-type thin layer, the p-type carrier population of p-type thin layer and N-type thin layer N-type carrier sum difference less than N-type thin layer type carrier population 10%；Due to PN thin layer Under have a thicker N-type drift region layer, in PN thin layer district, the p-type carrier of p-type thin layer compares N The part that the N-type carrier of type thin layer has more can be carried out with the N-type carrier in N-type drift region middle level Exhausting, that reduces the P type trap zone at p-well-N thin layer knot exhausts thickness, also reduces p-well-N thin Electric-field intensity at layer knot, can improve the breakdown voltage of device.But the p-type carrier of p-type thin layer Sum can not be too big, and during too conference causes PN thin layer district, transverse electric field and internal field strengthen, and lead Cause electric leakage and increase the problems such as low with breakdown reverse voltage.

Further improve is that the thickness of described PN thin layer region layer is more than 10 microns；PN thin layer is protected Hold certain thickness, preferably to be reduced the effect of conducting resistance.

Further improve is that described N-type drift region layer thickness is more than 10 microns；N-type drift region Layer keeps certain thickness, to strengthen impact resistance and the anti-electromagnetic interference capability of device.

The invention also discloses the manufacture method of super-junction device.The present invention can make manufacturing cost minimum Change, simultaneously can also pass between ratio conducting resistance and the switch performance of device of adjusting device easily System, improves power of resisting voltaic impingement and the anti-electromagnetic interference capability of device, and improves device shock resistance energy Power and the uniformity of anti-electromagnetic interference capability.

For solving above-mentioned technical problem, the invention provides the manufacture method of super-junction device, the first Manufacture method is the manufacture method of super junction flat-grid MOSFET component, comprises the steps:

Step one, carry out N-type epitaxial diposition at front side of silicon wafer, form a resistivity less than N-type silicon The N-type epitaxy layer of sheet resistance substrate rate；

Step 2, deposit the first silicon dioxide layer, the second silicon nitride layer and the 3rd successively at front side of silicon wafer Silicon dioxide layer；Utilize lithographic etch process successively to described 3rd silicon dioxide layer, described second nitrogen SiClx layer and described first silicon dioxide layer form groove figure mask；

Step 3, for mask, described silicon chip performed etching the multiple ditches of formation with described groove figure mask Groove；In described electric current flow region, the described N-type epitaxy layer between each described groove is laminate structure； Successively described 3rd silicon dioxide layer and described second silicon nitride layer of described groove figure mask are gone Removing, described first silicon dioxide layer retains；

Step 4, described front side of silicon wafer deposit P-type silicon epitaxial layer, described P-type silicon epitaxial layer is by institute State groove to be fully filled with；Silicon and the silica of described groove top surface are all removed；

In described electric current flow region, it is made up of the described P-type silicon epitaxial layer being filled in described groove P-type thin layer, is formed N-type thin layer by the described N-type epitaxy layer between p-type thin layer, alternately arranged N-type thin layer and p-type thin layer constitute described PN thin layer region layer.

Described N-type thin layer and p-type thin layer need to realize charge balance, the N of the most described N-type thin layer The absolute value of the difference of the p-type carrier population of type carrier population and its neighbouring described p-type thin layer Less than the 10% of the N-type carrier sum of described N-type thin layer, again smaller than the p-type of described p-type thin layer The 10% of carrier population；

Step 5, the top of each described p-type thin layer formed p-well, each described p-well also extends into portion Divide described N-type thin layer top；Described N-type thin layer top area between each described p-well is that N-type is led Logical district；

Step 6, successively deposit gate dielectric layer and polysilicon gate, use lithographic etch process to described many Crystal silicon grid perform etching, and the described polysilicon gate after described gate dielectric layer and etching forms described super junction The grid structure of flat-grid MOSFET component；Described polysilicon gate covers the conducting of described N-type from top District and the described p-well of part and the described p-well that vertically covered by described polysilicon gate are for forming horizontal stroke To raceway groove；

Step 7, carry out N+ ion implanting formed source region；Described source region is formed at described p-well top And and described polysilicon gate autoregistration；

Step 8, defining described source region described front side of silicon wafer formed interlayer film；Employing photoetching is carved Etching technique forms contact hole, and described contact hole is through described interlayer film and described source region or described polycrystalline Si-gate contacts；Carrying out P+ ion implanting and form p-well draw-out area, described p-well draw-out area is positioned at and institute Stating under bottom the described contact hole that source region contacts, described p-well draw-out area and described p-well contact；

Step 9, deposit front metal also carry out chemical wet etching to described front metal and form source electrode respectively And grid；

Step 10, from silicon chip back side, the substrate of described silicon chip is carried out thinning；

Step 11, carry out backside particulate injection and annealing formed described N-type Ohmic contact region layer, structure Become the drain region of described MOSFET element；

Step 12, carry out back face metalization and form the drain electrode of described MOSFET element.

The second manufacture method that the present invention provides is the manufacturer of super junction trench gate mosfet device Method, comprises the steps:

Step one, carry out N-type epitaxial diposition at front side of silicon wafer, form a resistivity less than N-type silicon The N-type epitaxy layer of sheet resistance substrate rate

Step 5, employing lithographic etch process form groove, and groove is positioned at the N-type of PN thin layer region layer In thin layer district, depositing gate dielectric film, groove is filled up completely with by depositing polysilicon grid afterwards, passes through afterwards Return to carve and form polysilicon grating structure；

Step 6, the top of each described p-type thin layer formed p-well, each described p-well also extends into portion Divide described N-type thin layer top；The described p-well vertically covered by described polysilicon gate is vertical for being formed To raceway groove；

Improve further and be, in the first manufacture method described and the second manufacture method in step 11 Annealing process at least include a laser annealing.Employing laser annealing technique can be at silicon chip back side Local obtain the temperature higher than more than 900 degrees Celsius and while silicon chip surface temperature relatively low, will not be right The metal in front impacts, so that the impurity that the back side is injected obtains high activity ratio, reduces Dosage that the device back side is injected also improves the performance of device.

Improve further and be, in the first manufacture method described and the second manufacture method, step 11 In backside particulate inject in inject at the phosphorus of 1MeV-3MeV including at least Implantation Energy.Pass through The ion implanting of the appropriate dosage of high energy, can obtain a high impurity concentration district in contact zone and N A gradual district of certain thickness impurity concentration between type drift region, improves the resistance to electricity of device further Stream impact capacity.

Accompanying drawing explanation

The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings, by readding Read the following drawings detailed description that non-limiting embodiments is done, the present invention and feature thereof, profile and excellent Point becomes readily apparent from.Sign identical in whole accompanying drawings represents identical part.Accompanying drawing simply shows It is intended to, is also not drawn to scale, it is preferred that emphasis is represent the purport of the present invention:

Fig. 1-1 is existing super-junction device top view one；

Fig. 1-2 is existing super-junction device top view two；

The device electric charge flow region profile of Fig. 2-1 prior art

The genesis analysis figure of the N-type region impurity concentration of Fig. 2-2 prior art electric charge flow region

Fig. 3-Fig. 8 is the device of the manufacture method part steps of the embodiment of the present invention one super-junction device Electric charge flow region profile；

Fig. 9-Figure 10 is the device of the part steps of the manufacture method of the embodiment of the present invention two super-junction device Part electric charge flow region profile；

Figure 11 is the electric charge flow region profile of the embodiment of the present invention three super-junction device；

Figure 12-1 is that in the embodiment of the present invention, the impurity of the N-type region of super-junction device electric charge flow region is dense The genesis analysis figure of degree；

Figure 12-2 is the N of super-junction device electric charge flow region in the bar state in the embodiment of the present invention The distribution map of the longitudinal electric field intensity in type district；

Detailed description of the invention

As Figure 1-1, it is the top view one of existing super-junction device.On top view, super junction Device can be divided into 1st district, 2nd district and 3rd district.1st district is the zone line of super-junction device, for electric current Flow region, described electric current flow region comprises alternately arranged territory, p type island region 25 and N-type region territory, described Territory, p type island region 25 namely be formed at the p-type thin layer in described electric current flow region, described N-type region territory also I.e. it is formed at the N-type thin layer in described electric current flow region；In the on-state, described N-type region territory carries For electric current path (electric current by source electrode through raceway groove arrive and through the thin region of N-type arrive drain electrode), And territory, described p type island region 25 is to be formed with described N-type region territory in the bar state to bear together with depletion region Voltage.2nd district and the terminal protection structure region that 3rd district are described super-junction device, when break-over of device Described terminal protection structure does not provide current path, is used for undertaking from 1 periphery, district unit at blocking state I.e. the surface in territory, p type island region, periphery 25 is to the lateral voltage of device outer-most end surface substrate with from 1st district All cell surfaces are to the longitudinal voliage of silicon chip substrate.2nd district have at least one p-type ring 24, Fig. 1-1 In be a p-type ring 24, the general p-type backgate i.e. p-well with 1st district of this p-type ring 24 is connected to one Rise；2nd district have the field plate dielectric film with certain inclination angle, also has for slowing down table in 2nd district Face electric field polycrystalline jumpy field plate sheet and Metal field plate, and p-type post 23；Can also in 2nd district It is not provided with described Metal field plate.3rd district are by p-type post 23 and the N-type being made up of N-type silicon epitaxy layer The voltage that post is alternatively formed undertakes district, and it has deielectric-coating, described p-type post 23 namely be formed at institute State the p-type thin layer in terminal protection structure, described N-type post namely be formed at described terminal protection structure In N-type thin layer；3rd district there is Metal field plate, 3rd district can also be not provided with described Metal field plate；3 District can have p-type ring 24 can also not have, when having p-type ring 24 p-type ring at this be not with electricity (suspension) that the p-type back-gate connection of stream flow region is connected；Outermost end in 3rd district has channel cutoff Ring 21, described channel cutoff ring 21 is by N+ (high concentration N-type ion) injection region or N+ injection region again Add medium formed thereon or medium to constitute plus metal；By Fig. 1-1 it can be seen that described electric current The territory, cellular construction the most described p type island region 25 of flow region and N-type region territory are all strip structure；Described end End protection structure ring is around in periphery and described p-type ring 24, the described p-type post of described electric current flow region 23 and described channel cutoff ring 21 all in tetragonal circulus, circulus can be square Corner be the circulus at right angle, it is also possible to be the tetragonal corner circulus that has circular arc.

As shown in Figure 1-2, it is the top view two of existing super-junction device, and device as Figure 1-1 Part difference is, in the territory, cellular construction the most described p type island region 25 and N of described electric current flow region Type region is all tetragonal structure, i.e. by territory, tetragonal described p type island region 25 and N-type region territory two On dimension direction, proper alignment forms the cell array of described electric current flow region.Territory 25, described p type island region He N-type region territory also can be hexagon, octagon and other shape, territory, described p type island region 25 and N-type region The arrangement mode in territory also can carry out certain dislocation at X and Y-direction；As long as ensure whole arrangement be by Certain rule, carries out repeating the most permissible.

In existing super junction MOSFET element the generalized section of electric current flow region (Fig. 2-1 be), MOSFET element unit, the N of electric current flow region all it is formed above the N-type thin layer of electric current flow region Type thin layer 3, p-type thin layer 4 and MOSFET element unit repeat completely, such as to a breakdown voltage For as a example by the 600V i.e. device of BVds-600V: the N+ silicon chip substrate 1 of device is Uniform Doped, Resistivity is 0.001-0.003 ohmcm, and on N+ substrate 1, deposition thickness is 45 microns, Resistivity is the N-type silicon epitaxial layers of the Uniform Doped of 0.5 ohmcm～5 ohmcms；It Rear formation groove, fills p-type silicon epitaxial layers 4 in the trench, and p-type silicon epitaxial layers 4 can be along vertical To Uniform Doped, it is also possible to along longitudinally varying doping, stay N-type thin after such etching groove The p-type thin layer 4 that layer 3 and extension are filled just constitutes the PN thin layer alternately of super-junction device；? In electric current flow region, except the region close to device terminal, probably due to Terminal Design and technique cause Outside some differences, all of device cell is consistent, and in the horizontal, the structure of PN thin layer has been Full weight is multiple.The lower section of PN thin layer, transition region (deposits outside N-type on N+ substrate to have one to include After prolonging layer, the region of N-type impurity change in concentration) epitaxial layer 3-1, a part of epitaxial layer 3-1 Resistivity is to become equal to the N-type electrical resistivity of epitaxy in PN thin layer, a part (transition region) resistivity Change, less than the N-type electrical resistivity of epitaxy in PN thin layer, PN thin layer and epitaxial layer 3-1 shared Blocking voltage.Under epitaxial layer 3-1, having a N+ substrate, it is micro-that thickness is generally 100-150 Rice.Along the BB ' direction shown in Fig. 2-1, in N-type conducting district, the distribution schematic diagram of impurity concentration is such as Shown in Fig. 2-2.

In order to manufacture existing device architecture, in its manufacture method, on the one hand need at high impurity concentration N+ silicon chip substrate 1 on deposit after N-type extension, then in N-type epitaxy layer, form groove, it Rear formation p-type thin layer, due to the thickest (blocking-up of 600-1000 volt of the epitaxial layer needed for high tension apparatus Voltage, the epitaxy layer thickness of needs is at 45-100 micron), the cost making device is the highest；On the other hand, After epitaxial diposition completes PN thin layer and its under with N thin layer shared blocking voltage, these are two years old The thickness sum (thickness of 3 as shown in Fig. 2-1 and the thickness sum of 3-1) of person is the most fixing, After etching groove after epitaxial diposition and trench fill, owing to gash depth is within silicon chip, silicon Between sheet-silicon chip, between batch and batch, there are certain change (typically in +/-2%～10%), groove The thickness of the epitaxial layer filled just can change, i.e. PN thickness of thin layer has certain change (N The thickness of type epitaxial layer 3-1 changes the most therewith: PN thin layer is thickening, and N-type epitaxy layer 3-1 is thinning；PN Thin layer is thinning, and N-type epitaxy layer 3-1 is thickening), this breakdown reverse voltage that can affect device and anti-impact Hit ability, particularly when epitaxial layer 3-1 is the thinnest, the impact resistance of device and anti-electromagnetism may be made Interference performance is affected, so that the reliability of device becomes problem.

In the PN thin layer region layer of the first paragraph of device, obtained the low resistance needed by epitaxial diposition The N thin layer of rate (high impurity doping concentration), in order to reduce the conducting resistance of device.This section of region The N-type thin layer of high impurity doping concentration, forms alternately arranged PN with the p-type thin layer formed afterwards Thin layer region layer, under device is in blocking state, p-type thin layer and N-type thin layer exhaust mutually, properly Charge balance under conditions of so that the afforded blocking voltage in this section of region is not by miscellaneous in N thin layer The restriction of matter concentration, such that it is able to obtain high blocking voltage and low conducting resistance simultaneously.

The N-type drift region layer of second segment, its resistivity is equal to silicon chip substrate resistivity, the N of second segment The blocking voltage of the PN thin layer region layer shared device of type drift region layer and first paragraph, second segment The thickness of N-type drift region layer be the impact resistance to device and anti-electromagnetic interference capability decision because of One of element.The thickness of the N-type drift region of second segment is determined by silicon chip back side reduction process, it is therefore desirable to The thickness of N-type drift region of second segment can be according to the data of the thickness of the PN thin layer formed Calculate, and realize by adjusting silicon chip back side reduction process, so can be according to the need of device Ask, obtain the breakdown reverse voltage of the device needed, or obtain the impact resistance of needs and anti-electromagnetism Interference performance, solves problem and existing skill that in prior art, resistance to rush of current ability uniformity is bad The impact resistance brought in art is not and the electromagnetism interference integrity problem such as not.

The N-type Ohmic contact region layer of the 3rd section, will form Ohmic contact with back metal, and therefore it connects The region touching metal must have higher than 1 × 10¹⁹atoms/cm³Impurity concentration, and high-voltage super knot The concentration of the N-type silicon chip substrate of device is generally below 1 × 10¹⁵atoms/cm³, therefore its contacting metal Zone resistance rate can be less than or equal to 1/100. this N-type Ohmic contact region layer of silicon chip substrate resistivity Can be formed by ion implanting and annealing process, its ion implanting can be one or many ion note Enter to be formed, when using repeatedly ion implanting, by a high-energy and the work of relatively small implantation dosage Skill, can and N-type drift region layer between form one to have certain thickness impurity concentration slowly varying Region, improve impact resistance and the anti-electromagnetic interference capability of device further, and low-yield high agent The injection of amount i.e. can form a high impurity concentration district contacted with metal.

Further improve and be, between described N-type Ohmic contact region layer and described N-type drift region layer The thickness of transition region is 0.2-3 micron, when transition region reaches more than 1 micron, will improve device Impact resistance and anti-electromagnetic interference capability, the thickness of this transition region is the biggest, the shock resistance energy of device Power and anti-electromagnetic interference capability are the strongest.The width of this transition region can be adjusted by the energy of ion implanting Whole.

Further improve and be, in described PN thin layer region layer, the p-type carrier population of p-type thin layer More than the N-type carrier sum of N-type thin layer, the p-type carrier population of p-type thin layer and N-type thin layer N-type carrier sum difference less than N-type thin layer type carrier population 10%；Due to PN thin layer Under have a thicker N-type drift region layer, in PN thin layer district, the p-type carrier of p-type thin layer compares N The part that the N-type carrier of type thin layer has more can consume with the N-type carrier in N-type drift region To the greatest extent, that reduces the P type trap zone at p-well-N thin layer knot exhausts thickness, also reduces p-well-N thin layer Electric-field intensity at knot, can improve the breakdown voltage of device.But the p-type carrier of p-type thin layer is total Number can not be too big, and during too conference causes PN thin layer district, transverse electric field and internal field strengthen, and cause The problems such as electric leakage increase.

As shown in Figures 3 to 8, it is each step of manufacture method of the embodiment of the present invention one super-junction device In device current flow region profile；The institute of the manufacture method of the embodiment of the present invention one super-junction device State the super junction flat-grid MOSFET component that super-junction device is breakdown reverse voltage 600 volts, including Following steps:

Step one, silicon chip substrate 1 ' (shown in Fig. 3) front deposit N-type epitaxy layer 3, formed one Individual resistivity is less than the N-type epitaxy layer of N-type silicon chip resistance substrate rate；(shown in Fig. 4)

The thickness of substrate 1 ' can be 700-750 micron (to 8 inch silicon wafer), the electricity of substrate 1 ' Resistance rate needs the requirement of the breakdown reverse voltage according to device, and considers the thickness of PN thin layer in device Select.For the requirement of fixing device reverse breakdown voltage, when PN thickness of thin layer strengthens, The resistivity of substrate can decline；When the thickness of PN thin layer reduces, the resistivity of this substrate needs Increase；Requirement to the breakdown voltage of 600 volts, typically can select its resistivity at 5-20 ohm. Centimetre.

Through epitaxial diposition, the resistivity N-type extension less than silicon chip substrate resistivity can be obtained Layer, the requirement to the breakdown voltage of 600 volts, the resistivity of N-type epitaxy layer may be selected in 3 ohm. Centimetre to 1 ohm. centimetre, thickness T1 ' can elect 15-35 micron as, this N-type epitaxy layer impurity Concentration is higher than substrate concentration but difference is within 1-2 the order of magnitude, the therefore transition region width of intermediate concentration Degree is little, does not considers at this.

In described electric current flow region, by the described P-type silicon epitaxial layer 4 being filled in described groove Composition p-type thin layer, is formed N-type thin layer by the described N-type epitaxy layer 3 between p-type thin layer, alternately The N-type thin layer of arrangement and p-type thin layer constitute described PN thin layer region layer, as shown in Figure 5.

Described N-type thin layer and p-type thin layer need to realize charge balance, the N of the most described N-type thin layer The absolute value of the difference of the p-type carrier population of type carrier population and its neighbouring described p-type thin layer Less than the 10% of the N-type carrier sum of described N-type thin layer, again smaller than the p-type of described p-type thin layer The 10% of carrier population；Dotted line frame as shown in Figure 5 is the P-N of a repetitive, i.e. electricity The requirement of lotus balance needs to ensure the p-type carrier population in p type island region 4 and N in this frame in this frame N-type current-carrying during the absolute value of the difference of N-type carrier sum is both less than in N-type this frame thin 3 in type district 3 The 10% of son sum, again smaller than 10%. such requirements of the p-type carrier population of 4 in this frame, protects Demonstrate,prove the breakdown voltage that can obtain higher device.

Step 5, the top of each described p-type thin layer 4 formed p-well 7, each described p-well 7 is also prolonged Reach part described N-type thin layer top；Described N-type thin layer top area between each described p-well is N-type conducting district；The injection of p-well can use boron, or boron fluoride, and annealed formation, its note Entering the requirement of the threshold voltage of the selection device to be met of dosage, general implantation dosage exists 1×10¹²atoms/cm²-1×10¹³atoms/cm²Level.As shown in Figure 6

Step 6, successively deposit gate dielectric layer 5 and polysilicon gate 6, use lithographic etch process to institute State polysilicon gate to perform etching, be made up of the described polysilicon gate 6 after described gate dielectric layer 5 and etching The grid structure of described super junction flat-grid MOSFET component；Described polysilicon gate covers institute from top State N-type conducting district and the described p-well of part 7, the described p-well that vertically covered by described polysilicon gate For forming lateral channel；Gate dielectric film is usually silica, thickness 500-1000 angstrom, polycrystalline Silicon thickness is usually 4000-8000 angstrom, usually n-type doping.As shown in Figure 6

Step 7, carry out N+ ion implanting formed source region 8；Described source region is formed at described p-well 7 Top and described polysilicon gate 6 autoregistration；N+ ion implanting can be phosphorus or arsenic, or they Combination, implantation dosage typically may be set to 5 × 10¹⁵atoms/cm², as shown in Figure 6

Step 8, defining described source region described front side of silicon wafer formed interlayer film 10；Use light Carve etching technics formed contact hole 11, described contact hole through described interlayer film and and described source region or Described polysilicon gate contacts；Carry out P+ ion implanting and form p-well draw-out area 9, described p-well draw-out area 9 are positioned under bottom the described contact hole contacted with described source region, described p-well draw-out area 9 and institute State p-well 7 to contact；

Interlayer film can be silicon oxide film, thickness 6000-10000 angstrom, and P+ ion implanting typically uses Boron injects.As shown in Figure 6

Step 9, deposit front metal 12 also carry out chemical wet etching to described front metal and are formed respectively Source electrode and grid；As shown in Figure 6

Step 10, from silicon chip back side, the substrate of described silicon chip is carried out thinning；Thickness after thinning, presses Requirement according to device electric breakdown strength is set.Such as Fig. 7, the device to the breakdown voltage of 600 volts, The region (PN thin layer region layer and the thickness sum of N-type drift region layer) undertaking voltage is typically set in 50-60 micron.

The most thinning thickness, the thickness of the N-type drift region that can more need is adjusted.With thickness The device property that degree needs.

Step 11, carry out backside particulate injection and annealing formed described N-type Ohmic contact region layer, structure Become the drain region of described MOSFET element；Such as Fig. 7, N-type ion implanting can inject phosphorus or arsenic, Concentration is 5 × 10¹⁵atoms/cm²Level, Implantation Energy can be at 400-800Kev, it is ensured that N+'s Junction depth T3 is more than 0.5 micron.Can also use and repeatedly inject, can be as injected primary energy 400KeV, 5 × 10¹⁵atoms/cm²N-type impurity (can be phosphorus or arsenic) and primary energy exist 1MeV-3MeV, dosage is 5 × 10¹¹atoms/cm²-5×10¹²atoms/cm²Phosphorus, the phosphorus of high energy ion implantation A thicker transition region, as shown in Figure 12-1, the wherein N of thickness T3 is formed after annealed The thickness of the impurity concentration variation zone in type contact zone is the biggest, and the resistance to rush of current ability of device is more High.

Step 12, carry out back face metalization and form the drain electrode of described MOSFET element.Back metal 13 thickness 0.5-2 microns, can be titaniums, nickel, silver or combinations thereof, it is also possible to be other gold Belong to.As shown in Figure 8

So, it is thus achieved that super-junction device electric current flow region profile as shown in Figure 8；Described electricity Stream flow region is vertically including at least three-stage structure, and first paragraph is PN thin layer region layer, such as Fig. 8 In first paragraph (C2 ' D2 '-C1D1) shown in, this section is the PN thin layer district formed after step 4 (in Fig. 5, thickness is T1 ') eliminates the p-type trap and horizontally arranged with p-type trap that step 5 is formed N-type conducting district after obtain.The described PN thin layer region layer of first paragraph is thin by alternately arranged N-type Layer and p-type thin layer are constituted, and N-type sheet resistance rate is less than the resistivity of silicon chip substrate, p-type thin-layer electric The setting of resistance rate to ensure that alternately arranged N-type thin layer and p-type thin layer realize charge balance, first paragraph In N-type thin layer realized by epitaxial deposition process；Second segment is N-type drift region layer, such as figure Shown in second segment in 8 (C1D1-C4D4), its resistivity is equal to silicon chip substrate resistivity；3rd section It is N-type Ohmic contact region layer, as shown in the 3rd section in Fig. 8 (C4D4-C3D3), described N-type Europe Nurse contact zone layer resistivity is less than the resistivity of described N-type drift region, and comprises a resistivity and be less than Contact zone equal to the 1/100 of silicon chip substrate resistivity.AA ' direction along Fig. 8, this N of three sections In type district, the distribution of impurity concentration is as shown in Figure 12-1, and thickness is that the region of T1 belongs to first paragraph, it Being realized by epitaxy technique, impurity concentration is higher than the impurity concentration of substrate；Thickness is that the region of T2 belongs to Second segment, it comprises the impurity concentration region equal to silicon chip substrate concentration；Thickness is the district of T3 Territory belongs to the 3rd section, and it comprises the impurity concentration district optionally greater than silicon chip substrate concentration 100 times Territory, and comprise a stepping region of impurity concentration.

In the device architecture of Fig. 8, (grid, source electrode and p-type trap when device is in blocking state Receiving 0 current potential, drain electrode 13 connects high pressure), the PN thin layer of first paragraph enters under relatively low reverse biased Gone having lateral depletion (on N thin layer, the carrier in the N-type region territory under grid also with horizontal P Trap has carried out having lateral depletion), along with the increase of drain voltage, in first paragraph, PN thin layer laterally consumed before this To the greatest extent, depletion layer extends at the N-type drift region layer of second segment afterwards, and when puncturing generation, depletion region can be Within N-type drift region layer, it is also possible to break-through N-type drift region layer.When puncturing generation, depletion region is at N Time within type drift region layer, the value of breakdown voltage is as being the area of trapezoidal OEWG in Figure 12-2；Hit Depletion region break-through N-type drift region layer when wearing generation, the value of breakdown voltage is as trapezoidal in Figure 12-2 The area of OEWHQ.It will be seen that when latter event occurs, device can from schematic diagram above To bear higher blocking voltage, the thickness of thinner first paragraph and second segment therefore can be used to obtain Obtain blocking voltage equally, thus improve the conducting resistance of device；And in the previous case, due to Region layer of drifting about when puncturing not yet exhausts, and the resistance to rush of current ability of device can improve, and anti-electromagnetism is done The ability of disturbing can improve, thus improves device and reliability.

In above-mentioned device architecture, if needing to obtain the lowest conducting resistance and preferable shock resistance When ability and anti-electromagnetic interference capability, it is possible to use method below: increase PN thin layer region layer Thickness, reduces the thickness of N-type drift region layer simultaneously；Need the resistance to rush of current ability providing device high When resisting with electromagnetic interference capability, it is possible to reduce the thickness of PN thin layer region layer, increase N-type drift region The thickness of layer；When needing to obtain minimum conducting resistance, and the resistance to rush of current of device can be resisted strenuously and When electromagnetic interference capability requires the lowest, it is possible to use the thickest PN thin layer, reduce N drift The thickness of region layer is even to 0.When using above method, the typesetting of device need not change, and manufactures The flow process of technique need not change, it is only necessary to changes the formation manufacturing process and afterwards in PN thin layer district Silicon chip back side reduction process, therefore can utilize same device to design (same domain), obtain Meet the device performance of different demand, improve the efficiency of device design.

Further improve and be, between described N-type Ohmic contact region layer and described N-type drift region layer The thickness of transition region is 0.2-3 micron, and the thickness of transition region is the biggest, the anti-electromagnetic interference capability of device The strongest with impact resistance.Use high-octane phosphonium ion to inject, deep N-type transition region can be obtained.

Further improve and be, in described PN thin layer region layer, the p-type carrier population of p-type thin layer More than the N-type carrier sum of N-type thin layer, the p-type carrier population of p-type thin layer and N-type thin layer N-type carrier sum difference less than N-type thin layer type carrier population 10%；Due to PN thin layer Under have a thicker N-type drift region layer, in PN thin layer district, the p-type carrier of p-type thin layer compares N The part that the N-type carrier of type thin layer has more can consume with the N-type carrier in N-type drift region To the greatest extent, that reduces the P type trap zone at p-well-N thin layer knot exhausts thickness, also reduces p-well-N thin layer Electric-field intensity at knot, can improve the breakdown voltage of device.But the carrier population of p type island region is the most not Can be too big, during too conference causes PN thin layer district, transverse electric field strengthens, and causes electric leakage increase and reversely hit Wear degradation problem under voltage.

Further improve is that described N-type drift region layer thickness is more than 10 microns；N-type drift region Layer keeps certain thickness, to strengthen anti-electromagnetic interference capability and the impact resistance of device.

In the PN thin layer region layer of the first paragraph of device, obtained the low electricity needed by deposit epitaxial layer The N thin layer of resistance rate (high impurity doping concentration), in order to reducing the conducting resistance of device, this section high miscellaneous The region of matter doping content, forms alternately arranged PN thin layer region layer with the p-type thin layer formed afterwards, Under device is in blocking state, p-type thin layer and N-type thin layer exhaust mutually, at suitable charge balance Under conditions of so that the afforded blocking voltage in this section of region is not limited by impurity concentration in N thin layer System, such that it is able to obtain high blocking voltage and low conducting resistance simultaneously.

The N-type drift region layer of second segment, its resistivity is equal to silicon chip substrate resistivity, the N of second segment The blocking voltage of the PN thin layer region layer shared device of type drift region layer and first paragraph.Second segment N-type drift region is not owing to having horizontal P thin layer to provide compensation electric charge, and therefore impurity doping concentration has Certain restriction.In Figure 12-2, longitudinal electric field intensity is approximately in the PN thin layer region layer of first paragraph Flat, progressively reduce from the longitudinal electric field intensity of the N-type drift region layer of second segment, this electric-field strength Area under degree distribution, if the area of OEWG is the blocking voltage of undertaken in the case of this, in order to Obtain more preferable anti-electromagnetic interference capability and strong impact resistance, when device designs, general warranty When breakdown voltage occurs, depletion region does not wants broadening to the scope beyond N-type drift region, because if this Time depletion region launch beyond N-type drift region and touched low-resistivity (high impurity doping concentration) N-type Ohmic contact region layer, anti-electromagnetic interference capability and the impact resistance of device are it is possible under Ming Xian Fall.

Owing to the PN thin layer region layer of first paragraph and the N-type drift region layer shared of second segment block electricity Pressure, the thickness of the N-type epitaxy layer deposited the most here is less than epitaxial layer deposition thickness of the prior art (for the device of same breakdown reverse voltage), thus reduce difficulty and the manufacture of epitaxial layer deposition Cost.

The N-type Ohmic contact region layer of the 3rd section, will form Ohmic contact with back metal, and therefore it connects The region touching metal must have higher than 1 × 10¹⁹atoms/cm³Impurity concentration, this N-type ohm connects Tactile region layer can be formed by ion implanting and annealing process, and its ion implanting can be one or many Ion implanting is formed, when using repeatedly ion implanting, by a high-energy and relatively small injectant The technique of amount, can form one with the impurity concentration difference of N-type drift region floor is not the biggest district Territory, improves anti-electromagnetic interference capability and the impact resistance of device further.

To further the improving of manufacture method of above-described embodiment one it is: the lehr attendant in step 11 Skill at least includes a laser annealing.Use laser annealing technique can obtain in silicon chip back side local Temperature higher than more than 900 degrees Celsius and simultaneously the temperature of silicon chip surface relatively low, will not be to the gold in front Genus impacts, so that the impurity that the back side is injected obtains high activity ratio, reduces the device back side The dosage injected the performance that improve device.

To further improving of the manufacture method of above-described embodiment one be: the back side in step 11 from Son injects at the phosphorus of 1MeV-3MeV including at least an Implantation Energy in injecting.By the appropriate agent of high energy (such as Implantation Energy exists the ion implanting of amount at 1MeV-3MeV, dosage 5×10¹¹atoms/cm²-5×10¹²atoms/cm²Phosphorus), the high impurity in contact zone can be obtained A gradual district of certain thickness impurity concentration between concentration district and N-type drift region, improves further The resistance to rush of current ability of device.

It it is exactly manufacturing step (the portion of the super junction flat-grid MOSFET component of embodiment two such as Fig. 9-10 Point) schematic diagram.

Embodiment two, unlike embodiment one, uses step 2, step 3, step in embodiment one Rapid four form p-type epitaxial layer；P-type ion implanting is used to be formed in embodiment two, p-type ion Can directly anneal after injection, it is also possible to the p-well after Gong Yonging and the pyroprocess of other techniques Carry out annealing and the diffusion of p-type thin layer, the p-type thin layer such as 4 ' in Fig. 9 of formation.Corresponding is super Level junction plane grid MOSFET component profile is as shown in Figure 10.

If Figure 11 is exactly the device architecture signal of the super junction trench gate mosfet device of embodiment three Figure.Unlike embodiment one, embodiment three have employed the structure of trench gate mosfet.Its system Make step as follows:

In described electric current flow region, by the described P-type silicon epitaxial layer 4 being filled in described groove Composition p-type thin layer, is formed N-type thin layer by the described N-type epitaxy layer 3 between p-type thin layer, alternately The N-type thin layer of arrangement and p-type thin layer constitute described PN thin layer region layer.As shown in Figure 5

Step 5, employing lithographic etch process form groove, and the N-type that groove is positioned at PN thin layer district is thin In floor district 3, depositing gate dielectric film 5, groove is filled up completely with by depositing polysilicon grid 6 afterwards, afterwards Return to carve and form polysilicon grating structure；Gash depth general 2-4 micron, gate dielectric film is usually titanium dioxide Silicon, thickness 500-1000 angstrom, polysilicon is usually n-type doping.(as shown in figure 11)

Step 6, the top of each described p-type thin layer formed p-well 7, each described p-well 7 also extends To part described N-type thin layer top；The described p-well vertically covered by described polysilicon gate is for shape Become longitudinal channel；The injection of p-well can use boron, or boron fluoride, and annealed formation, its note Entering the requirement of the threshold voltage of the selection device to be met of dosage, general implantation dosage exists 1×10¹²atoms/cm²-1×10¹³atoms/cm²Level.(as shown in figure 11)

Step 7, carry out N+ ion implanting formed source region 8；Described source region is formed at described p-well 7 Top and described polysilicon gate 6 autoregistration；(as shown in figure 11)

Step 9, deposit front metal 12 also carry out chemical wet etching to described front metal and are formed respectively Source electrode and grid；

Step 12, carry out back face metalization and form the drain electrode of described MOSFET element.Such as Figure 11 Shown in

Choosing of the parameter of above-described embodiment three, in addition to the difference of trench gate, is referred to substantially The parameter of embodiment one manufactures.

To further the improving of manufacture method of above-described embodiment three it is: the lehr attendant in step 11 Skill at least includes a laser annealing.Use laser annealing technique can obtain in silicon chip back side local Temperature higher than more than 900 degrees Celsius and simultaneously the temperature of silicon chip surface the highest, will not be to the gold in front Genus impacts, so that the impurity that the back side is injected obtains high activity ratio, reduces the device back side The dosage injected the performance that improve device.

To further improving of the manufacture method of above-described embodiment three be: the back side in step 11 from Son injects at the phosphorus of 1MeV-3MeV including at least an Implantation Energy in injecting.By the appropriate agent of high energy (such as Implantation Energy exists the ion implanting of amount at 1MeV-3MeV, dosage 5×10¹¹atoms/cm²-5×10¹²atoms/cm²Phosphorus), the high impurity in contact zone can be obtained A gradual district of certain thickness impurity concentration between concentration district and N-type drift region, improves further The resistance to rush of current ability of device.

In the above embodiments one, embodiment two and embodiment three, the thickness of N-type drift region layer be by Technique for thinning back side determines, in the step of manufacture method, this technique for thinning back side is thin at PN After layer is formed, accordingly, because the change of technique is when the thickness causing PN thin layer changes, The characteristic needed to ensure device to obtain, such as breakdown voltage and resistance to rush of current ability, it is possible to Adjusting reduction process, the thickness of the N-type drift region obtaining needs is compensated.If such as PN thin layer region layer thickness is the thickest, but for the resistance to rush of current ability of retainer member, N-type drift region layer Thickness also need to keep consistent, then just can adjust reduction process and realize.Which overcome existing Technique is in the defect of this aspect: such as in existing technique, PN thin layer after epitaxial diposition completes With the thickness sum of the N-type region with PN thin layer shared blocking voltage under it (such as Fig. 2-1 institute The thickness of 3 shown and the thickness sum of 3-1) the most fixing, when after PN thin layer 3 (such as by In etching groove, etching depth is many 2%-10%) thickness thickening 3-5 micron, at this moment to resistance to electric current The most crucial N-type epitaxy layer (such as 3 ' in Fig. 3) thickness of impact capacity will reduce 3-5 micron ( As this N-type epitaxy layer thickness 5-10 micron), the resistance to rush of current ability that will result in device substantially becomes Difference.

In above-described embodiment, N-type and p-type are replaced mutually, have just obtained super junction PMOSFET device, have been Full symmetric.

Above-described embodiment only lists super junction MOSFET element, three sections of knots of the embodiment of the present invention Structure is equally applicable to have in other power devices of super-junction structures.Such as it is equally applicable to super junction The high tension apparatus such as high-voltage diode.In super junction P+N diode, three-stage structure is with MOSFET's Three section mechanisms are consistent；

Above by specific embodiment, the present invention has been described in detail, but these not constitute right The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art also can do Going out many deformation and improve, these also should be regarded as protection scope of the present invention.

Claims

1. a super-junction device, described super-junction device is formed on N-type silicon chip substrate, and the zone line of described super-junction device is electric current flow region, and terminal protection structure is surrounded on the periphery of described electric current flow region；It is characterized in that:

Described electric current flow region is vertically including at least three-stage structure, first paragraph is PN thin layer region layer, it is made up of alternately arranged N-type thin layer and p-type thin layer, N-type sheet resistance rate is less than the resistivity of silicon chip substrate, the setting of p-type sheet resistance rate to ensure that alternately arranged N-type thin layer and p-type thin layer realize charge balance, and the N-type thin layer in first paragraph is realized by epitaxial deposition process；Second segment is N-type drift region layer, and its resistivity is equal to silicon chip substrate resistivity；3rd section is N-type Ohmic contact region layer, and described N-type ohmic contact regions layer resistivity is less than the resistivity of described N-type drift region, and comprises the resistivity contact zone less than or equal to the 1/100 of silicon chip substrate resistivity.

2. super-junction device as claimed in claim 1, it is characterised in that: the thickness of the transition region between described N-type Ohmic contact region layer and described N-type drift region layer is 0.2-3 micron.

3. super-junction device as claimed in claim 1, it is characterised in that: the p type island region of described PN thin layer region layer can be manufactured by ion implanting and annealing process, it is also possible to is the technique manufacture by trench fill.

4. super-junction device as claimed in claim 1, it is characterized in that: in described PN thin layer region layer, the p-type carrier population of p-type thin layer is less than the 10% of N-type thin layer type carrier population more than the N-type carrier sum of N-type thin layer, the p-type carrier population of p-type thin layer with the difference of the N-type carrier sum of N-type thin layer.

5. super-junction device as claimed in claim 1, it is characterised in that: the thickness of described PN thin layer region layer is more than 10 microns.

6. super-junction device as claimed in claim 1, it is characterised in that: described N-type drift region layer thickness is more than 10 microns.

7. a manufacture method for super-junction device, described super-junction device is super junction flat-grid MOSFET component, it is characterised in that comprise the steps:

Step one, carry out N-type epitaxial diposition at front side of silicon wafer, form the resistivity N-type epitaxy layer less than N-type silicon chip resistance substrate rate；

Step 2, deposit the first silicon dioxide layer, the second silicon nitride layer and the 3rd silicon dioxide layer successively at front side of silicon wafer；Lithographic etch process is utilized successively described 3rd silicon dioxide layer, described second silicon nitride layer and described first silicon dioxide layer to be formed groove figure mask；

Step 3, for mask, described silicon chip performed etching the multiple grooves of formation with described groove figure mask；In described electric current flow region, the described N-type epitaxy layer between each described groove is laminate structure；Described 3rd silicon dioxide layer and described second silicon nitride layer of described groove figure mask being removed successively, described first silicon dioxide layer retains；

Step 4, described front side of silicon wafer deposit P-type silicon epitaxial layer, described groove is fully filled with by described P-type silicon epitaxial layer；Silicon and the silica of described groove top surface are all removed；

In described electric current flow region, the described P-type silicon epitaxial layer being filled in described groove form p-type thin layer, the described N-type epitaxy layer between p-type thin layer form N-type thin layer, alternately arranged N-type thin layer and p-type thin layer and constitute described PN thin layer region layer.

Described N-type thin layer and p-type thin layer need to realize charge balance, the absolute value of the difference of the N-type carrier sum of the most described N-type thin layer and the p-type carrier population of its neighbouring described p-type thin layer is less than the 10% of the N-type carrier sum of described N-type thin layer, again smaller than the 10% of the p-type carrier population of described p-type thin layer；

Step 5, the top of each described p-type thin layer formed p-well, each described p-well also extends into part described N-type thin layer top；Described N-type thin layer top area between each described p-well is that N-type turns on district；

Step 6, successively deposit gate dielectric layer and polysilicon gate, use lithographic etch process to perform etching described polysilicon gate, is made up of the grid structure of described super junction flat-grid MOSFET component the described polysilicon gate after described gate dielectric layer and etching；Described polysilicon gate covers described N-type conducting district and the described p-well of part, the described p-well that vertically covered by described polysilicon gate for forming lateral channel from top；

Step 7, carry out N+ ion implanting formed source region；Described source region is formed at described p-well top and described polysilicon gate autoregistration；

Step 8, defining described source region described front side of silicon wafer formed interlayer film；Using lithographic etch process to form contact hole, described contact hole through described interlayer film and contacts with described source region or described polysilicon gate；Carrying out P+ ion implanting and form p-well draw-out area, described p-well draw-out area is positioned under bottom the described contact hole contacted with described source region, and described p-well draw-out area and described p-well contact；

Step 9, deposit front metal also carry out chemical wet etching to described front metal and form source electrode and grid respectively；

Step 11, carry out backside particulate injection and annealing formed described N-type Ohmic contact region layer, constitute the drain region of described MOSFET element；

8. a manufacture method for super-junction device, described super-junction device is super junction trench gate mosfet device, it is characterised in that comprise the steps:

Step 5, employing lithographic etch process form groove, and groove is positioned in the N-type thin layer district in PN thin layer district, deposits gate dielectric film, and groove is filled up completely with by depositing polysilicon grid afterwards, return afterwards and form polysilicon grating structure quarter；

Step 6, the top of each described p-type thin layer formed p-well, each described p-well also extends into part described N-type thin layer top；The described p-well vertically covered by described polysilicon gate is for forming longitudinal channel；

9. the manufacture method of the super-junction device as described in claim 7 and claim 8, it is characterised in that: the annealing process in step 11 at least includes a laser annealing.

10. the manufacture method of the super-junction device as described in claim 7 and claim 8, it is characterised in that: the backside particulate in step 11 injects at the phosphorus of 1MeV-3MeV including at least an Implantation Energy in injecting.