CN115064583B - High-avalanche-tolerance silicon carbide MOSFET device and preparation method thereof - Google Patents
High-avalanche-tolerance silicon carbide MOSFET device and preparation method thereof Download PDFInfo
- Publication number
- CN115064583B CN115064583B CN202210959324.2A CN202210959324A CN115064583B CN 115064583 B CN115064583 B CN 115064583B CN 202210959324 A CN202210959324 A CN 202210959324A CN 115064583 B CN115064583 B CN 115064583B
- Authority
- CN
- China
- Prior art keywords
- type
- body region
- type body
- heavily doped
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 210000000746 body region Anatomy 0.000 claims abstract description 150
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- -1 aluminum ions Chemical class 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention relates to a silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) device with high avalanche tolerance and a preparation method thereof, wherein the device comprises an N-type drain electrode and drain electrode metal, an N-type epitaxial layer is arranged on the N-type drain electrode, longitudinal grooves are arranged above the N-type epitaxial layer, groove gate polycrystalline silicon is arranged inside the longitudinal grooves, the peripheries of the groove gate polycrystalline silicon are wrapped by groove gate oxide layers, a P-type body region is arranged between two adjacent longitudinal grooves in the N-type epitaxial layer, the P-type body region is vertically intersected with the two adjacent longitudinal grooves, an N-type source electrode and a P-type source electrode are arranged on the surface of the P-type body region, a plane gate oxide layer is arranged on the surfaces of the N-type source electrode, the P-type body region and the N-type epitaxial layer, a plane gate polycrystalline silicon is further arranged above the plane gate oxide layer, contact holes are further arranged on the surfaces of the N-type source electrode and the P-type source electrode to connect the surface of the source electrode to the source electrode metal, and an insulating medium layer is further arranged between the gate polycrystalline silicon and the source electrode metal. The invention effectively improves the avalanche tolerance of the MOSFET device and can reduce the characteristic on-resistance of the device.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a silicon carbide power semiconductor device with high avalanche tolerance and a preparation method thereof.
Background
Silicon carbide (SiC) as a third-generation semiconductor material has the advantages of wide forbidden bandwidth, high critical breakdown electric field, high saturation drift speed and the like compared with the existing silicon material, and an MOSFET device prepared from the SiC material has the advantages of low on-resistance, small size, high switching speed and the like compared with a silicon-based MOSFET with the same withstand voltage level.
The power MOSFET device, particularly the SiC MOSFET device, is mainly applied to the field of high-voltage power, the voltage of the power MOSFET device is 900V-3300V, the MOSFET device is used as a switching device, lower on-resistance is needed when the power MOSFET device is switched on, and small on-voltage drop is generated when current flows through the MOSFET device, and at the moment, although the on-current is large, the on-voltage drop is small, so that the on-power consumption is low. When the power MOSFET is turned off, the power MOSFET device is required to bear high voltage, the smaller the leakage current is, the better the leakage current is, and at the moment, the voltage at two ends of the power MOSFET is very large but the conduction current is very small, so that the turn-off power consumption is also very low. The power consumption of the MOSFET device during turning off and turning on is the static power consumption of the MOSFET device, and the smaller the power consumption of the part is, the higher the overall efficiency of the system is.
Furthermore, the reliability of the power device is related to the normal use of the power device, the Unclamped Inductive Switching (UIS) condition is generally considered as the most extreme stress situation suffered by the power MOSFET device in power electronics applications, and the UIS test essentially evaluates the avalanche tolerance of the device, and the higher the avalanche tolerance of the device, i.e. means that the device has a higher safety margin in the face of the most extreme stress.
When UIS testing is performed, the test circuit is shown in FIG. 7, wherein the DUT is a device under test. During testing, pulse voltage is applied to the grid voltage of the device to be tested to enable the device to be tested to be started, then the device is closed, and in the process, the grid voltage, the drain voltage and the drain current of the device to be tested are detected by an oscilloscope. As shown in fig. 8, when the gate voltage VGon of the device under test is gradually increased, the device under test is turned on, and the drain current also starts to increase, because the current in the circuit cannot change suddenly due to the inductance, the drain current will gradually increase linearly until the gate voltage of the device is reduced to 0 again, and during the turn-on process of the device, the drain voltage will be small because the on-resistance of the device under test is small. After the device to be tested is turned off, the drain current starts to gradually decrease, the device to be tested is turned off at the moment, the drain current cannot smoothly flow into the ground through the device to be tested, the energy in the inductor can only be released through the device to be tested, when the large current in the inductor directly impacts the device to be tested, avalanche breakdown of the device can be caused, the drain voltage of the device to be tested can rise to the breakdown voltage BVDSS of the device, and once the device to be tested cannot bear simultaneous impact of voltage and current, the device to be tested can fail. In general, the avalanche capability of the device can beTo be evaluated by avalanche current, i.e. maximum current I during the test, or by avalanche energy AS The avalanche energy is the energy which can safely absorb reverse avalanche breakdown after the device to be tested is turned off.
Disclosure of Invention
The invention aims to provide a silicon carbide MOSFET device with high avalanche tolerance and a preparation method thereof.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a silicon carbide MOSFET device with high avalanche tolerance comprises a high-concentration N-type drain electrode and drain electrode metal, wherein a low-concentration N-type epitaxial layer is arranged on the high-concentration N-type drain electrode, the high-concentration N-type drain electrode is arranged between the drain electrode metal and the N-type epitaxial layer, a plurality of parallel longitudinal grooves are formed in the surface of one end, away from the high-concentration N-type drain electrode, of the N-type epitaxial layer, grooved gate polycrystalline silicon is arranged inside the longitudinal grooves, the periphery of the grooved gate polycrystalline silicon is wrapped by a grooved gate oxide layer, a plurality of P-type body areas are arranged between every two adjacent longitudinal grooves in the N-type epitaxial layer, the injection depth of the P-type body areas in the N-type epitaxial layer is larger than the depth of the longitudinal grooves, and the P-type body areas and the two adjacent longitudinal grooves are vertically intersected on the surface of the N-type epitaxial layer, the surface of the P-type body region is divided into a first P-type body region, a second P-type body region and a third P-type body region in the direction perpendicular to the longitudinal grooves, the second P-type body region is arranged between the first P-type body region and the third P-type body region, the first P-type body region is a heavily doped first P-type source electrode which is arranged on the surface of the P-type body region and intersected with the longitudinal grooves on one side, the heavily doped first P-type source electrode is not intersected with the longitudinal grooves on the other side, the second P-type body region is a heavily doped first N-type source electrode which is arranged on the surface of the P-type body region and intersected with the longitudinal grooves on the two sides, the third P-type body region is a heavily doped second P-type source electrode and a heavily doped second N-type source electrode which are arranged on the surface of the P-type body region, and the heavily doped second N-type source electrode of the third P-type body region separates the longitudinal grooves on one side where the heavily doped second P-type source electrode and the heavily doped first P-type source electrode are intersected, the heavily doped second P-type source electrode is intersected with the longitudinal groove on the other side, the heavily doped second N-type source electrode of the third P-type body region is connected with the heavily doped first N-type source electrode of the second P-type body region to form a heavily doped N-type source electrode, the doped N-type source electrode and the N-type epitaxial layer are separated by the first P-type body region, the second P-type body region and the surface of the N-type epitaxial layer are further provided with planar gate oxide layers, the planar gate oxide layers are respectively terminated in the second P-type body region along the longitudinal groove direction, the planar gate oxide layers are respectively terminated on the longitudinal groove and the surface of the heavily doped first P-type source electrode, the planar gate oxide layers are further arranged above the planar gate oxide layers, the heavily doped N-type source electrode, the heavily doped first P-type contact hole and the surface of the heavily doped second P-type source electrode are further provided with a source electrode metal, a planar gate metal layer is arranged between the planar gate metal and the source electrode metal and the surface of the heavily doped second P-type epitaxial layer.
Furthermore, at least one group of P-type body regions is arranged between every two adjacent longitudinal grooves, each group of P-type body regions is formed by arranging the two P-type body regions at intervals, the interval width between the two P-type body regions is 1um to 100um, and one side of a first P-type body region of one P-type body region is spaced from one side of a first P-type body region of the other P-type body region through an N-type epitaxial layer.
Furthermore, two adjacent groups of P-type body regions are connected, and one side of the third P-type body region of one P-type body region in one group of P-type body regions is connected with one side of the third P-type body region of one P-type body region in the other group of P-type body regions.
Further, the trench gate oxide layer at the bottom of the longitudinal trench is thicker than the trench gate oxide layers at two sides.
Further, the length w2 of the first P-type source electrode is variable, the variation range is 0.1um to 100um, and the length of the first P-type source electrode is smaller than the length of the P-type body region.
The invention also discloses a preparation method for realizing the high avalanche tolerance silicon carbide MOSFET device, which comprises the following steps:
the method comprises the following steps: selecting an N-type substrate material as a high-concentration N-type drain electrode and epitaxially growing a low-concentration N-type epitaxial layer;
step two: selectively injecting aluminum ions into the surface of the N-type epitaxial layer to form a P-type body region;
step three: selectively etching a longitudinal groove on the surface of the N-type epitaxial layer;
step four: growing an oxide layer with a certain thickness on the surface of the N-type epitaxial layer to serve as a trench gate oxide layer, depositing polycrystalline silicon in the longitudinal trench to form trench gate polycrystalline silicon, and removing redundant oxide layers and polycrystalline silicon on the surface of the N-type epitaxial layer;
step five: growing a plane gate oxide layer on the surfaces of the P-type body region and the N-type epitaxial layer, and depositing and forming plane gate polycrystalline silicon above the plane gate oxide layer;
step six: injecting nitrogen ions into the surface of a P-type body area to form a heavily doped N-type source electrode, selectively injecting aluminum ions into the surface of the P-type body area to form a first heavily doped P-type source electrode and a second heavily doped P-type source electrode, and diffusing the heavily doped N-type source electrode to the lower part of the planar gate oxide after high-temperature activation by using the planar gate oxide layer and a planar gate polycrystalline silicon above the planar gate oxide layer as a barrier layer;
step seven: depositing an insulating medium layer on the surface of the N-type epitaxial layer, selectively etching a contact hole on the insulating medium layer, depositing metal on the insulating medium layer, selectively etching the metal to form source metal, and depositing metal on the back of the high-concentration N-type drain to form drain metal.
Compared with the prior art, the invention has the following main advantages:
(1) The first P-type source electrode provided by the invention can absorb hole current in an avalanche state, so that the hole current can directly flow out of the device through the source electrode, the hole current is prevented from flowing into a P-type body area below the N-type source electrode, and the conduction of a parasitic triode in the device is avoided, thereby improving the avalanche tolerance of the device.
(2) The MOSFET device provided by the invention improves the avalanche tolerance of the device and reduces the characteristic on-resistance of the device. The silicon carbide MOSFET device respectively provides two current paths of a plane gate and a groove gate, and the current can flow into a drift region of the device from the two channels at the same time, so that the current capability of the device is improved, and the characteristic on-resistance of the device is reduced.
Drawings
Fig. 1 is a top view of a high avalanche capability silicon carbide MOSFET device provided by the present invention.
Fig. 2 is a schematic cross-sectional structure view of the high avalanche resistance silicon carbide MOSFET device along the AA' direction.
Fig. 3 is a schematic cross-sectional structure view of the high avalanche resistance silicon carbide MOSFET device provided by the invention along the BB' direction.
Fig. 4 is a schematic cross-sectional structure view of the high avalanche resistance silicon carbide MOSFET device along the CC' direction.
Fig. 5 is a waveform diagram of a conventional planar silicon carbide MOSFET device under UIS testing.
Fig. 6 is a waveform diagram of a MOSFET device of the present invention under UIS testing.
FIG. 7 is a circuit diagram of a MOSFET device when subjected to UIS testing.
FIG. 8 is a typical waveform diagram of a MOSFET device when subjected to UIS testing.
Description of the reference numerals: 01 a-a first heavily doped P-type source; 01 b-a heavily doped second P-type source; 02 a-a heavily doped first N-type source; 02 b-a heavily doped second N-type source; 02-heavily doped N-type source; 03-N type epitaxial layer; 04 a-trench gate polysilicon; 04 b-plane gate polysilicon; 05-longitudinal grooves; 07-P-type body region; 08-N type drain; 09-drain metal; 10 a-trench gate oxide; 10 b-a planar gate oxide layer; 11-source metal; 13-insulating dielectric layer; 14-contact holes.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Example 1
The invention provides a high avalanche tolerance silicon carbide MOSFET device, as shown in FIG. 1 (it should be noted that, the top view in FIG. 1 is a top view after an insulating medium layer 13 and a source metal 11 are actually removed, and can also be understood as a transverse cross-sectional view along the upper surface of a P-type body region 07), as shown in FIG. 2, FIG. 3 and FIG. 4, the high-concentration N-type drain 08 and a drain metal 09 are included, a low-concentration N-type epitaxial layer 03 is arranged on the high-concentration N-type drain 08, the high-concentration N-type drain 08 is arranged between the drain metal 09 and the N-type epitaxial layer 03, a plurality of parallel longitudinal trenches 05 are arranged on one end surface of the N-type epitaxial layer 03 away from the high-concentration N-type drain 08, trench gate polysilicon 04a is arranged inside the longitudinal trenches 05, the periphery of the trench gate polysilicon 04a is wrapped by a trench gate oxide layer 10a, a plurality of P-type body regions 07 are arranged between two adjacent longitudinal trenches 05 in the N-type epitaxial layer 03, at least one group of P-type body regions is arranged between two adjacent longitudinal trenches 05, and the P-type body regions 07 is implanted to a depth greater than the depth of the N-type epitaxial layer 07.
The P-type body region 07 is vertically intersected with two adjacent longitudinal trenches 05 on the surface of an N-type epitaxial layer 03, the surface of the P-type body region 07 is divided into a first P-type body region, a second P-type body region and a third P-type body region in the direction perpendicular to the longitudinal trenches 05, and the second P-type body region is arranged between the first P-type body region and the third P-type body region.
The first P-type body region is a heavily doped first P-type source 01a arranged on the surface of the P-type body region 07 and intersected with the longitudinal groove 05 on one side, and the heavily doped first P-type source 01a is not intersected with the longitudinal groove 05 on the other side, as shown in fig. 1, the length of the heavily doped first P-type source 01a is w2, and the length of the first P-type source 01a without the heavily doped source is w1. The second P-type body region is a heavily doped first N-type source 02a which is arranged on the surface of the P-type body region 07 and intersects with the longitudinal grooves 05 on two sides, the third P-type body region is a heavily doped second P-type source 01b and a heavily doped second N-type source 02b which are arranged on the surface of the P-type body region 07, the heavily doped second N-type source 02b of the third P-type body region separates the heavily doped second P-type source 01b from the longitudinal grooves 05 on one side where the heavily doped first P-type source 01a intersects, the heavily doped second P-type source 01b intersects with the longitudinal grooves 05 on the other side, the heavily doped second N-type source 02b of the third P-type body region is connected with the heavily doped first N-type source 02a of the second P-type body region to form a heavily doped N-type source 02a heavily doped source 02a of the second P-type body region, the heavily doped second P-type source 02a of the third P-type body region and the heavily doped first N-type source 02b of the second P-type body region, and the heavily doped source 02b of the heavily doped first P-type body region separate the heavily doped source 02a from the heavily doped source 02a of the first P-type epitaxial layer 02a of the second P-type body region, and the first P-type epitaxial layer 02b, and the first P-type epitaxial layer are separated from the first P-type epitaxial layer 02 a.
In this embodiment, a group of P-type body regions is disposed between two adjacent longitudinal trenches 05, wherein a first P-type body region side of one P-type body region 07 is spaced apart from a first P-type body region side of another P-type body region 07 by an N-type epitaxial layer 03. The first P-type body region, the second P-type body region and the surface of the N-type epitaxial layer 03 are further provided with a planar gate oxide layer 10b, specifically, in fig. 1, with the direction of a longitudinal trench 05 as the x direction and the direction perpendicular to the longitudinal trench 05 as the y direction, the planar gate oxide layer 10b is respectively terminated on the surface of the heavily doped N-type source 02 in the second P-type body region of the two P-type body regions 07 in the x direction, that is, in the x direction, the planar gate oxide layer 10b is arranged from the second P-type body region of one P-type body region 07 to the second P-type body region of the N-type epitaxial layer 03 and is terminated to the other P-type body region, the planar gate oxide layer 10b is respectively terminated on the surface of the longitudinal trench 05 which is not intersected with the heavily doped first P-type source 01a and the heavily doped first P-type source 01a, that is on the surface of the N-type epitaxial layer, that is on the y direction, the planar gate oxide layer 10b is arranged from the contact hole to the surface of the first P-type source 01a which is not intersected with the longitudinal trench 05 which is not provided with the heavily doped first P-type source 01a, and the source 01a which is not provided with the heavily doped first P-type source 01a, and the source 11 b, and the planar gate oxide layer 10b are further provided with the source 11 b, and the polysilicon gate oxide layer 10b are further provided with the source 04, and the source 11 b, and the source 11 are provided with the source insulator layer 11 b, and the polysilicon gate oxide layer 10b, and the polysilicon layer 11 b, and the polysilicon gate oxide layer 11.
In this embodiment, the trench gate oxide layer at the bottom of the longitudinal trench 05 is thicker than the trench gate oxide layers at both sides, and the thicker oxide layer at the bottom can improve the gate oxide reliability of the device.
As shown in fig. 4, when the device is subjected to voltage withstanding, the P-type body region 07 is preferentially depleted from the N-type epitaxial layer 03 to bear high voltage, the concentration of the N-type epitaxial layer 03 is generally lower than that of the P-type body region 07, the depletion region is preferentially expanded in the N-type epitaxial layer 03, the potential is gradually reduced along with the expansion of the depletion region, the potential below the longitudinal trench 05 is greatly reduced through the depletion effect of the P-type body region 07 on the N-type epitaxial layer 03, and the breakdown risk of the oxide layer below the longitudinal trench 05 is reduced, so that the gate oxide reliability of the device can be improved by the device structure of the present invention.
As shown in fig. 1, the length w1 of the P-type body region 07 with an undoped surface and the length w2 of the first P-type source 01a are variable, the variation range is 0.1um to 100um, and the size of w1 and w2 can be adjusted to adjust the avalanche tolerance of the device. Specifically, as the w2 size increases, the avalanche capability of the device may further increase; and as w2 is reduced in size, the avalanche capability of the device may be reduced. When the device is designed, the sizes of w1 and w2 can be flexibly adjusted, and it should be noted that when the size of w1 is reduced, the planar channel of the device is also reduced, and the current of the longitudinal channel is not affected, so the current is also reduced in a small amplitude.
When performing the avalanche tolerance test, as shown in fig. 5, the MOSFET device is turned on to charge the inductor in the circuit, and then turned off, at this time, the energy stored in the inductor is dissipated through the MOSFET device, the MOSFET device is also in an avalanche state, the number of electrons and holes in the MOSFET device is increased sharply, wherein the electrons flow out through the heavily doped N-type drain, and the holes only flow out through the heavily doped first P-type source and the heavily doped second P-type source.
For a planar MOSFET device with a conventional structure, as shown in fig. 3, that is, in a planar gate MOSFET device structure shown in a BB' section of the structure, a hole current needs to flow through a region below a heavily doped N-type source 02 to reach a second heavily doped P-type source 01b, a voltage drop is generated when the hole current flows through the region below the heavily doped N-type source 02, and when the voltage drop is greater than a conduction voltage drop of a PN junction composed of a P-type body region 07 and the heavily doped N-type source 02, a parasitic NPN transistor composed of the heavily doped N-type source 02, the P-type body region 07, and an N-type epitaxial layer 03 is turned on, so that the current is rapidly increased, and the device fails due to a rapid increase in junction temperature.
For the structure of the present invention, when the above state occurs, the hole current can flow out not only through the second P-type source 01b, but also through the first P-type source 01a, and at this time, the hole current can directly flow into the first P-type source 01a without flowing under the N-type source 02, so the structure can effectively reduce the hole current flowing into the second P-type source, that is, reduce the current component flowing under the heavily doped N-type source, reduce the voltage drop between the heavily doped N-type source and the P-type body region, reduce the probability of the parasitic triode NPN conduction, and further improve the avalanche tolerance of the device.
In order to further improve the avalanche capability of the device, as shown in fig. 2, the size x2 of the N-type source 02 can be further reduced, and the size x1 of the first P-type source 01a can be increased, and as the size x1 of the first P-type source 01a is increased, the device structure of the invention can flow out hole current more quickly, further reduce the probability that the hole current flows below the N-type source in the BB' cross section, and improve the avalanche capability of the device.
As shown in fig. 5 and fig. 6, which are avalanche capability practical diagrams of the conventional planar MOSFET structure and the device structure of the present invention, respectively, the maximum tolerable avalanche energy of the device is shown in the diagrams, it can be seen that the avalanche current of the device structure of the present invention can reach 95A, and the avalanche energy is 1538mJ, whereas for the conventional planar MOSFET device, the avalanche current can only reach 80A, and the corresponding avalanche energy is only 1122.53mJ, so that the avalanche capability of the device can be greatly improved by the structure of the present invention.
When the device structure is conducted, namely the voltage on the plane gate polycrystalline silicon and the groove gate polycrystalline silicon is larger than the starting voltage of the device, a current channel is formed below the plane gate oxide layer, current channels are also formed on two sides of the longitudinal groove 05, electrons respectively flow through the current channels from the heavily doped N-type source electrode to enter the N-type epitaxial layer, and then flow out of the device through the heavily doped N-type drain electrode and the drain electrode metal to form current. Therefore, the device can provide a plane channel and a longitudinal channel at the same time, the current density of the device during conduction is increased, and the characteristic conduction resistance of the device is further reduced.
Finally, when the MOSFET device is turned off, an N-type epitaxial layer and a P-type body region are required to bear the withstand voltage. Because the trench gate polysilicon in the longitudinal trench 05 is grounded when the device is turned off, and the N-type epitaxial layer is in a high-voltage state, if the lower part of the longitudinal trench 05 is the N-type epitaxial layer, the oxide layer below the trench gate polysilicon needs to bear high withstand voltage, and because the oxide layer is relatively thin, the typical thickness of the oxide layer does not exceed 1um, the oxide layer at the position is necessarily broken down by a high voltage difference.
The invention also provides a preparation method for realizing the high avalanche tolerance silicon carbide MOSFET device, which comprises the following steps:
the method comprises the following steps: selecting an N-type substrate material as a high-concentration N-type drain electrode 08 and epitaxially growing a low-concentration N-type epitaxial layer 03;
step two: selectively implanting aluminum ions into the surface of the N-type epitaxial layer 03 to form a P-type body region 07;
step three: selectively etching a longitudinal groove 05 on the surface of the N-type epitaxial layer 03;
step four: growing an oxide layer with a certain thickness on the surface of the N-type epitaxial layer 03 to serve as a trench gate oxide layer 10a, depositing polycrystalline silicon in the longitudinal trench 05 to form trench gate polycrystalline silicon 04a, and removing redundant oxide layers and polycrystalline silicon on the surface of the N-type epitaxial layer 03;
step five: growing a planar gate oxide layer 10b on the surfaces of the first P-type body region, the second P-type body region and the N-type epitaxial layer 03, and depositing planar gate polysilicon 04b above the planar gate oxide layer 10 b;
step six: the method comprises the steps that a planar gate oxide layer 10b and planar gate polycrystalline silicon 04b above the planar gate oxide layer are used as blocking layers, nitrogen ions are injected into the surface of a P type body region 07 to form a heavily doped N type source electrode 02, aluminum ions are selectively injected into the surface of the P type body region 07 to form a heavily doped first P type source electrode 01a and a heavily doped second P type source electrode 01b, and after high-temperature activation, the heavily doped N type source electrode 02 can be diffused to the position below the planar gate oxide layer 10 b;
step seven: depositing an insulating medium layer 13 on the surface of the N-type epitaxial layer 03, then selectively etching a contact hole 14 on the insulating medium layer 13, then depositing metal on the insulating medium layer 13 and selectively etching the metal to form a source metal 11, and depositing metal on the back of the high-concentration N-type drain 08 to form a drain metal 09.
Example 2
The present example differs from example 1 in that: two adjacent be equipped with two sets of and above P type body district between the vertical slot 05, every group P type body district is by two the P type body district of group separates to set up to form, and is specific, and the first P type body district one side in a P type body district in every group is separated apart through N type epitaxial layer and the first P type body district one side in another P type body district, and the interval width is 1um to 100um, and N type epitaxial layer 03 width between two P type body districts is 1um to 100um promptly. Two groups of P-type body regions are connected, namely one side of a third P-type body region of one P-type body region in one group of P-type body regions is connected with one side of a third P-type body region of the other group of P-type body regions, more specifically, in the two connected P-type body regions, a heavily doped second P-type source electrode in the third P-type body region of one P-type body region in one group is connected with a heavily doped second P-type source electrode in one P-type body region in the other group, and a heavily doped N-type source electrode in the third P-type body region is connected with a heavily doped N-type source electrode in one P-type body region in the other group of P-type body regions.
The above embodiments illustrate the arrangement of multiple identical cells within a silicon carbide MOSFET device, and in fact, multiple identical cells within a silicon carbide MOSFET device are arranged in a certain arrangement, which can increase the chip area of the MOSFET device and increase the current capability of the device.
The present invention and its embodiments have been described above, the description is not intended to be limiting, and the embodiments shown in the drawings are merely typical examples of the present invention, and the actual configuration is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A high avalanche tolerance silicon carbide MOSFET device comprises a high concentration N-type drain (08) and a drain metal (09), wherein a low concentration N-type epitaxial layer (03) is arranged on the high concentration N-type drain (08), the high concentration N-type drain (08) is arranged between the drain metal (09) and the N-type epitaxial layer (03), a plurality of parallel longitudinal grooves (05) are arranged on one end surface of the N-type epitaxial layer (03) far away from the high concentration N-type drain (08), groove gate polycrystalline silicon (04 a) is arranged in each longitudinal groove (05), the periphery of each groove gate polycrystalline silicon (04 a) is wrapped by a groove gate oxide layer (10 a), a plurality of P-type body regions (07) are arranged between two adjacent longitudinal grooves (05) in the N-type epitaxial layer (03), and the injection depth of each P-type body region (07) in the N-type epitaxial layer (03) is larger than that of each longitudinal groove (05),
the P-type body region (07) is vertically intersected with two adjacent longitudinal trenches (05) on the surface of the N-type epitaxial layer (03), the surface of the P-type body region (07) is divided into a first P-type body region, a second P-type body region and a third P-type body region in the direction perpendicular to the longitudinal trenches (05), the second P-type body region is arranged between the first P-type body region and the third P-type body region,
the first P type body region is a heavily doped first P type source electrode (01 a) which is arranged on the surface of the P type body region (07) and intersected with the longitudinal groove (05) at one side, the heavily doped first P type source electrode (01 a) is not intersected with the longitudinal groove (05) at the other side, the second P type body region is a heavily doped first N type source electrode (02 a) which is arranged on the surface of the P type body region (07) and intersected with the longitudinal grooves (05) at two sides, the third P type body region is a heavily doped second P type source electrode (01 b) and a heavily doped second N type source electrode (02 b) which are arranged on the surface of the P type body region (07), the heavily doped second N-type source (02 b) of the third P-type body region separates the longitudinal trench (05) at one side, which is intersected by the heavily doped second P-type source (01 b) and the heavily doped first P-type source (01 a), the heavily doped second P-type source (01 b) is intersected by the longitudinal trench (05) at the other side, the heavily doped second N-type source (02 b) of the third P-type body region is connected with the heavily doped first N-type source (02 a) of the second P-type body region to form the heavily doped N-type source (02), and the first P-type body region separates the doped N-type source (02) and the N-type epitaxial layer (03),
the surfaces of the first P type body region, the second P type body region and the N type epitaxial layer (03) are further provided with a planar gate oxide layer (10 b), the planar gate oxide layer (10 b) is respectively terminated on the surface of the heavily doped N type source electrode (02) in the second P type body region along the direction of a longitudinal groove (05), the planar gate oxide layer (10 b) is respectively terminated on the surfaces of the longitudinal groove (05) and the heavily doped first P type source electrode (01 a) which are not intersected with the heavily doped first P type source electrode (01 a) along the direction of a P type body region (07), and a planar gate polysilicon layer (04 b) is further arranged above the planar gate oxide layer (10 b),
the surface of the heavily doped N-type source electrode (02), the surface of the heavily doped first P-type source electrode (01 a) and the surface of the heavily doped second P-type source electrode (01 b) are also provided with contact holes (14) for connecting the surface of the source electrode to source metal (11), and insulating medium layers (13) are also arranged between the planar gate polycrystalline silicon (04 b) and the source metal (11) and between the source metal (11) and the surface of the N-type epitaxial layer (03).
2. The high avalanche tolerance silicon carbide MOSFET device of claim 1, wherein at least one set of P-type body regions is provided between two adjacent said longitudinal trenches (05), said set of P-type body regions being comprised of two said P-type body regions (07) spaced apart, wherein a first P-type body region side of one P-type body region (07) is spaced apart from a first P-type body region side of another P-type body region (07) by an N-type epitaxial layer (03).
3. A high avalanche capability silicon carbide MOSFET device according to claim 2 wherein two adjacent sets of P-type body regions are connected and wherein the third P-type body region side of one P-type body region (07) of one set of P-type body regions is connected to the third P-type body region side of one P-type body region (07) of the other set of P-type body regions.
4. The high avalanche tolerance silicon carbide MOSFET device according to claim 1, wherein the trench gate oxide layer (10 a) at the bottom of the longitudinal trench (05) is thicker than the trench gate oxide layers (10 a) on both sides.
5. The high avalanche tolerance silicon carbide MOSFET device according to claim 1, wherein the first P type source (01 a) has a variable length ranging from 0.1um to 100um, and the length of the first P type source (01 a) is smaller than the length of the P type body region (07).
6. The method of claim 1, wherein the method comprises the steps of:
the method comprises the following steps: selecting an N-type substrate material as a high-concentration N-type drain electrode (08) and epitaxially growing a low-concentration N-type epitaxial layer (03);
step two: selectively implanting aluminum ions into the surface of the N-type epitaxial layer (03) to form a P-type body region (07);
step three: selectively etching a longitudinal groove (05) on the surface of the N-type epitaxial layer (03);
step four: growing an oxide layer with a certain thickness on the surface of the N-type epitaxial layer (03) to serve as a trench gate oxide layer (10 a), depositing polycrystalline silicon in the longitudinal trench (05) to form trench gate polycrystalline silicon (04 a), and removing redundant oxide layers and polycrystalline silicon on the surface of the N-type epitaxial layer (03);
step five: growing a plane gate oxide layer (10 b) on the surfaces of the P-type body region (07) and the N-type epitaxial layer (03), and depositing and forming plane gate polycrystalline silicon (04 b) above the plane gate oxide layer (10 b);
step six: by using a planar gate oxide layer (10 b) and planar gate polysilicon (04 b) above the planar gate oxide layer as barrier layers, injecting nitrogen ions into the surface of a P type body region (07) to form a heavily doped N type source electrode (02), selectively injecting aluminum ions into the surface of the P type body region (07) to form a heavily doped first P type source electrode (01 a) and a second P type source electrode (01 b), and after high-temperature activation, diffusing the heavily doped N type source electrode (02) to the lower part of the gate oxide layer (10 b);
step seven: an insulating medium layer (13) is deposited on the surface of the N-type epitaxial layer (03), then a contact hole (14) is selectively etched on the insulating medium layer (13), then metal is deposited on the insulating medium layer (13) and selectively etched to form source metal (11), and metal is deposited on the back of the high-concentration N-type drain electrode (08) to form drain metal (09).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210959324.2A CN115064583B (en) | 2022-08-11 | 2022-08-11 | High-avalanche-tolerance silicon carbide MOSFET device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210959324.2A CN115064583B (en) | 2022-08-11 | 2022-08-11 | High-avalanche-tolerance silicon carbide MOSFET device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115064583A CN115064583A (en) | 2022-09-16 |
| CN115064583B true CN115064583B (en) | 2022-10-25 |
Family
ID=83208045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210959324.2A Active CN115064583B (en) | 2022-08-11 | 2022-08-11 | High-avalanche-tolerance silicon carbide MOSFET device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115064583B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130256786A1 (en) * | 2012-03-29 | 2013-10-03 | Feei Cherng Enterprise Co., Ltd. | Trench mosfet with shielded electrode and avalanche enhancement region |
| CN106024892A (en) * | 2016-05-26 | 2016-10-12 | 东南大学 | Hole current shunting type power transistor with high avalanche tolerance and preparation method thereof |
| CN106505106A (en) * | 2016-10-11 | 2017-03-15 | 东南大学 | A kind of shielding gated power transistors of high avalanche capability and preparation method thereof |
| CN108336139A (en) * | 2018-04-08 | 2018-07-27 | 无锡新洁能股份有限公司 | A kind of deep-groove power device of high avalanche capability |
-
2022
- 2022-08-11 CN CN202210959324.2A patent/CN115064583B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN115064583A (en) | 2022-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101015767B1 (en) | Semiconductor component with a drift region and with a drift control region | |
| US8809911B2 (en) | Semiconductor device | |
| CN110767753B (en) | SiC power device | |
| US8334565B2 (en) | Trench type insulated gate MOS semiconductor device | |
| CN104995738A (en) | Semiconductor device | |
| CN111048594B (en) | SiC power device integrated with fast recovery diode | |
| EP3659180B1 (en) | Insulated gate power semiconductor device and method for manufacturing such device | |
| JP2012527113A (en) | Super junction semiconductor device | |
| CN102683408A (en) | Super junction high-voltage power device structure | |
| CN103165604A (en) | Semiconductor component with a space saving edge structure | |
| CN105706241B (en) | MOS bipolar device | |
| CN112038401A (en) | Insulated gate bipolar transistor structure and preparation method thereof | |
| WO2009051812A1 (en) | Variable threshold trench igbt with offset emitter contacts | |
| CN105895689A (en) | Super-junction device structure and manufacturing method thereof | |
| US11264475B2 (en) | Semiconductor device having a gate electrode formed in a trench structure | |
| US20240063267A1 (en) | Semiconductor device and method for producing same | |
| US20220352315A1 (en) | Semiconductor device and method for producing same | |
| CN115064583B (en) | High-avalanche-tolerance silicon carbide MOSFET device and preparation method thereof | |
| CN105895690A (en) | Super-junction device structure and manufacturing method thereof | |
| CN113745339B (en) | High-reliability power semiconductor device and manufacturing method thereof | |
| CN115295628A (en) | Power VDMOSFET device with high UIS avalanche tolerance and preparation method thereof | |
| CN114512538B (en) | Fast recovery shielding grid power device and manufacturing method thereof | |
| CN215731727U (en) | Super junction LIGBT device with low turn-on voltage | |
| JP4005156B2 (en) | High capacity low loss high speed diode with high voltage structure | |
| CN117832279A (en) | Shielding type buried U-groove SIC MOSFET structure for increasing source contact of JFET region |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |