CN115295628A - Power VDMOSFET device with high UIS avalanche tolerance and preparation method thereof - Google Patents
Power VDMOSFET device with high UIS avalanche tolerance and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000407 epitaxy Methods 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 238000003892 spreading Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 11
- 239000007924 injection Substances 0.000 abstract description 11
- 238000001465 metallisation Methods 0.000 abstract 1
- 210000004027 cell Anatomy 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- 239000000243 solution Substances 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 210000003850 cellular structure Anatomy 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
The invention discloses a power VDMOSFET device with high UIS avalanche tolerance and a preparation method thereof, wherein the device comprises: an N-type substrate region; an N-type drift region formed by one-time epitaxy above the N-type substrate region; the injection region is arranged in the grooves on two sides above the N-type drift region and comprises a P-type light concentration doping base region, a P-type high concentration doping region and an N-type high concentration source region, and the N-type high concentration source region is arranged between the P-type light concentration doping base region and the P-type high concentration doping region; the functional region is formed above the N-type drift region through multiple times of epitaxy and comprises a current expansion layer and a P-type high-concentration shielding layer; the gate region is formed on two sides of the functional region through high-temperature oxidation and comprises a gate oxide layer and a gate; and the source electrode and the drain electrode are both formed by metallization of the device. The UIS avalanche resistance of the MOSFET device can be improved by forming the current expansion layer and the P-type high-concentration shielding layer under the condition of not sacrificing the basic electrical characteristics of the device.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a power VDMOSFET device with high UIS avalanche tolerance and a preparation method thereof.
Background
The power semiconductor device has the advantages of large driving current, high breakdown voltage, high speed, low power, large output power and the like, can realize power control and conversion in different ranges, is widely applied to power management of satellites, spacecrafts and electric automobiles, and has huge development potential in the fields of space and vehicle-mounted application. The silicon carbide power semiconductor device generally has the characteristics of small size and high energy density, but when a circuit has parasitic inductance and the device is in reverse bias, and when the switching state of the circuit is changed, the energy stored in the inductance can be released through the power device, so that the device enters an avalanche state, a large number of electron hole pairs are generated, a current flowing through a base region causes triggering of a parasitic transistor, and the device finally fails due to excessive current or overheating, and the avalanche tolerance of the existing MOSFET device is not large enough, so that the working reliability is low.
Disclosure of Invention
The invention provides a power VDMOSFET device with high UIS avalanche tolerance and a preparation method thereof, which aim to solve the problem of low avalanche tolerance of the conventional semiconductor power device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a power VDMOSFET device of high UIS avalanche tolerance comprising:
an N-type substrate region;
an N-type drift region on an upper surface of the N-type substrate region;
the injection region is arranged in the grooves on two sides above the N-type drift region and comprises: the N-type high-concentration source region is arranged between the P-type light-concentration doping base region and the P-type high-concentration doping region;
a functional region intermediate over the N-type drift region, comprising: the current spreading layer is arranged below the P-type high-concentration shielding layer;
the gate regions are arranged on two sides of the functional region and comprise: the grid oxide layer surrounds the periphery of the grid;
the source electrode is connected above the gate region and the functional region;
a drain connected below the N-type substrate region.
Furthermore, the thickness of the current spreading layer in the functional region is 0.6 μm, the width is 1.15 μm, and the ion doping concentration range is 8 × 10 16 cm -3 To 2X 10 17 cm -3 (ii) a The thickness of the P-type high-concentration shielding layer is 0.3 μm, the width is 1.15 μm, and the peak value of the ion doping concentration is 1 × 10 19 cm -3 。
Further, the depth range of the groove where the injection region is located is 0.3-0.6 μm; the width of the P-type light concentration doping base region is 2.1 mu m, the depth is 1.0 mu m, and the range of the ion doping concentration peak value is 1 multiplied by 10 17 cm -3 To 5X 10 18 cm -3 (ii) a The width of the P-type high-concentration doping region is 1.2 mu m, the depth is 0.8 mu m, and the range of the ion doping concentration peak value is 1 multiplied by 10 20 cm -3 To 2X 10 20 cm -3 。
Further, the total thickness of the N-type drift region is 10.6 μm, and the ion doping concentration range is 6 × 10 15 cm -3 To 8X 10 15 cm -3 。
Further, the thickness of the gate oxide layer is 0.05 μm.
Further, a method for preparing a power VSMOSFET device with high UIS avalanche tolerance is provided, comprising the steps of:
s1, preparing an N-type substrate area required by a power VDMOSFET device with high UIS avalanche tolerance;
s2, forming an N-type drift region on the upper surface of the N-type substrate region in a one-time chemical vapor deposition epitaxy mode;
s3, forming a current expansion layer on the upper surface of the N-type drift region again in a chemical vapor deposition epitaxy mode;
s4, implanting a mask plate at a position with a thickness of 30nm to 200nm above the current extension layer, and forming a P-type high-concentration shielding layer in a multi-time ion implantation mode;
s5, forming grooves by utilizing a plasma etching method under the blocking of the mask plate through a grooving technology, wherein the grooves are formed on two sides of the top end of the N-type drift region;
s6, sequentially forming a P-type light concentration base region, an N-type high concentration source region and a P-type high concentration doping region on the groove in an ion implantation mode;
s7, carrying out high-temperature dry oxygen oxidation on the obtained device, forming a grid oxide layer above the groove, depositing polycrystalline silicon and doping phosphorus for etching to form a grid;
s8, carrying out metal contact opening on the obtained semiconductor device, depositing high-melting-point metal nickel or metal titanium, and annealing to form a source electrode and a drain electrode with ohmic contact characteristics.
Has the advantages that: the invention discloses a power VDMOSFET device with high UIS avalanche tolerance and a preparation method thereof, wherein the on-resistance of the device and the temperature generated when current flows through a JFET area can be effectively reduced by forming a current expansion layer; the electric field of the grid oxide layer can be reduced and the injection of hot holes in the grid oxide layer can be inhibited when the device enters single-pulse and repeated-pulse non-clamping inductive stress by forming the P-type high-concentration shielding layer; based on the two technical means of the electric field modulation method and the electric field shielding effect, the UIS avalanche tolerance of the MOSFET device can be obviously improved under the condition of not sacrificing the basic electrical characteristics of the device, so that the reliability and the stability of the device during working are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a cell structure of a planar gate power MOSFET device in the prior art;
FIG. 2 is a schematic diagram of a cell structure of the high UIS avalanche tolerance VDMOSFET device of the present invention;
FIG. 3 is a schematic structural diagram of the preparation method of the present invention after the end of steps S1 to S4;
FIG. 4 is a schematic structural diagram corresponding to step S5 in the preparation method of the present invention;
FIG. 5 is a schematic structural diagram corresponding to the first half of step S6 in the preparation method of the present invention;
FIG. 6 is a schematic structural diagram corresponding to the latter half of step S6 in the preparation method of the present invention;
FIG. 7 is a schematic structural diagram corresponding to step S7 in the preparation method of the present invention;
FIG. 8 is a schematic structural diagram corresponding to step S8 in the preparation method of the present invention;
FIG. 9 is a flow chart of a method of fabricating a VDMOSFET device of the present invention;
FIG. 10 is a graph of device lattice temperature versus time under UIS avalanche conditions for the structure shown in FIG. 1;
FIG. 11 is a graph of device lattice temperature over time under UIS avalanche conditions for the structure shown in FIG. 2;
in the figure: 100. an N-type substrate region; 101. an N-type drift region; 102. a P-type light concentration doped base region; 103. a P-type high-concentration doped region; 104. an N-type high concentration source region; 105. a current spreading layer; 106. a P-type high-concentration shielding layer; 200. a drain electrode; 201. a source electrode; 300. a gate oxide layer; 400. and a gate.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
Example 1
The present embodiment provides a power VDMOSFET device with high UIS avalanche capability, as shown in fig. 2, comprising:
an N-type substrate region 100;
an N-type drift region 101, wherein the N-type drift region 101 is arranged on the upper surface of the N-type substrate region 100;
an implantation region in the trench above the N-type drift region 101, including: the semiconductor device comprises a P-type light concentration doping base region 102, a P-type high concentration doping region 103 and an N-type high concentration source region 104, wherein the N-type high concentration source region 104 is arranged between the P-type light concentration doping base region 102 and the P-type high concentration doping region 103;
a functional region in the middle above the N-type drift region 101, comprising: a current spreading layer 105 and a P-type high concentration shield layer 106, the current spreading layer 105 being below the P-type high concentration shield layer 106;
the gate region is arranged on two sides of the functional region and comprises: the gate structure comprises a gate oxide layer 300 and a gate 400, wherein the gate oxide layer 300 surrounds the periphery of the gate 400;
the source electrode 201 is connected above the gate region and the functional region;
a drain 200, said drain 200 being connected below said N-type substrate region 100.
Specifically, two groups of injection regions and trenches in which the injection regions are located are respectively arranged on the left side and the right side of the device, each injection region comprises a P-type light-concentration doping base region 102, a P-type high-concentration doping region 103 and an N-type high-concentration source region 104, wherein the N-type high-concentration source region 104 is arranged on the uppermost portion of the injection region and is located between the P-type light-concentration doping base region 102 and the P-type high-concentration doping region 103; the size of the P-type lightly doped base region 102 is divided into two parts, namely the inner and outer heights are different, wherein the inner height of the P-type lightly doped base region 102 is larger and equal to the height of the P-type highly doped region 103 and larger than the height of the N-type highly doped source region 104, the outer height of the P-type lightly doped base region 102 is smaller, and the sum of the outer height of the P-type lightly doped base region and the height of the N-type highly doped source region 104 is equal to the height of the P-type highly doped region 103.
Specifically, the current spreading layer 105 (CSL) in the functional region is located below the P-type high-concentration shielding layer 106, and the sum of the heights of the two layers is equal to the height of the gate region; two groups of gate regions are arranged above the two groups of injection regions respectively, the two groups of gate regions are connected through the functional region, the source electrode 201 is connected above the two groups of gate regions, the sum of the widths of the gate regions and the two groups of injection regions is equal to the total width of the device, and the gate oxide layer 300 in the gate regions surrounds the periphery of the gate 400.
In this embodiment, a comparison study and discussion are performed on the cell structure of the present invention and the conventional cell structure through a simulation verification manner, as shown in fig. 1, which is a schematic diagram of the cell structure of a planar gate power MOSFET device in the prior art, a 1200V planar gate power MOSFET device is selected, the cell width is 9 μm, the drift region thickness is 10 μm, and the ion doping concentration of the drift region is 6 × 10 15 cm -3 The thickness of the grid oxide layer is 0.05 mu m; FIG. 2 is a schematic diagram showing a reinforced cell structure of a power VDMOSFET device with high UIS avalanche capability according to the present invention, wherein the cell width is 9 μm, the thickness of the N-type drift region 101 is 10.6 μm, and the ion doping concentration of the N-type drift region 101 is 6 × 10 15 cm -3 The thickness of the gate oxide layer 300 is 0.05 μm.
It should be noted that the non-clamped inductive switch means that when there is parasitic inductance in the circuit, the device will release the energy stored in the inductance to the device in a very short time in a switching state, thereby forcing the device to enter into an avalanche state. Based on the principle, the cell devices with two structures are subjected to simulation test.
FIG. 10 is a graph showing the temperature of the device lattice under UIS avalanche conditions for a conventional cell structure as a function of time. When the size of an inductor connected in series at two ends of a device is 2mH, the bias voltage at two ends of the inductor is 100V, the gate of the device is in a high level and is in a stage of charging the inductor, the charging time is set to be 660 microseconds, when the device is in a closing moment, the device is forced to enter an avalanche state, the avalanche voltage of the device reaches 1500V, the highest temperature of the device also exceeds 960K at the moment, and the temperature can cause serious degradation of structures such as metal aluminum and the like so that the device finally fails.
As shown in fig. 11, is a graph of the device lattice temperature versus time under UIS avalanche conditions for the high UIS avalanche tolerant cell structure of the present invention. The size of the inductor connected in series at the drain 200 of the device is also 2mH, the bias voltage of the inductor is also 100V, when the time of the high level of the gate is increased to 730 microseconds, the maximum avalanche voltage of the reinforced cellular structure is reduced to 1400V, and the maximum lattice temperature is about 1000K, i.e. the charging time of the inductor is increased by 70 microseconds, and the temperature is only increased by 40K. In addition, the current expansion layer 105 and the P-type high-concentration shielding layer 106 are introduced above the JFET region in the reinforced cellular structure, the current expansion layer 105 can inhibit resistance increase caused by the top P-type high-concentration shielding layer 106, and the resistance of the JFET region is further reduced, so that the same current can flow through the JFET region to generate smaller heat; when the device is in an avalanche state, electrons generated by impact ionization are rapidly extracted by the drain electrode 200, a part of holes with higher energy are injected into the gate oxide layer 300 under the action of negative gate bias voltage, and a hole release path can be formed by introducing the P-type high-concentration shielding layer 106 above the JFET, so that the injection of 'hot holes' into the gate oxide layer 300 is effectively inhibited, the gate oxide layer 300 is better protected, the UIS avalanche tolerance of the device is improved, and the advanced breakdown of the gate oxide layer 300 is inhibited at the same time, therefore, the gate reliability of the reinforced cellular structure is far higher than that of a common cellular structure, the electric field distribution in the device is more uniform when the device enters the avalanche state due to the introduction of the P-type high-concentration shielding layer 106, and the P-type high-concentration shielding layer 106 can also effectively absorb hole current and inhibit the false opening of an avalanche transistor, and further improve the tolerance of the device.
Example 2
The embodiment provides a method for manufacturing a power VDMOSFET device with high UIS avalanche tolerance, as shown in fig. 9, including the following steps:
s1, preparing high UIS avalancheThe N-type substrate region 100 required by the power VDMOSFET device with the tolerance has the ion doping concentration of 5 multiplied by 10 18 cm -3 ；
S2, forming an N-type drift region 101 on the upper surface of the N-type substrate region 100 in a mode of one-time chemical vapor deposition epitaxy, wherein the doping concentration of the N-type drift region is 6 multiplied by 10 15 cm -3 The breakdown voltage of the planar junction of the device can be ensured to be not lower than 1500V;
s3, forming a current expansion layer 105 on the upper surface of the formed N-type drift region 101 again in a chemical vapor deposition epitaxial mode, wherein the doping concentration is 1 x 10 17 cm -3 The doping concentration can reduce the on-resistance of the device so as to reduce the heat generated when current flows through the JFET area;
s4, implanting a mask at a position with a thickness of 30nm to 200nm above the current expansion layer 105, and forming a P-type high-concentration shielding layer 106 connected with the source electrode 201 in a multi-time ion implantation mode, wherein the existence of the mask can effectively inhibit a channel effect generated by ion implantation and can better control the implantation depth;
s5, forming the grooves with better anisotropy by utilizing a plasma etching method under the blocking of the mask plate through a grooving technology, wherein the grooves are arranged on two sides of the top end of the N-type drift region 101;
s6, sequentially forming a P-type light-concentration doped base region 102, an N-type high-concentration source region 104 and a P-type high-concentration doped region 103 on the groove in an ion implantation mode;
s7, carrying out high-temperature dry oxygen oxidation on the obtained device to form a grid oxide layer 300 with good quality, and then depositing polycrystalline silicon and doping phosphorus for etching to form a grid 400;
s8, after the obtained semiconductor device is subjected to metal contact opening, high-melting-point metal nickel or metal titanium is deposited, and then annealing is carried out to form the source electrode 201 and the drain electrode 200 which are good in ohmic contact characteristics.
Specifically, the cell structure shown in fig. 3 corresponds to the above steps S1 to S4: firstly, an N-type substrate area 100 is manufactured, then an N-type drift area 101 is formed on the upper surface of the N-type substrate area 100 through once epitaxy, and then the upper surface of the N-type drift area 101 is subjected to once epitaxyEpitaxially forming a current spreading layer 105 (CSL), and forming a P-type high-concentration shielding layer 106 on the upper surface of the current spreading layer 105 by means of multiple times of ion implantation; wherein the total thickness of the N-type drift region 101 is 10.6 μm, and the ion doping concentration range is 6 × 10 15 cm -3 To 8X 10 15 cm -3 The thickness of the drift region and the ion doping concentration can enable the breakdown voltage of the device plane node to be higher than 1500V all the time;
specifically, the current spreading layer 105 had a thickness of 0.6 μm, a width of 1.15 μm, and an ion doping concentration ranging from 8X 10 16 cm -3 To 2X 10 17 cm -3 When elected, 1X 10 17 cm -3 The ion doping concentration is an optimal value, so that the on-resistance and on-loss of the device can be effectively reduced, the heat generated when current flows through the JFET region is reduced, the breakdown of the device is not adversely affected, and the reliability of the device is remarkably improved;
specifically, the thickness of the P-type high concentration shielding layer 106 is 0.3 μm, the width is 2.3 μm, and the size can protect the gate oxide layer 300 when absorbing hot carriers, and can not increase the on-resistance of the device due to the formation of an excessively large depletion region; the ion doping concentration of the P-type high concentration shielding layer 106 is 1 × 10 19 cm -3 The concentration can form an ohmic contact electrode connected to the source electrode, can shield the electric field of the gate oxide layer 300 so as to improve the reliability of the gate oxide layer 300, and cannot influence the breakdown voltage of the device due to the overlarge depletion region.
The cell structure shown in fig. 4 corresponds to the step S5, that is, two trenches are etched on two sides of the top end of the epitaxial wafer of the structure shown in fig. 3 by using a conventional grooving technology, the depth range of the trench is 0.3 μm to 0.6 μm, and the device obtains an optimal effect when the depth of the trench is 0.6 μm, that is, the charge in the drift region can be depleted without affecting the breakdown voltage, and the on-state characteristic of the device is not greatly affected at the thickness.
The cell structure shown in fig. 5 and 6 corresponds to the step S6, that is, in the trench of the structure shown in fig. 4 obtained above, an implantation region is formed by multiple ion implantations, and the formation sequence is as follows: firstly, injecting from the upper part of the groove to form a P-type light concentration doping base region 102, then injecting from the upper part of the groove to form an N-type high concentration source region 104, and finally injecting from the outer side of the groove inwards to form a P-type high concentration doping region 103;
specifically, the width of the P-type lightly doped base region 102 is 2.1 μm, the junction depth of the doped base region is 1.0 μm, and the range of the ion doping concentration peak is 1 × 10 17 cm -3 To 5X 10 18 cm -3 The doping concentration in the range not only enables the threshold voltage of the device to be in a reasonable range, but also enables the device to have higher avalanche tolerance, and the higher doping concentration of the P-type light concentration doping base region 102 can inhibit the device from penetrating through and can reduce the parasitic resistance of the P-type light concentration doping base region 102, so that the threshold voltage triggered by a parasitic BJT can be improved;
specifically, the width of the P-type high concentration doped region 103 is 1.2 μm, the effective depth is 0.8 μm, and the range of the ion doping concentration peak is 1 × 10 20 cm -3 To 2X 10 20 cm -3 The high doping concentration is beneficial to the formation of ohmic contact with low contact resistance, and meanwhile, the depletion of the P-type light concentration doping base region 102 is avoided to a certain extent, and the breakdown voltage of the device is improved.
The cell structure shown in fig. 7 corresponds to the step S7, that is, a gate region is formed above the trench of the structure shown in fig. 6 by high-temperature oxidation, the gate region includes a gate 400 and a gate oxide layer 300, the gate oxide layer 300 is made of silicon dioxide material and surrounds the periphery of the gate 400; the thicknesses of the gate oxide layer 300 and the sidewall oxide layer of the device are both 0.05 μm, and the gate oxide layer 300 can further improve the gate oxide reliability of the device by forming an oxide layer with higher interface quality in a dry oxygen oxidation manner at 1300 ℃.
The cell structure shown in fig. 8 corresponds to the step S8, i.e. in the device shown in fig. 7, the source 201 is formed on the top of the device to connect the trench and the functional region, and the drain 200 is formed on the bottom of the device to connect the N-type substrate region 100.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A power VDMOSFET device with high UIS avalanche capability, comprising:
an N-type substrate region (100);
an N-type drift region (101), the N-type drift region (101) being on an upper surface of the N-type substrate region (100);
an implanted region in the trench on both sides above the N-type drift region (101), comprising: the light-concentration P-type doping base region (102), the high-concentration P-type doping region (103) and the high-concentration N-type source region (104), wherein the high-concentration N-type source region (104) is arranged between the light-concentration P-type doping base region (102) and the high-concentration P-type doping region (103);
a functional region intermediate over the N-type drift region (101), comprising: a current spreading layer (105) and a P-type high concentration shield layer (106), the current spreading layer (105) being below the P-type high concentration shield layer (106);
the gate region is arranged on two sides of the functional region and comprises: the grid electrode structure comprises a grid electrode oxide layer (300) and a grid electrode (400), wherein the grid electrode oxide layer (300) surrounds the periphery of the grid electrode (400);
a source (201), the source (201) connected above the gate region and the functional region;
a drain (200), the drain (200) connected below the N-type substrate region (100).
2. The VDMOSFET device with high UIS avalanche capability as claimed in claim 1, wherein the current spreading layer (105) in the functional region has a thickness of 0.6 μm, a width of 1.15 μm, and an ion doping concentration range of 810 16 cm -3 To 2X 10 17 cm -3 ；
The thickness of the P-type high-concentration shielding layer (106) is 0.3 μm, the width is 1.15 μm, and the peak value of the ion doping concentration is 1 × 10 19 cm -3 。
3. The high UIS avalanche capability power VDMOSFET device of claim 1 wherein said implanted region is located in a trench depth ranging from 0.3 μm to 0.6 μm;
the width of the P-type light concentration doping base region (102) is 2.1 mu m, the depth is 1.0 mu m, and the range of the ion doping concentration peak value is 1 multiplied by 10 17 cm -3 To 5X 10 18 cm -3 ；
The width of the P-type high-concentration doping region (103) is 1.2 mu m, the depth is 0.8 mu m, and the range of the ion doping concentration peak value is 1 multiplied by 10 20 cm -3 To 2X 10 20 cm -3 。
4. The VDMOSFET device of claim 1, wherein the N-type drift region (101) has a total thickness of 10.6 μm and an ion doping concentration in the range of 6 x 10 15 cm -3 To 8X 10 15 cm -3 。
5. A power VDMOSFET device of high UIS avalanche tolerance according to claim 1, characterized in that the thickness of said gate oxide layer (300) is 0.05 μm.
6. The method of fabricating a power VSMOSFET device with high UIS avalanche tolerance as claimed in any one of claims 1 to 5, comprising the steps of:
s1, preparing an N-type substrate region (100) required by a power VDMOSFET device with high UIS avalanche tolerance;
s2, forming an N-type drift region (101) on the upper surface of the N-type substrate region (100) in a one-time chemical vapor deposition epitaxy mode;
s3, forming a current expansion layer (105) on the upper surface of the N-type drift region (101) in a chemical vapor deposition epitaxy mode again;
s4, implanting a mask plate at a position with a thickness of 30nm to 200nm above the current expansion layer (105), and forming a P-type high-concentration shielding layer (106) in a multi-time ion implantation mode;
s5, forming grooves by utilizing a plasma etching method under the blocking of the mask plate through a grooving technology, wherein the grooves are formed on two sides of the top end of the N-type drift region (101);
s6, sequentially forming a P-type light-concentration doped base region (102), an N-type high-concentration source region (104) and a P-type high-concentration doped region (103) on the groove in an ion implantation mode;
s7, carrying out high-temperature dry oxygen oxidation on the obtained device, forming a grid oxide layer (300) above the groove, depositing polysilicon, doping phosphorus and etching to form a grid (400);
s8, depositing high-melting-point metal nickel or metal titanium on the obtained semiconductor device after metal contact opening, and then annealing to form a source electrode (201) and a drain electrode (200) with ohmic contact characteristics.
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| CN116403910A (en) * | 2023-05-29 | 2023-07-07 | 深圳市威兆半导体股份有限公司 | Silicon carbide MOSFET device and manufacturing method thereof |
| CN116403910B (en) * | 2023-05-29 | 2023-08-22 | 深圳市威兆半导体股份有限公司 | Silicon carbide MOSFET device and manufacturing method thereof |
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