CN114512406A - Manufacturing method of super junction device - Google Patents
Manufacturing method of super junction device Download PDFInfo
- Publication number
- CN114512406A CN114512406A CN202210411907.1A CN202210411907A CN114512406A CN 114512406 A CN114512406 A CN 114512406A CN 202210411907 A CN202210411907 A CN 202210411907A CN 114512406 A CN114512406 A CN 114512406A
- Authority
- CN
- China
- Prior art keywords
- manufacturing
- type
- epitaxial layer
- etching
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 238000001312 dry etching Methods 0.000 claims description 9
- 210000000746 body region Anatomy 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 abstract description 13
- 238000005429 filling process Methods 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 238000009826 distribution Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The embodiment of the invention provides a manufacturing method of a super junction device, and belongs to the technical field of chips. The manufacturing method of the super junction device comprises the following steps: manufacturing a first conductive epitaxial layer on a semiconductor substrate in a layering mode by adopting a multi-time epitaxial growth technology; and manufacturing and filling second conductive type regions on each first conductive type epitaxial layer to form a structure in which the first conductive type regions and the second conductive type regions are alternately arranged. The super junction device is manufactured by combining a multi-time epitaxy process and a deep groove single-time epitaxy filling process, a P column with uniform concentration distribution can be obtained on the device structure by comparing the multi-time epitaxy process, better groove depth uniformity can be obtained by comparing the deep groove single-time epitaxy filling process, and a P column cavity is avoided; compared with the two processes in the aspect of device performance, the breakdown voltage which meets the design requirements can be obtained, and meanwhile, good uniformity of the breakdown voltage can be guaranteed.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a manufacturing method of a super junction device.
Background
The super junction is a novel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device, and is composed of P-type Semiconductor thin layers (P columns for short) and N-type Semiconductor thin layers (N columns for short) which are alternately arranged. The structure can realize charge compensation by exhausting the P column and the N column at a lower voltage in a cut-off state, so that the P column and the N column can realize high breakdown voltage at a higher doping concentration, and meanwhile, low on-resistance can be obtained, and the theoretical limit of the traditional power MOSFET is broken through.
The current super junction power device manufacturing process mainly comprises two types: the method comprises the steps of firstly, adopting a multiple-time epitaxial technology, and obtaining alternately arranged P columns and N columns by adopting a multiple-time N-type epitaxial layer growth and P-type doping process; the other is a deep trench single epitaxial filling technology, which adopts a process of performing single deep trench etching on an N-type epitaxial layer and filling a P-type epitaxial layer at a time to obtain alternately arranged P columns and N columns.
The two existing process schemes have the disadvantages that: the doping process of the multi-time epitaxial process has the problem of uneven concentration distribution, so that the concentration gradient exists in each section of P column, the final P column doping concentration distribution is uneven, and the breakdown voltage of a device is influenced; the single epitaxial filling process of the deep groove has the defects that the difficulty of the etching process of the groove with a high depth-to-width ratio is high, the uniformity of the etching depth is not easy to control, and a cavity is easily formed during epitaxial filling to influence the breakdown voltage of a device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a super junction device, which can avoid the defects of the existing super junction device manufacturing process.
In order to achieve the above object, an embodiment of the present invention provides a method of manufacturing a super junction device, including: manufacturing a first conductive epitaxial layer on a semiconductor substrate in a layering manner by adopting a multi-time epitaxial growth technology; and manufacturing and filling second conductive type regions on each first conductive type epitaxial layer to form a structure in which the first conductive type regions and the second conductive type regions are alternately arranged.
Optionally, the semiconductor substrate is a heavily doped N-type substrate.
Optionally, the first conductivity type epitaxial layer is an N-type epitaxial layer, and the second conductivity type region is a P-type doped region.
Optionally, the manufacturing a second conductivity type region on each first conductivity type epitaxial layer includes: after the first conductive epitaxial layer is epitaxially grown, growing a hard mask layer by a chemical vapor deposition process; defining an etching area of the second conductive type area on the hard mask layer through a photoresist layer; taking the photoresist layer as a mask, and carrying out first-class etching on the hard mask layer; and performing first-type etching on the first conductive epitaxial layer to form the second conductive type region.
Optionally, after the etching of the hard mask layer, the method for manufacturing the super junction device further includes: and removing the photoresist layer after etching until the surface of the first conductive epitaxial layer is exposed.
Optionally, after the second conductive type region is fabricated and filled, the method for manufacturing the superjunction device further includes: and removing the hard mask layer through second etching.
Optionally, the hard mask layer is silicon oxide.
Optionally, the first type of etching is dry etching, and the second type of etching is wet etching.
Optionally, the manufacturing method of the super junction device further includes: and forming a P-type body region and a source region on the surface of the epitaxial layer of the structure in which the first conductive type regions and the second conductive type regions are alternately arranged.
Optionally, the method for manufacturing the super junction device further includes: and forming a gate structure above the P-type body region and the source region, wherein the gate structure comprises a gate oxide layer and a gate layer.
According to the technical scheme, the super junction device is manufactured by combining a multi-time epitaxy process and a deep groove single-time epitaxy filling process, the P column with uniform concentration distribution can be obtained by comparing the multi-time epitaxy process on the device structure, and better groove depth uniformity and P column cavities can be obtained and avoided by comparing the deep groove single-time epitaxy filling process; compared with the two processes in the aspect of device performance, the breakdown voltage which meets the design requirements can be obtained, and meanwhile, good uniformity of the breakdown voltage can be guaranteed.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 a-1 f are schematic structural diagrams illustrating various manufacturing links when a super junction device is manufactured based on a multi-epitaxial process;
2 a-2 d are schematic structural diagrams of manufacturing links of a super junction device based on a deep trench single epitaxial filling process;
fig. 3 is a schematic flow chart of a method for manufacturing a superjunction device provided by an embodiment of the present invention;
fig. 4 a-4 i are schematic structural diagrams of manufacturing links when a super junction device is manufactured according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an exemplary superjunction device provided by an embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Before describing the embodiments of the present invention in detail, a brief introduction will be made to the design ideas of the prior art and the embodiments of the present invention.
The current super junction power device manufacturing process mainly comprises two types: the method comprises the steps of firstly, adopting a multiple-time epitaxial technology, and obtaining alternately arranged P columns and N columns by adopting a multiple-time N-type epitaxial layer growth and P-type doping process; the other is a deep trench single epitaxial filling technology, which adopts a process of performing single deep trench etching on an N-type epitaxial layer and filling a P-type epitaxial layer at a time to obtain alternately arranged P columns and N columns.
Fig. 1 a-1 f show schematic structural diagrams of manufacturing links when a super junction device is manufactured based on a multi-time epitaxial process. Taking an N-type heavily doped substrate (N + substrate) as an example, and performing a triple epitaxial process, the step of fabricating the alternating structure of the P-pillar and the N-pillar of the super junction device by using a multiple epitaxial process may include:
1) on the N + substrate, a first N-type epitaxial layer is grown, and a photoresist is formed to define a P-type doped region, forming the structure shown in fig. 1 a.
2) After P-type doping is performed on the first N-type epitaxial layer, the photoresist is removed, resulting in the structure shown in fig. 1 b.
3) On the first N-type epitaxial layer, a second N-type epitaxial layer is grown, and a photoresist is formed to define a P-type doped region, thereby forming the structure shown in fig. 1 c.
4) After P-type doping is performed on the second N-type epitaxial layer, the photoresist is removed, resulting in the structure shown in fig. 1 d.
5) And growing a third N-type epitaxial layer on the second N-type epitaxial layer, forming a photoresist, defining a P-type doped region, and forming the structure shown in FIG. 1 e.
6) And (3) carrying out P-type doping on the third N-type epitaxial layer, and then removing the photoresist to form the structure shown in the figure 1 f.
Fig. 2 a-2 d show schematic structural diagrams of manufacturing links when a super junction device is manufactured based on a deep trench single epitaxial filling process. Taking an N + substrate as an example, the step of manufacturing the alternating structure of the P column and the N column of the super junction device by adopting the deep trench single epitaxial filling process may include:
1) on the N + substrate, an N-type epitaxial layer and silicon oxide are grown, and a photoresist is formed, defining a P-pillar trench etching region, forming the structure shown in fig. 2 a.
2) And (3) taking the photoresist as a mask, carrying out dry etching on the silicon oxide until the surface of the epitaxial layer is exposed, and then removing the photoresist to form the structure shown in figure 2 b.
3) And (3) performing dry etching on the epitaxial layer by using the silicon oxide as a hard mask, and etching the deep groove to a target depth to form the structure shown in fig. 2 c.
4) And filling the P-type epitaxial layer to enable the surface of the P column to be flush with the surface of the N-type epitaxial layer, and removing the silicon oxide by wet etching to form the structure shown in figure 2 d.
The two existing process schemes have the disadvantages that: the doping process of the multi-time epitaxial process has the problem of uneven concentration distribution, so that the concentration gradient exists in each section of P column, the final P column doping concentration distribution is uneven, and the breakdown voltage of a device is influenced; the single epitaxial filling process of the deep groove has the defects that the difficulty of the etching process of the groove with a high depth-to-width ratio is high, the uniformity of the etching depth is not easy to control, and a cavity is easily formed during epitaxial filling to influence the breakdown voltage of a device.
However, both processes also have advantages: the advantage of the multiple epitaxial process is that the P column is formed by P-type doping, the process is simple and easy to control; the advantage of the single epitaxial filling process of the deep trench is that the single epitaxial filling can obtain a P column with uniform concentration.
The manufacturing method of the super junction device provided by the embodiment of the invention can combine the advantages of the two processes and avoid the disadvantages of the two processes.
Fig. 3 is a schematic flowchart of a method for manufacturing a super junction device according to an embodiment of the present invention, and referring to fig. 3, the method for manufacturing a super junction device may include the following steps:
step S110: on a semiconductor substrate, a first conductive epitaxial layer is manufactured in a layered mode by adopting a multiple epitaxial growth technology.
The semiconductor substrate selectable in the embodiment of the invention is a heavily doped N-type substrate. I.e., an N + substrate.
The first conductive type epitaxial layer can be an N type, and multiple times of epitaxial growth can be adopted to manufacture the first conductive type epitaxial layer, namely a multi-layer N type epitaxial layer.
Step S120: and manufacturing and filling a second conduction type region on each first conduction type epitaxial layer to form a structure in which the first conduction type regions and the second conduction type regions are alternately arranged.
Optionally, the first conductivity type epitaxial layer is an N-type epitaxial layer, and the second conductivity type region is a P-type doped region.
The second conductivity type of the embodiment of the invention can be a P type, and on each N epitaxial layer, deep trenches can be adopted for single epitaxial filling to fill the P type epitaxial layer so as to form alternately arranged P column and N column structures.
According to the manufacturing process of the super junction device provided by the embodiment of the invention, the two processes of multiple epitaxy and single epitaxy filling of the deep groove are combined, and the process of forming the P column through P type doping is changed into the process of etching the groove and filling the P type epitaxy layer on the basis of the multiple epitaxy process, so that the problem of uneven concentration distribution of the P column formed through P type doping can be avoided, and the problem of uniformity of the depth of the groove caused by single deep groove etching and the problem of filling holes caused by deep groove epitaxy filling can also be avoided.
In a preferred embodiment of the present invention, the fabricating a second conductivity type region on each first conductivity type epitaxial layer includes: after the first conductive epitaxial layer is epitaxially grown, growing a hard mask layer by a chemical vapor deposition process; defining an etching area of the second conductive type area on the hard mask layer through a photoresist layer; taking the photoresist layer as a mask, and carrying out first-class etching on the hard mask layer; and performing first-type etching on the first conductive epitaxial layer to form the second conductive type region.
Preferably, after the etching of the hard mask layer, the method for manufacturing a super junction device further includes: and removing the photoresist layer after etching until the surface of the first conductive epitaxial layer is exposed.
Preferably, after the second conductive type region is fabricated and filled, the method for manufacturing a superjunction device further comprises: and removing the hard mask layer through second etching.
Preferably, the hard mask layer is silicon oxide.
Further preferably, the first etching is dry etching, and the second etching is wet etching.
Fig. 4a to fig. 4i are schematic structural diagrams of various manufacturing links when manufacturing a super junction device according to an embodiment of the present invention, so as to select an N + substrate and combine the N + substrate with a deep trench single epitaxial filling process by three epitaxial processes, where a preferred manufacturing method of a super junction device according to an embodiment of the present invention may include the following steps:
1) on the N + substrate, a first conductive type epitaxial layer (e.g., a first N-type epitaxial layer) and a hard mask layer (e.g., silicon oxide) are grown, and a photoresist (layer) is formed to define an etching region (e.g., a P-pillar etching region) of a second conductive type region, thereby forming the structure shown in fig. 4 a.
2) And (3) performing first-type etching (for example, dry etching) on the silicon oxide by using the photoresist as a mask until the surface of the first N-type epitaxial layer is exposed, and removing the photoresist to form the structure shown in fig. 4 b.
3) And (4) taking the silicon oxide as a hard mask, carrying out dry etching on the first N-type epitaxial layer to a target depth, and forming the structure shown in fig. 4 c.
4) And filling a second conductive type region (for example, a P-type epitaxial layer) in the first N-type epitaxial layer to make the surface of the P column flush with the surface of the N-type epitaxial layer, and removing silicon oxide by using first etching (for example, wet etching) to form the structure shown in fig. 4 d.
5) On the first N-type epitaxial layer, a second N-type epitaxial layer and silicon oxide are grown, and a photoresist is formed to define a P-pillar etching region, forming the structure shown in FIG. 4 e.
6) And (5) taking the photoresist as a mask, carrying out dry etching on the silicon oxide until the surface of the second N-type epitaxial layer is exposed, and removing the photoresist to form the structure shown in the figure 4 f.
7) And (5) taking silicon oxide as a hard mask, carrying out dry etching on the second N-type epitaxial layer until the surface of the P column of the first N-type epitaxial layer is etched, and forming the structure shown in fig. 4 g.
8) And filling a P-type epitaxial layer into the second N-type epitaxial layer to enable the surface of the P column to be flush with the surface of the N-type epitaxial layer, and removing silicon oxide by wet etching to form the structure shown in fig. 4 h.
9) And 5) repeating the steps 5) -8), and performing growth, groove etching and epitaxial filling of the third N-type epitaxial layer by using the same process to form the structure shown in fig. 4i (similar to fig. 1 f), namely, forming the final P-pillar and N-pillar structure which are alternately arranged.
Preferably, the method for manufacturing the superjunction device may further include: and forming a P-type body region and a source region on the surface of the epitaxial layer of the structure in which the first conductive type regions and the second conductive type regions are alternately arranged.
Further preferably, the method for manufacturing the superjunction device may further include: and forming a gate structure above the P-type body region and the source region, wherein the gate structure comprises a gate oxide layer and a gate layer.
By way of example, after the structure shown in fig. 4i, i.e., the P-pillar and N-pillar structures arranged alternately, is formed, a P-type body region and a gate oxide and gate structure are formed on the surface of the epitaxial layer, and a final super junction device can be formed.
Therefore, the super junction device formed by the manufacturing process of the embodiment of the invention can obtain the P column with uniform concentration distribution compared with a multi-time epitaxial process on the device structure, and can obtain better trench depth uniformity and avoid a P column cavity compared with a single-time epitaxial filling process of a deep trench; compared with the two processes in the aspect of device performance, the breakdown voltage which meets the design requirements can be obtained, and meanwhile, good uniformity of the breakdown voltage can be guaranteed.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A method of manufacturing a super junction device, comprising:
manufacturing a first conductive epitaxial layer on a semiconductor substrate in a layering mode by adopting a multi-time epitaxial growth technology; and
and manufacturing and filling second conductive type regions on each first conductive type epitaxial layer to form a structure in which the first conductive type regions and the second conductive type regions are alternately arranged.
2. The method for manufacturing a super junction device according to claim 1, wherein the semiconductor substrate is a heavily doped N-type substrate.
3. The method for manufacturing a super junction device according to claim 1, wherein the first conductivity type epitaxial layer is an N-type epitaxial layer, and the second conductivity type region is a P-type doped region.
4. The method for manufacturing a super junction device according to claim 1, wherein the step of forming a second conductivity type region on each first conductivity type epitaxial layer comprises:
after the first conductive epitaxial layer is epitaxially grown, growing a hard mask layer by a chemical vapor deposition process;
defining an etching area of the second conductive type area on the hard mask layer through a photoresist layer;
taking the photoresist layer as a mask, and carrying out first-class etching on the hard mask layer; and
and carrying out first-type etching on the first conductive epitaxial layer to form the second conductive type region.
5. The method of manufacturing a superjunction device of claim 4, wherein after said etching the hard mask layer, the method of manufacturing a superjunction device further comprises:
and removing the photoresist layer after etching until the surface of the first conductive epitaxial layer is exposed.
6. The method of manufacturing a superjunction device of claim 4, wherein after said fabricating and filling second conductivity type regions, the method of manufacturing a superjunction device further comprises:
and removing the hard mask layer through second etching.
7. The method for manufacturing a super junction device according to any one of claims 4 to 6, wherein the hard mask layer is silicon oxide.
8. The method for manufacturing the super junction device according to claim 6, wherein the first type of etching is dry etching, and the second type of etching is wet etching.
9. The method of manufacturing a superjunction device of claim 1, further comprising:
and forming a P-type body region and a source region on the surface of the epitaxial layer of the structure in which the first conductive type regions and the second conductive type regions are alternately arranged.
10. The method of manufacturing a superjunction device of claim 9, further comprising:
forming a gate structure over the P-type body region and the source region,
the gate structure includes a gate oxide layer and a gate layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210411907.1A CN114512406A (en) | 2022-04-19 | 2022-04-19 | Manufacturing method of super junction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210411907.1A CN114512406A (en) | 2022-04-19 | 2022-04-19 | Manufacturing method of super junction device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114512406A true CN114512406A (en) | 2022-05-17 |
Family
ID=81555085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210411907.1A Pending CN114512406A (en) | 2022-04-19 | 2022-04-19 | Manufacturing method of super junction device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114512406A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115148791A (en) * | 2022-09-05 | 2022-10-04 | 深圳市威兆半导体股份有限公司 | Super junction MOSFET |
| CN115662952A (en) * | 2022-11-02 | 2023-01-31 | 瑶芯微电子科技(上海)有限公司 | Groove type super junction field effect transistor and preparation method thereof |
| CN116646251A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN117476468A (en) * | 2023-12-26 | 2024-01-30 | 北京智芯微电子科技有限公司 | Super junction structure, manufacturing method thereof, super junction semiconductor device and semiconductor structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863623A (en) * | 2020-08-25 | 2020-10-30 | 上海维安半导体有限公司 | Preparation method of multilayer super junction semiconductor device |
-
2022
- 2022-04-19 CN CN202210411907.1A patent/CN114512406A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863623A (en) * | 2020-08-25 | 2020-10-30 | 上海维安半导体有限公司 | Preparation method of multilayer super junction semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115148791A (en) * | 2022-09-05 | 2022-10-04 | 深圳市威兆半导体股份有限公司 | Super junction MOSFET |
| CN115662952A (en) * | 2022-11-02 | 2023-01-31 | 瑶芯微电子科技(上海)有限公司 | Groove type super junction field effect transistor and preparation method thereof |
| CN115662952B (en) * | 2022-11-02 | 2023-04-07 | 瑶芯微电子科技(上海)有限公司 | Groove type super junction field effect transistor and preparation method thereof |
| CN116646251A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN116646251B (en) * | 2023-07-27 | 2023-09-19 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN117476468A (en) * | 2023-12-26 | 2024-01-30 | 北京智芯微电子科技有限公司 | Super junction structure, manufacturing method thereof, super junction semiconductor device and semiconductor structure |
| CN117476468B (en) * | 2023-12-26 | 2024-03-22 | 北京智芯微电子科技有限公司 | Super junction structure, manufacturing method thereof, super junction semiconductor device and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114512406A (en) | Manufacturing method of super junction device | |
| JP3938964B2 (en) | High voltage semiconductor device and manufacturing method thereof | |
| KR101899697B1 (en) | Semiconductor structure with high energy dopant implantation technology | |
| KR100731141B1 (en) | Semiconductor device and method for fabricating the same | |
| JP3634848B2 (en) | Power semiconductor device | |
| CN111799322B (en) | Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method | |
| JP2006024770A (en) | Semiconductor device | |
| CN114420761B (en) | High-pressure-resistant silicon carbide device and preparation method thereof | |
| CN105103294A (en) | Device architecture and method for improved packing of vertical field effect devices | |
| JP2002368216A (en) | Semiconductor element and manufacturing method therefor | |
| JP2024023969A (en) | silicon carbide substrate | |
| CN107799419A (en) | Super junction power device and preparation method thereof | |
| US11158705B2 (en) | Method for forming a superjunction transistor device | |
| CN104409334B (en) | A kind of preparation method of superjunction devices | |
| CN110137245B (en) | Super junction device structure and preparation method thereof | |
| WO2024021977A1 (en) | Trench-gate power mosfet and manufacturing method therefor | |
| CN115064446B (en) | Super junction semiconductor device and preparation method thereof | |
| CN114744027B (en) | Silicon carbide LDMOSFET device manufacturing method and silicon carbide LDMOSFET device | |
| CN114664934B (en) | DMOS transistor with field plate and manufacturing method thereof | |
| CN115714141A (en) | JFET injection type N-channel SiC MOSFET device and preparation method thereof | |
| TWI460823B (en) | Methods for fabricating trench metal oxide semiconductor field effect transistors | |
| CN112599600A (en) | Vertical double-diffused transistor and manufacturing method thereof | |
| CN102751199B (en) | Manufacturing method for groove type semiconductor power device | |
| CN115966596B (en) | Separation groove transverse double-diffusion power device and manufacturing method thereof | |
| CN117174758B (en) | SGT MOSFET device and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220517 |