CN115064446B

CN115064446B - Super junction semiconductor device and preparation method thereof

Info

Publication number: CN115064446B
Application number: CN202210990168.6A
Authority: CN
Inventors: 赵东艳; 肖超; 陈燕宁; 邵瑾; 付振; 刘芳; 田俊; 张泉; 尹强
Original assignee: State Grid Corp of China SGCC; Beijing Smartchip Microelectronics Technology Co Ltd; Beijing Core Kejian Technology Co Ltd
Current assignee: State Grid Corp of China SGCC; Beijing Smartchip Microelectronics Technology Co Ltd; Beijing Core Kejian Technology Co Ltd
Priority date: 2022-08-18
Filing date: 2022-08-18
Publication date: 2022-12-16
Anticipated expiration: 2042-08-18
Also published as: CN115064446A; WO2024036792A1

Abstract

The invention relates to the field of power semiconductors, and particularly discloses a super junction semiconductor device and a preparation method thereof, wherein the preparation method comprises the following steps: etching a first preset area of a wafer by a deep trench etching process to obtain at least one Ai deep trench, and filling the Ai deep trench with the doping concentration of N _Ai The first epitaxial layer forms the ith epitaxial column of the first conductivity type; etching a second preset region of the wafer by a deep trench etching process to obtain at least one Di deep trench, and filling the Di deep trench with the doping concentration of N _Di Forming an ith epitaxial column of the second conductivity type on the second epitaxial layer; and circulating the steps to manufacture the super junction structure in the wafer. The technical scheme can solve the problem of cavities generated by single epitaxial filling of the traditional deep trench; the method is mainly used for preparing the super junction semiconductor device.

Description

Super junction semiconductor device and preparation method thereof

Technical Field

The disclosure relates to the field of power semiconductors, in particular to a super junction semiconductor device and a manufacturing method thereof.

Background

With the rapid development of energy transformation and automobile electromotion, the continuous improvement of the efficiency of power electronic systems is an urgent need of various system manufacturers in the world. The performance of the power semiconductor device, which acts as the "heart" of the power electronic system, itself determines the efficiency of the overall system. Compared with a traditional power Semiconductor device MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, the super-junction Semiconductor device SJ-MOSFET (super junction MOSFET) breaks the so-called silicon limit due to the adoption of a charge balance voltage-withstanding layer structure, can remarkably reduce the on-resistance of the device (the resistance can be reduced by 5 to 10 times under the condition of the same voltage class), and improves the system efficiency.

At present, the manufacturing process of the super junction semiconductor device mainly comprises two processes: one is a multi-time epitaxial process, and the other is a deep groove single epitaxial filling process; the multiple epitaxy process has the disadvantages of multiple epitaxy times, high cost and the like, so the conventional common manufacturing process is a deep trench single epitaxy filling process. The process of the single epitaxial filling process of the deep groove requires one deep groove etching to form the deep groove in the N-type epitaxial layer, and then the deep groove is filled with the P-type epitaxial material to form the P columns and the N columns which are alternately arranged; in the process flow, the deep groove etching and the epitaxial layer filling are only needed once, and the process is relatively simple. However, since the deep trench has a large aspect ratio (greater than 10.

Disclosure of Invention

In order to solve the problems in the related art, embodiments of the present disclosure provide a super junction semiconductor device and a method of manufacturing the same.

In a first aspect, a method for manufacturing a super junction semiconductor device is provided in the embodiments of the present disclosure.

The preparation method of the super junction semiconductor device comprises the following steps:

etching a first preset area of a wafer by a deep trench etching process to obtain at least one Ai deep trench, and filling the Ai deep trench with the doping concentration of N _Ai The first epitaxial layer forms the ith epitaxial column of the first conductivity type;

etching a second preset region of the wafer by a deep trench etching process to obtain at least one Di deep trench, and filling the Di deep trench with the doping concentration of N _Di Forming an ith epitaxial column of the second conductivity type on the second epitaxial layer; the Di deep groove is positioned between the ith layer of epitaxial pillars of the first conduction type;

the steps are circularly carried out until i = M, and a first epitaxial column and a second epitaxial column are obtained, wherein the first epitaxial column comprises M sections of first epitaxial layers, and the second epitaxial column comprises M sections of second epitaxial layers; the value of i is 1-M, M is an integer greater than or equal to 2, and the depth of the Ai deep groove is gradually reduced and the depth of the Di deep groove is also gradually reduced along with the increase of i.

In one possible embodiment, the method further comprises:

forming a silicon oxide thin layer on the surface of the ith epitaxial column of the first conductivity type in a thermal oxidation mode;

and forming a silicon oxide thin layer on the surface of the ith layer of epitaxial column of the second conductivity type by means of thermal oxidation.

In one possible implementation, the etching at least one Ai deep trench on the wafer by the deep trench etching process includes:

when i is more than or equal to 2, forming a light resistance required by Ai deep groove etching when i is more than or equal to 2, wherein the opening of the light resistance is more than that of the epitaxial column of the first conductivity type of the (i-1) th layer;

and etching the wafer by a deep groove etching process based on the light resistance to obtain at least one Ai deep groove.

In one possible embodiment, the method further comprises:

and an annealing process is adopted to enable the first epitaxial column and the second epitaxial column to be in contact.

In one possible embodiment, when the wafer includes a semiconductor substrate and an epitaxial layer, the method includes:

an epitaxial layer of the second conductivity type is grown on an upper surface of the semiconductor substrate of the second conductivity type.

In one possible embodiment, the wafer comprises a low-doped high-resistance wafer of the second conductivity type, and the method further comprises:

after the A1 deep groove and the D1 deep groove are obtained through etching, injecting a second conduction type groove to form a super junction field stop layer;

and implanting a first conductive type into the surfaces of the wafer and the super junction structure, forming a first conductive type body region at the first epitaxial column, and forming a field limiting ring at the terminal region.

In one possible embodiment, the method further comprises:

thinning the thickness of the low-doped high-resistance wafer to a preset thickness by a back thinning process;

and performing second conductive type injection and laser annealing on the back surface of the low-doped high-resistance wafer to form a substrate of the second conductive type.

In one possible embodiment, the method further comprises:

the thickness of the low-doped high-resistance wafer is reduced to a preset thickness through a back thinning process;

and performing first conductive type injection and laser annealing on the back of the low-doped high-resistance wafer to form a first conductive type substrate.

In one possible embodiment, the method further comprises:

and forming a first conductive type body region at the first epitaxial pillar, and forming a gate oxide layer and a polysilicon gate layer on the surface of the second epitaxial pillar.

In one possible embodiment, the method further comprises:

forming a first conductivity type body region at the first epitaxial pillar;

and etching a groove at the upper end of the second epitaxial column, thermally oxidizing to form a groove-shaped groove gate oxide layer, and then depositing polycrystalline silicon to form a groove polycrystalline silicon gate layer.

In one possible implementation, the range of the gap between the adjacent Ai deep trench and the Di deep trench includes greater than 0 and equal to or less than 0.05um.

In a possible embodiment, the electric field strength at the central axis of any one of the first epitaxial pillars forms an inflection point at the intersection of any two adjacent first epitaxial layers, the central axis passing through the geometric center of the transverse cross section of the first epitaxial pillar and extending along the longitudinal direction, the transverse direction being a direction parallel to the wafer surface, and the longitudinal direction being a direction perpendicular to the wafer surface.

In one possible embodiment, the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, and the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di And meeting the preset condition to ensure that the super junction structure achieves charge balance.

In a possible embodiment, in the case where M is an even number, if i is an odd number, then N is _Ai >N _Di If i is an even number, then N _Ai <N _Di 。

In one possible embodiment, in the case where M is an odd number, if i = (M + 1)/2, then N _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is smaller than (M + 1)/2, then N _Ai <N _Di If i is an odd number and is greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di 。

In one possible embodiment, the first epitaxial pillar and the second epitaxial pillar are both the same width.

In a possible embodiment, the width of the first epitaxial column or the second epitaxial column ranges from 1 um to 6um.

In one possible embodiment, the thickness of each segment of the first epitaxial layer and each segment of the second epitaxial layer are the same.

In a possible implementation mode, the thickness of each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10um.

In a possible embodiment, the value range of M is 2 to 10.

In one possible embodiment, the first conductivity type is N-type and the second conductivity type is P-type;

or, the first conductivity type is P-type, and the second conductivity type is N-type.

In one possible embodiment, the doping concentration N _Ai And the doping concentration N _Di The value range of (1) is 1e15 to 1e17cm ^-3 。

In a second aspect, the disclosed embodiments provide a superjunction semiconductor device.

The super junction semiconductor device comprises the super junction semiconductor device manufactured by applying the method of the first aspect, and the super junction semiconductor device comprises:

a wafer;

the super junction structure is formed in the wafer and comprises at least one first epitaxial column of a first conductivity type and at least one second epitaxial column of a second conductivity type, wherein the first epitaxial column and the second epitaxial column are transversely and alternately arranged, the first epitaxial column comprises M sections of first epitaxial layers, the second epitaxial column comprises M sections of second epitaxial layers, the first conductivity type is opposite to the second conductivity type, M is an integer greater than or equal to 2, and the transverse direction is parallel to the surface of the wafer.

In a third aspect, a superjunction semiconductor device is provided in embodiments of the present disclosure.

The super junction semiconductor device includes:

a wafer;

the super junction structure is formed in the wafer and comprises at least one first epitaxial column of a first conductivity type and at least one second epitaxial column of a second conductivity type, the first epitaxial column and the second epitaxial column are transversely and alternately arranged, the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations, the first conductivity type is opposite to the second conductivity type, M is an integer greater than or equal to 2, and the transverse direction is a direction parallel to the surface of the wafer;

wherein, the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di The super junction structure can reach charge balance by meeting the preset condition; if M is an even number, if i is an odd number, then N _Ai >N _Di If i is an even number, then N _Ai <N _Di 。

In one possible embodiment, in the case where M is an odd number, if i = (M + 1)/2, then N _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di 。

In one possible embodiment, the first epitaxial pillar and the second epitaxial pillar are all the same in width.

In a possible embodiment, the value range of M is 2 to 10.

In one possible embodiment, the wafer comprises:

a semiconductor substrate of a second conductivity type;

and the second conduction type epitaxial layer is deposited on the semiconductor substrate, wherein the super junction structure is formed in the second conduction type epitaxial layer.

In one possible embodiment, the wafer comprises a low-doped high-resistance wafer of a second conductivity type; the super junction semiconductor device further includes:

a super junction field stop layer located below the super junction structure in the wafer;

and the super junction terminal structure is positioned at the edge of the super junction semiconductor device.

In one possible embodiment, the super junction termination structure includes a field limiting ring.

In one possible implementation, the method further includes:

and the substrate of the second conduction type is positioned below the low-doped high-resistance wafer of the second conduction type.

In one possible embodiment, the method further comprises:

and the substrate of the first conduction type is positioned below the low-doped high-resistance wafer of the second conduction type.

In one possible embodiment, the method further comprises:

the first conduction type body region is formed on the surface of the super junction structure;

a gate oxide layer on an upper surface of the second epitaxial pillar;

and the polysilicon gate layer is positioned on the upper surface of the gate oxide layer.

In one possible implementation, the method further includes:

the groove gate oxide layer is in a groove shape and is positioned in the groove at the upper end of the second epitaxial column;

and the groove polycrystalline silicon gate layer is positioned in the groove of the groove gate oxide layer.

In one possible embodiment, the first conductivity type is N-type, and the second conductivity type is P-type;

In a fourth aspect, a superjunction semiconductor device is provided in embodiments of the present disclosure.

The super junction semiconductor device includes:

a wafer;

the super junction structure is formed in the wafer and comprises at least one first epitaxial column of a first conductivity type and at least one second epitaxial column of a second conductivity type, the first epitaxial column and the second epitaxial column are transversely and alternately arranged, the first epitaxial column comprises M sections of first epitaxial layers, the second epitaxial column comprises M sections of second epitaxial layers corresponding to the first epitaxial layers, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2;

the electric field intensity of the central axis of any first epitaxial column forms an inflection point at the junction of any two adjacent first epitaxial layers, the central axis passes through the geometric center of the transverse section of the first epitaxial column and extends along the longitudinal direction, the transverse direction is parallel to the surface of the wafer, and the longitudinal direction is perpendicular to the surface of the wafer.

In one possible embodiment, the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, and the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di And meeting a preset condition to enable the super-junction structure to reach charge balance.

In a possible embodiment, in the case where M is even, if i is odd, then N _Ai >N _Di If i is an even number, then N _Ai <N _Di 。

In one possible embodiment, in the case where M is an odd number, if i = (M + 1)/2, then N _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is an odd number and is greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di 。

In a possible implementation manner, the value range of the thickness of each section of the first epitaxial layer and each section of the second epitaxial layer includes 5 to 10um.

According to the technical scheme provided by the embodiment of the disclosure, the first epitaxial column and the second epitaxial column in the super junction structure comprise a plurality of sections of epitaxial layers, and need to be formed by multiple times of deep trench etching and filling, and the aspect ratio is smaller and smaller in multiple times of trench filling processes, so that the problem of cavities generated by single epitaxial filling of the traditional deep trench can be solved; in addition, compared with a multi-time epitaxial process, when the super junction structure is manufactured, the multi-time epitaxial process needs 8-9 times of photoetching process to manufacture the epitaxial column, the epitaxial column manufactured by using the multi-time groove etching only needs M times of photoetching process, generally, M takes a value of 2-3 times, namely, the epitaxial column can be manufactured by only 2-3 times of photoetching process, the required photoetching process times are less, the cost is lower, in addition, the deep groove etching process is adopted to manufacture each epitaxial column, the transverse diffusion of the epitaxial column is smaller, the cell pitch (unit gap), namely, the gap between two epitaxial columns can be smaller, and the doping concentration of each epitaxial column is also easier to control.

Furthermore, the first epitaxial column and the second epitaxial column in the super junction structure comprise a plurality of sections of epitaxial layers, the electric field intensity at the longitudinal central axis of the first epitaxial column forms an inflection point at the junction of any two adjacent first epitaxial layers, triangular wave electric field distribution can be formed, and compared with the parabolic electric field distribution formed by the traditional single epitaxial layer with the same concentration, the breakdown voltage of the super junction semiconductor device disclosed by the invention is less influenced by the fluctuation of epitaxial filling concentration, and has a larger process window.

Further, the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers may be set _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di Different and satisfies that if i is an odd number in the case where M is an even number, thenN _Ai >N _Di If i is an even number, then N _Ai <N _Di (ii) a If M is an odd number, N is N if i = (M + 1)/2 _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _D (ii) a Therefore, when the device is subjected to reverse breakdown, compared with the traditional single deep groove with the epitaxial layers with the same concentration on the epitaxial columns, the breakdown voltage is less influenced by the fluctuation of the doping concentration of the epitaxial layers, and under the condition that the breakdown voltage meets the requirement, the doping concentration range of each epitaxial layer is larger, and a larger process window is provided.

Further, in N _Ai Is not equal to N _Di When, set | N _A1 -N _D1 |=|N _A2 -N _D2 |=……=|N _AM -N _DM |<2e12/W, under the condition that the breakdown voltage meets the requirement, the fluctuation range of the doping concentration of each epitaxial layer can be further increased, and a larger process window is provided.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments when taken in conjunction with the accompanying drawings. In the drawings.

Fig. 1 shows a flow chart of a conventional single epitaxial filling process for deep trenches.

Fig. 2 shows a schematic flow diagram of a method for manufacturing a superjunction semiconductor device according to an embodiment of the present disclosure.

Fig. 3 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.

Fig. 4 shows a schematic flow diagram of steps in a method for manufacturing a super junction semiconductor device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic flow diagram of steps in a method for manufacturing a super junction semiconductor device according to an embodiment of the present disclosure.

Fig. 6 shows a partial step flow schematic diagram in a method of manufacturing a super junction semiconductor device according to an embodiment of the present disclosure.

Fig. 7A shows an effective doping concentration distribution and an electric field distribution diagram of an electric field strength at a central axis of a second epitaxial pillar in a depth direction of the second epitaxial pillar according to an embodiment of the present disclosure.

Fig. 7B shows an electric field distribution diagram of electric field intensity at the longitudinal central axis of the N-type epitaxial column of the even-segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device along the depth direction of the N-type epitaxial column.

Fig. 7C shows the variation of breakdown voltage of the even-segment-doped and uniformly-doped superjunction semiconductor devices as a function of P-type epitaxial column concentration.

Fig. 7D shows an electric field distribution diagram of electric field intensity at the longitudinal central axis of the N-type epitaxial pillar of the odd-segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device along the depth direction of the N-type epitaxial pillar.

Fig. 7E shows the variation of the breakdown voltage of the odd-segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device with the concentration of the P-type epitaxial pillar.

Fig. 8 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.

Fig. 9 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.

Fig. 10 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. Furthermore, parts that are not relevant to the description of the exemplary embodiments have been omitted from the drawings for the sake of clarity.

In the present disclosure, it is to be understood that terms such as "including" or "having," etc., are intended to indicate the presence of the disclosed features, numbers, steps, behaviors, components, parts, or combinations thereof, and are not intended to preclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or combinations thereof may be present or added.

It should be further noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

As mentioned above, at present, there are two main processes for manufacturing a super junction semiconductor device: one is a multi-time epitaxial process, and the other is a deep groove single epitaxial filling process; the multiple epitaxy process has the disadvantages of multiple epitaxy times, high cost and the like, so the conventional common manufacturing process is a deep trench single epitaxy filling process. Fig. 1 shows a flow chart of a conventional single epitaxial filling process for deep trenches, which, as shown in fig. 1, may include the following steps:

(1) As shown in a diagram in fig. 1, silicon oxide 12 and a photoresist 13 required for deep trench etching are formed on an N epitaxial layer 11;

(2) As shown in fig. 1B, transferring the photoresist 13 pattern to the silicon oxide barrier layer 14 and etching the N epitaxial layer to a desired depth to obtain a deep trench 15;

(3) As shown in fig. 1C, the deep trench 15 is filled with P-type epitaxial material to form P pillars and N pillars alternately arranged;

(4) As shown in fig. 1D, the surface of the silicon oxide barrier layer 14 is removed and P-type body regions 16, gate oxides 17 and polysilicon gates 18 are formed.

In the process flow, the deep groove etching and the epitaxial layer filling are only required to be carried out once, and the process is relatively simple. However, since the deep trench has a large aspect ratio (greater than 10.

In order to solve the above problems, the present disclosure provides a super junction semiconductor device and a method of manufacturing the same.

The present disclosure provides a method for manufacturing a super junction semiconductor device, and fig. 2 shows a schematic flow chart of a method for manufacturing a super junction semiconductor device according to an embodiment of the present disclosure, and as shown in fig. 2, the method includes the steps of:

in step S201, at least one Ai deep trench is obtained by etching a first predetermined region of a wafer through a deep trench etching process, and the Ai deep trench is filled with a doping concentration of N _Ai The first epitaxial layer forms an ith epitaxial column of the first conductivity type;

in step S202, at least one Di deep trench is obtained by etching in a second predetermined region of the wafer through a deep trench etching process, and the Di deep trench is filled with a doping concentration of N _Di Forming an ith epitaxial column of the second conductivity type on the second epitaxial layer; the Di deep groove is positioned between the epitaxial columns of the ith layer of the first conduction type;

in step S203, the above steps are cyclically performed until i = M, so as to obtain a first epitaxial pillar and a second epitaxial pillar, where the first epitaxial pillar includes M sections of first epitaxial layers, and the second epitaxial pillar includes M sections of second epitaxial layers; the value of i is 1-M, M is an integer greater than or equal to 2, and the depth of the Ai deep groove is gradually reduced and the depth of the Di deep groove is also gradually reduced along with the increase of i.

In one possible implementation, fig. 3 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure. As shown in fig. 3, a super junction structure 30 may be formed in the wafer 20 through multiple deep trench etching processes, where the super junction structure 30 includes at least one first epitaxial pillar 31 of a first conductivity type and at least one second epitaxial pillar 32 of a second conductivity type, the first epitaxial pillar 31 and the second epitaxial pillar 32 are alternately arranged in a lateral direction, and the lateral direction is a direction parallel to the surface of the wafer, so that the super junction structure 30 may be formed.

In one possible implementation, as shown in fig. 3, the first epitaxial pillar 31 includes M segments of the first epitaxial layer 311, the second epitaxial pillar 32 includes M segments of the second epitaxial layer 321, the first conductivity type is opposite to the second conductivity type, and when the first conductivity type is N type, the second conductivity type is P type; or, when the first conductivity type is P-type, the second conductivity type is N-type. M is an integer greater than or equal to 2; optionally, the value range of M may be 2 to 10, for example, M in fig. 3 takes a value of 4.

In a possible implementation manner, the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers is _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di And meeting the preset condition to ensure that the super junction structure achieves charge balance.

In one possible embodiment, the doping concentration N of the M sections of the first epitaxial layer in the first epitaxial column 31 _Ai The doping concentration N of the M sections of the second epitaxial layer 321 in the second epitaxial column 32 can be the same or different _Di May be the same or different.

According to the super-junction semiconductor device prepared by the method, the first epitaxial column and the second epitaxial column in the super-junction structure comprise a plurality of sections of epitaxial layers and are formed by multiple times of groove etching and filling, the depth-to-width ratio is smaller and smaller in multiple times of groove filling processes, the problem of cavities generated by single epitaxial filling of a traditional deep groove can be solved, and compared with a multiple times of epitaxial process, the cost is lower.

In one possible embodiment, the method further comprises:

In this embodiment, after the ith layer of the epitaxial pillar of the first conductivity type is obtained by performing step S201, a thin silicon oxide layer is formed on the surface of the ith layer of the epitaxial pillar of the first conductivity type by thermal oxidation, and then step S202 is performed to deep-trench etch at least one Di deep trench, where the thin silicon oxide layer can serve as a barrier layer to protect the ith layer of the epitaxial pillar of the first conductivity type from being etched.

In this embodiment, after the ith layer of the epitaxial pillar of the second conductivity type is obtained by performing step S202, a thin silicon oxide layer is formed on the surface of the ith layer of the epitaxial pillar of the second conductivity type by thermal oxidation, and then step S201 can be performed cyclically to continue the deep trench etching, where the thin silicon oxide layer can serve as a barrier layer to protect the ith layer of the epitaxial pillar of the second conductivity type from being etched.

In one possible embodiment, the etching at least one Ai deep trench on the wafer by the deep trench etching process includes:

when i is more than or equal to 2, forming a light resistance required by Ai deep groove etching, wherein the opening of the light resistance is more than that of the (i-1) th layer of the epitaxial column with the first conductivity type;

and etching the wafer by a deep trench etching process based on the photoresist to obtain at least one Ai deep trench.

In this embodiment, there are two types of photoresists, including positive photoresist (positive photoresist) and negative photoresist (negative photoresist), and the light irradiated portion of the positive photoresist is dissolved in the photoresist developer, while the light non-irradiated portion is not dissolved in the photoresist developer; negative photoresist portions that are exposed to light are not dissolved in the photoresist developer, while portions that are not exposed to light are dissolved in the photoresist developer. The whole photoresist layer can be covered firstly, then the photoresist required by Ai deep groove etching is formed through development, then at least one Ai deep groove can be obtained on the wafer through deep groove etching technology according to the photoresist pattern, and when the photoresist required by Ai deep groove etching is formed, the opening of the photoresist is larger than that of the i-1 st layer epitaxial column of the first conduction type, so that the Ai deep groove etching can be conveniently carried out on the i-1 st layer epitaxial column of the first conduction type. It should be noted here that when i =1, the opening of the photoresist required for forming the Ai deep trench etching is a preset value.

For example, taking the wafer including the semiconductor substrate and the epitaxial layer as an example for description, assuming that the first conductivity type is P-type and the second conductivity type is N-type, fig. 4 is a schematic flow chart of each step in a method for manufacturing a super junction semiconductor device according to an embodiment of the disclosure; the method for manufacturing the super junction semiconductor device comprises the following steps:

step 401, as shown in a diagram a in fig. 4, performing step S201, etching on the N-type epitaxial layer 41 by a deep trench etching process to obtain at least one A1 deep trench, and filling the A1 deep trench with a concentration of N _A1 The P-type epitaxial material of (1) forms a layer 1P-type epitaxial pillar, i.e., P1 pillar 42; forming a silicon oxide thin layer 43 on the surface of the P1 column in a thermal oxidation mode, and then forming a photoresist 44 required by N-type deep groove etching;

thermal oxidation, as used herein, refers to a process in which silicon chemically reacts with gases containing oxidizing species, such as water vapor and oxygen, at high temperatures to produce a dense silicon dioxide (SiO 2) film on the surface of the wafer. There are two types of photoresist, including positive photoresist (positive photoresist) and negative photoresist (negative photoresist), where the light irradiated part of the positive photoresist is dissolved in the photoresist developer, and the light non-irradiated part is not dissolved in the photoresist developer; negative photoresist portions that are exposed to light are not dissolved in the photoresist developer, while portions that are not exposed to light are dissolved in the photoresist developer. A full layer of photoresist may be applied and then developed to form the pattern required for N-type deep trench etch, i.e., the pattern of photoresist 44 required for N-type deep trench etch.

Step 402, as shown in fig. 4B, performing step S202, etching on the N-type epitaxial layer by a deep trench etching process to obtain at least one D1 deep trench, i.e., an N-type deep trench, and filling the D1 deep trench with a concentration of N _D1 The N-type epitaxial material of (1) forms the 1 st layer of epitaxial pillars of the second conductivity type, i.e., N1 pillars 45; the D1 deep trench is located between adjacent P1 pillars 42;

the etching here refers to actually transferring the developed photoresist to the material under the photoresist to form a pattern defined by the photolithography technique, i.e. as shown in fig. 4B, the uncovered portion of the photoresist 44 required for etching the N-type deep trench is etched, usually, the etching includes dry etching and wet etching, the deep trench etching process in the present disclosure is a dry etching process, and the dry etching process generally refers to an etching technique for performing pattern transfer (pattern transfer) by using glow discharge (glow discharge) to generate plasma containing charged particles such as ions and electrons and neutral atoms, molecules and radicals with high chemical activity.

Because the silicon oxide has a high etching selection ratio to silicon, when the D1 deep trench is etched, the silicon oxide thin layer on the surface of the P1 column can be used as a barrier layer to protect the P1 column from being etched, the etching depth of the D1 deep trench is required to be consistent with that of the A1 deep trench, and the filling concentration is N _D1 The N-type epitaxial layer material of (1) forms N1 pillars. It should be noted that, in order to better protect the P1 pillar from being etched when the D1 deep trench is etched, as shown in a diagram B in fig. 4, a predetermined space is formed between the etched D1 deep trench and the A1 deep trench.

In step 403, as shown in fig. 4C, a thin silicon oxide layer 46 is formed on the surface of the N1 pillar 45 by thermal oxidation, and then a photoresist 47 required for A2 deep trench etching is formed.

As shown in fig. 4C, when forming the photoresist 47 required for the A2 deep trench etching, the opening of the photoresist 47 is larger than the opening of the P1 pillar, so that the A2 deep trench etching can be conveniently performed.

Step 404, as shown in fig. 4D, continuing with step S201, etching the previously filled P1 pillar to a predetermined depth (the thickness of the etched P1 pillar is left 5 to 10 um) by A2 deep trench etching, and then filling the pillar with a concentration of N _A2 The P-type epitaxial layer of (2) forms a layer of P-type epitaxial column (P2 column 48); a thin silicon oxide layer 49 is formed on the surface of the P2 pillar by thermal oxidation.

Step 405, as shown in E of fig. 4, proceeds to step 202, and the same process is used to etch the N1 pillar to the same remaining thickness as the P1 pillar, and the filling concentration is N _D2 The N-type epitaxial material of (2) forms a layer 2 of epitaxial pillars of the second conductivity type, i.e., N2 pillars 410;

step 406, as shown in fig. 4F, the same process is used to cyclically perform steps S201 to S202, and the filling and etching of the Pi column and the Ni column are performed, so that the P-type epitaxial column, i.e., the first epitaxial column 31, and the N-type epitaxial column, i.e., the second epitaxial column 32, formed in this way are respectively composed of 5 epitaxial layers with the same thickness but different concentrations.

In a possible embodiment, the above preparation method may further include the steps of:

In this embodiment, the annealing process refers to a heat treatment process of slowly heating to a certain temperature, maintaining for a sufficient time, and then cooling at a suitable rate.

In this embodiment, the epitaxial layer may be grown using an epitaxial layer growth process, which refers to a process of growing a single crystal layer having a complete crystal lattice and may have different impurity concentrations and thicknesses on one single crystal wafer along its original direction of the crystal axis by using the principle of two-dimensional structural similarity nucleation on the crystal interface. The epitaxial growth process includes vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, etc., and the vapor phase epitaxy process is commonly used at present.

Still taking the above example as an example, the second conductivity type is N type, and an N type epitaxial layer may be generated on the upper surface of the N + substrate.

In one possible embodiment, when the wafer includes a low-doped high-resistance wafer of the second conductivity type, the method may further include:

after the A1 deep groove and the D1 deep groove are formed, second conduction type groove injection is carried out, and a super junction field stop layer is formed;

and implanting the first conductive type on the surface, forming a first conductive type body region at the first epitaxial pillar, and forming a field limiting ring at the terminal region.

In this embodiment, the implantation refers to ion implantation.

In this embodiment, the electric field decay gradient is proportional to the charge concentration according to the poisson equation, so a higher concentration of the superjunction field stop layer, which may also be referred to as a buffer layer, enables the electric field to decay rapidly and stop at this layer, preventing the depletion region from expanding to the back surface of the device and causing punch-through.

For example, taking the wafer as an N-low doped high resistance wafer as an example for description, assuming that the first conductivity type is P-type and the second conductivity type is N-type, fig. 5 is a schematic flow chart of steps in a method for manufacturing a super junction semiconductor device according to an embodiment of the disclosure; the method for manufacturing the super junction semiconductor device comprises the following steps:

step 501, as shown in a diagram in fig. 5, performing step S201, etching on the N-low-doped high-resistance wafer 51 by a deep trench etching process to obtain at least one A1 deep trench, performing N-type trench injection at the bottom of the A1 deep trench, and forming a part of the super junction field stop layer 52 below the A1 deep trench; filling N into the A1 deep groove _A1 The P-type epitaxial material of (1) forms a layer of P-type epitaxial pillars, i.e., P1 pillars 53; forming a silicon oxide thin layer 54 on the surface of the P1 column in a thermal oxidation mode, and then forming a photoresist 55 required by N-type deep groove etching;

step 502, as shown in fig. 5B, performing step S202, etching on the N-low doped high-resistance wafer 51 by a deep trench etching process to obtain at least one D1 deep trench, i.e., an N-type deep trench, performing N-type trench injection at the bottom of the D1 deep trench to form another part of super junction field stop layer 56, and forming the super junction field stop layer together with the part of super junction field stop layer below the A1 deep trench; filling N into the D1 deep groove _D1 The layer 1 epitaxial column of the second conductivity type, i.e., N1 column 57, is formed of the N-type epitaxial material; the D1 deep groove is positioned between the adjacent P1 columns;

because the silicon oxide has a high etching selection ratio to silicon, when the D1 deep trench is etched, the silicon oxide thin layer on the surface of the P1 column can be used as a barrier layer to protect the P1 column from being etched, the etching depth of the D1 deep trench is required to be consistent with that of the A1 deep trench, and the filling concentration is N _D1 The N-type epitaxial layer material of (1) forms N1 pillars. It should be noted that, in order to better protect the P1 pillar from being etched when the D1 deep trench is etched, as shown in a diagram B in fig. 5, a predetermined interval is formed between the etched D1 deep trench and the A1 deep trench.

Step 503, as shown in fig. 5C, forming a silicon oxide thin layer 58 on the surface of the N1 pillar 57 by thermal oxidation, and then forming a photoresist 59 required by the A2 deep trench etching, wherein the opening of the photoresist 59 is larger than that of the P1 pillar;

step 505, as shown in a diagram D in fig. 5, continuing with step S201, etching the previously filled P1 pillar to a predetermined depth (the thickness of the etched P1 pillar is remained 5 to 10 um) by a deep trench A2 etching, and then filling the pillar with a filling concentration of N _A2 The P-type epitaxial layer of (2) forms a layer of 2P-type epitaxial pillars, i.e., P2 pillars 510; a thin silicon oxide layer 511 is formed on the surface of the P2 pillar 510 by thermal oxidation.

Step 505, as shown in E of fig. 5, proceed to step S202, etch the N1 pillar to the same residual thickness as the P1 pillar by the same process method as above, and fill the N1 pillar with a concentration N _D2 The N-type epitaxial material of (2) forms a layer 2 epitaxial pillar of the second conductivity type, i.e., N2 pillar 512;

step 506, as shown in fig. F of fig. 5, the same process is adopted to cyclically perform steps S201 to S202, and the filling and etching of the Pi column and the Ni column are performed, so that the P-type epitaxial column, i.e., the first epitaxial column 31, and the N-type epitaxial column, i.e., the second epitaxial column 32, are respectively composed of 5 epitaxial layers with the same thickness but different concentrations.

Fig. 6 shows a partial step flow schematic diagram in a method of manufacturing a superjunction semiconductor device according to an embodiment of the present disclosure; after the above steps are performed to form the P-type epitaxial pillar and the N-type epitaxial pillar, a surface process and a back process are required, and a main process flow is shown in fig. 6 and includes the following steps:

step 407, as shown in a of fig. 6, performing a surface process, and performing P-type implantation on the surface to form a P body region 61 and a terminal field limiting ring 62; and performing thermal oxidation on the surface of the N-type epitaxial pillar to form a gate oxide layer 63, and then performing polysilicon deposition to form a polysilicon gate layer 64, so as to form a surface MIS (Metal-Insulator-Semiconductor) structure.

In a possible embodiment, after the above steps are performed, a back surface process is further performed, and the method may further include the following steps:

and performing second conductive type injection and laser annealing on the back of the low-doped high-resistance wafer to form a second conductive type substrate.

In this embodiment, still taking the N-low-doped high-resistance wafer as an example for explanation, as shown in a diagram B in fig. 6, a back surface process is performed, and the thickness of the low-doped high-resistance wafer is reduced to a preset thickness through a back surface reduction process, for example, the thickness of the entire wafer is 50 to 70um, and the low-doped high-resistance wafer can be reduced from the back surface to the vicinity of the super junction field stop layer; an N-type implant is then performed on the backside and laser annealing is performed to form an N + substrate 65. The N-type implantation refers to implanting N-type material by ion implantation, and the N-type material refers to material mainly conducting electrons.

In the embodiment, the back thinning process is an important semiconductor manufacturing process, and aims to remove redundant materials on the back of a wafer so as to effectively reduce the packaging volume of the wafer, reduce the thermal resistance, improve the heat dissipation performance of a device, reduce the risk of cracking of a packaged chip due to uneven heating and improve the reliability of a product; meanwhile, the mechanical property and the electrical property of the thinned chip are also obviously improved. The back thinning process has many kinds, such as grinding, polishing, dry polishing, electrochemical etching, wet etching, plasma-assisted chemical etching, atmospheric plasma etching, etc. Among them, the grinding thinning technique is a thinning technique with high efficiency and low cost, and has been widely used, and the technique realizes wafer thinning by rotating, pressing, damaging, breaking and removing a grinding wheel on the surface of a wafer.

In one possible embodiment, the back-side process may also be the following steps:

In this embodiment, the Super Junction semiconductor device may be a SJ-IGBT (Super Junction Insulated Gate Bipolar Transistor) device, and the back surface process is different from the above process in that the thickness of the low-doped high-resistance wafer is reduced to a preset thickness by a back surface reduction process, for example, the thickness of the entire wafer is 50 to 70um, and the low-doped high-resistance wafer can be reduced from the back surface to the vicinity of the Super Junction field stop layer; and then carrying out P-type implantation on the back and carrying out laser annealing to form a P + substrate. The P-type implantation refers to implanting P-type material by ion implantation, and the N-type material refers to material mainly conducting holes.

Still taking the above example as an example, a P-type implantation may be performed at the P-type epitaxial pillar to form a P-body region, a thermal oxidation may be performed on the surface of the N-type epitaxial pillar to form a gate oxide layer, and then a polysilicon deposition may be performed to form a polysilicon gate layer. Illustratively, as shown in a of fig. 6, a gate oxide layer 63 is formed on the surface of the N-type epitaxial pillar by thermal oxidation, and then a polysilicon gate layer 64 is formed by polysilicon deposition, thereby forming a surface MIS structure.

forming a first conductivity type body region at the first epitaxial pillar;

In this embodiment, a P-type implantation may be performed at the P-type epitaxial pillar to form a P-body region, a trench etching may be performed on the upper end of the surface of the N-type epitaxial pillar, a thermal oxidation may be performed to form a trench gate oxide layer, and a polysilicon deposition may be performed on the trench of the trench gate oxide layer to form a trench polysilicon gate layer, thereby forming a trench MIS structure.

In a possible implementation manner, the range of values of the gap between the adjacent Ai deep trench and the adjacent Di deep trench includes that the gap is greater than 0 and less than or equal to 0.05um; the two types of deep grooves can be etched conveniently without mutual influence.

In a possible embodiment, the electric field intensity at the central axis of any first epitaxial pillar forms an inflection point at the intersection of any two adjacent first epitaxial layers, the central axis passing through the geometric center of the transverse cross section of the first epitaxial pillar and extending along the longitudinal direction, the transverse direction is a direction parallel to the surface of the wafer, and the longitudinal direction is a direction perpendicular to the surface of the wafer. Due to charge balance in the super junction structure, the electric field intensity at the central axis of any one second epitaxial column can form an inflection point at the junction of any two adjacent second epitaxial layers.

The first epitaxial column and the second epitaxial column in the super junction semiconductor device comprise a plurality of sections of epitaxial layers and can be formed by multiple times of groove filling, and the depth-to-width ratio is smaller and smaller in the multiple times of groove filling processes, so that the problem of cavities generated by single epitaxial filling of the traditional deep groove can be solved; moreover, when the device is reversely broken down, an inflection point is formed at the junction of any two adjacent first epitaxial layers by the electric field intensity at the longitudinal central axis of the first epitaxial column, triangular wave electric field distribution can be formed, and compared with the parabolic electric field distribution formed by the traditional single epitaxial layer with the same concentration, the breakdown voltage of the super-junction semiconductor device disclosed by the invention is less influenced by the fluctuation of epitaxial filling concentration and has a larger process window.

In a possible embodiment, in order to form the triangular wave electric field distribution, the first epitaxial column includes M sections of first epitaxial layers with different doping concentrations, and the second epitaxial column includes M sections of second epitaxial layers with different doping concentrations; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di And meeting a preset condition to enable the super-junction structure to reach charge balance.

In one possible embodiment, when M is an even number, N is an odd number if i is an odd number in order to form the triangular wave electric field distribution described above _Ai >N _Di If i is an even number, then N _Ai <N _Di 。

In this embodiment, assuming that M is 4, N _A1 >N _D1 ，N _A2 <N _D2 ，N _A3 >N _D3 ，N _A4 <N _D4 。

In one possible embodiment, when M is an odd number, the triangular wave electric field distribution is formed, and if i = (M + 1)/2, N is _Ai =N _Di If i is an odd number and is smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di 。

For example, assuming M is 5, then N _A1 >N _D1 ，N _A2 <N _D2 ，N _A3 =N _D3 ，N _A4 >N _D4 ，N _A5 <N _D5 。

In a possible embodiment, in order to satisfy the charge balance condition, the widths of the first epitaxial column and the second epitaxial column are the same, the thicknesses of each first epitaxial layer and each second epitaxial layer are the same, and the doping concentration is such that when N is equal _Ai Is not equal to N _Di When, | N _A1 -N _D1 |=|N _A2 -N _D2 |=……=|N _AM -N _DM |<2e12/W; wherein W is the firstA width of an epitaxial pillar or the second epitaxial pillar.

In one possible embodiment, the doping concentration N _Ai And the doping concentration N _Di The value range of (1) is 1e15 to 1e17cm ^-3 . The doping concentration is used to represent the number of doped impurity atoms in the host in units of doping atoms per cubic centimeter.

The performances of the superjunction semiconductor device with the epitaxial layers with different doping concentrations and the superjunction semiconductor device with the existing single epitaxial layer with the same concentration are compared and tested as follows:

fig. 7A shows an effective doping concentration distribution and an electric field distribution diagram of an electric field intensity at a central axis of the second epitaxial column along a depth direction of the second epitaxial column, an x-coordinate in fig. 7A is a depth of the second epitaxial column 32 along a depth direction AA' of the second epitaxial column 32, and a y 1-coordinate is an effective doping concentration N _Ai -N _Di And y2 is the electric field intensity at the longitudinal central axis of the second epitaxial column, assuming that the first epitaxial column 31 in the superjunction semiconductor device provided by the present disclosure has M =5 segments of the first epitaxial layer, the second epitaxial column 32 has M =5 segments of the second epitaxial layer, and N is the electric field intensity at the longitudinal central axis of the second epitaxial column _A1 >N _D1 ，N _A2 <N _D2 ，N _A3 =N _D3 ，N _A4 >N _D4 ，N _A5 <N _D5 Then effective doping concentration N _Ai -N _Di That is, as shown by a pulse broken line 701 in fig. 7A, based on the poisson equation, it can be obtained that the change of the electric field intensity at the longitudinal central axis of the second epitaxial pillar 32 along the depth direction of the second epitaxial pillar, that is, the AA 'direction, is shown as a triangular wave broken line 702 in fig. 7A, while the effective doping concentration of the conventional superjunction semiconductor device shown in fig. 1 is a straight line, due to the influence of the trench angle, the change of the electric field intensity at the central axis of the first epitaxial pillar of the superjunction semiconductor device shown in fig. 1 along the AA' direction is shown as a curve 703 in fig. 7A, and the longitudinal central axis of the second epitaxial pillar 32 formed by the multiple sections of the second epitaxial layers with different doping concentrations can form a triangular wave electric field distribution shown in fig. 7A, which will be formed at the junctions of any two adjacent first epitaxial layers, that is, a1, a2, a3 and a4An inflection point is formed (it should be noted here that a triangular wave electric field distribution is formed along the depth direction of the first epitaxial pillar 31 at the longitudinal central axis of the first epitaxial pillar 31 formed by the first epitaxial layers with different doping concentrations in multiple stages, and the shape is symmetrical to the curve 702). Compared with the existing super-junction semiconductor device formed by single epitaxial columns with the same concentration and capable of generating parabolic electric field distribution, the breakdown voltage of the super-junction semiconductor device is less affected by fluctuation of epitaxial filling concentration, and the super-junction semiconductor device has a larger process window.

The following are illustrated by specific examples:

in a specific example, the super-junction semiconductor device is an even-segment-doped super-junction semiconductor device, wherein M =2, a first epitaxial column in the even-segment-doped super-junction semiconductor device is a P-type epitaxial column (also called P column), a second epitaxial column is an N-type epitaxial column, and M =2,N _A1 =3.99e15cm ^-3 <N _D1 =4.2e15cm ^-3 ，N _A2 =4.2e15cm ^-3 >N _D2 =3.99e15cm ^-3 ，W=4.5um，|N _A1 -N _D1 |*W=|N _A2 -N _D2 |*W<2e12; the doping concentration N of the P-type epitaxial column in the uniformly doped super junction semiconductor device _A Doping concentration N of N-type epitaxial column _D Wherein, N is _A =N _D =4.2e15cm ^-3 . The uniformly doped superjunction semiconductor device and the even-segment doped superjunction semiconductor device are compared as follows:

fig. 7B shows an electric field distribution schematic diagram of electric field intensity at the longitudinal central axis of the N-type epitaxial pillar of the even-segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device along the depth direction of the N-type epitaxial pillar, as shown in fig. 7B, the electric field distribution at the longitudinal central axis of the N-type epitaxial pillar of the uniformly doped superjunction semiconductor device is parabolic distribution with a downward opening, and when M =2, the electric field intensity at the longitudinal central axis of the N-type epitaxial pillar of the even-segment doped superjunction semiconductor device forms an inflection point at the boundary of the two epitaxial layers, i.e., at the B1 position in fig. 7B, and the overall electric field distribution is triangular wave distribution, and the peak of the triangular wave is located at the boundary of the two epitaxial layers, i.e., at the B1 position in fig. 7B.

Meanwhile, fig. 7C shows a variation curve of breakdown voltages of the super junction semiconductor device doped in the even number segment and the super junction semiconductor device doped uniformly with the P-type epitaxial column concentration. As can be seen from fig. 7C, when the target value of the breakdown voltage is 600V, in the conventional uniformly doped super junction semiconductor device, when the doping concentration of the P-type epitaxial pillar can be changed within a range from-3% to 3% based on the original doping concentration, the breakdown voltage meets the requirement; in the super-junction semiconductor device doped with the even sections, when the doping concentration of the P-type epitaxial column can be changed within the range of-8% to 6% on the basis of the original doping concentration, the breakdown voltage meets the requirement, and the super-junction semiconductor device doped with the even sections has a larger device process manufacturing window under the condition that the breakdown voltage meets the requirement.

In another specific example, the super-junction semiconductor device is an odd-segment-doped super-junction semiconductor device, and M =3, in the odd-segment-doped super-junction semiconductor device, the first epitaxial column is a P-type epitaxial column (also called P-column), the second epitaxial column is an N-type epitaxial column, and N is an N-type epitaxial column _A1 =4.1e15cm ^-3 <N _D1 =4.3e15cm ^-3 ，N _A2 =4.2e15cm ^-3 =N _D2 =4.2e15cm ^-3 ，N _A3 =4.3e15cm ^-3 >N _D1 =4.1e15cm ^-3 ，W=4.5um，|N _A1 -N _D1 |*W=|N _A3 -N _D3 |*W<2e12; the doping concentration N of the P-type epitaxial column in the uniformly doped super junction semiconductor device _A Doping concentration N of N-type epitaxial column _D Wherein N is _A =N _D =4.2e15cm ^-3 . The uniformly doped superjunction semiconductor device and the odd-segment doped superjunction semiconductor device are compared as follows:

fig. 7D shows an electric field distribution diagram of electric field intensity at the longitudinal central axis of the N-type epitaxial pillar of the super junction semiconductor device doped with odd number segments and the super junction semiconductor device doped with uniform number segments along the depth direction of the N-type epitaxial pillar, as shown in fig. 7D, the electric field distribution at the longitudinal central axis of the N-type epitaxial pillar of the super junction semiconductor device doped with uniform number segments is a parabolic distribution with an opening facing downward, and when M =3, the super junction semiconductor device doped with odd number segments is outside the N-typeThe electric field intensity at the longitudinal central axis of the epitaxial pillar forms an inflection point at the junction of two epitaxial layers, i.e., the positions D1 and D2 in fig. 7D, the electric field distribution of the region where each two adjacent epitaxial layers are located is in triangular wave distribution, i.e., the electric field intensity of the region where the two epitaxial layers are located at the junction at the position D1 is as the left side of D1 in fig. 7D and the electric field intensity variation curve between D1 and D2, the electric field intensity of the region where the two epitaxial layers are located at the junction at the position D2 is as the right side of D2 in fig. 7D and the electric field intensity variation curve between D1 and D2, both the electric field intensity variation curves are triangular wave curves, and the peak value of the triangular wave is located at the junctions of two epitaxial layers, i.e., the positions D1 and D2 in fig. 7D. Here, it should be noted that N is _A2 =N _D2 Therefore, the electric field intensity distribution at the longitudinal central axis corresponding to the region where the second epitaxial layer is located (i.e., the region between the d1 position and the d2 position) is relatively gentle and almost a straight line.

Meanwhile, fig. 7E shows a variation curve of breakdown voltages of the super junction semiconductor device doped with odd-numbered segments and the super junction semiconductor device doped with uniform segments as a function of the concentration of the P-type epitaxial pillar. As shown in fig. 7E, when the target value of the breakdown voltage is 600V, in the conventional uniformly doped super junction semiconductor device, when the doping concentration of the P-type epitaxial column can be changed in a range from-3% to 3% based on the original doping concentration, the breakdown voltage meets the requirement; in the super-junction semiconductor device doped with the odd-numbered sections, when the doping concentration of the P-type epitaxial column can be changed within the range of-10% to 6% on the basis of the original doping concentration, the breakdown voltage meets the requirement, and the super-junction semiconductor device doped with the odd-numbered sections has a larger device process manufacturing window under the condition that the breakdown voltage meets the requirement.

The present disclosure also provides a super junction semiconductor device that can be prepared by the above-described preparation method, and as shown in fig. 3, may include a wafer 20 and a super junction type structure 30. The super junction structure 30 is formed in the wafer 20, and includes at least one first epitaxial pillar 31 of a first conductivity type and at least one second epitaxial pillar 32 of a second conductivity type, where the first epitaxial pillar 31 and the second epitaxial pillar 32 are arranged laterally and alternately, and the lateral direction is a direction parallel to the surface of the wafer, so that the super junction structure 30 can be formed.

The first epitaxial column 31 includes M segments of the first epitaxial layer 311, and the second epitaxial column 32 includes M segments of the second epitaxial layer 321, where the first conductivity type is opposite to the second conductivity type, one is mainly electron conduction, and the other is mainly hole conduction. Illustratively, when the first conductivity type is N-type (i.e., predominantly electrons participating in conduction), the second conductivity type is P-type (i.e., predominantly holes participating in conduction); or, when the first conductivity type is P-type, the second conductivity type is N-type. M is an integer greater than or equal to 2; optionally, the value range of M may be 2 to 10, for example, M in fig. 3 takes a value of 4.

Technical terms and technical features related to the present embodiment are the same as or similar to those of the technical terms and technical features shown in fig. 2 to 7E and mentioned in the related embodiments, and for explanation and explanation of the technical terms and technical features related to the related embodiments of the present embodiment, reference may be made to the above explanation of the related embodiments shown in fig. 2 to 7E, and no further description is provided here.

The present disclosure also provides a superjunction semiconductor device, which may include a wafer 20 and a superjunction type structure 30, as shown in fig. 3.

In one possible embodiment of the present disclosure, the wafer 20 is a silicon wafer used for manufacturing silicon semiconductor circuits, the raw material of which is silicon, high-purity polysilicon is dissolved and doped into a silicon crystal seed, and then slowly pulled out to form a cylindrical single crystal silicon, and a silicon crystal rod is ground, polished and sliced to form a silicon wafer, i.e., a wafer.

In one possible implementation of the present disclosure, fig. 8 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure; fig. 9 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure. The wafer may include a semiconductor substrate 21 and an epitaxial layer 22 as shown in fig. 8, the wafer preparation includes two main links of substrate preparation and epitaxial process, the substrate (substrate) is a wafer made of semiconductor single crystal material, and the substrate may directly enter the wafer manufacturing link to produce a semiconductor device, or may be processed by an epitaxial process to produce an epitaxial wafer. Epitaxy (epitaxiy) refers to a process of growing a new single crystal on a carefully processed single crystal substrate, such as cut, ground, polished, etc., where the new single crystal may be the same material as the substrate or a different material (homoepitaxy or heteroepitaxy). The new monocrystalline layer is grown as a crystal phase extension of the substrate and is called an epitaxial layer (thickness is usually several micrometers, taking silicon as an example: silicon epitaxial growth means that a layer of crystal with good lattice structural integrity with resistivity different from thickness in the same crystal orientation as the substrate is grown on a silicon monocrystalline substrate with a certain crystal orientation), and the substrate on which the epitaxial layer is grown is called an epitaxial wafer (epitaxial wafer = epitaxial layer + substrate). Device fabrication is typically spread out over the epitaxial layers.

In one possible embodiment of the present disclosure, the wafer may also be a lightly doped high resistance wafer 23 such as an FZ (Float Zone) wafer, as shown in fig. 9. Doping (doping) in the present disclosure is a process of introducing impurities to a pure intrinsic semiconductor in a semiconductor manufacturing process to change its electrical properties, the introduced impurities being related to the kind of semiconductor to be manufactured, there are mainly two common doping techniques of the semiconductor, the first being a technique of introducing a doping gas into a high temperature furnace in which a silicon wafer is placed, and diffusing the impurities into the silicon wafer, by high temperature (thermal) diffusion; the second method is an ion implantation method, i.e. ions to be doped are injected into the material in the form of ion beams through the acceleration and guidance of an ion implanter, the ion beams and atoms or molecules in the material generate a series of physicochemical reactions, and the injected ions gradually lose energy and cause the surface composition, structure and performance of the material to change, and finally stay in the material. The intrinsic semiconductor is doped to form an impurity semiconductor with better conductivity, and can be generally divided into an N-type semiconductor and a P-type semiconductor due to different conductivity types, for example, 1 free electron can be generated by doping 1 phosphorus atom in the intrinsic semiconductor, while the number of holes generated by intrinsic excitation is unchanged. Thus, in the phosphorus-doped semiconductor, the number of free electrons far exceeds the number of holes, and the electrons become majority carriers (hereinafter referred to as "majority carriers"), and the holes become minority carriers (hereinafter referred to as "minority carriers"). Obviously, the main electron involved in the conduction is electron, so this semiconductor is called electron type semiconductor, N type semiconductor for short, and this doping is also called N type doping. When a certain amount of boron atoms are doped, the number of holes in the semiconductor is far larger than that of intrinsic excited electrons, so that the holes become majority carriers, and the electrons become minority carriers. Obviously, the main part participating in the conduction is holes, so the semiconductor is called a hole type semiconductor, called a P type semiconductor for short, and the doping is also called P type doping.

In the embodiment, the super junction structure is composed of a P-type doped columnar region and an N-type doped columnar region, and when the number of charges in the P-type doped region is equal to that in the N-type doped region, so as to achieve balance, the super junction effect is optimal, and the balance relationship between the withstand voltage and the on-resistance is optimal.

In one possible embodiment of the present disclosure, as shown in fig. 3, a super junction structure 30 is formed in the wafer 20, and includes at least one first epitaxial pillar 31 of a first conductivity type and at least one second epitaxial pillar 32 of a second conductivity type, where the first epitaxial pillar 31 and the second epitaxial pillar 32 are arranged alternately in a lateral direction, which is a direction parallel to a surface of the wafer, so that the super junction structure 30 can be formed.

In one possible embodiment of the present disclosure, as shown in fig. 3, the first epitaxial pillar 31 includes M segments of the first epitaxial layer 311, and the second epitaxial pillar 32 includes M segments of the second epitaxial layer 321, where the first conductivity type is opposite to the second conductivity type, one is mainly electron conductive and the other is mainly hole conductive. Illustratively, when the first conductivity type is N-type (i.e., predominantly electrons participating in conduction), the second conductivity type is P-type (i.e., predominantly holes participating in conduction); or, when the first conductivity type is P-type, the second conductivity type is N-type. M is an integer greater than or equal to 2; optionally, the value range of M may be 2 to 10, for example, M in fig. 3 takes a value of 4.

In one possible embodiment of the present disclosure, the first epitaxial pillar 31 includes M sections of first epitaxial layers 311 with different doping concentrations, and the second epitaxial pillar 32 includes M sections of second epitaxial layers 321 with different doping concentrations; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers 311 _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers 321 _Di And meeting a preset condition to enable the super-junction structure to reach charge balance.

In a possible embodiment of the present disclosure, if M is an even number, N is an odd number _Ai >N _Di If i is an even number, then N _Ai <N _Di . Illustratively, as shown in FIG. 3, if M is 4, then N _A1 >N _D1 ，N _A2 <N _D2 ，N _A3 >N _D3 ，N _A4 <N _D4 。

The first epitaxial column and the second epitaxial column in the super junction structure comprise a plurality of sections of epitaxial layers with different doping concentrations, and the doping concentration N of the ith section of the first epitaxial layer in the M section of the first epitaxial layer _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di Different and satisfies that if i is an odd number, N is _Ai >N _Di If i is an even number, then N _Ai <N _Di (ii) a Therefore, when the device is subjected to reverse breakdown, compared with the traditional epitaxial column with the same doping concentration, the breakdown voltage is less influenced by the fluctuation of the doping concentration of the epitaxial column, namely under the condition that the breakdown voltages meet the requirement, the even-numbered epitaxial layer can have a larger fluctuation range and a larger process window.

In a possible embodiment of the present disclosure, if i = (M + 1)/2, then N is given when M is an odd number _Ai =N _Di If i is an odd number and is smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is smaller than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, thenN _Ai >N _Di 。

The first epitaxial column and the second epitaxial column in the super junction structure comprise a plurality of sections of epitaxial layers with different doping concentrations, and the doping concentration N of the ith section of the first epitaxial layer in the M sections of the first epitaxial layer _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di Different and satisfies that if i is an odd number, N is _Ai >N _Di If i is an even number, then N _Ai <N _Di (ii) a Therefore, when the device is subjected to reverse breakdown, compared with the traditional epitaxial column with the same doping concentration, the breakdown voltage is less influenced by the fluctuation of the doping concentration of the epitaxial column, namely under the condition that the breakdown voltage meets the requirement, the doping concentration of the odd-numbered epitaxial layers can have a larger fluctuation range and a larger process window.

In a possible embodiment, in order to satisfy the charge balance condition, the widths of the first epitaxial column and the second epitaxial column are the same, the thicknesses of each first epitaxial layer and each second epitaxial layer are the same, and the doping concentration is such that when N is equal _Ai Is not equal to N _Di When, | N _A1 -N _D1 |=|N _A2 -N _D2 |=……=|N _AM -N _DM |<2e12/W; wherein W is a width of the first or second epitaxial pillar.

In one possible embodiment, as shown in fig. 8, the wafer comprises: a semiconductor substrate 21 of a second conductivity type; and an epitaxial layer 22 of a second conductivity type deposited on the semiconductor substrate 21, wherein the super junction structure 30 is formed in the epitaxial layer 22 of the second conductivity type.

For example, when the second conductivity type is N-type, the semiconductor substrate may be an N + substrate, N + represents a high concentration N-type doping, and the epitaxial layer may be an N-epitaxial layer. The material of the substrate may be other wide bandgap semiconductor materials such as GaN (gallium nitride), siC (silicon carbide), etc.

In one possible embodiment, as shown in fig. 9, the wafer 20 includes a low-doped high-resistance wafer 23 of the second conductivity type; the super junction semiconductor device further includes:

a super junction Field Stop (Field Stop) layer 28 located below the super junction type structure in the wafer; for example, as shown in fig. 9, the second conductivity type is N-type, and the super junction field stop layer may be formed by N-type implantation. Of course, if the second conductivity type is P-type, the super junction field stop layer may be formed by P-type implantation, where implantation refers to ion implantation.

And the super junction terminal structure 29 is positioned at the edge of the super junction semiconductor device.

The super junction termination structure 29 may include termination structures such as field limiting rings, field plates, lateral variable doping (VLD) and Junction Termination Extension (JTE), and preferably, as shown in fig. 9, the super junction termination structure 29 may include field limiting rings.

In one possible embodiment, as shown in fig. 9, a substrate 24 is disposed under the low-doped high-resistance wafer of the second conductivity type, and the substrate 24 may be a substrate of the second conductivity type, or when the super-junction semiconductor device is an SJ-IGBT device, the substrate 24 may be a substrate of the first conductivity type.

In one possible embodiment, as shown in fig. 8 and 9, the superjunction semiconductor device further includes: a first conductivity type body region 25, a gate oxide layer 26, and a polysilicon gate layer 27.

As shown in fig. 8 or 9, the first conductivity-type body region 25 is formed at the surface of the super junction-type structure, and the first conductivity-type body region 25 may be formed by implanting the first conductivity-type into the surface of the first epitaxial pillar. The gate oxide layer 26 is positioned on the upper surface of the second epitaxial pillar; the polysilicon gate layer 27 is located on the upper surface of the gate oxide layer 26, thus forming a surface MIS structure.

For example, the process of manufacturing the superjunction semiconductor device shown in fig. 8 may include:

growing an epitaxial layer 22 of the second conductivity type on an upper surface of a semiconductor substrate 21 of the second conductivity type;

through steps S201 to S203, forming a super junction structure 30 on the epitaxial layer 22, where the super junction structure 30 includes at least one first epitaxial pillar of a first conductivity type and at least one second epitaxial pillar of a second conductivity type, the first epitaxial pillar and the second epitaxial pillar are laterally and alternately arranged, the first epitaxial pillar includes M sections of first epitaxial layers with different doping concentrations, the second epitaxial pillar includes M sections of second epitaxial layers with different doping concentrations, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2;

a first conductivity type body region 25 is formed at the first epitaxial pillar and a gate oxide layer 26 and a polysilicon gate layer 27 are formed at the surface of the second epitaxial pillar.

For example, the process of manufacturing the superjunction semiconductor device shown in fig. 9 may include:

through steps S501 to S506, forming a super junction structure 30 on the low-doped high-resistance wafer 23, and forming a super junction field stop layer 28 below the super junction structure, where the super junction structure 30 includes at least one first epitaxial pillar of a first conductivity type and at least one second epitaxial pillar of a second conductivity type, the first epitaxial pillar and the second epitaxial pillar are laterally and alternately arranged, the first epitaxial pillar includes M first epitaxial layers with different doping concentrations, the second epitaxial pillar includes M second epitaxial layers with different doping concentrations, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2;

performing a surface process, performing first conductivity type injection on the surface, forming a first conductivity type body region 25 at the first epitaxial pillar, and forming a super junction terminal structure 29, namely a field limiting ring, at the terminal region; forming a gate oxide layer 26 and a polysilicon gate layer 27 on the surface of the second epitaxial pillar;

performing a back face process, and thinning the thickness of the low-doped high-resistance wafer to a preset thickness through a back face thinning process; and performing second conductivity type injection and laser annealing on the back of the low-doped high-resistance wafer to form a substrate 24 of the second conductivity type.

In one possible implementation, fig. 10 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure, and as shown in fig. 10, the superjunction semiconductor device further includes: a first conductivity type body region 25, a trench gate oxide layer 210, and a trench polysilicon gate layer 211.

The super junction semiconductor device may be an SGT (Shielded Gate trench) device in which the first conductivity type body region 25 is formed at the surface of the super junction type structure, and the first conductivity type body region 25 may be formed by performing implantation of the first conductivity type at the surface of the first epitaxial pillar, as shown in fig. 10. The trench gate oxide layer 210 is groove-shaped and is positioned in a groove at the upper end of the second epitaxial pillar; and the groove polycrystalline silicon gate layer 211 is positioned in the groove of the groove gate oxide layer 210, so that a groove MIS structure is formed.

For example, the process of manufacturing the superjunction semiconductor device shown in fig. 10 may include:

through steps S501 to S506, a super junction structure 30 is formed on the low-doped high-resistance wafer 23, and a super junction field stop layer 28 is formed below the super junction structure; the super junction structure 30 comprises at least one first epitaxial column of a first conductivity type and at least one second epitaxial column of a second conductivity type, wherein the first epitaxial column and the second epitaxial column are transversely and alternately arranged, the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2;

performing a surface process, forming a first conductive type body region 25 at the first epitaxial pillar, forming a super junction terminal structure 29, namely a field limiting ring, at the terminal region, performing trench etching and thermal oxidation at the upper end of the second epitaxial pillar to form a trench-shaped trench gate oxide layer 210, and then performing polysilicon deposition to form a trench polysilicon gate layer 211;

performing a back face process, and thinning the thickness of the low-doped high-resistance wafer to a preset thickness through a back face thinning process; performing second conductive type injection and laser annealing on the back of the low-doped high-resistance wafer to form a substrate 24 of a second conductive type;

The present disclosure also provides a superjunction semiconductor device, which may include a wafer 20 and a superjunction-type structure 30, as shown in fig. 3.

In this embodiment, the super junction structure is composed of a P-type doped columnar region and an N-type doped columnar region, and when the amount of charges in the P-type doped region is equal to the amount of charges in the N-type doped region, so as to achieve balance, the super junction effect is optimal, and the balance relationship between the withstand voltage and the on-resistance is optimal, so in this embodiment, the charges in the super junction structure are balanced.

In one possible embodiment of the present disclosure, as shown in fig. 3, a super junction structure 30 is formed in the wafer 20, and includes at least one first epitaxial pillar 31 of a first conductivity type and at least one second epitaxial pillar 32 of a second conductivity type, where the first epitaxial pillar 31 and the second epitaxial pillar 32 are laterally arranged alternately, so as to form the super junction structure 30.

In one possible embodiment of the present disclosure, as shown in fig. 3, the first epitaxial pillar 31 includes M segments of the first epitaxial layer 311, and the second epitaxial pillar 32 includes M segments of the second epitaxial layer 321, where the first conductivity type is opposite to the second conductivity type, one is mainly electron conductive, and the other is mainly hole conductive. Illustratively, when the first conductivity type is N-type (i.e., predominantly electrons participating in conduction), the second conductivity type is P-type (i.e., predominantly holes participating in conduction); or, when the first conductivity type is P-type, the second conductivity type is N-type. M is an integer greater than or equal to 2; optionally, the value range of M may be 2 to 10, and for example, M in fig. 3 is 4.

In a possible embodiment of the present disclosure, the electric field intensity at the central axis of any first epitaxial pillar forms an inflection point at the intersection of any two adjacent first epitaxial layers, the central axis passes through the geometric center of the transverse cross section of the first epitaxial pillar and extends along the longitudinal direction, the transverse direction is a direction parallel to the surface of the wafer, and the longitudinal direction is a direction perpendicular to the surface of the wafer. Due to charge balance in the super junction structure, the electric field intensity at the central axis of any one second epitaxial column can form an inflection point at the junction of any two adjacent second epitaxial layers.

For example, as shown in fig. 7A, the variation of the electric field strength at the longitudinal central axis of the second epitaxial pillar 32 along the depth direction of the second epitaxial pillar, i.e., the AA 'direction, is shown as a triangular wave broken line 702 in fig. 7A, while the effective doping concentration of the superjunction semiconductor device shown in fig. 1 is a straight line, due to the influence of the trench angle, the variation of the electric field strength at the central axis of the first epitaxial pillar of the superjunction semiconductor device shown in fig. 1 along the AA' direction is shown as a curve 703 in fig. 7A, and the longitudinal central axis of the second epitaxial pillar 32 formed by the multiple segments of second epitaxial layers with different doping concentrations can form a triangular wave electric field distribution shown in fig. 7A, which also forms a corner point at the boundary of any two adjacent first epitaxial layers, i.e., at a1, a2, a3 and a4 (it should be noted here that the shape of the triangular wave electric field distribution is symmetrical to the curve 702 at the longitudinal central axis of the first epitaxial pillar 31 formed by the multiple segments of first epitaxial layers with different doping concentrations along the depth direction of the first epitaxial pillar 31). Compared with the existing super-junction semiconductor device formed by single epitaxial columns with the same concentration and capable of generating parabolic electric field distribution, the breakdown voltage of the super-junction semiconductor device is less affected by fluctuation of epitaxial filling concentration, and the super-junction semiconductor device has a larger process window.

In one possible embodiment, in order to form the triangular wave electric field distribution, the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, and the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di And meeting a preset condition to enable the super-junction structure to reach charge balance.

In a possible embodiment, in the case where M is an even number, if i is an odd number, then N is _Ai >N _Di If i is an even number, then N _Ai <N _Di (ii) a For example, assuming M is 4, then N _A1 >N _D1 ，N _A2 <N _D2 ，N _A3 >N _D3 ，N _A4 <N _D4 。

For example, as shown in fig. 7B, the electric field distribution at the longitudinal central axis of the N-type epitaxial pillar of the uniformly doped superjunction semiconductor device is a parabolic distribution with a downward opening, and when M =2, the electric field intensity at the longitudinal central axis of the N-type epitaxial pillar of the even-numbered super junction semiconductor device forms an inflection point at the boundary of the two epitaxial layers, i.e., at the B1 position in fig. 7B, and the overall electric field distribution is in a triangular wave distribution, and the peak of the triangular wave is located at the boundary of the two epitaxial layers, i.e., at the B1 position in fig. 7B. As shown in fig. 7C, when the target value of the breakdown voltage is 600V, in the conventional uniformly doped super junction semiconductor device, when the doping concentration of the P-type epitaxial pillar can be changed within a range from-3% to 3% based on the original doping concentration, the breakdown voltage meets the requirement; when the doping concentration of the P-type epitaxial column of the super-junction semiconductor device doped in the even sections can be changed within the range of-8% to 6% on the basis of the original doping concentration, the breakdown voltage meets the requirement, and the super-junction semiconductor device doped in the even sections has a larger device process manufacturing window under the condition that the breakdown voltage meets the requirement.

In one possible embodiment, in the case where M is an odd number, if i = (M + 1)/2, then N _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is an odd number and is greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di . Assuming that M is 5, N _A1 >N _D1 ，N _A2 <N _D2 ，N _A3 =N _D3 ，N _A4 >N _D4 ，N _A5 <N _D5 。

For example, as shown in fig. 7D, the electric field distribution at the longitudinal central axis of the N-type epitaxial column of the uniformly doped super junction semiconductor device is a parabolic distribution with an opening facing downward, and when M =3, the electric field intensity of the odd-numbered stage doped super junction semiconductor device at the longitudinal central axis of the N-type epitaxial column is in two stages of epitaxial columnsInflection points are formed at the junctions of the layers, namely D1 and D2 in fig. 7D, the electric field distribution of the region where each two adjacent epitaxial layers are located is triangular wave distribution, namely, the electric field intensity of the region where the two epitaxial layers which are bounded at the D1 position are located is as shown in the left side of D1 and the electric field intensity change curve between D1 and D2 in fig. 7D, the electric field intensity of the region where the two epitaxial layers which are bounded at the D2 position are located is as shown in the right side of D2 and the electric field intensity change curve between D1 and D2 in fig. 7D, the two electric field intensity change curves are triangular wave curves, and the peak value of the triangular wave is located at the pairwise junction of the two epitaxial layers, namely at the D1 and D2 positions in fig. 7D. Here, it should be noted that N is a number _A2 =N _D2 Therefore, the electric field intensity distribution at the longitudinal central axis corresponding to the region where the second epitaxial layer is located (i.e., the region between the d1 position and the d2 position) is relatively gentle and almost a straight line. As shown in fig. 7E, when the target value of the breakdown voltage is 600V, in the conventional uniformly doped super junction semiconductor device, when the doping concentration of the P-type epitaxial pillar can be changed within a range from-3% to 3% based on the original doping concentration, the breakdown voltage meets the requirement; in the super-junction semiconductor device doped with the odd-numbered sections, when the doping concentration of the P-type epitaxial column can be changed within the range of-10% to 6% on the basis of the original doping concentration, the breakdown voltage meets the requirement, and the super-junction semiconductor device doped with the odd-numbered sections has a larger device process manufacturing window under the condition that the breakdown voltage meets the requirement.

In one possible embodiment, to satisfy the charge balance condition, the first epitaxial pillar and the second epitaxial pillar are provided with a plurality of holesThe width of each epitaxial column is the same, the thickness of each first epitaxial layer and the thickness of each second epitaxial layer are the same, and the doping concentration is satisfied when N is _Ai Is not equal to N _Di When, | N _A1 -N _D1 |=|N _A2 -N _D2 |=……=|N _AM -N _DM |<2e12/W; wherein W is a width of the first or second epitaxial pillar.

In one possible embodiment, the doping concentration N _Ai And the doping concentration N _Di The value range of (1) is 1e15 to 1e17cm ^-3 . The doping concentration is used to indicate the number of doped impurity atoms in the host, and the unit is the number of doped atoms per cubic centimeter.

In one possible embodiment, as shown in fig. 8, the wafer comprises: a semiconductor substrate 21 of a second conductivity type; and an epitaxial layer 22 of the second conductivity type deposited on the semiconductor substrate 21, wherein the super junction structure 30 is formed in the epitaxial layer 22 of the second conductivity type.

For example, when the second conductivity type is N-type, the semiconductor substrate may be an N + substrate, N + represents a high concentration N-type doping, and the epitaxial layer may be an N epitaxial layer. The material of the substrate may be other wide bandgap semiconductor materials such as GaN (gallium nitride), siC (silicon carbide), etc.

a superjunction Field Stop (Field Stop) layer 28 located below the superjunction structure in the wafer; for example, as shown in fig. 9, if the second conductivity type is N-type, the super junction field stop layer may be formed by N-type implantation. Of course, if the second conductivity type is P-type, the super junction field stop layer may be formed by P-type implantation, where implantation refers to ion implantation.

As shown in fig. 8 or 9, the first conductivity type body region 25 is formed at the surface of the super junction structure, and the first conductivity type body region 25 may be formed by performing implantation of the first conductivity type at the surface of the first epitaxial pillar. The gate oxide layer 26 is positioned on the upper surface of the second epitaxial pillar; the polysilicon gate layer 27 is located on the upper surface of the gate oxide layer 26, thus forming a surface MIS structure.

The super junction semiconductor device may be an SGT device, in which the first conductivity type body region 25 is formed at the surface of the super junction type structure, and the first conductivity type body region 25 may be formed by performing first conductivity type implantation at the surface of the first epitaxial pillar, as shown in fig. 10. The trench gate oxide layer 210 is groove-shaped and is positioned in a groove at the upper end of the second epitaxial pillar; and the groove polysilicon gate layer 211 is positioned in the groove of the groove gate oxide layer 210, so that a groove MIS structure is formed.

It should be noted here that, with reference to the method described in fig. 2 to fig. 6 in the above embodiment, the superjunction semiconductor device provided by the present disclosure may be formed by multiple trench etching and filling, and in the multiple trench filling process, the aspect ratio is smaller and smaller, which may solve the problem of voids generated by single epitaxial filling of the conventional deep trench, and compared with multiple epitaxial processes, the cost is lower, and the lateral diffusion of the epitaxial pillar is smaller, the cell pitch may be smaller, and the doping concentration of each epitaxial pillar is also easier to control.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is possible without departing from the inventive concept. For example, the above features and (but not limited to) the features disclosed in this disclosure having similar functions are replaced with each other to form the technical solution.

Claims

1. A method for manufacturing a super junction semiconductor device is characterized by comprising the following steps:

step 1: etching a first preset area of a wafer through a deep groove etching process to obtain at least one Ai deep groove, wherein the Ai deep groove is filled with doping concentration N _Ai The first epitaxial layer forms the ith epitaxial column of the first conductivity type;

step 2: etching a second preset area of the wafer through a deep groove etching process to obtain at least one Di deep groove, and filling the Di deep groove with the doping concentration of N _Di Forming an ith epitaxial column of the second conductivity type on the second epitaxial layer; the Di deep groove is positioned between the epitaxial columns of the ith layer of the first conduction type;

circularly performing the step 1 and the step 2 until i = M, so as to obtain a first epitaxial column and a second epitaxial column, wherein the first epitaxial column comprises M sections of first epitaxial layers, and the second epitaxial column comprises M sections of second epitaxial layers; the value of i is 1 to M, M is an integer greater than or equal to 2, and the depth of the Ai deep groove is gradually reduced and the depth of the Di deep groove is also gradually reduced along with the increase of i;

in the case that M is oddIf i = (M + 1)/2, then N _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di 。

2. The method of claim 1, further comprising:

3. The method of claim 1, wherein etching the at least one Ai deep trench in the first predetermined area of the wafer by a deep trench etching process comprises:

and etching the first preset area of the wafer by a deep groove etching process based on the light resistance to obtain at least one Ai deep groove.

4. The method of claim 1, further comprising:

and enabling the first epitaxial column and the second epitaxial column to be in contact by adopting an annealing process.

5. The method of claim 1, wherein when the wafer comprises a semiconductor substrate and an epitaxial layer, the method comprises:

6. The method of claim 1, wherein the wafer comprises a low-doped, high-resistance wafer of a second conductivity type, the method further comprising:

after the A1 deep groove and the D1 deep groove are obtained through etching, second conduction type groove injection is carried out, and a super junction field stop layer is formed;

and implanting a first conductive type into the wafer and the surface of the super junction structure, forming a first conductive type body region at the first epitaxial column, and forming a field limiting ring at the terminal region.

7. The method of claim 6, further comprising:

8. The method of claim 6, further comprising:

9. The method according to any one of claims 5 to 8, further comprising:

10. The method of any of claims 6 to 8, further comprising:

forming a first conductivity type body region at the first epitaxial pillar;

11. The method of claim 1, wherein a range of values of a gap between adjacent Ai deep trenches and Di deep trenches comprises greater than 0 and less than or equal to 0.05um.

12. The method of claim 1,

13. The method of claim 12,

the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, and the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations; doping concentration N of ith first epitaxial layer in M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di The super-junction structure can reach charge balance by meeting the preset condition.

14. The method of claim 13, wherein if i is odd, then N is even if M is even greater than 2 _Ai >N _Di If i is an even number, then N _Ai <N _Di 。

15. The method of claim 14,

the first epitaxial pillar and the second epitaxial pillar are the same in width.

16. The method of claim 1,

the width of the first epitaxial column or the second epitaxial column ranges from 1 um to 6um.

17. The method of claim 15,

the thickness of each section of the first epitaxial layer is the same as that of each section of the second epitaxial layer.

18. The method of claim 1, wherein the thickness of each first epitaxial layer and each second epitaxial layer ranges from 5 to 10um.

20. The method according to claim 1, wherein the value of M ranges from 2 to 10.

21. The method of claim 1,

the first conduction type is an N type, and the second conduction type is a P type;

or, the first conductivity type is a P type, and the second conductivity type is an N type.

22. The method of claim 1, wherein the doping concentration N is _Ai And doping concentration N _Di The value range of (1) is 1e15 to 1e17cm ^-3 。

23. A superjunction semiconductor device comprising a superjunction semiconductor device fabricated by applying the method of any of claims 1 to 22, the superjunction semiconductor device comprising:

a wafer;

24. A super junction semiconductor device, comprising:

a wafer;

wherein, the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di The super junction structure can reach charge balance by meeting the preset condition; in the case where M is an even number greater than 2, if i is an odd number, N is _Ai >N _Di If i is an even number, then N _Ai <N _Di (ii) a If i = (M + 1)/2, if M is an odd number, then N is _Ai =N _Di If i is odd and smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i isEven number greater than (M + 1)/2, then N _Ai >N _Di 。

25. The superjunction semiconductor device of claim 24,

26. The superjunction semiconductor device of claim 25,

28. The superjunction semiconductor device of claim 24,

29. The super-junction semiconductor device according to claim 24, wherein the thickness of each of the first epitaxial layer and the second epitaxial layer ranges from 5 to 10um.

30. The super-junction semiconductor device according to claim 24, wherein the value range of M is 2 to 10.

31. The superjunction semiconductor device of claim 24, wherein the wafer comprises:

a semiconductor substrate of a second conductivity type;

and the super junction structure is formed in the epitaxial layer of the second conduction type.

32. The superjunction semiconductor device of claim 24, wherein the wafer comprises a low-doped high-resistance wafer of the second conductivity type; the super junction semiconductor device further includes:

33. The superjunction semiconductor device of claim 32, wherein the superjunction termination structure comprises a field limiting ring.

34. The superjunction semiconductor device of claim 32, further comprising:

35. The superjunction semiconductor device of claim 32, further comprising:

36. The superjunction semiconductor device of any one of claims 31 to 35, further comprising:

a gate oxide layer on an upper surface of the second epitaxial pillar;

37. The superjunction semiconductor device of any one of claims 32 to 35, further comprising:

38. The superjunction semiconductor device of claim 24,

39. The superjunction semiconductor device of claim 24, wherein a doping concentration N _Ai And doping concentration N _Di The value range of (1) is 1e15 to 1e17cm ^-3 。

40. A super junction semiconductor device, comprising:

a wafer;

the super junction type structure is formed in the wafer and comprises at least one first epitaxial column of a first conductivity type and at least one second epitaxial column of a second conductivity type, the first epitaxial column and the second epitaxial column are transversely and alternately arranged, the first epitaxial column comprises M sections of first epitaxial layers, the second epitaxial column comprises M sections of second epitaxial layers corresponding to the first epitaxial layers, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2;

the electric field intensity of the central axis of any first epitaxial column forms an inflection point at the junction of any two adjacent first epitaxial layers, the central axis passes through the geometric center of the transverse section of the first epitaxial column and extends along the longitudinal direction, the transverse direction is parallel to the surface of the wafer, and the longitudinal direction is perpendicular to the surface of the wafer; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai And the ith section of the M section of second epitaxial layerDoping concentration N of the epitaxial layer _Di Satisfies the following conditions: if i = (M + 1)/2, if M is an odd number, then N is _Ai =N _Di If i is an odd number and is smaller than (M + 1)/2, then N _Ai >N _Di If i is an even number and is less than (M + 1)/2, then N _Ai <N _Di If i is odd and greater than (M + 1)/2, then N _Ai <N _Di If i is an even number and is greater than (M + 1)/2, then N _Ai >N _Di 。

41. The super-junction semiconductor device according to claim 40,

the first epitaxial column comprises M sections of first epitaxial layers with different doping concentrations, and the second epitaxial column comprises M sections of second epitaxial layers with different doping concentrations; the doping concentration N of the ith first epitaxial layer in the M first epitaxial layers _Ai The doping concentration N of the ith second epitaxial layer in the M second epitaxial layers _Di And meeting the preset condition to ensure that the super junction structure achieves charge balance.

42. The super-junction semiconductor device according to claim 41, wherein in the case where M is an even number greater than 2, if i is an odd number, then N is _Ai >N _Di If i is an even number, then N _Ai <N _Di 。

43. The superjunction semiconductor device of claim 42,

44. The super-junction semiconductor device according to claim 43,

46. The superjunction semiconductor device of claim 40,

47. The super-junction semiconductor device according to claim 40, wherein the thickness of each first epitaxial layer and each second epitaxial layer ranges from 5um to 10um.

48. The super-junction semiconductor device according to claim 41, wherein the doping concentration N is _Ai And the doping concentration N _Di The value range of (1) is 1e15 to 1e17cm ^-3 。