CN117727772A - Silicon carbide super-junction MOSFET device and preparation method thereof - Google Patents
Silicon carbide super-junction MOSFET device and preparation method thereof Download PDFInfo
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- CN117727772A CN117727772A CN202311830957.4A CN202311830957A CN117727772A CN 117727772 A CN117727772 A CN 117727772A CN 202311830957 A CN202311830957 A CN 202311830957A CN 117727772 A CN117727772 A CN 117727772A
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 91
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 104
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 12
- 238000000407 epitaxy Methods 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 9
- -1 aluminum ions Chemical class 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 238000011049 filling Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention discloses a silicon carbide super-junction MOSFET device and a preparation method thereof, wherein the silicon carbide super-junction MOSFET device comprises drain electrode metal, an N+ type silicon carbide substrate, an N type silicon carbide epitaxial layer, an N-type silicon carbide epitaxial layer, a P-type column region, a P-type body region, an N+ type source region, a P+ type source region, an interlayer insulating medium and source electrode metal, a longitudinal groove is arranged at one end of the N type silicon carbide epitaxial layer far away from the N+ type silicon carbide substrate, penetrates through the N-type silicon carbide epitaxial layer and the P-type body region, the bottom extends to the N type silicon carbide epitaxial layer and is wrapped by the P-type column region, polysilicon is arranged in the groove, the surface of upper polysilicon is covered by the insulating medium, the lower polysilicon is wrapped by a shielding gate oxide layer, and all polysilicon is isolated by IPO. When the device is in a reverse voltage-resistant state, the trench gate is connected with zero potential or negative potential, the P-type column region and the N-type silicon carbide epitaxy are transversely exhausted, and the breakdown voltage is improved. The P-type column region can also protect the shielding gate oxide layer and improve the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, and particularly discloses a silicon carbide super-junction MOSFET device and a preparation method thereof
Background
Silicon carbide (SiC) materials have been attracting attention and research because of their superior physical properties, and the higher thermal conductivity of silicon carbide materials determines their high current density characteristics, and the higher forbidden band width determines the high breakdown field strength and high operating temperature of SiC devices. Although SiC MOSFETs have lower on-resistance than conventional Si-based MOSFETs, there is a problem in that on-resistance rises sharply with the 2.5 power of withstand voltage. The loss of the device is increased in a high-voltage working state, and the on-resistance of the device is reduced by adopting a super junction technology.
The super junction technology is a technology for achieving charge compensation and acting as a voltage-resistant layer by adopting an alternating P-type doped region and N-type doped region structure to simultaneously obtain low specific on-resistance and high voltage-resistant capability. Through super junction structural design and optimization, the conduction performance of the high-power silicon carbide device can be effectively improved on the premise of guaranteeing the blocking performance.
The existing silicon carbide super junction preparation technology is divided into multiple epitaxy and deep groove etching filling epitaxy, the time and material resource cost consumed by the multiple epitaxy technology is high, the production efficiency is low, and particularly for high-voltage application requiring a thick drift region, the steps of epitaxial growth, ion implantation and the like are required to be repeated. Multiple epitaxial growth and ion implantation are more prone to introducing defects. By etching trenches and then epitaxially growing to refill the epitaxial layer, the epitaxial filling method requires high growth temperatures, and also has high risks of void formation and non-uniform doping, severely affecting the reliability of the device.
Disclosure of Invention
In view of the above, the invention provides a silicon carbide super-junction MOSFET device and a preparation method thereof, which adopts a mode of ion oblique angle injection after deep groove etching, solves the problems of high labor cost in time of multiple epitaxy and defect introduction in multiple epitaxial growth in the prior art, and solves the problems of void filling and uneven doping of epitaxy after groove etching.
The specific technical scheme of the invention is as follows.
The silicon carbide superjunction MOSFET device specifically comprises drain metal and an N+ type silicon carbide substrate above the drain metal, wherein an N type silicon carbide epitaxial layer, an N-type silicon carbide epitaxial layer, a P-type column region, a P-type body region, an N+ type source region, a P+ type source region, an interlayer insulating medium and source metal are sequentially arranged above the N+ type silicon carbide substrate, a longitudinal groove is formed in one end, far away from the N+ type silicon carbide substrate, of the N type silicon carbide epitaxial layer, the longitudinal groove penetrates through the N-type silicon carbide epitaxial layer and the P-type body region, the lower end of the longitudinal groove extends to the N type silicon carbide epitaxial layer, and the bottom of the groove is covered by the P-type column region. Upper and lower discrete polysilicon isolated by IPO (inter-polysilicon oxide) is arranged in the longitudinal groove, wherein the upper surface of the upper polysilicon is covered by an interlayer insulating medium, the lower surface and the side surface are wrapped by a groove gate oxide, the left and right surfaces of the lower polysilicon are wrapped by a shielding gate oxide, and the lower surface is wrapped by a P-type column region; the sidewalls and bottom of each longitudinal trench are capped by a P-type pillar region that is connected to the source metal through the lower polysilicon.
The doping concentration of the N-type silicon carbide epitaxy is larger than that of the N-type silicon carbide epitaxy.
The P-type column region is connected with the source electrode metal through lower polysilicon.
The side wall and the bottom of the groove are covered by the P-type column region, and the lower polycrystal is connected with the source metal through a layout design connecting line.
In order to achieve the above purpose, the invention provides a preparation method of a silicon carbide super junction MOSFET, comprising the following steps:
step one: selecting an N-type substrate as a high-concentration N+ type drain electrode, and growing an N-type silicon carbide epitaxial layer;
step two: growing an N-type silicon carbide epitaxial layer on the top of the N-type silicon carbide epitaxial layer;
step three: forming a P-type body region by selectively injecting acceptor ions into the top of the N-type silicon carbide epitaxial layer by using a mask layer;
step four: selectively injecting donor and acceptor ions into the top of the N-type silicon carbide epitaxial layer by using a mask layer to form an N+ type source region and a P+ type source region;
step five: selectively etching a longitudinal groove on the top of the N-type epitaxial layer by using a mask layer, wherein the longitudinal groove penetrates through the N-type silicon carbide epitaxial layer and extends into the N-type silicon carbide epitaxial layer, and the side wall and the bottom of the longitudinal groove are covered by a P-type column region;
step six: injecting aluminum ions by using an oblique angle ion injection mode to form a P-type column region;
step seven: generating a groove side wall oxide layer (shielding gate oxide layer) by utilizing a high-temperature furnace tube thermal oxidation and low-pressure chemical vapor deposition mode, and etching the groove bottom oxide layer by utilizing a plasma etching mode;
step eight: filling P-type doped polysilicon in the trench, and selectively etching the P-type polysilicon and the oxide layer above the trench by using the mask layer to form a blank region above the trench;
step nine: nitrogen ions are injected by utilizing an oblique angle ion injection mode to form an N-type region
Step nine: forming an IPO dielectric layer on the upper surface of the P-type polycrystalline silicon by utilizing a high-density plasma vapor deposition technology;
step ten: growing a gate oxide layer
Step eleven: depositing N-type polysilicon, and grinding off the rest N-type polysilicon by using a chemical mechanical grinding technology;
step twelve: depositing an interlayer insulating medium on the upper surface of the N-type silicon carbide epitaxial layer, and selectively etching by using a mask layer and then depositing metal to form source metal; and depositing metal on the back surface to form drain metal.
The main advantages of the invention are as follows:
the invention provides a groove type silicon carbide MOSFET device and a preparation method thereof. The existence of the P-type column region can protect the shielding gate oxide layer and improve the reliability of the device.
When the device is in a reverse voltage-resistant state, the grid electrode is connected with zero potential or negative potential, and the P-type column region is connected with the source electrode through the lower polysilicon, so that the trench gate oxide layer and the shielding gate oxide layer can be protected, and the breakdown voltage of the device is improved. Meanwhile, the lateral depletion of the device can be increased by introducing the lower polysilicon structure and the P-type column region, so that N-type silicon carbide epitaxy with higher doping amount can be used, and the on-resistance of the device is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of an N-type silicon carbide formed by extension.
Fig. 2 is a schematic cross-sectional structure of an N-type silicon carbide epitaxial layer after formation.
Fig. 3 is a schematic cross-sectional structure after forming the P-type body region.
Fig. 4 is a schematic cross-sectional structure after forming an n+ source region.
Fig. 5 is a schematic cross-sectional structure after forming a p+ type source region.
Fig. 6 is a schematic cross-sectional view of the deep trench structure after formation.
Fig. 7 is a schematic cross-sectional structure after forming a P-type pillar region.
Fig. 8 is a schematic cross-sectional structure after forming a trench sidewall oxide layer.
FIG. 9 is a schematic cross-sectional view of the trench bottom oxide after etching away.
Fig. 10 is a schematic cross-sectional structure of a P-doped polysilicon after filling.
Fig. 11 is a schematic cross-sectional structure of the P-type polysilicon and a portion of the oxide layer over the trench after etching.
Fig. 12 is a schematic cross-sectional view of the N-type implant region after formation.
Fig. 13 is a schematic cross-sectional structure after forming an IPO dielectric layer.
FIG. 14 is a schematic cross-sectional view of a grown gate oxide, deposited N-type polysilicon, and polished to remove the top remaining silicon.
Fig. 15 is a schematic cross-sectional structure after forming an insulating medium, source and drain metals.
In the figure, a 01-N+ type silicon carbide substrate, a 02-N type silicon carbide epitaxial layer, a 03-N type silicon carbide epitaxial layer, a 04-P type body region, a 05-N+ type source region, a 06-P+ type source region, a 07-longitudinal groove, a 08-P type column region, a 09-shielding gate oxide layer, 10-lower polysilicon, 11-N type regions, 12-IPO, 13-groove gate oxide layer, 14-upper polysilicon, 15-interlayer insulating medium, 16-source metal and 17-drain metal.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to solve the problems in the prior art, the present invention provides a silicon carbide superjunction MOSFET, refer to fig. 15, which is a diagram of a final embodiment of a silicon carbide superjunction MOSFET device and a method for manufacturing the same.
In the embodiment, the trench is prepared by preparing a silicon carbide trench with the width of 1-3um, preparing a trench gate oxide layer and a shielding gate oxide layer on the side wall in the trench, removing the shielding gate oxide layer at the bottom of the trench by a dry plasma etching process, isolating upper and lower polysilicon by using an IPO dielectric layer, and connecting a P-type column region with source metal by using lower polysilicon. When the device is in a reverse voltage-resistant state, the P-type column region and the N-type silicon carbide epitaxy are transversely exhausted, so that the breakdown voltage of the device is improved. In addition, the existence of the P-type column region can protect the shielding gate oxide layer and improve the reliability of the device.
The invention provides a preparation method of a groove type silicon carbide MOSFET device, which comprises the following steps:
step one: selecting an N+ type substrate 01 as a high-concentration N type drain electrode, wherein the N+ type substrate 01 is made of a silicon carbide material, the silicon carbide substrate can be 4H-SiC, 6H-SiC or 3C-SiC and other materials, the most commonly used material is 4H-SiC, then epitaxially growing an N type silicon carbide epitaxial layer 02, and then cleaning an epitaxial wafer to obtain a device structure shown in figure 1;
step two: growing an N-type silicon carbide epitaxial layer 03 on the N silicon carbide epitaxial layer to obtain a device structure shown in figure 2;
step three: depositing a mask layer on the top of the N-type silicon carbide epitaxial layer 03, etching an ion implantation window through photoetching and etching processes, selectively implanting aluminum ions to form a P-type body region 04, and removing the mask layer to obtain a device structure shown in figure 3;
step four: a mask layer is deposited on the top of the N-type silicon carbide epitaxial layer 03, an ion implantation window is etched through photoetching and etching processes, nitrogen ions are selectively implanted to form an N+ type source region 05, and then the mask layer is removed. Obtaining a device structure as shown in fig. 4;
step five: depositing a mask layer on the top of the N-type silicon carbide epitaxial layer 03, etching an ion implantation window through a photoetching process and an etching process, selectively implanting aluminum ions to form a P+ type source region 06, and removing the mask plate to obtain a device structure shown in FIG. 5;
step six: depositing a mask layer on the top of the N-type silicon carbide epitaxial layer 03, etching a groove etching window through photoetching and etching processes, and etching a longitudinal groove 07 downwards by utilizing the characteristics of different plasma etching selectivity ratios to obtain a device structure shown in figure 6;
step seven: aluminum ions are implanted into the bottom and the side wall of the groove by utilizing an ion implantation mode to obtain the P-type column region 08. The ions are injected in two times: first 0 ° angle injection; and a second 4 DEG angle four quadrant injection. Finally, a device structure as shown in fig. 7 is obtained.
Step eight: first, a sacrificial oxide layer is grown in the longitudinal grooves 07, then the sacrificial oxide layer is removed, and then a shielding gate oxide layer 09 is grown by means of thermal oxygen growth and low-pressure chemical vapor deposition, so as to obtain the device structure shown in fig. 8.
Step nine: and removing an oxide layer at the bottom of the groove by a dry etching mode, carrying out annealing treatment after NRCA cleaning, and finally removing the mask layer to obtain the device structure shown in fig. 9.
Step ten: p-type polysilicon 10 is deposited within the longitudinal trenches 07 to result in the device structure shown in fig. 10.
Step eleven: removing the polysilicon on the surface through chemical mechanical polishing, and then removing part of the polysilicon and the oxide layer through dry etching and wet etching respectively to obtain a device structure shown in FIG. 11;
step twelve: forming an N-type doped region 11 by using oblique angle ion implantation to obtain a device structure shown in FIG. 12;
step thirteen: forming an IPO dielectric layer on the upper surface of the P-type polycrystalline silicon by utilizing a high-density plasma vapor deposition technology to obtain a device structure shown in FIG. 13;
step fourteen: growing a sacrificial oxide layer, removing the sacrificial oxide layer, growing a trench gate oxide layer 13 by a thermal oxidation growth mode, annealing, depositing a trench gate N-type polysilicon 14, removing redundant silicon dioxide and polysilicon on the surface of the N-type epitaxial layer 03, and forming a gate structure in the trench to obtain a device structure shown in figure 14;
fifteen steps: an insulating dielectric layer 15 is deposited on the surface of the N-type epitaxial layer 04, a metal contact hole is etched through a photoetching process, a source metal 16 is deposited, and a drain metal 17 is formed by depositing metal on the back surface, so that the device structure shown in fig. 15 is obtained.
Claims (9)
1. The trench type silicon carbide MOSFET device is characterized by comprising drain metal (17) and an N+ type silicon carbide substrate (01) above the drain metal (17), wherein an N type silicon carbide epitaxial layer (02), a P-type column region (08), an N-type silicon carbide epitaxial layer (03), a P-type body region (04), an N+ type source region (05), a P+ type source region (06), an interlayer insulating medium (15) and source metal (16) are sequentially arranged above the N+ type silicon carbide substrate (01), a longitudinal trench (07) is formed in one end, far away from the N+ type silicon carbide substrate (01), of the N-type silicon carbide epitaxial layer (03), the longitudinal trench (07) penetrates through the N-type silicon carbide epitaxial layer (03) and the P-type body region (04), the lower end of the longitudinal trench extends to the N-type silicon carbide epitaxial layer (02), and the side wall and the bottom of the trench are covered by the P-type column region; upper and lower discrete polysilicon isolated by IPO (12) are arranged in the longitudinal groove (07), wherein the upper surface of the upper polysilicon (14) is covered by an interlayer insulating medium (15), the side surface is wrapped by a groove gate oxide layer (13), the left and right surfaces of the lower polysilicon (10) are wrapped by a shielding gate oxide layer (09), and the lower surface is wrapped by a P-type column region; the sidewalls and bottom of each longitudinal trench are capped by a P-type pillar region (08) that is connected to the source metal by a lower polysilicon (10).
2. The silicon carbide superjunction MOSFET device according to claim 1, characterized in that the doping concentration of the N-type silicon carbide epitaxy (02) is greater than the doping concentration of the N-type silicon carbide epitaxy (03).
3. The silicon carbide superjunction MOSFET device according to claim 1, wherein the P-type pillar region (08) is connected to the source metal (16) by means of a lower polysilicon (10).
4. The silicon carbide superjunction MOSFET device of claim 1, wherein the trench sidewalls and bottom are capped with P-type pillar regions, and the lower poly is connected to the source metal by layout design lines.
5. The silicon carbide superjunction MOSFET device of claim 1, wherein the trench has a depth of 2-20 um.
6. The silicon carbide superjunction MOSFET device of claim 1, wherein the trench has a width of 1-3 um.
7. The silicon carbide superjunction MOSFET device of claim 1, wherein the shield gate oxide layer has a thickness of 0.3-0.8 um and the lower poly has a width of 0.4-2.4 um.
8. The silicon carbide superjunction MOSFET device of claim 2, wherein the P-type pillar region has a doping concentration substantially lower than the P-type body region.
9. A method of fabricating a silicon carbide superjunction MOSFET device according to any of claims 1-8, comprising the steps of:
step one: selecting an N-type substrate (01) as a high-concentration N+ type drain electrode, and growing an N-type silicon carbide epitaxial layer (02);
step two: growing an N-type silicon carbide epitaxial layer (03) on the top of the N-type silicon carbide epitaxial layer (02);
step three: forming a P-type body region (04) by selectively injecting acceptor ions into the top of the N-type silicon carbide epitaxial layer (03) by utilizing a mask layer;
step four: forming an N+ type source region (05) and a P+ type source region (06) by selectively injecting donor and acceptor ions into the top of the N-type silicon carbide epitaxial layer (03) through a mask layer;
step five: a longitudinal groove (07) is selectively etched on the top of the N-type epitaxial layer (03) by utilizing a mask layer, the longitudinal groove (07) penetrates through the N-type silicon carbide epitaxial layer (03) to extend into the N-type silicon carbide epitaxial layer (02), and the side wall and the bottom of the longitudinal groove (07) are coated by a P-type column region (08);
step six: aluminum ions are injected by utilizing an oblique angle ion injection mode to form a P-type column region (08);
step seven: generating a groove side wall oxide layer (shielding gate oxide layer) (09) by utilizing a high-temperature furnace tube thermal oxidation and low-pressure chemical vapor deposition mode, and etching the groove bottom oxide layer by utilizing a plasma etching mode;
step eight: p-type doped polysilicon (10) is filled in the groove, and the mask layer is utilized to selectively etch the P-type polysilicon and the oxide layer above the groove to form a blank area above the groove;
step nine: n-type region (11) is formed by implanting nitrogen ions by means of oblique angle ion implantation
Step nine: forming an IPO dielectric layer (12) on the upper surface of the P-type polycrystalline silicon (10) by utilizing a high-density plasma vapor deposition technology;
step ten: growing gate oxide layer (13)
Step eleven: depositing N-type polycrystalline silicon (14), and grinding off the rest N-type polycrystalline silicon by using a chemical mechanical grinding technology;
step twelve: depositing an interlayer insulating medium (15) on the upper surface of the N-type silicon carbide epitaxial layer (04), and forming a source metal (16) by depositing metal after selective etching by using a mask layer; a drain metal (17) is formed by depositing metal on the back side.
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| CN202311830957.4A CN117727772A (en) | 2023-12-28 | 2023-12-28 | Silicon carbide super-junction MOSFET device and preparation method thereof |
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| CN202311830957.4A CN117727772A (en) | 2023-12-28 | 2023-12-28 | Silicon carbide super-junction MOSFET device and preparation method thereof |
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