CN115966596B - Separation groove transverse double-diffusion power device and manufacturing method thereof - Google Patents
Separation groove transverse double-diffusion power device and manufacturing method thereof Download PDFInfo
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- CN115966596B CN115966596B CN202310234418.8A CN202310234418A CN115966596B CN 115966596 B CN115966596 B CN 115966596B CN 202310234418 A CN202310234418 A CN 202310234418A CN 115966596 B CN115966596 B CN 115966596B
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a separation groove transverse double-diffusion power device and a manufacturing method thereof, and belongs to the technical field of basic electric elements. The device comprises a semiconductor substrate and an active region which are sequentially overlapped from bottom to top; the active region comprises a semiconductor drain region, a semiconductor drift region and a semiconductor well region, wherein the semiconductor well region comprises a semiconductor source region and a semiconductor body contact region; etching separation grooves and grid grooves in the semiconductor drift region and the grid region active region, filling high-dielectric constant dielectric materials at the bottoms and the peripheries of the separation grooves and the grid grooves, filling the separation grooves with silicon dioxide, and simultaneously etching and depositing the separation grooves and the grid grooves; the drift region of the separation groove structure longitudinally expands the current conduction region and increases the modulation area of the high-dielectric constant medium, so that the doping concentration of the drift region is effectively improved; the groove-shaped gate MIS prepared by using the high-dielectric-constant dielectric material is increased in capacitance, the electron accumulation layer is increased in density, and the on-resistance of the device is reduced under the condition that the withstand voltage is unchanged.
Description
Technical Field
The invention relates to the technology of semiconductor power devices, in particular to a separation groove transverse double-diffusion power device and a manufacturing method thereof, belonging to the technical field of basic electric elements.
Background
The power semiconductor device is a core component of a power integrated circuit, and the transverse power device has the advantages of small volume, easy integration, large breakdown voltage, low on-resistance, high gain, excellent conversion performance, good process compatibility and the like, and is widely applied to radio frequency base stations, automobile electronics and intelligent furniture. The transverse power device is often accompanied with the increase of specific on-resistance while improving the breakdown voltage, and the contradictory relation is a key factor for limiting the application of the transverse power device in the high-voltage and high-current fields.
In order to relieve the contradiction relation between breakdown voltage and specific on-resistance, the technology of reducing the surface electric field, the super junction technology and the high-K dielectric technology are widely applied. In addition, trench technology has been of interest to many researchers and has achieved significant benefits in alleviating the problem of "silicon limiting". The groove type device is generally etched with grooves in the whole active region, various mediums are filled in the grooves, the drift region is folded to expand the current conduction region longitudinally, but the prior groove type device cannot fully excavate the grooves and the potential of the mediums in the grooves for modulating effects in the drift region; in addition, the trench device with the gate recess is relatively complex in process implementation due to the non-uniform gate recess depth and drift region recess depth.
In summary, the present invention is directed to a split-trench lateral double-diffused power device and a method for manufacturing the same, which overcome the defects of the conventional trench device.
Disclosure of Invention
The invention aims to overcome the defects of the background art, and provides a separation groove transverse double-diffusion power device and a manufacturing method thereof, wherein the separation groove transverse double-diffusion power device is provided with a drift region with a separation groove structure and a groove-shaped grid structure of a high dielectric constant grid medium, so that the aims of effectively improving the doping concentration of the drift region and reducing the on-resistance of the device by longitudinally expanding an electron accumulation layer of a current conduction region and a grid surface drift region are fulfilled, and the technical problems of poor medium modulation effect and complex multi-groove manufacturing process of the drift region of the conventional groove transverse double-diffusion power device are solved.
The invention adopts the following technical scheme for realizing the purposes of the invention: a separation groove transverse double-diffusion power device comprises a semiconductor substrate and an active region which are sequentially overlapped from bottom to top, a grid groove is formed in the active region of a grid region, a semiconductor drift region with at least two strip conductors is formed in the active region between a semiconductor well region and a drain region, a separation groove structure is formed by grooves between the at least two strip conductors, the depth of the grid groove is consistent with the depth of the separation groove structure, a semiconductor body contact region and a semiconductor source region are formed in the semiconductor well region, a semiconductor drain region is formed in the drain region, a first dielectric layer with high dielectric constant dielectric materials is deposited at the bottom and the periphery of the separation groove structure, the deposition thickness of the high dielectric constant dielectric materials in the separation groove structure is the same as the deposition thickness of the high dielectric constant dielectric materials in the grid groove, a second dielectric layer with insulating materials is deposited in the first dielectric layer of the separation groove structure, and metal is deposited on the surfaces of the first dielectric layer at the bottom and the periphery of the grid groove, the top of the semiconductor source region and the semiconductor body contact region, a grid electrode, a drain electrode and a drain electrode are formed at the top of the semiconductor source region and the semiconductor body contact region.
Further, the active region material of the separation groove transverse double-diffusion power device is silicon, but the active region material is not limited to silicon, silicon carbide, gallium nitride, gallium oxide and other wide-bandgap semiconductor materials.
Further, in the separation trench lateral double-diffusion power device, the width of each trench in the semiconductor drift region separation trench structure is the same and is a, the width of silicon between separation trenches is the same and is b, a and b are 1-5 micrometers, a: b= (5, 4, 3, 2) 1 or 1 (1, 2, 3, 4, 5).
Further, a first dielectric layer of the separation groove transverse double-diffusion power device is 0.1-0.5 microns, and a second dielectric layer medium is silicon dioxide.
Further, the separation groove structure of the separation groove transverse double-diffusion power device can be applied to not only bulk silicon devices, but also common transverse power devices such as IGBT (insulated gate bipolar transistor) devices, SOI (silicon on insulator) devices and the like.
A manufacturing method of a separation groove transverse double-diffusion power device comprises the following steps:
step 1: epitaxially doping a semiconductor of a first conductivity type on a semiconductor substrate to form an active region;
step 2: etching an active region of a gate region, an active region between a semiconductor well region and a drain region by using photoresist as a mask through a dry etching process, controlling the etching depth of the active region of the gate region to be consistent with that of the active region between the semiconductor well region and the drain region, forming a semiconductor drift region with at least two strip conductors in the active region between the semiconductor well region and the drain region, forming a transverse separation groove structure in a groove between the at least two strip conductors, and forming a longitudinal gate groove in the active region of the gate region;
step 3: using photoresist as a mask, and adopting an ion implantation process to implant second conductivity type impurities in an active region between the grid groove and the separation groove structure to form a second conductivity type well region, namely a semiconductor well region;
step 4: using photoresist as a mask, and adopting an ion implantation process to implant highly doped first conductivity type semiconductor impurities into the active regions of the semiconductor well region and the drain region to form a semiconductor source region and a semiconductor drain region;
step 5: using photoresist as a mask, and adopting an ion implantation process to implant highly doped second conductivity type semiconductor impurities into the semiconductor well region to form a semiconductor body contact region;
step 6: using photoresist as a mask, adopting magnetron sputtering deposition equipment to deposit high-dielectric-constant dielectric materials at the bottom and the periphery of the separation groove structure and at the bottom and the periphery of the grid groove, and controlling the thickness of the deposited high-dielectric-constant dielectric materials in the separation groove structure to be the same as the thickness of the deposited high-dielectric-constant dielectric materials in the grid groove to prepare a first dielectric layer;
step 7: taking photoresist as a mask, adopting chemical vapor deposition equipment, and filling silicon dioxide into a first dielectric layer deposited in a groove in a separation groove structure to prepare a second dielectric layer;
step 8: flattening the surface of the active region after the second dielectric layer is prepared in the step 7 by adopting chemical mechanical polishing;
step 9: and depositing metal on the surface of the first dielectric layer deposited at the bottom and the periphery of the grid groove, the top of the semiconductor source region and the semiconductor body contact region and the top of the semiconductor drain region by taking photoresist as a mask and adopting magnetron sputtering deposition equipment, and annealing to prepare a grid electrode, a source electrode and a drain electrode.
Further, in step 6 of a method for manufacturing a split-trench lateral double-diffusion power device, a layer of semiconductor oxide is oxidized in the split-trench structure and the gate recess as a buffer layer before the first dielectric layer is manufactured.
The invention adopts the technical scheme and has the following beneficial effects:
(1) According to the invention, the separation groove structure is prepared in the semiconductor drift region, the high-dielectric-constant dielectric material is filled at the bottom and the periphery of the separation groove to form the first dielectric layer, the insulating material is filled in the first dielectric layer in each groove of the separation groove, the manufacture of the drift region separation groove is completed, the current conduction region is expanded in the longitudinal direction of the device through the separation groove structure of the drift region, meanwhile, the modulation area of the high-dielectric-constant dielectric is increased, the doping concentration of the drift region is effectively increased, and the on-resistance of the device is reduced.
(2) The planar gate is prepared into the groove-shaped gate, the groove-shaped gate structure transfers the device channel to the longitudinal direction, so that the longitudinal electron accumulation layer is expanded, the gate dielectric is prepared by using a high-dielectric-constant dielectric material, MIS capacitance formed by the gate electrode, the gate oxide and the drift region is increased, the density of the electron accumulation layer is increased when the MIS capacitor is in an on state, and the on-state resistance of the device is reduced under the condition that the withstand voltage is unchanged.
(3) The depth of the grid groove of the transverse double-diffusion power device is consistent with the depth of the separation groove of the drift region, and the grid medium is prepared from the same material as the high dielectric constant medium in the drift region, so that the etching and deposition processes of the grid groove and the separation groove structure can be simultaneously carried out, and the process steps are greatly saved.
Drawings
Fig. 1 is a schematic structural diagram of a lateral double-diffusion power device with a separation groove.
Fig. 2 is a schematic diagram of a lateral double-diffused power device structure formed after an active region is epitaxially grown on a semiconductor substrate in process step 1 according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a lateral double-diffusion power device structure after a drift region separation groove and a gate groove are dry etched in a process step 2 according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a lateral double-diffusion power device structure after ion implantation is used to prepare a semiconductor well region, a semiconductor body contact region, a semiconductor source region, and a semiconductor drain region in steps 3 to 5 of the embodiment of the present invention.
Fig. 5 is a schematic diagram of a lateral double-diffused power device structure after a first dielectric layer is deposited in process step 6 according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a lateral double-diffused power device structure after a second dielectric layer is deposited in process step 7 according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a final structure of a lateral double-diffusion power device after preparing a gate electrode, a source electrode and a drain electrode by magnetron sputtering in step 9 according to an embodiment of the present invention.
Fig. 8 is a longitudinal cross-sectional view taken along line A1 of the final structure of the lateral double diffused power device shown in fig. 7.
Fig. 9 is a longitudinal cross-sectional view taken along line A2 of the final structure of the lateral double diffused power device shown in fig. 7.
Fig. 10 is a longitudinal cross-sectional view taken along line A3 of the final structure of the lateral double diffused power device shown in fig. 7.
Fig. 11 is a longitudinal cross-sectional view taken along line B1 of the final structure of the lateral double diffused power device shown in fig. 7.
Fig. 12 is a longitudinal cross-sectional view taken along line B2 of the final structure of the lateral double diffused power device of fig. 7.
Fig. 13 is a longitudinal cross-sectional view taken along line B3 of the final structure of the lateral double diffused power device of fig. 7.
Fig. 14 is a longitudinal cross-sectional view taken along line B4 of the final structure of the lateral double diffused power device of fig. 7.
Fig. 15 is a longitudinal cross-sectional view taken along line B5 of the final structure of the lateral double diffused power device of fig. 7.
Fig. 16 is a longitudinal cross-sectional view taken along line B6 of the final structure of the lateral double diffused power device of fig. 7.
Fig. 17 is a schematic diagram showing the concentration EAD distribution of the electron accumulation layer in the on state of the lateral double-diffusion power device according to the present invention.
Fig. 18 is a graph showing the breakdown voltage and specific on-resistance of a conventional lateral power device structure and a lateral double-diffused power device according to the present invention, which are related to the doping concentration of the drift region.
Fig. 19 is a graph comparing the FOM values of the conventional lateral power device structure and the lateral double-diffused power device according to the present invention with the doping concentration of the drift region.
The reference numerals in the figures illustrate: 1. the semiconductor device comprises a semiconductor substrate 2, an active region 3, a semiconductor drain region 4, a semiconductor drift region 51, a separation groove structure 52, a gate groove 6, a semiconductor body contact region 7, a semiconductor source region 8, a semiconductor well region 9, a first dielectric layer 10, a second dielectric layer 11, a gate electrode 12, a source electrode 13 and a drain electrode.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings.
In this embodiment, the silicon-based N-type drift region lateral double-diffusion power device is taken as an example to describe the separation groove lateral double-diffusion power device and the manufacturing method thereof in detail, and instead, the separation groove lateral double-diffusion power device and the manufacturing method thereof of the present invention can also be applied to various lateral power devices such as P-type drift region lateral double-diffusion power devices, SOI devices, IGBT devices, etc.
The invention provides a separation groove transverse double-diffusion power device, which is shown in figure 1, and comprises a semiconductor substrate 1 and an active region 2 which are sequentially stacked from bottom to top; the active region comprises a semiconductor drain region 3, a semiconductor drift region 4 and a semiconductor well region 8, wherein the semiconductor well region comprises a semiconductor source region 7 and a semiconductor body contact region 6; the semiconductor drift region comprises a separation groove structure 51, a first dielectric layer 9 with high dielectric constant dielectric materials deposited on the bottom and the periphery of the separation groove structure and the bottom and the periphery of a grid groove, and a second dielectric layer 10 with insulating materials deposited in the first dielectric layer of the groove in the separation groove structure; the grid electrode is positioned on the side surface of the semiconductor source region and provided with a grid electrode groove 52, and the grid dielectric is consistent with the first dielectric layer 9; the gate electrode 11 is arranged on the side surface and the top of the gate dielectric, the source electrode 12 and the drain electrode 13 are arranged on the top of the semiconductor active region, the source electrode is contacted with the semiconductor source region and the semiconductor body contact region, and the drain electrode is contacted with the semiconductor drain region.
The material of the semiconductor active region is silicon, but is not limited to silicon, silicon carbide, gallium nitride, gallium oxide and other wide bandgap semiconductor materials.
The semiconductor drift region separation groove structure comprises a plurality of grooves.
The width of each groove in the semiconductor drift region separation groove structure is the same as a, the width of silicon between separation grooves is the same as b, a and b are 1-5 microns, a is b= (5, 4, 3, 2) 1 or 1 (1, 2, 3, 4, 5).
The depth of the semiconductor drift region separation groove structure is consistent with the depth of the grid groove.
The first dielectric layer is a high dielectric constant dielectric, the gate dielectric and the first dielectric layer are identical, the thickness is also the same, the thickness is 0.1-0.5 microns, and the second dielectric layer is silicon dioxide.
Before preparing the first dielectric layer, a layer of semiconductor oxide is oxidized in the separation groove structure and the grid groove to serve as a buffer layer. The buffer layer can be arranged to enable the interface between the first dielectric layer and the drift region to have good contact effect, and silicon dioxide is preferentially selected for the buffer layer.
The number of grooves in the semiconductor drift region separation groove structure is 3-5, and the grooves can be automatically increased and reduced during layout drawing according to the size and performance requirements of the device. The width a of the separation groove and the silicon width b between the separation grooves are 1-5 microns, and a: b= (5, 4, 3, 2) is 1 or 1 (1, 2, 3, 4, 5). When designing, the layout linewidth is adjusted according to the requirement.
A manufacturing method of a separation groove transverse double-diffusion power device comprises the following 9 steps.
Step 1: an N-doped semiconductor is epitaxially formed on a semiconductor substrate 1 to form an active region 2, forming a lateral double diffused power device structure as shown in fig. 2.
Step 2: and etching the active region of the gate region, the active region between the semiconductor well region and the drain region by using the photoresist as a mask through a dry etching process, controlling the etching depth of the active region of the gate region to be consistent with that of the active region between the semiconductor well region and the drain region, forming a semiconductor drift region 4 with strip conductors in the active region between the semiconductor well region and the drain region, forming a transverse separation groove structure 51 by grooves among a plurality of strip conductors, forming a longitudinal gate groove 52 in the active region of the gate region while forming the separation groove structure 51, and forming a transverse double-diffusion power tube structure after the separation groove structure and the gate groove as shown in fig. 3.
In the embodiment, N-doped silicon is selected as an active region, the dry etching process is mature, the etching depth is convenient to control, and the etching anisotropy is good, so that dry etching is selected. If the active region is made of other semiconductor materials, an etching method is selected according to practical situations. The depth of the separation groove is consistent with that of the grid groove, so that the process step of independently etching the grid groove is not needed, the grid groove with the same depth can be etched while the separation groove structure is etched, and a large number of process steps are saved.
Step 3: and (3) taking the photoresist as a mask, and adopting an ion implantation process to implant P-type impurities in the active region between the grid groove and the separation groove structure to form a P-type well region, namely a semiconductor well region 8.
Step 4: and using photoresist as a mask, and adopting an ion implantation process to implant highly doped N-type semiconductor impurities into the semiconductor well region 8 and the active region of the drain region to form a semiconductor source region 7 and a semiconductor drain region 3.
Step 5: and taking the photoresist as a mask, and adopting an ion implantation process to implant highly doped P-type semiconductor impurities into the semiconductor well region 8 to form the semiconductor body contact region 6. The structure of the lateral double-diffusion power device after the formation of the semiconductor well region, the semiconductor body contact region, the semiconductor source region and the semiconductor drain region is shown in fig. 4.
Step 6: and preparing a first dielectric layer 9 by using photoresist as a mask and adopting magnetron sputtering deposition equipment to deposit high-dielectric-constant dielectric materials at the bottom and the periphery of the separation groove structure and at the bottom and the periphery of the grid groove, wherein the thickness of the deposited high-dielectric-constant dielectric materials in the separation groove structure is the same as that of the deposited high-dielectric-constant dielectric materials in the grid groove, and the transverse double-diffusion power device structure after the first dielectric layer is deposited is shown in figure 5.
Before preparing the first dielectric layer, a buffer layer is prepared, and silicon is selected as an active area in the embodiment, so that silicon dioxide is generated by adopting a thermal oxidation method to form the buffer layer. If the active region is prepared from other materials, a chemical vapor deposition method can be selected to deposit a buffer layer, and the buffer layer is preferably silicon dioxide, because the interface contact effect of the silicon dioxide and various semiconductor materials is good, the thickness of the buffer layer material is only 10 nanometers. The separation groove structure can increase the modulation area of the high-dielectric-constant medium, so that a good modulation effect can be achieved by only depositing a thin high-dielectric-constant medium. Simulation verification proves that the deposition thickness of the high-dielectric-constant dielectric material is selected to be 0.2-0.4 microns, and a good modulation effect can be achieved.
Step 7: and using photoresist as a mask, filling silicon dioxide into the first dielectric layer deposited in the groove in the separation groove structure by using chemical vapor deposition equipment to prepare a second dielectric layer 10, and forming the structure of the transverse double-diffusion power device after the second dielectric layer is deposited as shown in fig. 6.
Step 8: and (3) flattening the surface of the active region by adopting chemical mechanical polishing on the transverse double-diffusion power device structure after the second dielectric layer is prepared in the step (7).
Step 9: and (3) taking photoresist as a mask, adopting magnetron sputtering deposition equipment to deposit metal on the surface of a first dielectric layer deposited at the bottom and the periphery of a grid groove, the top of a semiconductor source region 7 and a semiconductor body contact region 6 and the top of a semiconductor drain region 3, and performing annealing treatment to prepare a grid electrode 11, a source electrode 12 and a drain electrode 13, wherein the final structure of the transverse double-diffusion power device after the grid electrode, the source electrode and the drain electrode are formed is shown in fig. 7, and the longitudinal sections of the final structure of the transverse double-diffusion power device shown in fig. 7 along the line A1, the line A2, the line A3, the line B1, the line B2, the line B3, the line B4, the line B5 and the line B6 are shown in fig. 8-16.
Fig. 17 shows a schematic diagram of concentration EAD distribution of an electron accumulation layer when the transverse double-diffusion power device is in an on state, and as can be seen from fig. 17, a trench gate structure expands a longitudinal electron accumulation layer, and meanwhile, a gate medium is a high-K medium, so that the density of the electron accumulation layer is higher.
Fig. 18 is a graph showing the breakdown voltage and specific on-resistance of a conventional lateral power device structure and a lateral double-diffused power device according to the present invention, which are related to the doping concentration of the drift region. As can be seen from fig. 18, the structure effectively reduces the on-resistance of the device under the condition of ensuring that the breakdown voltage is unchanged, and compared with the conventional structure, the on-resistance of the lateral double-diffusion power device provided by the invention is reduced by about 50% through calculation.
Fig. 19 is a graph showing the FOM value of the conventional lateral power device structure and the lateral double-diffused power device according to the present invention as a function of the doping concentration of the drift region. As can be seen from fig. 19, the FOM value of the structure of the present invention is greatly improved compared with the conventional structure, and calculated by calculation, the FOM value is improved by 83.5%.
The above examples are only for illustrating the principle and the effect of the present invention, and not for limiting the present invention, and various equivalent changes can be made within the scope of the technical idea of the present invention, which are all included in the scope of the present invention.
Claims (10)
1. A split-tank lateral double-diffused power device, comprising: the semiconductor device comprises a semiconductor substrate and an active region which are sequentially overlapped from bottom to top, wherein a longitudinal grid groove is formed in the active region of the grid region, a semiconductor drift region with at least two strip-shaped conductors is formed in the active region between the semiconductor well region and the drain region, a transverse separation groove structure is formed in the groove between the at least two strip-shaped conductors, the depth of the longitudinal grid groove is consistent with that of the transverse separation groove structure, a semiconductor well region is formed between the longitudinal grid groove and the transverse separation groove structure, a semiconductor body contact region and a semiconductor source region are formed in the semiconductor well region, a semiconductor drain region is formed in the drain region, a first dielectric layer with a high dielectric constant dielectric material is deposited at the bottom and the periphery of the transverse separation groove structure, a first dielectric layer with the high dielectric constant material is deposited at the bottom and the periphery of the longitudinal grid groove structure, a second dielectric layer with an insulating material is deposited in the first dielectric layer of the groove in the transverse separation groove structure, and a metal is deposited at the bottom and the periphery of the longitudinal grid groove, the surfaces of the first dielectric layer, the semiconductor source region, the semiconductor drain region and the top of the semiconductor well region are formed at the bottom and the top of the semiconductor well region.
2. The split-trench lateral double-diffused power device of claim 1, wherein said active region is made of silicon or a wide bandgap semiconductor material, said wide bandgap semiconductor material being silicon carbide or gallium nitride or gallium oxide.
3. The device of claim 1, wherein the lateral separation channel structure comprises 3 to 5 grooves, each groove has the same width a, each groove has the same width b, a and b are 1 to 5 micrometers, a: b= (5, 4, 3, 2): 1 or 1 (1, 2, 3, 4, 5).
4. The split-trench lateral double-diffused power device of claim 1, wherein said first dielectric layer has a thickness of 0.1 to 0.5 microns.
5. The split-tank lateral double-diffused power device of claim 1, wherein said second dielectric layer of insulating material is a second dielectric layer of silicon dioxide material.
6. The method of manufacturing a split-tank lateral double-diffused power device according to claim 1, comprising the steps of:
step 1, a semiconductor is doped with a first conductive type on a semiconductor substrate in an epitaxial manner to form an active region;
step 2, etching an active region of a gate region, an active region between a semiconductor well region and a drain region, controlling the etching depth of the active region of the gate region to be consistent with that of the active region between the semiconductor well region and the drain region, forming a semiconductor drift region with at least two strip-shaped conductors in the active region between the semiconductor well region and the drain region, forming a transverse separation groove structure in a groove between the at least two strip-shaped conductors, and forming a longitudinal gate groove in the active region of the gate region;
step 3, taking photoresist as a mask, and adopting an ion implantation process to implant second conductivity type impurities into the active region between the longitudinal grid groove and the transverse separation groove structure to form a semiconductor well region;
step 4, using photoresist as a mask, and adopting an ion implantation process to implant highly doped first conductivity type semiconductor impurities into the active regions of the semiconductor well region and the drain region to form a semiconductor source region and a semiconductor drain region;
step 5, using photoresist as a mask, and adopting an ion implantation process to implant highly doped second conductivity type semiconductor impurities into the semiconductor well region to form a semiconductor body contact region;
step 6, using photoresist as a mask, adopting magnetron sputtering deposition equipment to deposit high-dielectric constant dielectric materials at the bottom and the periphery of the transverse separation groove structure and at the bottom and the periphery of the longitudinal grid groove, and controlling the thickness of the deposited high-dielectric constant dielectric materials in the transverse separation groove structure to be the same as the thickness of the deposited high-dielectric constant dielectric materials in the longitudinal grid groove to prepare a first dielectric layer;
step 7, using photoresist as a mask, and adopting chemical vapor deposition equipment to fill insulating materials in the first dielectric layer deposited in the groove in the transverse separation groove structure to prepare a second dielectric layer;
step 8, flattening the surface of the active region after the second dielectric layer is prepared in the step 7;
and 9, depositing metal on the surface of the first dielectric layer deposited at the bottom and the periphery of the longitudinal grid groove, the top of the semiconductor source region and the semiconductor body contact region and the top of the semiconductor drain region by taking photoresist as a mask and adopting magnetron sputtering deposition equipment, and performing annealing treatment to prepare a grid electrode, a source electrode and a drain electrode.
7. The method of manufacturing a split-trench lateral double-diffused power device according to claim 6, wherein step 1 epitaxially forms an active region of the first conductivity-type doped silicon on the semiconductor substrate, and step 2 etches the active region of the gate region, the active region between the semiconductor well region and the drain region using a dry process.
8. The method of manufacturing a split-trench lateral double-diffused power device according to claim 6, wherein in the step 2, the active region of the gate region, the active region between the semiconductor well region and the drain region are etched, and the layout line width is adjusted so that the width of each trench is equal to a and the width between each trench is equal to b, a: b= (5, 4, 3, 2): 1 or 1 (1, 2, 3, 4, 5).
9. The method of manufacturing a split-trench lateral double-diffused power device according to claim 6, wherein before the first dielectric layer is formed in step 6, a buffer layer with a thickness of 10 nm is formed at the bottom and around the lateral split-trench structure and at the bottom and around the longitudinal gate recess.
10. The method of manufacturing a split-trench lateral double-diffused power device according to claim 6, wherein said step 6 is to deposit a high-k dielectric material having a thickness of 0.2 to 0.4 μm at the bottom and around the lateral split-trench structure and at the bottom and around the longitudinal gate recess.
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