CN107785433B - Stepped high-K dielectric layer wide band gap semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor - Google Patents
Stepped high-K dielectric layer wide band gap semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 17
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 17
- 238000009792 diffusion process Methods 0.000 title description 4
- 238000005192 partition Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 10
- 238000009826 distribution Methods 0.000 abstract description 3
- 230000000779 depleting effect Effects 0.000 abstract description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention provides a wide band gap semiconductor longitudinal double-diffused metal oxide semiconductor field effect transistor (VDMOS) with a step High-K dielectric layer. And a dielectric layer with low dielectric constant is arranged below the step of the High-k dielectric layer. When the device is switched off, the High K dielectric layer is modulated by an electric field to assist in depleting the drift region, so that the depletion capability of the drift region of the device is greatly improved, the doping concentration of the drift region of the device is increased, and the on-resistance is reduced. The step high-K dielectric layer optimized in the partition mode can introduce a new electric field peak in the drift region, and the electric field distribution of the drift region is further optimized. In combination with the above advantages, the invention has higher withstand voltage and lower conduction loss under the condition of the same drift region length.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a Trench (Trench) type longitudinal double-diffusion metal oxide semiconductor field effect transistor.
Background
The wide-band-gap semiconductor material has the characteristics of large forbidden band width, high critical breakdown electric field, high thermal conductivity, high electronic saturation drift velocity and the like, so the wide-band-gap semiconductor material has very wide application prospect in the field of high-power, high-temperature and high-frequency power electronics. Among field effect transistors using SiC as a substrate, which is a typical wide band gap semiconductor, a vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) is one of the objects of extensive study. In 1991, chen assist in teaching independently proposes a Composite Buffer (CB) structure, namely a super junction voltage-withstanding layer, which successfully breaks the "silicon limit" of the conventional voltage-withstanding layer.
In order to solve the problem that the super junction voltage-withstanding layer is easily affected by charge imbalance, in 2007, chen teaches a voltage-withstanding layer (high-K voltage-withstanding layer) using a high-K insulating medium. However, the breakdown voltage of the super junction voltage withstanding device is slightly higher than that of the high K insulating dielectric voltage withstanding device under the same specific on-resistance. Thus, this solution does not currently represent an advantage. The conventional improvement scheme is mainly to perform lateral partition optimization on the doping concentration of a drift region to improve the performance of the device.
Disclosure of Invention
The invention provides a vertical double-diffusion metal oxide semiconductor field effect transistor (VDMOS) with a stepped high-K dielectric layer, and aims to further optimize the contradiction relationship between the breakdown voltage and the specific on-resistance of a VDMOS device.
The technical scheme of the invention is as follows:
the wide band gap longitudinal double-diffused metal oxide semiconductor field effect transistor (VDMOS) of the stepped high-K dielectric layer comprises:
a substrate of semiconductor material, also serving as a drain region;
a drift region formed by epitaxial growth on the substrate;
a left base region and a right base region which are formed on the upper surface of the drift region in a doped mode; a groove is etched between the left base region and the right base region;
a source region formed by doping on the upper part of the inner side of the base region;
a channel substrate contact formed by doping on the outer side of the base region corresponding to the whole of the base region and the source region;
a source electrode formed on the upper surface of the whole contact body of the source region and the channel substrate;
a drain electrode formed on the lower surface of the drain region;
it is characterized in that:
the substrate material is a wide bandgap semiconductor material; a groove between the left base region and the right base region longitudinally reaches the top of the drift region, a gate insulating layer is formed on the inner surface of the groove, and a gate is formed on the surface of the gate insulating layer corresponding to the base region and the source region;
step-type High K media are filled in the regions, corresponding to the lower part of the channel substrate contact, on the two sides of the drift region, and the two ends of the High K media are respectively connected with the channel substrate contact and the drain region of the device; the whole stepped High K dielectric is equal to the drift region in the longitudinal direction, and the thicknesses of the corresponding High K dielectric subareas are gradually reduced from top to bottom.
Based on the above scheme, the invention further optimizes as follows:
the relative dielectric constant of the High K dielectric material is 100-2000.
The number of partitions (namely the number of steps) of the step type High K medium is 2-5.
The thickness of the step type High K dielectric is determined according to the breakdown voltage requirement of a device, and the typical value range is 0.2-5 mu m.
The corresponding outer side depressions of each partition of the stepped High K medium are filled with a low dielectric constant material, and the relative dielectric constant of the low dielectric constant material is 1-5.
The thickness of the gate insulating layer is determined according to the threshold voltage, and is typically 0.02 to 0.1 μm.
When the withstand voltage is 600V, a wide band gap semiconductor material with the thickness of 25-50 mu m is epitaxially grown on the substrate to form a drift region.
Typical values for the substrate doping concentration of wide bandgap semiconductor materials are 1 x 1013cm-3～1×1015cm-3。
The wide band gap semiconductor material is gallium nitride, silicon carbide or diamond.
A method for manufacturing the stepped high-K dielectric layer wide band gap longitudinal double-diffused metal oxide semiconductor field effect transistor comprises the following steps:
1) taking a substrate made of wide band gap semiconductor material as a drain region at the same time;
2) forming an epitaxial layer on a substrate as a drift region;
3) etching two sides of the drift region, forming a groove which reaches the drain region along the longitudinal direction, and filling a dielectric layer with a low dielectric constant in the groove;
4) etching the dielectric layer with low dielectric constant, wherein a groove formed by first etching reaches the drain region along the longitudinal direction and is adjacent to the drift region, and High K dielectric material is filled in the groove; sequentially carrying out multiple times of etching with gradually reduced depth in the peripheral area filled with the High K dielectric material and filling the High K dielectric material to finally form a stepped High K dielectric layer;
5) forming an epitaxial layer on the drift region, and forming a base region on the epitaxial layer through ion implantation;
6) etching a groove in the middle of the base region to enable the groove to reach the top of the drift region downwards;
7) forming a gate insulating layer on the side wall and the bottom of the groove;
8) doping the base region to form a source region and a channel substrate contact respectively;
9) depositing polycrystalline silicon in the groove with the surface serving as the gate insulating layer and heavily doping the polycrystalline silicon to form a gate;
10) depositing metal on the contact surfaces of the source region and the channel substrate for forming a source electrode;
11) depositing a passivation layer on the surface of the device, and etching a contact hole;
12) etching the deposited metal and the polysilicon to respectively form a source electrode and a grid electrode;
13) and forming a drain electrode on the lower surface of the drain region.
The technical scheme of the invention has the following beneficial effects:
and forming a stepped High dielectric constant (High K) medium on the side wall of the drift region of the VDMOS device by utilizing multiple times of epitaxial growth. When the device is switched off, under the condition that the longitudinal electric field of the High K dielectric layer is not changed greatly, the transverse electric field of the drift region is greatly improved, the depletion capability of the device is increased, and meanwhile, the electric field distribution in the middle of the drift region is further optimized through High K dielectric partition optimization, so that the doping concentration of the drift region of the device is greatly improved, and the device has lower conduction loss when being switched on.
In a word, compared with the traditional VDMOS device, the stepped high-K dielectric layer VDMOS device based on the wide-bandgap semiconductor material has higher withstand voltage and lower conduction loss under the condition of the same drift region length, and has better performance.
Drawings
Fig. 1 is a schematic structural view (front view) of an embodiment of the present invention, in which the device structure is mirror-symmetrical along the dotted line.
The reference numbers illustrate:
1-a source electrode; 2-a source region; 3-base region; 4-channel substrate contact; 5-High K material; 6-a dielectric layer of low dielectric constant; a 7-wide band gap semiconductor material substrate (also serving as a drain region); 8-a drain electrode; 9-a drift region; 10-a gate insulating layer; 11-gate.
Detailed Description
As shown in fig. 1, the vertical double-diffused mosfet with a stepped high-K dielectric layer includes:
the wide band gap semiconductor material substrate 7 simultaneously serves as a drain region, and the doping concentration is that of a common material, typically 1 × 1013cm-3～1×1015cm-3(ii) a The wide band gap semiconductor material is typically represented by a third generation semiconductor material such as gallium nitride, silicon carbide or diamond;
a drift region 9 formed by an epitaxial layer on the substrate; the depth (length) of the drift region is determined according to the breakdown voltage requirement of the device, for example, when the withstand voltage is 600V, a wide band gap semiconductor material with the thickness of 25-50 μm is epitaxially grown on the substrate to form the drift region;
a base region 3 formed on the drift region in a doped mode;
etching a groove between the left base region and the right base region, wherein the groove reaches the top of the drift region downwards;
filling High K materials 5 in areas corresponding to the lower part of the channel substrate contact on two sides of the drift region, wherein the relative dielectric constant is 100-1000, and the depth of the High K materials is the same as the length of the drift region; the overall shape of the High K material is a step shape, the thickness of the High K material is 0.2-5 mu m, and two ends of the High K material are respectively connected with a channel substrate contact region and a drain region of the device; the thickness of the corresponding High K medium subareas (steps) is gradually reduced from top to bottom;
the step-type High K dielectric region can carry out optimized partition on the High K dielectric layer for 2 to 5 times according to the process cost and the performance requirement, and the more the number of partitions (the number of steps), the better the voltage resistance;
doping the base region to form a source region 2 and a channel substrate contact 4 respectively;
forming a gate insulating layer 10 with a thickness of 0.02-0.1 μm on the inner surface of the trench between the left and right base regions, depositing polysilicon on the surface of the gate insulating layer 10, and performing high-concentration doping (for example, 10)18～1020cm-3) And forming a gate 4;
a source is formed on the source region 2 and the channel substrate contact 4.
When the device is switched off, the High K dielectric layer is modulated by an electric field to assist in depleting the drift region, so that the depletion capability of the drift region of the device is greatly improved, the doping concentration of the drift region of the device is increased, and the on-resistance is reduced. The step-shaped high-K dielectric layer optimized in the partition mode can cause a new electric field peak in the drift region, and the electric field distribution of the drift region is further optimized. The overall performance of the wide-bandgap semiconductor VDMOS device combined with the advantages is remarkably improved.
Taking an N-channel VDMOS as an example, the preparation method can specifically comprise the following steps:
1) taking a substrate made of wide band gap semiconductor material as a drain region at the same time;
2) forming an epitaxial layer on a substrate as a drift region;
3) etching two sides of the drift region, forming a groove which reaches the drain region along the longitudinal direction, and filling a dielectric layer with a low dielectric constant in the groove;
4) etching the dielectric layer with low dielectric constant, wherein a groove formed by first etching reaches the drain region along the longitudinal direction and is adjacent to the drift region, and High K dielectric material is filled in the groove; sequentially carrying out multiple times of etching with gradually reduced depth in the peripheral area filled with the High K dielectric material and filling the High K dielectric material to finally form a stepped High K dielectric layer;
5) forming an epitaxial layer on the drift region, and forming a base region on the epitaxial layer through ion implantation;
6) etching a groove in the middle of the base region to enable the groove to reach the top of the drift region downwards;
7) forming a gate insulating layer on the side wall and the bottom of the groove;
8) doping the base region to form a source region and a channel substrate contact respectively;
9) depositing polycrystalline silicon in the groove with the surface serving as the gate insulating layer and heavily doping the polycrystalline silicon to form a gate;
10) depositing metal on the contact surfaces of the source region and the channel substrate for forming a source electrode;
11) depositing a passivation layer on the surface of the device, and etching a contact hole;
12) etching the deposited metal and the polysilicon to respectively form a source electrode and a grid electrode;
13) and forming a drain electrode on the lower surface of the drain region.
Through ISE-TCAD simulation, the performance of the novel device provided by the invention is obviously improved compared with the traditional device with a high-K dielectric layer, and when the two devices have equal on-resistance, the breakdown voltage of the novel device is improved by more than 20%.
Of course, the VDMOS in the present invention may also be a P-channel VDMOS, and the structure of the VDMOS is equivalent to that of an N-channel VDMOS, which should be considered as falling within the protection scope of the claims of the present application and will not be described herein again.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions also fall into the protection scope of the present invention.
Claims (9)
1. A stepped high-K dielectric wide bandgap semiconductor vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) comprising:
a substrate of semiconductor material, also serving as a drain region;
a drift region formed by epitaxial growth on the substrate;
a left base region and a right base region which are formed on the upper surface of the drift region in a doped mode; a groove is etched between the left base region and the right base region;
a source region formed by doping on the upper part of the inner side of the base region;
a channel substrate contact formed by doping on the outer side of the base region corresponding to the whole of the base region and the source region;
a source electrode formed on the upper surface of the whole contact body of the source region and the channel substrate;
a drain electrode formed on the lower surface of the drain region;
the method is characterized in that:
the material of the substrate is a wide band gap semiconductor material; a groove between the left base region and the right base region longitudinally reaches the top of the drift region, a gate insulating layer is formed on the inner surface of the groove, and a gate is formed on the surface of the gate insulating layer corresponding to the base region and the source region;
step-type High K media are filled in the regions, corresponding to the lower part of the channel substrate contact, on the two sides of the drift region, and the two ends of the High K media are respectively connected with the channel substrate contact and the drain region of the device; the whole stepped High K dielectric is longitudinally equal to the drift region in height, and the thicknesses of the corresponding High K dielectric subareas are sequentially reduced from top to bottom; the corresponding outer side depressions of each partition of the stepped High K medium are filled with a low dielectric constant material, and the relative dielectric constant of the low dielectric constant material is 1-5.
2. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 1, wherein: the relative dielectric constant of the High K dielectric material is 100-2000.
3. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 2, wherein: the number of the partitions of the stepped High K medium is 2-5.
4. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 1, wherein: the thickness of the step type High K dielectric is determined according to the breakdown voltage requirement of a device, and the typical value range is 0.2-5 mu m.
5. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 1, wherein: the thickness of the gate insulating layer is determined according to the threshold voltage, and is typically 0.02 to 0.1 μm.
6. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 1, wherein: and when the withstand voltage is 600V, epitaxially growing a wide band gap semiconductor material with the thickness of 25-50 mu m on the substrate to form a drift region.
7. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 1, wherein: typical values for the substrate doping concentration of wide bandgap semiconductor materials are 1 x 1013cm-3～1×1015cm-3。
8. The vertical double-diffused metal oxide semiconductor field effect transistor of a wide band gap semiconductor of a stepped high-K dielectric layer of claim 1, wherein: the wide band gap semiconductor material is gallium nitride, silicon carbide or diamond.
9. A method for manufacturing the stepped high-K dielectric layer wide band gap semiconductor vertical double diffused metal oxide semiconductor field effect transistor of claim 1, comprising the steps of:
1) taking a substrate made of wide band gap semiconductor material as a drain region at the same time;
2) forming an epitaxial layer on a substrate as a drift region;
3) etching two sides of the drift region, forming a groove which reaches the drain region along the longitudinal direction, and filling a dielectric layer with a low dielectric constant in the groove;
4) etching the dielectric layer with low dielectric constant, wherein a groove formed by first etching reaches the drain region along the longitudinal direction and is adjacent to the drift region, and High K dielectric material is filled in the groove; sequentially carrying out multiple times of etching with gradually reduced depth in the peripheral area filled with the High K dielectric material and filling the High K dielectric material to finally form a stepped High K dielectric layer;
5) forming an epitaxial layer on the drift region, and forming a base region on the epitaxial layer through ion implantation;
6) etching a groove in the middle of the base region to enable the groove to reach the top of the drift region downwards;
7) forming a gate insulating layer on the side wall and the bottom of the groove;
8) doping the base region to form a source region and a channel substrate contact respectively;
9) depositing polycrystalline silicon in the groove with the surface serving as the gate insulating layer and heavily doping the polycrystalline silicon to form a gate;
10) depositing metal on the contact surfaces of the source region and the channel substrate for forming a source electrode;
11) depositing a passivation layer on the surface of the device, and etching a contact hole;
12) etching the deposited metal and the polysilicon to respectively form a source electrode and a grid electrode;
13) and forming a drain electrode on the lower surface of the drain region.
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| CN102148256B (en) * | 2011-03-21 | 2013-03-06 | 哈尔滨工程大学 | Grid enhanced-power semiconductor field effect transistor |
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