CN107785433A - A kind of ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS FET - Google Patents
A kind of ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS FET Download PDFInfo
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- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
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- 239000002131 composite material Substances 0.000 description 1
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- 239000004020 conductor Substances 0.000 description 1
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- 238000002353 field-effect transistor method Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The present invention proposes a kind of ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS FET (VDMOS), and the device mainly forms ladder high-k (High K) dielectric layer in device drift region both sides.It is the dielectric layer of low-k below High k dielectric layers ladder.For High K dielectric layers by Electric Field Modulated assisted depletion drift region, the ability that exhausts that device drift region is greatly improved causes the drift doping concentration of device to increase when device turns off, and conducting resistance reduces.The ladder high-K dielectric layer of partition zone optimizing can introduce new electric field peak in drift region, further optimize the Electric Field Distribution of drift region.With reference to above advantage, in the case of identical drift region length, the present invention has higher pressure-resistant and lower conduction loss.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of longitudinal double diffused metal of groove (Trench) type
Oxide semiconductor field effect pipe.
Background technology
Wide bandgap semiconductor materials have big energy gap, high critical breakdown electric field, high heat conductance and high electronics saturation
The features such as drift velocity, therefore it has boundless application prospect in the field of power electronics of high-power, high temperature and high frequency.
At present using the typical SiC of wide band gap semiconducter as in the FET of substrate, vertical DMOS field
Effect pipe (VDMOS) is one of object being widely studied.1991, Chen Xing assist in educations, which are awarded, independently proposed compound buffer layer
(Composite Buffer, CB) structure, that is, superjunction Withstand voltage layer, have successfully broken " the silicon limit " of traditional Withstand voltage layer.
Easily influenceed to solve superjunction Withstand voltage layer by charge unbalance, 2007, Chen Xing assist in educations, which are awarded, proposes utilization
The Withstand voltage layer (high K Withstand voltage layers) of high K dielectrics.However, in breakdown of the identical than under conducting resistance, superjunction is pressure-resistant layer device
The voltage ratio high pressure-resistant layer device of K dielectrics is slightly higher.Therefore, the program does not embody advantage at present.Conventional improvement
Scheme mainly carries out horizontal partition optimization to improve the performance of device to drift doping concentration.
The content of the invention
The present invention proposes a kind of ladder high-K dielectric layer vertical double-diffused MOS FET
(VDMOS), it is intended to further optimization VDMOS device breakdown voltage and the contradictory relation than conducting resistance.
Technical scheme is as follows：
The ladder high-K dielectric layer broad-band gap vertical double-diffused MOS FET (VDMOS), including：
The substrate of semi-conducting material, as drain region；
In the drift region that substrate Epitaxial growth is formed；
Base to be formed left and right two is adulterated in the drift region upper surface；Ditch is etched between base at left and right two
Groove；
Inside upper part in base adulterates the source region to be formed；
Corresponding to the entirety of base and source region, the channeled substrate to be formed contact is adulterated in the outside of base；
In the source electrode that the overall upper surface of the source region and channeled substrate contact is formed；
In the drain electrode that the drain region lower surface is formed；
It is characterized in that：
The backing material is wide bandgap semiconductor materials；Groove at left and right two between base reaches drift along longitudinal direction
At the top of area, grooved inner surface forms gate insulation layer, corresponds to base in gate electrode insulation surface and source region forms grid；
Stepped High K media, both ends are filled with the both sides of drift region, corresponding to channeled substrate contact lower zone
The channeled substrate contact of interface unit and drain region respectively；Stepped High K media are overall longitudinally contour with drift region, accordingly
The thickness of High K medium subregions successively decreases successively from top to bottom.
Based on above scheme, the present invention has also further made following optimization：
The relative dielectric constant of High K dielectric materials is 100~2000.
The number of partitions (i.e. " ladder " number) of stepped High K media is 2~5.
The thickness of stepped High K media requires determination according to device electric breakdown strength, and Typical value range is 0.2~5 μm.
The corresponding outside depression of stepped each subregion of High K media is filled by advanced low-k materials, and the low dielectric is normal
The relative dielectric constant of number material is 1~5.
The thickness of gate insulation layer determines that representative value is 0.02~0.1 μm according to threshold voltage.
It is pressure-resistant when being 600V, form drift region in the wide bandgap semiconductor materials of the μ m-thick of substrate Epitaxial growth 25~50.
The representative value of the substrate doping of wide bandgap semiconductor materials is 1 × 1013cm-3~1 × 1015cm-3。
The wide bandgap semiconductor materials are gallium nitride, carborundum or diamond.
A kind of side for making above-mentioned ladder high-K dielectric layer broad-band gap vertical double-diffused MOS FET
Method, comprise the following steps：
1) take the substrate of wide bandgap semiconductor materials while be used as drain region；
2) epitaxial layer is formed on substrate as drift region；
3) performed etching in drift region both sides, the groove of formation reaches drain region along longitudinal direction, and it is normal that low dielectric is filled in groove
Several dielectric layers；
4) dielectric layer of low-k is performed etching, etches the groove of formation first along longitudinal direction arrival drain region, and with
Drift region is abutted, and High K dielectric materials are filled in groove；Enter successively in the outer peripheral areas for having been filled with High K dielectric materials
Multiple etching that row depth is successively decreased simultaneously fills High K dielectric materials, ultimately forms stepped High K dielectric layers；
5) epitaxial layer is formed on drift region, base is formed by ion implanting to epitaxial layer；
6) etching groove in the middle part of base, groove is made to reach down at the top of drift region；
7) gate insulation layer is formed in trenched side-wall and bottom；
8) doping forms source region and channeled substrate contact respectively on base；
9) turn into depositing polysilicon in the groove of gate insulation layer on surface and carry out heavy doping, for forming grid；
10) source region and channeled substrate contact surface deposition metal, for forming source electrode；
11) device surface deposit passivation layer, and etch contact hole；
12) metal to deposit and polysilicon perform etching forms source electrode and grid respectively；
13) drain region lower surface forms drain electrode.
Technical solution of the present invention has the beneficial effect that：
Ladder high-k (High K) Jie is formed in the side wall of VDMOS device drift region using multiple epitaxial growth
Matter.When device turns off, High K dielectric layers drastically increase the horizontal stroke of drift region in the case of longitudinal electric field change less
To electric field, the ability that exhausts of device is added, while the electric field among drift region is further optimized by high K dielectric partition zone optimizing
Distribution, thus the doping concentration of device drift region is greatly improved so that there is relatively low conduction loss during break-over of device.
In a word, the ladder high-K dielectric layer VDMOS device based on wide bandgap semiconductor materials compares traditional VDMOS device,
In the case of identical drift region length, ladder high-K dielectric layer VDMOS device has higher pressure-resistant and lower conducting damage
Consumption, ladder high-K dielectric layer VDMOS device have better performance.
Brief description of the drawings
Fig. 1 be the embodiment of the present invention structural representation (front view), device architecture dotted line specular along figure.
Drawing reference numeral explanation：
1- source electrodes；2- source regions；3- bases；4- channeled substrates contact；5-High K materials；The medium of 6- low-ks
Layer；7- wide bandgap semiconductor materials substrate (doubles as drain region)；8- drains；9- drift regions；10- gate insulation layers；11- grids.
Embodiment
As shown in figure 1, there should be stepped high-K dielectric layer vertical double-diffused MOS FET bag
Include：
Wide bandgap semiconductor materials substrate 7 is used as drain region simultaneously, and doping concentration is the concentration of general material, representative value 1
×1013cm-3~1 × 1015cm-3；Wide bandgap semiconductor materials Typical Representative is the third generations such as gallium nitride, carborundum or diamond
Semi-conducting material；
The drift region 9 that epitaxial layer on substrate is formed；The depth (length) of drift region is according to the breakdown voltage of device
It is required that be determined, for example, it is pressure-resistant when being 600V, formed in 25~50 μm of wide bandgap semiconductor materials of substrate Epitaxial growth
Drift region；
The base 3 of formation is adulterated on the drift region；
The etching groove between base at left and right two, groove are reached down at the top of drift region；
In the both sides of drift region, corresponding to channeled substrate contact lower zone filling High K materials 5, relative dielectric constant
Depth for 100~1000, High K materials is identical with drift region length；And the global shape of High K materials is ladder
Type, thickness are 0.2~5 μm, the channeled substrate contact of both ends difference interface unit and drain region；Corresponding High K medium subregions
The thickness of (step) successively decreases successively from top to bottom；
Stepped High K dielectric areas can carry out 2 to 5 according to process costs and performance requirement to High K dielectric layers
Secondary optimization subregion, the number of partitions (" ladder " number) is more, and pressure-resistant performance is better；
Adulterated on base and form source region 2 and channeled substrate contact 4 respectively；
Grooved inner surface at left and right two between base forms gate insulation layer 10, and thickness is 0.02~0.1 μm, exhausted in grid
The surface deposition polysilicon of edge layer 10 simultaneously carries out high-concentration dopant (such as 1018~1020cm-3) and form grid 4；
Source electrode is formed in source region 2 and channeled substrate contact 4.
Device drift is greatly improved by Electric Field Modulated assisted depletion drift region in High K dielectric layers when device turns off
The ability that exhausts in area causes the drift doping concentration of device to increase, and conducting resistance reduces.The stepped high K dielectric of partition zone optimizing
Layer can cause new electric field peak in drift region, further optimize the Electric Field Distribution of drift region.With reference to the broad-band gap of above advantage
The overall performance of semiconductor VDMOS device is significantly improved.
By taking N-channel VDMOS as an example, it can specifically be prepared by following steps：
1) take the substrate of wide bandgap semiconductor materials while be used as drain region；
2) epitaxial layer is formed on substrate as drift region；
3) performed etching in drift region both sides, the groove of formation reaches drain region along longitudinal direction, and it is normal that low dielectric is filled in groove
Several dielectric layers；
4) dielectric layer of low-k is performed etching, etches the groove of formation first along longitudinal direction arrival drain region, and with
Drift region is abutted, and High K dielectric materials are filled in groove；Enter successively in the outer peripheral areas for having been filled with High K dielectric materials
Multiple etching that row depth is successively decreased simultaneously fills High K dielectric materials, ultimately forms stepped High K dielectric layers；
5) epitaxial layer is formed on drift region, base is formed by ion implanting to epitaxial layer；
6) etching groove in the middle part of base, groove is made to reach down at the top of drift region；
7) gate insulation layer is formed in trenched side-wall and bottom；
8) doping forms source region and channeled substrate contact respectively on base；
9) turn into depositing polysilicon in the groove of gate insulation layer on surface and carry out heavy doping, for forming grid；
10) source region and channeled substrate contact surface deposition metal, for forming source electrode；
11) device surface deposit passivation layer, and etch contact hole；
12) metal to deposit and polysilicon perform etching forms source electrode and grid respectively；
13) drain region lower surface forms drain electrode.
Emulated through ISE-TCAD, the performance of new device proposed by the present invention has high-K dielectric layer device compared to tradition
It is obviously improved, when two kinds of devices have equal conducting resistance, the breakdown voltage of new device improves more than 20%.
Certainly, the VDMOS in the present invention can also be P-type channel, and its structure is equal with N-channel VDMOS, and these all should be regarded
To belong to the application scope of the claims, will not be repeated here.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and replacement can also be made, these improve and replaced
Scheme also fall into protection scope of the present invention.
Claims (10)
1. a kind of ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS FET (VDMOS),
Including：
The substrate of semi-conducting material, as drain region；
In the drift region that substrate Epitaxial growth is formed；
Base to be formed left and right two is adulterated in the drift region upper surface；Groove is etched between base at left and right two；
Inside upper part in base adulterates the source region to be formed；
Corresponding to the entirety of base and source region, the channeled substrate to be formed contact is adulterated in the outside of base；
In the source electrode that the overall upper surface of the source region and channeled substrate contact is formed；
In the drain electrode that the drain region lower surface is formed；
It is characterized in that：
The material of the substrate is wide bandgap semiconductor materials；Groove at left and right two between base reaches drift region along longitudinal direction
Top, grooved inner surface form gate insulation layer, correspond to base in gate electrode insulation surface and source region forms grid；
Stepped High K media, both ends difference are filled with the both sides of drift region, corresponding to channeled substrate contact lower zone
The channeled substrate contact of interface unit and drain region；Overall, the corresponding High longitudinally contour with drift region of stepped High K media
The thickness of K medium subregions successively decreases successively from top to bottom.
2. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：The relative dielectric constant of High K dielectric materials is 100~2000.
3. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 2
FET, it is characterised in that：The number of partitions of stepped High K media is 2~5.
4. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：The thickness of stepped High K media requires determination, Typical value range according to device electric breakdown strength
It is 0.2~5 μm.
5. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：The corresponding outside depression of stepped each subregion of High K media is filled by advanced low-k materials,
The relative dielectric constant of the advanced low-k materials is 1~5.
6. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：The thickness of gate insulation layer determines that representative value is 0.02~0.1 μm according to threshold voltage.
7. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：It is pressure-resistant when being 600V, in the broad-band gap band semiconductor material of the μ m-thick of substrate Epitaxial growth 25~50
Material forms drift region.
8. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：The representative value of the substrate doping of wide bandgap semiconductor materials is 1 × 1013cm-3~1 ×
1015cm-3。
9. ladder high-K dielectric layer wide band gap semiconducter vertical double-diffused MOS according to claim 1
FET, it is characterised in that：The wide bandgap semiconductor materials are gallium nitride, carborundum or diamond.
10. ladder high-K dielectric layer wide band gap semiconducter longitudinal double diffusion metal oxide described in one kind making claim 1 is partly led
The method of body FET, comprises the following steps：
1) take the substrate of wide bandgap semiconductor materials while be used as drain region；
2) epitaxial layer is formed on substrate as drift region；
3) performed etching in drift region both sides, the groove of formation reaches drain region along longitudinal direction, and low-k is filled in groove
Dielectric layer；
4) dielectric layer of low-k is performed etching, etches the groove of formation first and reach drain region along longitudinal direction, and with drift
Area is abutted, and High K dielectric materials are filled in groove；Depth is carried out successively in the outer peripheral areas for having been filled with High K dielectric materials
Spend the multiple etching successively decreased and fill High K dielectric materials, ultimately form stepped High K dielectric layers；
5) epitaxial layer is formed on drift region, base is formed by ion implanting to epitaxial layer；
6) etching groove in the middle part of base, groove is made to reach down at the top of drift region；
7) gate insulation layer is formed in trenched side-wall and bottom；
8) doping forms source region and channeled substrate contact respectively on base；
9) turn into depositing polysilicon in the groove of gate insulation layer on surface and carry out heavy doping, for forming grid；
10) source region and channeled substrate contact surface deposition metal, for forming source electrode；
11) device surface deposit passivation layer, and etch contact hole；
12) metal to deposit and polysilicon perform etching forms source electrode and grid respectively；
13) drain region lower surface forms drain electrode.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112885889A (en) * | 2021-01-14 | 2021-06-01 | 电子科技大学 | Transverse pressure-resistant area containing combined medium deep groove |
| CN115966596A (en) * | 2023-03-13 | 2023-04-14 | 南京邮电大学 | Transverse double-diffusion power device with separation grooves and manufacturing method thereof |
| CN116387347A (en) * | 2023-05-29 | 2023-07-04 | 深圳市威兆半导体股份有限公司 | Silicon carbide MOSFET device with high UIS capability and manufacturing method thereof |
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| CN101159233A (en) * | 2006-10-03 | 2008-04-09 | 电力集成公司 | Trench-gate vertical mosfet manufacturing method |
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| CN112885889B (en) * | 2021-01-14 | 2022-06-03 | 电子科技大学 | Transverse pressure-resistant area containing combined medium deep groove |
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