CN206976353U - A kind of channel-type semiconductor device for optimizing terminal structure - Google Patents
A kind of channel-type semiconductor device for optimizing terminal structure Download PDFInfo
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- CN206976353U CN206976353U CN201720877752.5U CN201720877752U CN206976353U CN 206976353 U CN206976353 U CN 206976353U CN 201720877752 U CN201720877752 U CN 201720877752U CN 206976353 U CN206976353 U CN 206976353U
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Abstract
It the utility model is related to a kind of trench-type power semiconductor device for optimizing terminal structure, it is characterised in that：First conductive type epitaxial layer is provided with least one second class groove, the surface of second the first conductive type epitaxial layer of class groove both sides is sequentially provided with the second conductivity type body region and insulating medium layer, heavy doping the second conduction type source region is provided with the second conductivity type body region between first kind groove and the second class groove, source metal passes through through hole and the second conduction type of heavy doping source contact on insulating medium layer, layer of oxide layer is provided with second class groove, covered with polysilicon in the oxide layer of trenched side-wall, and the inter polysilicon of side wall is insulated by insulating medium layer, second class beneath trenches are provided with the second conduction type well region；The utility model manufacture method is compatible with existing semiconductor technology, and reduces photolithography plate quantity, and reduces the width of terminal, reduces manufacturing cost, while the voltage endurance capability of device is improved by optimizing terminal structure.
Description
Technical field
A kind of semiconductor devices is the utility model is related to, especially a kind of trench-type power semiconductor for optimizing terminal structure
Device, belong to the manufacturing technology field of semiconductor devices.
Background technology
In power semiconductor field, trench mosfet（Metal-Oxide-
Semiconductor Field-Effect Transistor, MOSFET）Compared to plane MOSFET, can significantly improve
Gully density, specific on-resistance is reduced, therefore, trench MOSFET has been widely adopted.Existing trench MOSFET
Generally use field limiting ring structure is as terminal structure, as shown in figure 3, along A- in the terminal protection area accompanying drawing 1 of the traditional structure
A ' cross-section structure, the terminal protection area include also serving as the first conduction type silicon substrate 1 in drain region, the first conduction type silicon lining
Bottom 1 is provided with the first conductive type epitaxial layer 2, the first conductive type epitaxial layer 2 between first kind groove 3 and field limiting ring 17
Surface be provided with the second conductivity type body region 6, set in the second conductivity type body region 6 between first kind groove 3 and field limiting ring 17
There is the second conduction type of heavy doping source region 8, source metal 10 passes through the through hole on insulating medium layer 9 and the conductive-type of heavy doping second
Contacted in the contact hole on the surface of the second conductivity type body region 6 of the type source region 7 between first kind groove 3 and field limiting ring 17,
One conductive type epitaxial layer 2 is provided with least one second conduction type field limiting ring 17, and the surface of the first conductive type epitaxial layer 2 is set
There is insulating medium layer 9.
Although the structure of field limiting ring 17 can effectively improve, terminal is pressure-resistant, when making field limiting ring 17, it is necessary to extra
Photolithography plate, while the width of the terminal of the structure of field limiting ring 17 is larger, this 2 points can all cause the manufacturing cost of device to rise.
Impact ionization rate when as shown in Figure 18, to be punctured using the traditional structure of field limiting ring terminal is on sectional structure
Schematic diagram, when bearing pressure-resistant, PN junction that terminal protection area only has p-type field limiting ring and N-type epitaxy layer to be formed bears resistance to device
Pressure, electric field almost concentrate on the bottom of field limiting ring 17, can so make internal field too high, cause device breakdown, breakdown point is located at
The bottom of the field limiting ring 17 in terminal protection area, because the bottom electric field of field limiting ring 17 is too high, traditional structure breakdown occurred at end
End regions, this is unfavorable for device, can limit the resistance to voltage levels of device.
The content of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, the purpose of this utility model be overcome it is existing
It is insufficient present in technology, there is provided a kind of channel-type semiconductor device and its manufacture method for optimizing terminal structure, the device system
Make that method is compatible with existing semiconductor technology, and the quantity of photolithography plate can be reduced, reduce the width of terminal, and then reduce manufacture
Cost, while can improve the voltage endurance capability of device by optimizing terminal structure.
To realize above technical purpose, the technical solution of the utility model is：A kind of groove-shaped work(for optimizing terminal structure
Rate semiconductor devices, including cellular region and terminal protection area, the cellular region are located at the center of device, the terminal protection area
It is looped around around cellular region, the cellular region includes several cellular units, and the cellular unit includes semiconductor substrate, institute
Stating semiconductor substrate includes the first conductivity type substrate and the first conductive type epitaxial layer in the first conductivity type substrate,
First conductive type epitaxial layer is provided with first kind groove, and grid oxide layer, the grid oxide layer are provided with the first kind groove
The grid polycrystalline silicon formed by conductive polycrystalline silicon is provided with the groove of formation, first between two neighboring first kind groove is conductive
The surface of type epitaxial layer is provided with the second conductivity type body region, and it is conductive to be provided with heavy doping second in second conductivity type body region
Type source region and heavy doping the first conduction type source region, and the first conduction type of heavy doping source region is located at the second conduction type source region
Both sides, be provided with insulating medium layer above the first kind groove and the second conductivity type body region, set on the insulating medium layer
There are source metal and gate bus metal, the source metal passes through through hole and the second conductivity type body region in insulating medium layer
Interior the first conduction type of heavy doping source region, heavy doping the second conduction type source contact, the gate bus metal are looped around
Around source metal；The terminal protection area include the first conductivity type substrate and in the first conductivity type substrate first
Conductive type epitaxial layer, it is characterised in that：First conductive type epitaxial layer is provided with least one second class groove, described
The surface of first conductive type epitaxial layer of the second class groove both sides is sequentially provided with the second conductivity type body region and insulating medium layer,
Heavy doping the second conduction type source region, institute are provided with the second conductivity type body region between the first kind groove and the second class groove
Source metal is stated through the through hole on insulating medium layer and the second conduction type of heavy doping source contact, the second class ditch
Layer of oxide layer is provided with groove, covered with polysilicon on the trenched side-wall that oxide layer is formed, and the inter polysilicon of side wall passes through
Insulating medium layer insulate, and the second described class beneath trenches are provided with the second conduction type well region.
Further, for N-type trench-type power semiconductor device, first conduction type is that N-type is conductive, described the
Two conduction types are P-type conduction；For p-type trench-type power semiconductor device, first conduction type is P-type conduction, institute
It is conductive for N-type to state the second conduction type.
Further, the width of the second class groove is more than first kind groove.
Further, the polysilicon in the second class groove is floating, it is not necessary to which metal is drawn.
Further, the trench-type power semiconductor device is mos field effect transistor or insulation
Grid bipolar transistor.
In order to further realize above technical purpose, the utility model also proposes a kind of groove-shaped work(for optimizing terminal structure
The preparation method of rate semiconductor devices, it is characterized in that, comprise the following steps：
Step 1：The first conductivity type substrate is provided, the conduction type of growth regulation one in first conductivity type substrate
Epitaxial layer, the upper surface of first conductive type epitaxial layer are the first interarea, and the lower surface of the first conductivity type substrate is the
Two interareas；
Step 2：First kind groove and the second class ditch are gone out by first piece of photolithography plate selective etch on the first interarea
Groove；
Step 3：In the thermally grown layer of oxide layer of the first main surface, the oxide layer in first kind groove is grid oxide layer；
Step 4：One layer of conductive polycrystalline silicon is deposited in oxide layer；
Step 5：Conductive polycrystalline silicon is performed etching, grid polycrystalline silicon is formed in first kind groove, in the second class groove
Interior formation polysilicon；
Step 6：The impurity of the second conduction type, and thermal annealing are injected on the first interarea, in first kind groove and second
Class groove both sides form the second conductivity type body region, and the second conduction type well region is formed in the second class beneath trenches；
Step 7：On the first interarea, using second piece of conductive type impurity of photolithography plate Selective implantation first, weight is formed
The first conduction type source region is adulterated, then deposits one layer of dielectric, forms insulating medium layer；
Step 8：Using the 3rd piece of photolithography plate selective etch insulating medium layer, and continue to etch silicon, form through hole,
The second conductive type impurity of injection forms the conductivity type source region of heavy doping second in through hole；
Step 9：Metal is deposited in through hole, and uses the 4th block of photolithography plate selective etch metal, forms source metal
With gate bus metal；
Step 10：Metal is deposited on the second interarea, forms drain metal.
Further, the thickness of conductive polycrystalline silicon is less than the width of the second class groove, the step 5 in the step 4
In in the second class groove both sides side wall the gross thickness of polysilicon be less than the width of the second class groove.
Further, the step 6 can also be：
Step 1 injects the impurity of the second conduction type for the first time on the first interarea, and deposits one layer of dielectric；
Step 2 etches the dielectric of the first main surface, makes still to fill up dielectric in the second class groove；
Second of impurity for injecting the second conduction type of step 3, and thermal annealing, in first kind groove and the second class ditch
Groove both sides form the second conductivity type body region, and the second conduction type well region is formed in the second class beneath trenches；
Compared with conventional power semiconductors device, the utility model has advantages below：
1) compared with the preparation method of trench MOSFET of the tradition with field limiting ring terminal, the utility model proposes
Preparation method reduces one piece of photolithography plate, saves production cost；Foreign ion in second conduction type well region is by
Polysilicon in two class grooves carries out autoregistration injection, due to the stop of the polysilicon in the second class groove, the second conduction type
The space of two inter polysilicons that can only inject in the second class groove of impurity, can form the second class trench bottom by thermal annealing
The field limiting ring in portion, i.e. the second conduction type well region；
2）It is pressure-resistant that the utility model compared to the trench MOSFET with field limiting ring terminal improves terminal, reduces end
Hold width；The floating polysilicon of two pieces of mutual insulatings in the second class groove be present, led in the second class channel bottom in the presence of second
Electric type well region, when the utility model device architecture is pressure-resistant, floating polysilicon can play aobvious with the second conduction type well region
The effect of the scattered electric field write, the single field limiting ring of resistance to pressure ratio that single second class groove can undertake is high, therefore the utility model
Terminal area voltage endurance capability is improved, while reduces terminal width.
Brief description of the drawings
Accompanying drawing 1 is the utility model embodiment 1 and the plan view from above of traditional structure.
Accompanying drawing 2 is the utility model embodiment 1 in fig. 1 along A-A ' cross-sectional view.
Accompanying drawing 3 is traditional structure in fig. 1 along A-A ' cross-sectional view.
Accompanying drawing 4~11 is specific for embodiment 1 of the utility model by taking N-type trench gate MOSFET semiconductor devices as an example
Implementation steps in fig. 1 along A-A ' cross section structure diagram, wherein：
Accompanying drawing 4 is the cross section structure diagram for forming the first conductive type epitaxial layer.
Accompanying drawing 5 is the cross section structure diagram for forming first kind groove and the second class groove.
Accompanying drawing 6 is the cross section structure diagram for forming grid oxide layer.
Accompanying drawing 7 is the cross section structure diagram of deposit conductive polycrystalline silicon.
Accompanying drawing 8 is the cross section structure diagram for forming grid polycrystalline silicon and polysilicon.
Accompanying drawing 9 is the cross section structure diagram for forming PXing Ti areas and P type trap zone.
Accompanying drawing 10 is to form heavily doped N-type source region and the cross section structure diagram of insulating medium layer.
Accompanying drawing 11 is the cross section structure diagram for forming through hole and heavily doped P-type source region.
In the embodiment 1 of accompanying drawing 12 in optimization method first time implanting p-type impurity cross section structure diagram.
The sectional structure after the full second class groove of dielectric filling is deposited in the embodiment 1 of accompanying drawing 13 in optimization method to show
It is intended to.
Accompanying drawing 14 is to etch the cross section structure diagram after dielectric in embodiment 1 in optimization method.
Accompanying drawing 15 is the cross section structure diagram of second of implanting p-type impurity in optimization method in embodiment 1.
Accompanying drawing 16 is the cross section structure diagram for forming PXing Ti areas and P type trap zone in embodiment 1 in optimization method.
The schematic diagram on sectional structure when accompanying drawing 17 is the utility model device breakdown.
The schematic diagram on sectional structure when accompanying drawing 18 is traditional structure device breakdown.
Description of reference numerals：1-the first conductivity type substrate；2-the first conductive type epitaxial layer；3-first kind ditch
Groove；4-grid oxide layer；5-grid polycrystalline silicon；6-the second conductivity type body region；7-heavy doping the second conduction type source region；8—
Heavy doping the first conduction type source region；9-insulating medium layer；10-source metal；11-the second class groove；12-polysilicon；
13-the second conduction type well region；14-gate bus metal；15-drain metal；16-oxide layer；17-field limiting ring.
Embodiment
With reference to specific drawings and examples, the utility model is described in further detail.
The utility model is not limited to following embodiment, and each figure of institute's reference is to be able to pair in the following description
Content of the present utility model is understood and set that is, the utility model is not limited to the device architecture that each figure is illustrated, and is applicable
In all structures of trench gate mos field effect transistor or groove-grid-type insulated gate bipolar transistor.
As shown in Figures 1 and 2, by taking N-type trench gate MOSFET semiconductor devices as an example, first conduction type is
N-type is conductive, and second conduction type is P-type conduction；A kind of trench-type power semiconductor device for optimizing terminal structure, including
Cellular region and terminal protection area, the cellular region are located at the center of device, and the terminal protection area is looped around the week of cellular region
Enclose, the cellular region includes several cellular units, and the cellular unit includes semiconductor substrate, and the semiconductor substrate includes
N-type substrate 1 and the N-type epitaxy layer 2 in N-type substrate 1, the N-type epitaxy layer 2 are provided with first kind groove 3, and described first
Grid oxide layer 4 is provided with class groove 3, the grid polycrystalline silicon formed by conductive polycrystalline silicon is provided with the groove that the grid oxide layer 4 is formed
5, the surface of the N-type epitaxy layer 2 between two neighboring first kind groove 3 is provided with PXing Ti areas 6, and weight is provided with the PXing Ti areas 6
Doped p-type source region 7 and heavily doped N-type source region 8, and heavily doped N-type source region 8 is located at the both sides of p-type source region 7, the first kind ditch
Groove 3 and the top of PXing Ti areas 6 are provided with insulating medium layer 9, and the insulating medium layer 9 is provided with source metal 10 and grid bus gold
Category 14, the source metal 10 pass through through hole and the heavily doped N-type source region 8 in P bodies area 6, heavy doping P in insulating medium layer 9
Type source region 7 is contacted, and the gate bus metal 14 is looped around around source metal 10, and the decentralization of N-type substrate 1 is provided with drain electrode gold
Category 15；The terminal protection area includes N-type substrate 1 and the N-type epitaxy layer 2 in N-type substrate 1, it is characterised in that：The N
Type epitaxial layer 2 is provided with least one second class groove 11, the surface of the N-type epitaxy layer 2 of the both sides of the second class groove 11 according to
It is secondary to be provided with PXing Ti areas 6 and insulating medium layer 9, it is provided with weight in the JianPXing Ti areas 6 of 3 and second class groove of first kind groove 11
Doped p-type source region 7, the source metal 10 contact through the through hole on insulating medium layer 9 with the heavily doped P-type source region 7, institute
State in the second class groove 11 and be provided with oxide layer 16, covered with polysilicon 12 on the trenched side-wall of the formation of oxide layer 16, and side wall
Polysilicon 12 between insulated by insulating medium layer 9, the lower section of described the second class groove 11 is provided with P type trap zone 13.
A kind of trench-type power semiconductor device of optimization terminal structure of the utility model embodiment 1 can be by following
Processing step is prepared, and comprises the following steps：
As shown in figure 4, step 1 provides N-type substrate 1, N-type epitaxy layer 2, the N-type are grown in the N-type substrate 1
The upper surface of epitaxial layer 2 is the first interarea 001, and the lower surface of N-type substrate 1 is the second interarea 002；
As shown in figure 5, step 2 goes out first kind ditch on the first interarea 001 by first piece of photolithography plate selective etch
The class groove 11 of groove 3 and second；
As shown in fig. 6, step 3 is in the thermally grown layer of oxide layer 16 in the surface of the first interarea 001, in first kind groove 3
Oxide layer be grid oxide layer 4；
As shown in fig. 7, step 4 deposits one layer of conductive polycrystalline silicon in oxide layer, conductive polycrystalline silicon is deposited by controlling
Thickness, make conductive polycrystalline silicon thickness be less than the second class groove width；
As shown in figure 8, step 5 performs etching to conductive polycrystalline silicon, grid polycrystalline silicon is formed in first kind groove 3
5, polysilicon 12 is formed in the side wall in the second class groove 11, the etching of conductive polycrystalline silicon does not need photolithography plate here, described
The gross thickness of polysilicon 12 is less than the width of the second class groove 11 in the both sides side wall of second class groove 11；
As shown in figure 9, the impurity of step 6 implanting p-type on the first interarea 001, and thermal annealing, in first kind groove 3
PXing Ti areas 6 are formed with the both sides of the second class groove 11, in 11 P type trap zone 13 formed below of the second class groove；
As shown in Figure 10, step 7 is on the first interarea 001, using second piece of photolithography plate Selective implantation N-type impurity,
Heavily doped N-type source region 8 is formed, then deposits one layer of dielectric, forms insulating medium layer 9；
As shown in figure 11, step 8 uses the 3rd piece of photolithography plate selective etch insulating medium layer 9, and continues to etch
Silicon, through hole is formed, implanting p-type impurity forms the second conductivity type source region of heavy doping 7 in through hole；
As shown in Fig. 2 step 9 deposits metal in through hole, and the 4th block of photolithography plate selective etch metal is used,
Form source metal 10 and gate bus metal 14；
Step 10 deposits metal on the second interarea 002, forms drain metal 15.
In addition, in order to more accurately control the concentration of the lower section P type trap zone 13 of the second class groove 11, further precision control
The voltage endurance capability of part, the step six in method made above can also be prepared by following optimization method：
As shown in Figures 12 and 13, step 1 the first interarea 001 upper first time implanting p-type impurity, and deposit one layer
Dielectric；
As shown in figure 14, step 2 etches the dielectric on the surface of the first interarea 001, makes still to fill out in the second class groove 11
Full dielectric；
As shown in figs, the impurity of second of implanting p-type of step 3, and thermal annealing, in first kind groove 3 and
The both sides of two class groove 11 form PXing Ti areas 6, in 11 P type trap zone 13 formed below of the second class groove；
Method optimized as above further can accurately control the doping of P type trap zone 13 dense by the impurity of first time implanting p-type
Degree, due to having blocking for dielectric in the second class groove 11, so second of implanting p-type impurity is not noted to the second class groove 11
The P type trap zone 13 of lower section, therefore, the implantation concentration of the impurity by controlling second of p-type, the doping in PXing Ti areas 6 can be controlled
Concentration.
The utility model device breakdown principle：As shown in figure 17, ionization by collision when puncturing for the utility model embodiment 1
Schematic diagram of the rate on sectional structure, for device when bearing pressure-resistant, the breakdown point of device is located at the bottom of first kind groove 03, this table
Bright terminal protection area it is pressure-resistant pressure-resistant higher than cellular region, when device pressure-resistant is determined by cellular region is pressure-resistant, the performance of device
Optimum level can just be reached；Terminal protection area of the present utility model is when bearing pressure-resistant, except the bottom of the second class groove 11
Second conduction type well region 13（Second conduction type well region 13 and the first conductive type epitaxial layer 2 form PN junction）Bear pressure-resistant
Outside, the polysilicon 12 in the second class groove 11 can equally be born pressure-resistant, in the second conduction type well region 13 and polysilicon
12 common resistance to pressure, electric field can be uniformly distributed in terminal protection area, and this point can significantly improve the resistance to of terminal protection area
Pressure energy power.
The utility model and embodiments thereof are described above, this describe it is no restricted, shown in accompanying drawing
Also it is one of embodiment of the present utility model, practical structures are not limited thereto.All in all if this area it is common
Technical staff is enlightened by it, in the case where not departing from the utility model and creating objective, without designing and the skill for creativeness
The similar frame mode of art scheme and embodiment, all should belong to the scope of protection of the utility model.
Claims (5)
1. a kind of trench-type power semiconductor device for optimizing terminal structure, including cellular region and terminal protection area, the cellular
Area is located at the center of device, and the terminal protection area is looped around around cellular region, and the cellular region includes several cellulars
Unit, the cellular unit include semiconductor substrate, and the semiconductor substrate includes the first conductivity type substrate（1）And positioned at
One conductivity type substrate（1）On the first conductive type epitaxial layer（2）, first conductive type epitaxial layer（2）It is provided with the
A kind of groove（3）, the first kind groove（3）It is interior to be provided with grid oxide layer（4）, the grid oxide layer（4）Be provided with the groove of formation by
The grid polycrystalline silicon that conductive polycrystalline silicon is formed（5）, in two neighboring first kind groove（3）Between the first conductive type epitaxial layer
（2）Surface be provided with the second conductivity type body region（6）, second conductivity type body region（6）It is interior to be provided with the conduction of heavy doping second
Type source region（7）With heavy doping the first conduction type source region（8）, and heavy doping the first conduction type source region（8）Led positioned at second
Electric type source region（7）Both sides, the first kind groove（3）With the second conductivity type body region（6）Top is provided with insulating medium layer
（9）, the insulating medium layer（9）It is provided with source metal（10）With gate bus metal（14）, the source metal（10）Wear
Cross insulating medium layer（9）Interior through hole and the second conductivity type body region（6）Interior heavy doping the first conduction type source region（8）, again
Adulterate the second conduction type source region（7）Contact, the gate bus metal（14）It is looped around source metal（10）Around, described the
One conductivity type substrate（1）Decentralization is provided with drain metal（15）；The terminal protection area includes the first conductivity type substrate（1）And
Positioned at the first conductivity type substrate（1）On the first conductive type epitaxial layer（2）, it is characterised in that：First conduction type
Epitaxial layer（2）It is provided with least one second class groove（11）, the second class groove（11）Outside first conduction type of both sides
Prolong layer（2）Surface be sequentially provided with the second conductivity type body region（6）And insulating medium layer（9）, the first kind groove（3）With
Two class grooves（11）Between the second conductivity type body region（6）It is interior to be provided with heavy doping the second conduction type source region（7）, the source electrode gold
Category（10）Through insulating medium layer（9）On through hole and the second conduction type of heavy doping source region（7）Contact, second class
Groove（11）It is interior to be provided with oxide layer（16）, in oxide layer（16）Covered with polysilicon on the trenched side-wall of formation（12）, and side wall
Polysilicon（12）Between pass through insulating medium layer（9）Insulation, the second described class groove（11）Lower section is provided with the second conduction type
Well region（13）.
A kind of 2. trench-type power semiconductor device for optimizing terminal structure according to claim 1, it is characterised in that：It is right
In N-type trench-type power semiconductor device, first conduction type is that N-type is conductive, and second conduction type is led for p-type
Electricity；For p-type trench-type power semiconductor device, first conduction type is P-type conduction, and second conduction type is N
Type is conductive.
A kind of 3. trench-type power semiconductor device for optimizing terminal structure according to claim 1, it is characterised in that：Institute
State the second class groove（11）Width be more than first kind groove（3）.
A kind of 4. trench-type power semiconductor device for optimizing terminal structure according to claim 1, it is characterised in that：Institute
State the second class groove（11）Interior polysilicon（12）It is floating, it is not necessary to which metal is drawn.
A kind of 5. trench-type power semiconductor device for optimizing terminal structure according to claim 1, it is characterised in that：Institute
It is mos field effect transistor or insulated gate bipolar transistor to state trench-type power semiconductor device.
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| CN201720877752.5U CN206976353U (en) | 2017-07-19 | 2017-07-19 | A kind of channel-type semiconductor device for optimizing terminal structure |
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| CN201720877752.5U CN206976353U (en) | 2017-07-19 | 2017-07-19 | A kind of channel-type semiconductor device for optimizing terminal structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| CN109148569A (en) * | 2018-08-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Groove type double-layer gate MOSFET and its manufacturing method |
| WO2020114073A1 (en) * | 2018-12-03 | 2020-06-11 | 珠海格力电器股份有限公司 | Insulated gate bipolar transistor and preparation method therefor, and electrical device |
-
2017
- 2017-07-19 CN CN201720877752.5U patent/CN206976353U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| CN107204372B (en) * | 2017-07-19 | 2023-06-06 | 无锡新洁能股份有限公司 | Trench type semiconductor device with optimized terminal structure and manufacturing method |
| CN109148569A (en) * | 2018-08-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Groove type double-layer gate MOSFET and its manufacturing method |
| WO2020114073A1 (en) * | 2018-12-03 | 2020-06-11 | 珠海格力电器股份有限公司 | Insulated gate bipolar transistor and preparation method therefor, and electrical device |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20180206 Effective date of abandoning: 20230606 |