CN106098777A - A kind of splitting bar accumulation type DMOS device - Google Patents
A kind of splitting bar accumulation type DMOS device Download PDFInfo
- Publication number
- CN106098777A CN106098777A CN201610456967.XA CN201610456967A CN106098777A CN 106098777 A CN106098777 A CN 106098777A CN 201610456967 A CN201610456967 A CN 201610456967A CN 106098777 A CN106098777 A CN 106098777A
- Authority
- CN
- China
- Prior art keywords
- type
- doped region
- district
- oxide layer
- grid electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009825 accumulation Methods 0.000 title claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 2
- 230000009514 concussion Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 8
- 230000012010 growth Effects 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- -1 Fig. 7 Chemical compound 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention belongs to power semiconductor technologies field, relate to a kind of splitting bar accumulation type DMOS device.The present invention essentially consists in by introducing accumulation type region, reduces threshold voltage and conducting resistance；Meanwhile, the advantage that the present invention has Split gate structure.Use the present invention can have the characteristics such as bigger forward current, less threshold voltage, less conducting resistance and the concussion of the higher anti-drain voltage ability on grid impact.
Description
Technical field
The invention belongs to power semiconductor technologies field, relate to a kind of splitting bar accumulation type DMOS device.
Background technology
The development of power MOS (Metal Oxide Semiconductor) device is on the basis of MOS device its own advantages, makes great efforts to improve pressure and fall is low-loss
Process.
VDMOSFET is a kind of planar structure using double diffusion technique, and it is the power of first Successful commercial application
MOSFET, the development to power MOSFET serves crucial impetus.In VDMOSFET structure, it is not necessary to expensive covers
Template but by control two knot the degree of depth formed raceway grooves.But due to the existence in its internal JFET district, make leading of VDMOSFET
Energising resistance is relatively big, this also development for grooved gate power device provide chance.Trench MOSFET structure uses U-shaped groove knot
Structure, conducting channel is longitudinal channel, the same with VDMOSFET, and Trench MOSFET is also high cellular density device, but
Trench MOSFET eliminates JFET district resistance, so its conducting resistance is less, this makes it the most welcome.
In low pressure and ultralow pressure direction, drain-source on state resistance (specific on-resistance) Rds (on) and unit
Area gate charge Qg is two important parameters.Reduce source and drain on state resistance and advantageously reduce on-state loss, reduce gate charge
Then advantageously reduce switching loss.But, now it is difficult to two parameters are the most significantly optimized, this is because with existing
Some technique, optimizes any one parameter therein and another parameter will be brought certain adverse influence.In order to improve
The performance of DMOS, proposes the new structure such as chinampa unipolar device and grid dividing structure (Split-gate) both at home and abroad.Chinampa one pole
Device is by increasing p-type dividing potential drop island in N-epitaxial layer, thus the maximum field of drift region is divided into two parts, outside same
Prolonging under layer doping content, breakdown voltage can rise.And Split-gate structure can utilize its ground floor polycrystal layer
(Shield) electric field of drift region is reduced as " internal field plate ", so Split-gate structure is generally of lower conducting
Resistance and higher breakdown voltage, and can be used for the TRENCH MOS product of high voltage (20V-250V).
Although the new structures such as chinampa unipolar device and grid dividing structure (Split-gate) are optimizing conducting resistance and grid electricity
Lotus aspect achieves bigger progress.But in recent years, the fierce market competition is more and more higher to the performance requirement of device, so
The MOSFET structure design how using advanced person reduces device R ds (on) simultaneously and Qg remains the direction that each producer makes great efforts.
Summary of the invention
To be solved by this invention, it is simply that for the problems referred to above, a kind of splitting bar accumulation type DMOS device is proposed.
The technical scheme is that as it is shown in figure 1, a kind of splitting bar accumulation type DMOS device, including depending on from bottom to up
Metalized drain 1, N+ substrate 2, N-drift region 3 and the metallizing source 11 that secondary stacking is arranged；Described N-drift region 3 has oxygen
Change floor 6, bar shaped N-type is lightly doped district 7, p-type doped region 8, P+ heavily doped region 9 and N+ heavily doped region 10；Described oxide layer 6 is positioned at
The N-type of both sides is lightly doped between district 7 and N+ heavily doped region 10, and the upper surface of oxide layer 6 contacts with metallizing source 11；Described N
+ heavily doped region 10 is positioned at N-type and the surface in district 7 is lightly doped and district 7 is lightly doped with N-type contacts, the upper table of N+ heavily doped region 10
Face contacts with metallizing source 11；Described N-type is lightly doped district 7 and contacts with p-type doped region 8 away from the side of oxide layer, and p-type is mixed
The junction depth that the junction depth in miscellaneous district 8 is lightly doped district 7 with N-type is identical, and described P+ heavily doped region 9 is positioned at the surface of p-type doped region 8 also
Contacting with p-type doped region 8, the upper surface of P+ heavily doped region 9 contacts with metallizing source 11；Described oxide layer 6 has control
Gate electrode 4 and shield grid electrode 5, described control grid electrode 4 is positioned at the top of shield grid electrode 5, table on described control grid electrode 4
The junction depth in face is lightly doped district 7 less than the junction depth of N+ heavily doped region 10 lower surface, the junction depth of control grid electrode 4 lower surface more than N-type
The junction depth of lower surface.
Further, the material that described oxide layer 6 uses is silicon dioxide or silicon dioxide and the composite wood of silicon nitride
Material.
Further, the material that described control grid electrode 4 and shield grid electrode 5 use is polysilicon.
Beneficial effects of the present invention is, compared to traditional structure, the structure of the present invention has bigger forward current, less
Threshold voltage, less conducting resistance and the higher anti-drain voltage concussion characteristic such as ability on grid impact.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the splitting bar accumulation type DMOS device of the present invention；
Fig. 2 be the splitting bar accumulation type DMOS device of the present invention when additional no-voltage, exhaust line schematic diagram；
Fig. 3 is the current path signal during splitting bar accumulation type DMOS device applied voltage arrival threshold voltage of the present invention
Figure；
Fig. 4-Figure 12 is the schematic diagram of a kind of manufacturing process flow of the splitting bar accumulation type DMOS device of the present invention；
Figure 13-Figure 21 is the schematic diagram of the another kind of manufacturing process flow of the splitting bar accumulation type DMOS device of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical scheme is described in detail:
As it is shown in figure 1, a kind of splitting bar accumulation type DMOS device that the present invention proposes, set including stacking gradually from bottom to up
Metalized drain 1, N+ substrate 2, N-drift region 3 and the metallizing source 11 put；Described N-drift region 3 have oxide layer 6, bar
Shape N-type is lightly doped district 7, p-type doped region 8, P+ heavily doped region 9 and N+ heavily doped region 10；Described oxide layer 6 is positioned at the N-of both sides
Type is lightly doped between district 7 and N+ heavily doped region 10, and the upper surface of oxide layer 6 contacts with metallizing source 11；Described N+ heavy doping
District 10 is positioned at N-type and the surface in district 7 is lightly doped and district 7 is lightly doped with N-type contacts, the upper surface of N+ heavily doped region 10 and metal
Change source electrode 11 to contact；Described N-type is lightly doped district 7 and contacts with p-type doped region 8 away from the side of oxide layer, the knot of p-type doped region 8
The junction depth that district 7 is deeply lightly doped with N-type is identical, and described P+ heavily doped region 9 is positioned at the surface of p-type doped region 8 and adulterates with p-type
District 8 contacts, and the upper surface of P+ heavily doped region 9 contacts with metallizing source 11；Described oxide layer 6 has control grid electrode 4 He
Shield grid electrode 5, described control grid electrode 4 is positioned at the top of shield grid electrode 5, the junction depth of described control grid electrode 4 upper surface
Less than the junction depth of N+ heavily doped region 10 lower surface, the junction depth of control grid electrode 4 lower surface is lightly doped district 7 lower surface more than N-type
Junction depth.
The operation principle of the present invention is:
Splitting bar accumulation type DMOS device provided by the present invention, electrode connection mode during its forward conduction is: control
Gate electrode 4 connects positive potential, and metalized drain 1 connects positive potential, metallizing source 11 connecting to neutral current potential.When control grid electrode 4 is zero electricity
When pressure or added positive voltage are the least, the doping content in district 7, P are lightly doped owing to the doping content of p-type doped region 8 is more than N-type
Type doped region 8 and N-type are lightly doped the Built-in potential of the PN junction that district 7 is constituted can make p-type doped region 8 and silicon dioxide gate oxygen
N-type between change floor 6 is lightly doped district 7 and exhausts, and electron channel is blocked, as in figure 2 it is shown, now accumulation type DMOS is still in pass
Closed state.
Along with the increase of positive voltage added by control grid electrode 4, p-type doped region 8 and N-type are lightly doped the PN junction that district 7 is constituted
Built-in barrier region be gradually reduced.Owing to N-type is lightly doped the existence in district 7, device is easier to open, thus reduces threshold value electricity
Pressure.After positive voltage added by control grid electrode 4 is equal to or more than cut-in voltage, at silicon dioxide oxide layer 6 side
N-type produces the accumulation layer of how sub-electronics in district 7 is lightly doped, this be that the flowing of many electron currents provides a low impedance path, as schemed
Shown in 3, now accumulation type DMOS conducting, how sub-electronics flows from N+ heavily doped region 10 under the effect of metalized drain 1 positive potential
To metalized drain 1.Further, since the effect of shield grid electrode 5, gate leakage capacitance Cgd some be coupled as gate-source capacitance
Cgs, so this structure has higher input capacitance (Ciss) and " Miller " electric capacity (Cgd) ratio, thus has higher
The anti-drain voltage concussion ability on grid impact.
The splitting bar accumulation type DMOS device of the present invention, electrode connection mode during its reverse blocking is: control grid electrode 4
With metallizing source 11 short circuit and connecting to neutral current potential, metalized drain 1 connects positive potential.
Owing to during zero-bias, N-type between p-type doped region 8 and oxide layer 6 is lightly doped district 7 and has been completely depleted, how son
The conductive path of electronics is by pinch off.When increasing backward voltage, depletion layer boundaries is by the N-drift near metalized drain 1 side
District 3 extends to bear backward voltage.Compared with common grooved DMOS, in the case of N-drift region 3 doping content is identical, by
Electric charge can be realized in the existence of shield grid electrode 5, the N-drift region 3 of the accumulation type DMOS with Split-gate structure to put down
Weighing apparatus, forms transverse electric field, and drift region electric field is improved.When breakdown voltage is identical, there is the accumulation of Split-gate structure
The conducting resistance of type DMOS is less, and gate leak current is less.
A kind of manufacturing process flow of the splitting bar accumulation type DMOS device shown in the present invention is:
1 monocrystal silicon prepares and epitaxial growth；Such as Fig. 4, using N-type heavy doping monocrystalline substrate 2, crystal orientation is<100>.Use
Method growth certain thickness and the N-drift regions 3 of doping content such as vapour phase epitaxy VPE；
2 ion implantings；Such as Fig. 5, utilize photolithography plate to carry out PXing Zhu district boron and inject, form p-type doped region 8, carry out N-type post
District's phosphorus injects, and the implantation dosage of phosphorus should be relatively low herein, forms N-type and district 7 is lightly doped；
3 cuttings；Such as Fig. 6, deposit the hard mask (such as the silicon nitride) barrier layer as follow-up grooving, utilize photolithography plate to carry out deeply
Groove etched, etch groove grid region, concrete etching technics can use reactive ion etching or plasma etching；
The filling of 4 silicon dioxide；Such as Fig. 7, remove hard mask, in groove, grow thick silicon dioxide layer 6；
The deposit of 5 polysilicons and etching；Such as Fig. 8, deposition gate polysilicon 5；Utilize photolithography plate carve fall thick oxide layer and
The top half of shield grid polysilicon；
6 thermal oxide layer growths；Such as Fig. 9, groove grid region is carried out oxide layer thermally grown, form sidewall gate oxide and shield grid
The oxide layer at top；
The deposit of 7 polysilicons and etching；Such as Figure 10, depositing control gate polysilicon 4, the thickness of polysilicon to guarantee to fill out
Tankful type region；Utilize photolithography plate to control gate etching polysilicon, and above control gate polysilicon deposit silicon dioxide, etching
Surface silica dioxide；
8 ion implantings；Such as Figure 11, p-type heavily doped region boron injects, and forms P+ heavily doped region 9, and N-type heavily doped region arsenic injects,
Form N+ heavily doped region 10；
9 metallization；Such as Figure 12, front-side metallization, metal etch, back face metalization, passivation etc..
The another kind of manufacturing process flow of the splitting bar accumulation type DMOS device shown in the present invention is:
1 monocrystal silicon prepares and epitaxial growth；Such as Figure 13, using N-type heavy doping monocrystalline substrate 2, crystal orientation is<100>.Adopt
With method growth certain thickness and the N-drift regions 3 of doping content such as vapour phase epitaxies VPE；
2 cuttings；Such as Figure 14, deposit the hard mask (such as the silicon nitride) barrier layer as follow-up grooving, utilize photolithography plate to carry out
Deep etching, etches groove grid region, and concrete etching technics can use reactive ion etching or plasma etching；
The filling of 3 silicon dioxide；Such as Figure 15, remove hard mask, in groove, grow thick silicon dioxide layer 6；
The deposit of 4 polysilicons and etching；Such as Figure 16, deposition gate polysilicon 5.Utilize photolithography plate carve fall thick oxide layer and
The top half of shield grid polysilicon；
5 thermal oxide layer growths；Such as Figure 17, groove grid region is carried out oxide layer thermally grown, form sidewall gate oxide and shielding
The oxide layer at grid top；
The deposit of 6 polysilicons and etching；Such as Figure 18, depositing control gate polysilicon 4, the thickness of polysilicon to guarantee to fill out
Tankful type region.Utilize photolithography plate to control gate etching polysilicon, and above control gate polysilicon deposit silicon dioxide, etching
Surface silica dioxide；
7 diffusing, dopings；Such as Figure 19, utilize photolithography plate to carry out PXing Zhu district diffusing, doping, form p-type doped region 8, carry out N-type
Post district diffusing, doping, the dopant dose of phosphorus should be relatively low herein, forms N-type and district 7 is lightly doped；
8 ion implantings；Such as Figure 20, p-type heavily doped region boron injects, and forms P+ heavily doped region 9, and N-type heavily doped region arsenic injects,
Form N+ heavily doped region 10；
9 metallization；Such as Figure 21, front-side metallization, metal etch, back face metalization, passivation etc..
During making devices, can also be used with the semi-conducting materials such as carborundum, GaAs or germanium silicon and substitute body silicon.
Use the accumulation type DMOS with Split-gate structure provided by the present invention, have bigger forward current,
Less threshold voltage, less conducting resistance and the concussion of higher anti-drain voltage are on characteristics such as the abilities that grid affects.
Claims (3)
1. a splitting bar accumulation type DMOS device, including the metalized drain (1) being cascading from bottom to up, N+ substrate
(2), N-drift region (3) and metallizing source (11)；Have oxide layer (6) in described N-drift region (3), bar shaped N-type is lightly doped
District (7), p-type doped region (8), P+ heavily doped region (9) and N+ heavily doped region (10)；Described oxide layer (6) is positioned at the N-type of both sides
Being lightly doped between district (7) and N+ heavily doped region (10), the upper surface of oxide layer (6) contacts with metallizing source (11)；Described N+
Heavily doped region (10) is positioned at N-type and the surface in district (7) is lightly doped and district (7) is lightly doped with N-type contacts, N+ heavily doped region (10)
Upper surface contact with metallizing source (11)；Described N-type is lightly doped the district (7) side and p-type doped region away from oxide layer
(8) contact, the junction depth that the junction depth of p-type doped region (8) is lightly doped district (7) with N-type is identical, and described P+ heavily doped region (9) is positioned at P
The surface of type doped region (8) also contacts with p-type doped region (8), the upper surface of P+ heavily doped region (9) and metallizing source (11)
Contact；Having control grid electrode (4) and shield grid electrode (5) in described oxide layer (6), described control grid electrode (4) is positioned at screen
Covering the top of gate electrode (5), the junction depth of described control grid electrode (4) upper surface is less than the knot of N+ heavily doped region (10) lower surface
Deeply, the junction depth of control grid electrode (4) lower surface is lightly doped the junction depth of district (7) lower surface more than N-type.
A kind of splitting bar accumulation type DMOS device the most according to claim 1, it is characterised in that described oxide layer (6) is adopted
Material be silicon dioxide or silicon dioxide and the composite of silicon nitride.
A kind of splitting bar accumulation type DMOS device the most according to claim 1, it is characterised in that described control grid electrode
And the material that uses of shield grid electrode (5) is polysilicon (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610456967.XA CN106098777A (en) | 2016-06-22 | 2016-06-22 | A kind of splitting bar accumulation type DMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610456967.XA CN106098777A (en) | 2016-06-22 | 2016-06-22 | A kind of splitting bar accumulation type DMOS device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106098777A true CN106098777A (en) | 2016-11-09 |
Family
ID=57238922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610456967.XA Pending CN106098777A (en) | 2016-06-22 | 2016-06-22 | A kind of splitting bar accumulation type DMOS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106098777A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731926A (en) * | 2017-10-24 | 2018-02-23 | 贵州芯长征科技有限公司 | Improve MOSFET element of pressure-resistant scope and preparation method thereof |
| CN107731908A (en) * | 2017-10-24 | 2018-02-23 | 贵州芯长征科技有限公司 | Improve pressure-resistant shield grid MOSFET structure and preparation method thereof |
| CN109860303A (en) * | 2019-03-26 | 2019-06-07 | 电子科技大学 | A kind of insulated-gate power device of accumulation type channel |
| CN109979823A (en) * | 2017-12-28 | 2019-07-05 | 深圳尚阳通科技有限公司 | A kind of shield grid power device and manufacturing method |
| CN110010692A (en) * | 2019-04-28 | 2019-07-12 | 电子科技大学 | A kind of power semiconductor and its manufacturing method |
| WO2022237112A1 (en) * | 2021-05-11 | 2022-11-17 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207154A (en) * | 2006-12-22 | 2008-06-25 | 万国半导体股份有限公司 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
| US20080179668A1 (en) * | 2007-01-30 | 2008-07-31 | Alpha & Omega Semiconductor, Ltd | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET |
| CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
-
2016
- 2016-06-22 CN CN201610456967.XA patent/CN106098777A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207154A (en) * | 2006-12-22 | 2008-06-25 | 万国半导体股份有限公司 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
| US20080179668A1 (en) * | 2007-01-30 | 2008-07-31 | Alpha & Omega Semiconductor, Ltd | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET |
| CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731926A (en) * | 2017-10-24 | 2018-02-23 | 贵州芯长征科技有限公司 | Improve MOSFET element of pressure-resistant scope and preparation method thereof |
| CN107731908A (en) * | 2017-10-24 | 2018-02-23 | 贵州芯长征科技有限公司 | Improve pressure-resistant shield grid MOSFET structure and preparation method thereof |
| CN107731926B (en) * | 2017-10-24 | 2020-09-25 | 贵州芯长征科技有限公司 | MOSFET device with improved voltage withstanding range and preparation method thereof |
| CN107731908B (en) * | 2017-10-24 | 2020-09-25 | 贵州芯长征科技有限公司 | Shielding gate MOSFET structure for improving voltage resistance and preparation method thereof |
| CN109979823A (en) * | 2017-12-28 | 2019-07-05 | 深圳尚阳通科技有限公司 | A kind of shield grid power device and manufacturing method |
| CN109860303A (en) * | 2019-03-26 | 2019-06-07 | 电子科技大学 | A kind of insulated-gate power device of accumulation type channel |
| CN110010692A (en) * | 2019-04-28 | 2019-07-12 | 电子科技大学 | A kind of power semiconductor and its manufacturing method |
| WO2022237112A1 (en) * | 2021-05-11 | 2022-11-17 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106098777A (en) | A kind of splitting bar accumulation type DMOS device | |
| US8519476B2 (en) | Method of forming a self-aligned charge balanced power DMOS | |
| CN109920854B (en) | MOSFET device | |
| CN110148629B (en) | Groove type silicon carbide MOSFET device and preparation method thereof | |
| CN106158973A (en) | A kind of accumulation type DMOS | |
| CN111668312B (en) | Low-on-resistance trench silicon carbide power device and manufacturing process thereof | |
| CN107204372A (en) | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure | |
| CN106298939A (en) | A kind of accumulation type DMOS with complex media Rotating fields | |
| CN109119461B (en) | Super-junction MOS type power semiconductor device and preparation method thereof | |
| CN102364688A (en) | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) | |
| CN105932051A (en) | Grooved gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) device | |
| CN110504310A (en) | A kind of RET IGBT and preparation method thereof with automatic biasing PMOS | |
| CN109904220A (en) | Groove gate type silicon carbide MOSFET device and preparation method | |
| CN105977302A (en) | Grooved gate MOS having buried layer structure | |
| CN109119463A (en) | A kind of lateral trench type MOSFET element and preparation method thereof | |
| CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
| CN206976353U (en) | A kind of channel-type semiconductor device for optimizing terminal structure | |
| CN107785433B (en) | Stepped high-K dielectric layer wide band gap semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor | |
| CN105845718B (en) | A kind of 4H-SiC trench-type insulated gate bipolar transistor | |
| CN110416295B (en) | Groove-type insulated gate bipolar transistor and preparation method thereof | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN105957894A (en) | DMOS with composite dielectric layer structure | |
| CN109920838B (en) | Groove type silicon carbide MOSFET device and preparation method thereof | |
| CN103117309A (en) | Horizontal power device structure and preparation method thereof | |
| CN106057906B (en) | A kind of accumulation type DMOS with p type buried layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161109 |