CN107731926A - Improve MOSFET element of pressure-resistant scope and preparation method thereof - Google Patents
Improve MOSFET element of pressure-resistant scope and preparation method thereof Download PDFInfo
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- CN107731926A CN107731926A CN201710997677.0A CN201710997677A CN107731926A CN 107731926 A CN107731926 A CN 107731926A CN 201710997677 A CN201710997677 A CN 201710997677A CN 107731926 A CN107731926 A CN 107731926A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 230000001413 cellular effect Effects 0.000 claims abstract description 180
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 144
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims description 112
- 239000010410 layer Substances 0.000 claims description 107
- 239000002184 metal Substances 0.000 claims description 51
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 4
- 210000005056 cell body Anatomy 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005090 crystal field Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The present invention relates to a kind of MOSFET element and preparation method thereof, especially a kind of MOSFET element for improving pressure-resistant scope and preparation method thereof, belong to the technical field of semiconductor devices.The active cellular of cellular region uses groove structure; some terminal trenches are set in terminal protection area; the depth of terminal trenches is more than the depth of cellular groove, and the terminal trenches conductive polycrystalline silicon is dielectrically separated from by the side wall and bottom wall of terminal trenches insulating oxide and terminal trenches；The terminal trenches of neighbouring cellular region contact with the second conduction type base region of the outer top of the cellular trenched side-wall of adjacent terminals protection zone, can effectively improve pressure-resistant scope, compatible with existing process, securely and reliably.
Description
Technical field
The present invention relates to a kind of MOSFET element and preparation method thereof, especially a kind of MOSFET devices for improving pressure-resistant scope
Part and preparation method thereof, belong to the technical field of semiconductor devices.
Background technology
VDMOSFET (high-voltage power MOSFET) can reduce conducting resistance by the way that the thickness of drain terminal drift region is thinned, so
And the thickness that drain terminal drift region is thinned will reduce the breakdown voltage of device, therefore in VDMOSFET, improve the breakdown of device
Voltage and the conducting resistance for reducing device are conflicts, and shield grid MOSFET structure is vertical using introducing two in groove
More crystal field versions, this not only causes device to introduce two new peak electric fields in drift region, increases the breakdown potential of device
Press (BV), and cause device vertically leaks to form one layer of bigger accumulation layer of concentration around field plate, reduce conducting resistance.By
Existing vertical field plate causes the gate drain capacitance value for influenceing devices switch speed between this new device longitudinal direction grid, leakage field plate
Be partially converted into device gate-source capacitance and drain source capacitance so that N-type region realizes high breakdown potential under high-dopant concentration
Pressure, so as to obtain low on-resistance and high-breakdown-voltage simultaneously, the theoretical limit for the power MOSFET ON resistance that breaks traditions.
Shield grid MOSFET structure has conduction loss low, and gate charge is low, and switching speed is fast, and device heating is small, efficiency
The advantages of high, product can be widely used for PC, notebook computer, net book or mobile phone, illumination (high-voltage gas discharging light)
The power supply or adapter of the high-end consumption electronic product such as product and television set (liquid crystal or plasma TV) and game machine.
Tied for shield grid MOSFET, it is pressure-resistant mainly to be undertaken by the thick oxygen post of the grid structure below deep groove structure,
But the limitation of technological ability, often limit the development continued toward high pressure/super-pressure direction.
Therefore it provides a kind of shield grid MOSFET structure and preparation method thereof, further to lift high-voltage MOSFET device
Voltage endurance capability is necessary.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of MOSFET devices for improving pressure-resistant scope
Part, its is compact-sized, can effectively improve pressure-resistant scope, compatible with existing process, securely and reliably.
According to technical scheme provided by the invention, the MOSFET element for improving pressure-resistant scope, including positioned at semiconductor
Cellular region and terminal protection area on substrate, cellular region are located at the center of semiconductor substrate, and terminal protection area is located at cellular
The outer ring and terminal protection area in area are around encirclement cellular region；The semiconductor substrate includes the first conductivity type substrate and is located at
The first conduction type drift layer above first conductivity type substrate；Active cellular in cellular region uses groove structure,
Trench gate structure is set in cellular groove；Top is provided with the second conduction type base region outside the cellular trenched side-wall, described
Second conduction type base region is located in the first conduction type drift layer and contacted with corresponding cellular trenched side-wall；In adjacent cellular
Be respectively provided with the first conduction type source region between groove in second conduction type base region of the outer top of side wall, the first conduction type source region with
The side wall contact of corresponding cellular groove；
Some terminal trenches are set in terminal protection area, the terminal trenches are located in the first conduction type drift layer,
Depth of the terminal trenches in the first conduction type drift layer is more than depth of the cellular groove in the first conduction type drift layer；
Terminal conductive polycrystalline silicon is set in terminal trenches, and the terminal trenches conductive polycrystalline silicon passes through terminal trenches insulating oxide and end
The side wall and bottom wall for holding groove are dielectrically separated from；The terminal trenches and the cellular channel side of adjacent terminals protection zone of neighbouring cellular region
The second conduction type base region contact of the outer top of wall.
Trench gate structure in the cellular groove includes shielded gate structures, and the shielded gate structures include lower floor in groove
Upper strata polysilicon body in polysilicon body and groove, the outer ring of lower floor's polysilicon body passes through lower insulation oxygen in groove in the groove
The side wall and bottom wall for changing layer and cellular groove are dielectrically separated from, and the outer ring of upper strata polysilicon body is insulated by upper in groove in groove
Oxide layer is dielectrically separated from lower floor's polysilicon body in the side wall and groove of cellular groove, the width of upper strata polysilicon body in groove
More than the width of lower floor's polysilicon body in groove；
Gate metal Ohmic contact in groove above upper strata polysilicon body and the first conduction type drift layer, in groove under
Source metal Ohmic contact above layer polysilicon body and the first conduction type drift layer；The source metal also with adjacent cellular
Second conduction type base region of the outer top of side wall and the first conductive-type in second conduction type base region between groove
Type source region Ohmic contact.
The depth of the cellular groove is 3 μm~6 μm, lower insulation oxygen in the thickness and groove of terminal trenches insulating oxide
The thickness for changing layer is consistent.
The first conduction type auxiliary layer is provided with the first conductivity type substrate and the first conduction type drift interlayer, described the
One conduction type auxiliary layer abuts the first conductivity type substrate and the first conduction type drift layer, the first conduction type auxiliary respectively
The thickness of layer is 10 μm~20 μm.
A kind of preparation method for the MOSFET element for improving pressure-resistant scope, the preparation method of the MOSFET element are included such as
Lower step：
Step 1, the semiconductor substrate with the first conduction type is provided, the semiconductor substrate includes the first conduction type
Substrate and the first conduction type drift layer above first conductivity type substrate；Optionally shelter and etch the
One conduction type drift layer, to obtain required cellular groove and terminal secondary trenches in the first conduction type drift layer；
Step 2, above-mentioned terminal secondary trenches are etched again, to obtain required terminal trenches, the terminal ditch
The depth of groove is more than the depth of cellular groove, and the depth of terminal trenches is less than the thickness of the first conduction type drift layer；
Step 3, required trench gate preparatory technology is carried out to above-mentioned cellular groove, it is required to be obtained in cellular groove
Trench gate structure, and when trench gate structure is prepared, terminal conductive polycrystalline silicon, the terminal ditch are obtained in terminal trenches
Groove conductive polycrystalline silicon is dielectrically separated from by the side wall and bottom wall of terminal trenches insulating oxide and terminal trenches；
Step 4, the injection of the second conductive type impurity ion, expansion are carried out in the top of above-mentioned first conduction type drift layer
The second required conduction type base region is formed in the both sides of cellular groove after dissipating, the second conduction type base region connects with cellular groove
Touch, the terminal trenches of neighbouring cellular region and the second conduction type base region of the outer top of the cellular trenched side-wall of adjacent terminals protection zone
Contact；
Step 5, the injection for carrying out above above-mentioned first conduction type drift layer the first conductive type impurity ion, with
It is conductive to the first conduction type source region between adjacent cellular groove outside side wall in the second conduction type base region of top, first
Type source region contacts with the side wall of corresponding cellular groove；
Step 6, the deposited metal above above-mentioned first conduction type drift layer, to obtain floating positioned at the first conduction type
The source metal and gate metal moved above layer, the source metal and the first conduction type source region and first conductive-type
The second conduction type base region Ohmic contact where type source region, gate metal electrically connect with the trench gate structure in cellular groove.
In step 3, when the trench gate structure of preparation is shielded gate structures, specific embodiment comprises the following steps：
Step 3-1, first groove insulating oxide is set simultaneously in cellular groove, terminal trenches, in cellular groove
First groove insulating oxide covers the side wall and bottom wall of cellular groove, and the first groove insulating oxide in terminal trenches covers
The side wall and bottom wall of lid terminal trenches, and after first groove insulating oxide is set, the first polycrystalline is formed in cellular groove
Silicon fills hole, and terminal trenches polysilicon filling hole is formed in terminal trenches；
Step 3-2, conductive polycrystalline silicon deposit is carried out above above-mentioned first conduction type drift layer, to obtain filling up first
Polysilicon fills the cellular polysilicon obturator in hole, and fills up the terminal conductive polycrystalline silicon in terminal trenches polysilicon filling hole；
First groove insulating oxide corresponding with terminal conductive polycrystalline silicon forms terminal trenches insulating oxide；
Step 3-3, above-mentioned cellular polysilicon obturator is performed etching, to obtain in the groove in cellular groove
Lower floor's polysilicon body and the etching positioning hole directly over lower floor's polysilicon body in the groove；
Step 3-4, the first groove insulating oxide of cellular groove internal upper part is carried out using above-mentioned etching positioning hole complete
Etching, to obtain lower insulating oxide and the lower floor in the groove in groove corresponding with lower floor's polysilicon body in groove
Upper tank body directly over polysilicon body, the width of upper tank body are consistent with the width of cellular groove；
Second groove insulating oxide, the covering of second groove insulating oxide are set step 3-5, in above-mentioned upper tank body
The side wall of upper tank body and bottom, the filling of the second polysilicon is formed after second groove insulating oxide is set in upper tank body
Hole；
Step 3-6, conductive polycrystalline silicon filling is carried out in above-mentioned second polysilicon filling hole, to obtain filling up the second polycrystalline
Upper strata polysilicon body in the groove in silicon filling hole, second groove insulating oxide corresponding with upper strata polysilicon body in groove are formed
Upper insulating oxide in groove, in groove upper strata polysilicon body by the side wall of upper insulating oxide in groove and cellular groove with
And lower floor's polysilicon body is dielectrically separated from groove；The width of upper strata polysilicon body is more than lower floor's polysilicon body in groove in groove
Width；
Gate metal and upper strata polysilicon body Ohmic contact in groove, source metal and lower floor's polysilicon body ohm in groove
Contact.
The first conduction type auxiliary layer is provided with the first conductivity type substrate and the first conduction type drift interlayer, described the
One conduction type auxiliary layer abuts the first conductivity type substrate and the first conduction type drift layer, the first conduction type auxiliary respectively
The thickness of layer is 10 μm~20 μm.
The material of the semiconductor substrate includes silicon, and the depth of cellular groove is 3 μm~6 μm.
In both described " first conduction type " and " the second conduction type ", led for N-type power MOSFET device, first
Electric type refers to N-type, and the second conduction type is p-type；For p-type power MOSFET device, the first conduction type and the second conductive-type
The signified type of type and N-type semiconductor device contrast.
Advantages of the present invention：The active cellular of cellular region uses groove structure, and some terminal ditches are set in terminal protection area
Groove, the depth of terminal trenches are more than the depth of cellular groove, and the terminal trenches conductive polycrystalline silicon is insulated oxygen by terminal trenches
The side wall and bottom wall for changing layer and terminal trenches are dielectrically separated from；The terminal trenches and the member of adjacent terminals protection zone of neighbouring cellular region
The second conduction type base region contact of the outer top of born of the same parents' trenched side-wall, can effectively improve pressure-resistant scope, safety compatible with existing process
Reliably.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention.
Fig. 2~Figure 11 is specific implementation process step sectional view of the present invention, wherein
Fig. 2 obtains the sectional view after cellular groove and terminal secondary trenches for the present invention.
Fig. 3 obtains the sectional view after terminal trenches for the present invention.
Fig. 4 is that the present invention obtains the first polysilicon filling hole and terminal trenches polysilicon fills the sectional view behind hole.
Fig. 5 obtains the sectional view after cellular polysilicon obturator and terminal conductive polycrystalline silicon for the present invention.
Fig. 6 is that the present invention obtains etching the sectional view after positioning hole.
Fig. 7 obtains the sectional view after upper tank body for the present invention.
Fig. 8 is that the present invention obtains the sectional view behind the first polysilicon filling hole.
Fig. 9 obtains the sectional view in groove after the polysilicon body of upper strata for the present invention.
Figure 10 obtains the sectional view after N+ source regions for the present invention.
Figure 11 obtains the sectional view after source metal, gate metal for the present invention.
Description of reference numerals：201-N+ substrates, 202-N types auxiliary layer, 203-N types drift layer, lower in 204- grooves insulate
Lower floor's polysilicon body in oxide layer, 205- grooves, upper insulating oxide in 206- grooves, upper strata polysilicon body in 207- grooves,
208-P types base, 209-N+ source regions, 210- source metals, 211- gate metals, 212- cellulars groove, 213- terminal trenches,
214- terminal trenches insulating oxide, 215- terminals conductive polycrystalline silicon, 216- terminals secondary trenches, 217- first grooves insulation oxygen
Change layer, the polysilicons of 218- first filling hole, 219- terminal trenches polysilicon filling hole, 220- cellular polysilicons obturator, 221-
Etch positioning hole, 222- upper tank bodies and the polysilicons of 223- second filling hole.
Embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in Fig. 1 and Figure 11：In order to effectively improve pressure-resistant scope, by taking N-type MOSFET element as an example, the present invention includes
Cellular region and terminal protection area on semiconductor substrate, cellular region are located at the center of semiconductor substrate, terminal protection
Area is located at the outer ring of cellular region and terminal protection area is around encirclement cellular region；The semiconductor substrate include N+ substrates 201 and
N-type drift layer 203 above the N+ substrates 201；Active cellular in cellular region uses groove structure, in cellular groove
Trench gate structure is set in 212；Top is provided with p-type base 208, the p-type base 208 outside the side wall of cellular groove 212
Contacted in N-type drift layer 203 and with the corresponding side wall of cellular groove 212；The top outside adjacent 212 side walls of cellular groove
P-type base 208 in be respectively provided with N+ source regions 209, N+ source regions 209 contact with the side wall of corresponding cellular groove 212；
Some terminal trenches 213 are set in terminal protection area, the terminal trenches 213 are located in N-type drift layer 203,
Depth of the terminal trenches 213 in N-type drift layer 203 is more than depth of the cellular groove 212 in N-type drift layer 203；Terminal ditch
Terminal conductive polycrystalline silicon 215 is set in groove 213, and the terminal trenches conductive polycrystalline silicon 215 passes through terminal trenches insulating oxide
214 are dielectrically separated from the side wall and bottom wall of terminal trenches 213；The terminal trenches 213 of neighbouring cellular region are protected with adjacent terminals
The p-type base 208 of the outer top of the side wall of cellular groove 212 in area contacts.
Specifically, the material of semiconductor substrate can select silicon or other conventional semi-conducting materials, and cellular region is positioned at half
The center of conductor substrate, terminal protection area is around encirclement cellular region, the specific effect and distribution of cellular region, terminal protection area
Position is consistent with existing power MOSFET device, and here is omitted.The doping concentration of N+ substrates 201 is big in semiconductor substrate
In the doping concentration of N-type drift layer 203, the active cellular of cellular region uses groove structure, and cellular groove 213 is arranged at N-type drift
Move in layer 203.
Top is respectively provided with p-type base 208 outside each side wall of cellular groove 212, and p-type base 208 is from N-type drift layer 203
Upper surface extends vertically downward, and p-type base 208 contacts with the lateral wall of cellular groove 213.In adjacent 213 sides of cellular groove
N+ source regions 209 are just set in p-type base 208 above wall, N+ source regions 209 with place p-type base 208 and meanwhile with corresponding cellular
The wall contacts of groove 213.Therefore, for the cellular groove 213 of adjacent terminals protection zone, the cellular of the adjacent terminals protection zone
The cellular groove of adjacent cellular groove 213, i.e. adjacent terminals protection zone is not present in the side of the adjacent terminals protection zone of groove 213
N+ source regions 209 are not present in the p-type base 208 of 213 adjacent terminals protection zones side.
Some terminal trenches 213 are set in terminal protection area, and the quantity of terminal trenches 213 can be selected as needed
It is determined that.Terminal trenches 213 are located in N-type drift layer 203, and the notch of terminal trenches 213 is located at the 212 of cellular groove notch
In same level, the depth of terminal trenches 213 is more than depth of the cellular groove 212 in N-type drift layer 203, and respectively less than N
The thickness of type drift layer 203.Terminal trenches insulating oxide 214 and terminal conductive polycrystalline silicon body are set in terminal trenches 213
215, terminal conductive polycrystalline silicon 215 is insulated by the side wall and bottom wall of terminal trenches insulating oxide 214 and terminal trenches 213
Isolation.The terminal trenches 213 of neighbouring cellular region and the p-type base of the outer top of the side wall of cellular groove 212 of adjacent terminals protection zone
208 contact, and between remaining terminal trenches 213 independently of each other, and do not exist with cellular region and associate.Pass through terminal in terminal protection area
The setting of the depth of groove 213, terminal conductive polycrystalline silicon 215 and terminal trenches insulating oxide 214 can effectively improve pressure-resistant
Scope, the application field of MOSFET element obtained by expansion.
Terminal conductive polycrystalline silicon 214 and terminal trenches insulating oxide 214 in terminal trenches 213 form floating field plate and made
After being more than the depth of cellular groove 212 with the depth of, terminal trenches 213, it can make to be distributed in terminal trenches insulating oxide 214
Potential density reduce, so as to avoid electric field from concentrating, improve it is pressure-resistant.Generally, pressure-resistant more high electric field having lateral depletion is faster,
So need more terminal trenches 213.
Further, the trench gate structure in the cellular groove 212 includes shielded gate structures, the shielded gate structures bag
Include in groove upper strata polysilicon body 207 in lower floor's polysilicon body 205 and groove, lower floor's polysilicon body 205 in the groove
Outer ring is dielectrically separated from by the side wall and bottom wall of lower insulating oxide 204 and cellular groove 212 in groove, and upper strata is more in groove
The outer ring of crystal silicon body 207 passes through upper insulating oxide 206 in groove and lower floor's polycrystalline in the side wall and groove of cellular groove 212
Silicon body 205 is dielectrically separated from, and the width of upper strata polysilicon body 207 is more than the width of lower floor's polysilicon body 205 in groove in groove；
Upper strata polysilicon body 207 and the Ohmic contact of gate metal 211 of the top of N-type drift layer 203 in groove, under groove is interior
Layer polysilicon body 205 and the Ohmic contact of source metal 210 of the top of N-type drift layer 203；The source metal 210 also with it is adjacent
The p-type base 208 of the outer top of 212 side walls of cellular groove and 209 ohm of the N+ source regions in the p-type base 208 connect
Touch.
In the embodiment of the present invention, trench gate structure in cellular groove 212 can use shielded gate structures or other are conventional
Grid structure form, when using shield grid, including upper strata polysilicon body in lower floor's polysilicon body 205 and groove in groove
207, the width of upper strata polysilicon body 207 is more than the width of lower floor's polysilicon body 205 in groove in groove.Source metal 210 and N
The Ohmic contact of lower floor's polysilicon body 205 in p-type base 208 and groove where+source region 209, N+ source regions 209, utilizes source electrode
Metal 210 can form the source electrode of MOSFET element, gate metal 211 and the Ohmic contact of upper strata polysilicon body 207 in groove, profit
The gate electrode of MOSFET element can be formed with gate metal 211.The active cellular of cellular region is connected with each other by source metal 210
Integrally.
Certainly, in the specific implementation, also need to set absolutely between source metal 210, gate metal 211 and N-type drift layer 203
Edge dielectric layer, with being dielectrically separated from needed for realization, specific structure for setting insulating medium layer etc. is ripe for those skilled in the art
Know, here is omitted.
When it is implemented, the depth of the cellular groove 212 is 3 μm~6 μm, the thickness of terminal trenches insulating oxide 204
Spend consistent with the thickness of lower insulating oxide 204 in groove.N-type is provided between N+ substrates 201 and N-type drift layer 203 to aid in
Layer 202, the N-type auxiliary layer 202 abut N+ substrates 201 and N-type drift layer 203 respectively, and the thickness of N-type auxiliary layer 202 is 10 μ
M~20 μm, the cut-off electric field of MOSFET element can be effectively improved by N-type auxiliary layer 202.
As shown in Fig. 2~Figure 11, the MOSFET element of the above-mentioned pressure-resistant scope of raising, it can be prepared by following processing steps
Obtain, specifically, the preparation method of the MOSFET element comprises the following steps：
Step 1, the semiconductor substrate with N conduction types is provided, the semiconductor substrate includes N+ substrates 201 and position
N-type drift layer 203 above the N+ substrates 201；Optionally shelter and etch N-type drift layer 203, to be drifted about in N-type
Required cellular groove 212 and terminal secondary trenches 216 are obtained in layer 203；
Specifically, the material of semiconductor substrate can use silicon or other materials, the technology commonly used using the art
Means, cellular groove 212 and terminal secondary trenches 216, cellular groove 212, end can be obtained in N-type drift layer 203 simultaneously
End secondary trenches 216 extend vertically downward from the upper surface of N-type drift layer 203, cellular groove 212, terminal secondary trenches 216
Depth is identical, as shown in Figure 2.The specific process that cellular groove 212 and terminal secondary trenches 216 are prepared is led for this technology
Known to the personnel of domain, here is omitted.
In addition, being provided with N-type auxiliary layer 202 between N+ substrates 201 and N-type drift layer 203, the N-type auxiliary layer 203 is distinguished
Adjacent N+ substrates 201 and N-type drift layer 203, the thickness of N-type auxiliary layer 202 is 10 μm~20 μm.
Step 2, above-mentioned terminal secondary trenches 216 are etched again, it is described to obtain required terminal trenches 213
The depth of terminal trenches 213 is more than the depth of cellular groove 212, and the depth of terminal trenches 213 is less than N-type drift layer 203
Thickness；
Specifically, the technological means commonly used using the art is only performed etching to terminal secondary trenches 215, to obtain
Depth is more than the terminal trenches 213 of cellular groove 212, and the depth of cellular groove is 3 μm~6 μm, as shown in Figure 3.
Step 3, required trench gate preparatory technology is carried out to above-mentioned cellular groove 212, to be obtained in cellular groove 212
Required trench gate structure, and when trench gate structure is prepared, terminal conductive polycrystalline silicon is obtained in terminal trenches 213
215, the terminal trenches conductive polycrystalline silicon 215 by the side walls of terminal trenches insulating oxide 214 and terminal trenches 213 and
Bottom wall is dielectrically separated from；
Specifically, when the trench gate structure of preparation is shielded gate structures, specific embodiment comprises the following steps：
Step 3-1, first groove insulating oxide 217, cellular are set simultaneously in cellular groove 212, terminal trenches 213
First groove insulating oxide 217 in groove 212 covers the side wall and bottom wall of cellular groove 212, in terminal trenches 213
First groove insulating oxide 217 covers the side wall and bottom wall of terminal trenches, and is setting first groove insulating oxide 217
Afterwards, the first polysilicon filling hole 218 is formed in cellular groove 212, terminal trenches polysilicon filling hole is formed in terminal trenches 213
219；
As shown in figure 4, first groove insulating oxide 217 can be silicon dioxide layer, first groove insulating oxide 217
Cellular groove 212 is covered in simultaneously, in terminal trenches 213, the set-up mode of first groove insulating oxide 217 can use heat
Oxidation or the mode of filling, can specifically carry out selection determination as needed, here is omitted.
Step 3-2, conductive polycrystalline silicon deposit is carried out above above-mentioned N-type drift layer 203, to obtain filling up the first polysilicon
The cellular polysilicon obturator 220 in hole 218 is filled, and fills up the terminal conductive polycrystalline in terminal trenches polysilicon filling hole 219
Silicon 215；First groove insulating oxide 217 corresponding with terminal conductive polycrystalline silicon 215 forms terminal trenches insulating oxide
214；
As shown in figure 5, the conductive polycrystalline silicon being filled in terminal trenches polysilicon filling hole 219 forms terminal conductive polycrystalline
Silicon 215, after terminal conductive polycrystalline silicon 215 is obtained, the first groove insulating oxide 217 in terminal trenches 213 forms terminal
Channel insulation oxide layer 214, the length of terminal conductive polycrystalline silicon 215 are more than the length of cellular polysilicon obturator 220.
Step 3-3, above-mentioned cellular polysilicon obturator 220 is performed etching, to obtain in cellular groove 212
Lower floor's polysilicon body 205 and the etching positioning hole 221 in the groove directly over lower floor's polysilicon body 205 in groove；
As shown in fig. 6, the technological means commonly used using the art is only carved to cellular polysilicon obturator 220
Erosion, to remove the top of cellular polysilicon obturator 220, i.e., the bottom of cellular polysilicon obturator 220 is in cellular groove 212
Lower floor's polysilicon body 205 in groove is formed, after the top of cellular polysilicon obturator 220 is removed, lower floor's polycrystalline in groove
The surface of silicon body 205 forms etching positioning hole 221, etches lower floor's polysilicon body 205 in the aperture and groove of positioning hole 221
External diameter is consistent.
Step 3-4, the first groove insulating oxide using above-mentioned etching positioning hole 221 to the internal upper part of cellular groove 212
217 carry out full etching, to obtain and lower insulating oxide 204 and position in 205 corresponding groove of lower floor's polysilicon body in groove
Upper tank body 222 directly over lower floor's polysilicon body in the groove 205, width and the cellular groove 212 of upper tank body 222
Width it is consistent；
As shown in fig. 7, using when etching positioning hole 221 first groove insulating oxide 217 being performed etching, top is obtained
Cell body 222, the height of upper tank body 222 is identical with etching positioning hole 221, width and the cellular groove 212 of upper tank body 222
Width is identical.After the first groove insulating oxide 217 on etching cellular groove 212 top, remaining first groove insulation oxygen
It is lower insulating oxide 204 in groove to change layer 217.
Step 3-5, second groove insulating oxide 224, second groove insulating oxide are set in above-mentioned upper tank body 222
Layer 224 covers side wall and the bottom of upper tank body 222, and shape after second groove insulating oxide 224 is set in upper tank body 222
Hole 223 is filled into the second polysilicon；
As shown in figure 8, it is used to be formed upper insulating oxide 206, groove in groove using second groove insulating oxide 224
The thickness of interior upper insulating oxide 206 is less than the thickness of lower insulating oxide 204 in groove.Second groove insulating oxide is set
After 224, the second polysilicon filling hole 223 is obtained.
Step 3-6, conductive polycrystalline silicon filling is carried out in above-mentioned second polysilicon filling hole 223, to obtain filling up second
Upper strata polysilicon body 207 in the groove in polysilicon filling hole 223, with 207 corresponding second groove of upper strata polysilicon body in groove
Insulating oxide 224 forms upper insulating oxide 206 in groove, and upper strata polysilicon body 207 is insulated by upper in groove in groove
Oxide layer 206 is dielectrically separated from lower floor's polysilicon body 205 in the side wall and groove of cellular groove 212；Upper strata polycrystalline in groove
The width of silicon body 207 is more than the width of lower floor's polysilicon body 205 in groove；
As shown in figure 9, the thickness one of the thickness of upper insulating oxide 206 and second groove insulating oxide 224 in groove
Cause, the width of upper strata polysilicon body 207 is more than the width of lower floor's polysilicon body 205 in groove in groove, therefore, upper exhausted in groove
The thickness of edge oxide layer 206 is less than the thickness of lower insulating oxide 204 in groove.
Step 4, the injection in the top of above-mentioned N-type drift layer 203 progress p type impurity ion, in cellular groove after diffusion
212 both sides form required p-type base 208, and p-type base 208 contacts with cellular groove 212, the terminal ditch of neighbouring cellular region
Groove 213 contacts with the p-type base 208 of the outer top of the wall of cellular channel side 212 of adjacent terminals protection zone；
Specifically, the technological means commonly used using the art carries out p type impurity ion implanting, and p-type base 208 is distributed
In the both sides of each cellular groove 212；The notch of p-type base 208 from cellular groove 212 extends downwardly, when in cellular groove 212
Trench gate when using shielded gate structures, p-type base 208 is located at the top of the bottom of upper strata polysilicon body 207 in groove.
Step 5, above above-mentioned N-type drift layer 203 carry out N-type impurity ion injection, to obtain being located at adjacent cellular
N+ source regions 209 in the p-type base 208 of the outer top of 212 side walls of groove, N+ source regions 209 and the side wall of corresponding cellular groove 212
Contact；
As shown in Figure 10, the technological means commonly used using the art carries out the injection of N-type impurity ion, N+ source regions
209 are only distributed in the p-type base 208 above adjacent 212 side walls of cellular groove, therefore, terminal trenches 213 and cellular groove
N+ source regions 209 are not present in p-type base 208 between 212.
Step 6, the deposited metal above above-mentioned N-type drift layer 203, to obtain positioned at the source of the top of N-type drift layer 203
Pole metal 210 and gate metal 211, p-type base of the source metal 210 where with N+ source regions 209 and the N+ source regions 209
The Ohmic contact of area 208, gate metal 211 electrically connect with the trench gate structure in cellular groove 211.
As shown in figure 11, source metal is prepared after the technological means deposited metal commonly used using the art
210 and gate metal 211, when using shielded gate structures, gate metal 211 and 207 ohm of upper strata polysilicon body in groove
Contact, source metal 210 and the Ohmic contact of lower floor's polysilicon body 205 in groove.It is specific that source metal 210, gate metal are set
Process and realize draw etc. technical process can use first realized with conventional process mode, specifically repeat no more.Specifically
It is mutually isolated between source metal 210 and gate metal during implementation, can between source metal 210, gate metal and N-type drift layer 203
To be dielectrically separated from by insulating medium layer etc., the active cellular in MOSFET element cellular region is connected into by source metal 210
One.
In addition it is also necessary to set drain electrode structure in the lower surface of N+ substrates 201, can be formed by the drain electrode structure
The concrete form of the drain electrode of MOSFET element, the specific technical process for forming drain electrode and drain electrode structure can select or
With reference to existing material, here is omitted.
Claims (9)
1. a kind of MOSFET element for improving pressure-resistant scope, including the cellular region on semiconductor substrate and terminal protection
Area, cellular region are located at the center of semiconductor substrate, and terminal protection area is located at the outer ring of cellular region and terminal protection area is around bag
Enclose cellular region；The semiconductor substrate includes the first conductivity type substrate and above first conductivity type substrate
First conduction type drift layer；Active cellular in cellular region uses groove structure, and trench gate structure is set in cellular groove；
Top is provided with the second conduction type base region outside the cellular trenched side-wall, and second conduction type base region is conductive positioned at first
Contacted in type drift layer and with corresponding cellular trenched side-wall；Between adjacent cellular groove outside side wall top the second conductive-type
The first conduction type source region is respectively provided with type base, the first conduction type source region contacts with the side wall of corresponding cellular groove；It is special
Sign is：
Some terminal trenches are set in terminal protection area, and the terminal trenches are located in the first conduction type drift layer, terminal
Depth of the groove in the first conduction type drift layer is more than depth of the cellular groove in the first conduction type drift layer；Terminal
Terminal conductive polycrystalline silicon is set in groove, and the terminal trenches conductive polycrystalline silicon passes through terminal trenches insulating oxide and terminal ditch
The side wall and bottom wall of groove are dielectrically separated from；Outside the terminal trenches of neighbouring cellular region and the cellular trenched side-wall of adjacent terminals protection zone
The second conduction type base region contact of top.
2. the MOSFET element according to claim 1 for improving pressure-resistant scope, it is characterized in that：Ditch in the cellular groove
Slot grid structure includes shielded gate structures, and the shielded gate structures include upper strata polycrystalline in lower floor's polysilicon body in groove and groove
Silicon body, the outer ring of lower floor's polysilicon body passes through side wall and bottom of the lower insulating oxide with cellular groove in groove in the groove
Wall is dielectrically separated from, in groove the outer ring of upper strata polysilicon body by the side wall of upper insulating oxide in groove and cellular groove and
Lower floor's polysilicon body is dielectrically separated from groove, and the width of upper strata polysilicon body is more than the width of lower floor's polysilicon body in groove in groove
Degree.
3. the MOSFET element according to claim 2 for improving pressure-resistant scope, it is characterized in that：Upper strata polysilicon body in groove
With the gate metal Ohmic contact above the first conduction type drift layer, lower floor's polysilicon body and the first conduction type float in groove
The source metal Ohmic contact moved above layer；Second conduction of source metal top outside side wall also between adjacent cellular groove
Type base and the first conduction type source region Ohmic contact in second conduction type base region.
4. the MOSFET element of the pressure-resistant scope of raising according to Claims 2 or 3, it is characterized in that：The cellular groove
Depth is 3 μm~6 μm, and the thickness of terminal trenches insulating oxide is consistent with the thickness of lower insulating oxide in groove.
5. the MOSFET element according to claim 1 for improving pressure-resistant scope, it is characterized in that：In the first conductivity type substrate
Be provided with the first conduction type auxiliary layer with the first conduction type drift interlayer, the first conduction type auxiliary layer respectively adjacent the
One conductivity type substrate and the first conduction type drift layer, the thickness of the first conduction type auxiliary layer is 10 μm~20 μm.
6. a kind of preparation method for the MOSFET element for improving pressure-resistant scope, it is characterized in that, the preparation side of the MOSFET element
Method comprises the following steps：
Step 1, the semiconductor substrate with the first conduction type is provided, the semiconductor substrate includes the first conductivity type substrate
And the first conduction type drift layer above first conductivity type substrate；First is optionally sheltered and etches to lead
Electric type drift layer, to obtain required cellular groove and terminal secondary trenches in the first conduction type drift layer；
Step 2, above-mentioned terminal secondary trenches are etched again, to obtain required terminal trenches, the terminal trenches
Depth is more than the depth of cellular groove, and the depth of terminal trenches is less than the thickness of the first conduction type drift layer；
Step 3, required trench gate preparatory technology is carried out to above-mentioned cellular groove, to obtain required groove in cellular groove
Grid structure, and when trench gate structure is prepared, terminal conductive polycrystalline silicon is obtained in terminal trenches, the terminal trenches are led
Electric polysilicon is dielectrically separated from by the side wall and bottom wall of terminal trenches insulating oxide and terminal trenches；
Step 4, the injection in the second conductive type impurity ion of the top of above-mentioned first conduction type drift layer progress, after diffusion
The second required conduction type base region, the second conduction type base region and cellular trench contact are formed in the both sides of cellular groove, it is adjacent
The terminal trenches of nearly cellular region contact with the second conduction type base region of the outer top of the cellular trenched side-wall of adjacent terminals protection zone；
Step 5, the injection for carrying out above above-mentioned first conduction type drift layer the first conductive type impurity ion, with place
The first conduction type source region between adjacent cellular groove outside side wall in the second conduction type base region of top, the first conduction type
Source region contacts with the side wall of corresponding cellular groove；
Step 6, the deposited metal above above-mentioned first conduction type drift layer, to obtain being located at the first conduction type drift layer
The source metal and gate metal of top, the source metal and the first conduction type source region and the first conduction type source
The second conduction type base region Ohmic contact where area, gate metal electrically connect with the trench gate structure in cellular groove.
7. the preparation method of the MOSFET element according to claim 6 for improving pressure-resistant scope, it is characterized in that, in step 3,
When the trench gate structure of preparation is shielded gate structures, specific embodiment comprises the following steps：
Step 3-1, first groove insulating oxide is set simultaneously in cellular groove, terminal trenches, first in cellular groove
Channel insulation oxide layer covers the side wall and bottom wall of cellular groove, and the first groove insulating oxide covering in terminal trenches is eventually
The side wall and bottom wall of groove are held, and forms the first polysilicon after first groove insulating oxide is set, in cellular groove and fills out
Hole is filled, terminal trenches polysilicon filling hole is formed in terminal trenches；
Step 3-2, conductive polycrystalline silicon deposit is carried out above above-mentioned first conduction type drift layer, to obtain filling up the first polycrystalline
Silicon fills the cellular polysilicon obturator in hole, and fills up the terminal conductive polycrystalline silicon in terminal trenches polysilicon filling hole；With end
First groove insulating oxide corresponding to conductive polycrystalline silicon is held to form terminal trenches insulating oxide；
Step 3-3, above-mentioned cellular polysilicon obturator is performed etching, to obtain the lower floor in the groove in cellular groove
Polysilicon body and the etching positioning hole directly over lower floor's polysilicon body in the groove；
Step 3-4, full etching is carried out to the first groove insulating oxide of cellular groove internal upper part using above-mentioned etching positioning hole,
To obtain lower insulating oxide and lower floor's polycrystalline in the groove in groove corresponding with lower floor's polysilicon body in groove
Upper tank body directly over silicon body, the width of upper tank body are consistent with the width of cellular groove；
Second groove insulating oxide, second groove insulating oxide covering top are set step 3-5, in above-mentioned upper tank body
The side wall of cell body and bottom, the second polysilicon filling hole is formed after second groove insulating oxide is set in upper tank body；
Step 3-6, conductive polycrystalline silicon filling is carried out in above-mentioned second polysilicon filling hole, is filled out with obtaining filling up the second polysilicon
Upper strata polysilicon body in the groove in hole is filled, second groove insulating oxide corresponding with upper strata polysilicon body in groove forms groove
Interior upper insulating oxide, upper strata polysilicon body passes through the side wall and ditch of upper insulating oxide and cellular groove in groove in groove
Cao Nei lower floors polysilicon body is dielectrically separated from；The width of upper strata polysilicon body is more than the width of lower floor's polysilicon body in groove in groove
Degree；
Gate metal connects with upper strata polysilicon body Ohmic contact in groove, source metal with lower floor's polysilicon body ohm in groove
Touch.
8. the preparation method of the MOSFET element according to claim 6 for improving pressure-resistant scope, it is characterized in that, led first
Electric type substrates are provided with the first conduction type auxiliary layer, the first conduction type auxiliary layer with the first conduction type drift interlayer
Abut the first conductivity type substrate and the first conduction type drift layer respectively, the thickness of the first conduction type auxiliary layer for 10 μm~
20μm。
9. the preparation method of the MOSFET element according to claim 6 for improving pressure-resistant scope, it is characterized in that, it is described partly to lead
The material of structure base board includes silicon, and the depth of cellular groove is 3 μm~6 μm.
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