CN104716192B - Pressure-resistant power MOS (Metal Oxide Semiconductor) device and preparation method thereof is realized using Charged Couple - Google Patents
Pressure-resistant power MOS (Metal Oxide Semiconductor) device and preparation method thereof is realized using Charged Couple Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 53
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 53
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000001413 cellular effect Effects 0.000 claims abstract description 313
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 239
- 239000002184 metal Substances 0.000 claims abstract description 94
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 230000004224 protection Effects 0.000 claims abstract description 88
- 229920005591 polysilicon Polymers 0.000 claims abstract description 87
- 238000009413 insulation Methods 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 51
- 238000002347 injection Methods 0.000 claims description 33
- 239000007924 injection Substances 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 6
- 230000037431 insertion Effects 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000003491 array Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000007363 ring formation reaction Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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Abstract
Pressure-resistant power MOS (Metal Oxide Semiconductor) device and preparation method thereof is realized the present invention relates to a kind of utilization Charged Couple, it connects pressure ring and uses groove structure, pressure-resistant conductive polycrystalline silicon is filled with pressure-resistant groove connecting；Active area includes some active cellulars, and Gate Electrode Conductive polysilicon is in contact by the gate oxide that insulate with the side wall of active cellular groove, and Gate Electrode Conductive polysilicon is isolated with cellular conductive polycrystalline silicon and cellular insulating oxide respectively by the gate oxide that insulate；The bottom of Gate Electrode Conductive polysilicon is located at the lower section of the second conduction type well region, the first conductivity type implanted region and the second conduction type well region with the active area metal ohmic contact on the interarea of active area first；Active area metal is electrically connected with the metal of resistance to nip, and cellular conductive polycrystalline silicon keeps equipotential with pressure-resistant conductive polycrystalline silicon.Voltage endurance capability of the present invention is strong, and pressure-resistant reliability is high, and the proportion of terminal protection area occupancy chip entire area is lower, is suitable for producing in batches.
Description
Technical field
Realized using Charged Couple pressure-resistant the present invention relates to a kind of power MOS (Metal Oxide Semiconductor) device and preparation method thereof, especially one kind
Power MOS (Metal Oxide Semiconductor) device and preparation method thereof, belong to the technical field of power MOS (Metal Oxide Semiconductor) device.
Background technology
Semiconductor power device usually requires to bear certain voltage, voltage range from tens volts to several kilovolts, and
It is the structure of the material that device is used and device to realize two pressure-resistant big key elements of device.The semiconductor being most widely used at present
Power device is silicon device, and used material is silicon materials, usually epitaxial silicon material, and it has specific resistivity and thickness
Degree；And the structure of device includes active area structure and terminal protection plot structure, electric current when the former is usually break-over of device work
Flow through region, the latter then work pressure-resistant for device when electric field laterally outwardly extended there is provided extension and born by active-surface
Region, so that it is guaranteed that device is not breakdown in the operating voltage range of permission.
Weigh a power device terminal protection plot structure it is good with bad major criterion including pressure-resistant limit capacity, pressure-resistant
Reliability and pressure-resistance structure shared by chip area proportion.In general, it usually needs terminal protection plot structure it is pressure-resistant
Ability is not less than the active area of device, and the resistance to pressure request of device is higher, then the size of terminal protection plot structure is bigger, that is, accounts for whole
The area proportion of chip is higher, and on the premise of the total area of chip is fixed, the area of active area will be forced to reduce, so that
The current capacity of device is reduced, therefore, preferable terminal protection plot structure is that voltage endurance capability is strong and size is small as far as possible.
Usually, terminal protection area includes pressure-resistant protection zone, and field limiting ring structure or field are used traditional pressure-resistant protection zone more
The combination of hardened structure or both, as shown in figure 1, specially a kind of pressure-resistant protection zone uses the trench MOSFET of field limiting ring structure
The structure chart of device, it includes N-type drift region 10 and the N-type substrate 11 abutted with the N-type drift region 10, in N-type drift
Groove-shaped cellular and multiple field limiting rings 39 are set in area 10, wherein, groove-shaped cellular includes active groove 40, the active ditch
Groove 40 is located in active p-well 38, and depth is stretched into N-type drift region 10, i.e., the bottom land of active groove 40 is located under active p-well 38
Side.The inwall growth of active groove 40 has insulation gate oxide 41, in the active groove 40 that growth has insulation gate oxide 41
Active conductive polycrystalline silicon 35 is filled, active N+ injection regions 34, the active N+ notes are provided with above the side wall of neighboring active groove 40
Enter top of the area 34 in active p-well 38, and be in contact with the lateral wall of active groove 40.The notch covering of active groove 40
There is dielectric layer 36, the dielectric layer 36 is also covered in the surface of the N-type drift region 10 of pressure-resistant protection zone, and active area metal 37 is covered
On dielectric layer 36, and with active p-well 38 and the active Ohmic contact of N+ injection regions 34.When it is implemented, in pressure-resistant protection zone
It is interior, form PN junction between the field limiting ring 39 and N-type drift region 10 that are formed by p-well.
When said structure is pressure-resistant, the PN junction in pressure-resistant protection zone can exhaust, and the region exhausted can be with the increase of voltage
Gradually laterally connect together to support electric field, the quantity of field limiting ring 39 determines pressure-resistant height, meanwhile, field limiting ring 39 it is dense
Degree, junction depth, spacing will be determined according to the drift region concentration of PN junction is formed therewith, it is therefore desirable to have specific technological process
To make field limiting ring 39, and easily influenceed by other techniques, thus cause device pressure-resistant stability and reliability easily by
Fluctuation.
In addition, in some semiconductor devices, the cellular in active area uses capacitor board structure, and the structure can be realized
Charged Couple, when the electric charge of coupling reaches balance with the electric charge in its surrounding drift region, the depletion region of two kinds of electric charge formation is
It is sustainable pressure-resistant, conventional power devices are contrasted, the resistivity of epitaxial silicon material is smaller used in this kind of device, can obtain more
Low conducting resistance, but higher drift region concentration proposes higher requirement, field limiting ring to the terminal pressure-resistance structure of device
39 quantity need it is more, and technique hold it is wide smaller, these reliabilities for being all detrimental to this kind of advanced device and cost performance.
The content of the invention
It is pressure-resistant that the purpose of the present invention overcomes the deficiencies in the prior art to be realized there is provided a kind of utilization Charged Couple
Power MOS (Metal Oxide Semiconductor) device and preparation method thereof, its voltage endurance capability is strong, and pressure-resistant reliability is high, and manufacture craft is simple, and terminal protection area
The proportion for taking chip entire area is lower, with high cost performance, is suitable for producing in batches.
The technical scheme provided according to the present invention, the utilization Charged Couple realizes pressure-resistant power MOS (Metal Oxide Semiconductor) device, described
In the top plan view of power MOS (Metal Oxide Semiconductor) device, including the active area positioned at semiconductor substrate and terminal protection area, the active area is located at
The center of semiconductor substrate, terminal protection area is located at the outer ring of active area and around the encirclement active area, terminal protection area
It is interior to include the pressure-resistant protection zone of adjacent active area；On the section of the power MOS (Metal Oxide Semiconductor) device, the semiconductor substrate includes being located at
First conduction type drift region of top and underlying first conductivity type substrate, first conductivity type substrate are adjacent
The first conduction type drift region is connect, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, first
Second interarea of the lower surface formation semiconductor substrate of conductivity type substrate；Its innovation is：
In the top plan view of the power MOS (Metal Oxide Semiconductor) device, at least one pressure ring, pressure-resistant protection are included in pressure-resistant protection zone
The pressure ring formation connection pressure ring of adjacent active regions in area；
On the section of the power MOS (Metal Oxide Semiconductor) device, connection pressure ring uses groove structure, and the pressure-resistant groove of connection is by the
One interarea extends vertically downward, and the extension depth for connecting pressure-resistant groove is less than the thickness of the first conduction type drift region, connects resistance to
The inwall and bottom wall of groove are pressed covered with pressure-resistant insulating oxide, in the pressure-resistant groove of connection covered with pressure-resistant insulating oxide
Filled with pressure-resistant conductive polycrystalline silicon；Insulating medium layer, and the insulating medium layer are provided with above the notch for connecting pressure-resistant groove
Also it is covered on the pressure-resistant insulating oxide on the interarea of terminal protection area first, resistance to nip gold is set on the insulating medium layer
Category；
On the section of the power MOS (Metal Oxide Semiconductor) device, having including some regular arrays and the distribution that is parallel to each other in active area
Source cellular, the active cellular uses groove structure, and the active cellular groove is extended downwardly, had downward vertically from the first interarea
The depth of source cellular groove extension is less than the thickness of the first conduction type drift layer；It is corresponding between neighboring active cellular groove
Covered with insulated gate oxide layer on madial wall, covered with cellular insulation oxygen on the bottom wall of active cellular groove and remaining side wall
Change layer, and be also filled with active cellular groove cellular conductive polycrystalline silicon and grid corresponding with the insulation gate oxide
Conductive polycrystalline silicon, Gate Electrode Conductive polysilicon is connected by gate insulator oxide layer with the side wall of active cellular groove, and grid is led
Electric polysilicon is isolated with cellular conductive polycrystalline silicon and cellular insulating oxide respectively by the gate oxide that insulate；Have adjacent
The second conduction type well region is provided between the cellular groove of source above corresponding outer wall side, is set in the second conduction type well region
Have the first conductivity type implanted region, the first conductivity type implanted region and the second conductive type of trap area respectively with corresponding insulated gate
Oxide layer contact connection, the bottom of Gate Electrode Conductive polysilicon is located at the lower section of the second conduction type well region, the first conduction type note
Enter area and the second conduction type well region and active area metal ohmic contact, active area metal is led by insulating medium layer with grid
Electric polysilicon is isolated；
Active area metal is electrically connected with the metal of resistance to nip, and the cellular conductive polycrystalline silicon in active cellular groove is resistance to being connected
The pressure-resistant conductive polycrystalline silicon in groove is pressed to keep equipotential.
On the section of the power MOS (Metal Oxide Semiconductor) device, covered with connection conductive polycrystalline above the notch for connecting pressure-resistant groove
Silicon, the connection conductive polycrystalline silicon and the cellular in the pressure-resistant conductive polycrystalline silicon and active cellular groove that are connected in pressure-resistant groove
Conductive polycrystalline silicon is electrically connected after being in contact, and insulating medium layer is covered on connection conductive polycrystalline silicon, and the metal of resistance to nip is led with being connected
Electric polysilicon electrical connection.
In the top plan view of the power MOS (Metal Oxide Semiconductor) device, active area includes the connection member positioned at the active area outmost turns
Regular array and the active cellular for the distribution that is parallel to each other are located in connection cellular ring in born of the same parents' ring, active area, the connection pressure ring
It is parallel with connection cellular ring；Active cellular in active area is connected with being connected cellular ring；What is be parallel to each other in active area is active
Spacing between cellular is equal.
On the section of the power MOS (Metal Oxide Semiconductor) device, connection cellular ring uses groove structure, and the connection cellular groove is by the
One interarea extends vertically downward, and the extension depth for connecting pressure-resistant groove is less than the thickness of the first conduction type drift region, connection member
Born of the same parents' groove on the madial wall of the active upper lateral part of cellular groove one covered with insulated gate oxide layer, and the bottom of connection cellular groove
Covered with cellular insulating oxide on wall and remaining side wall；Connect in cellular groove filled with cellular conductive polycrystalline silicon and with
Insulate the corresponding Gate Electrode Conductive polysilicon of gate oxide, and Gate Electrode Conductive polysilicon is by the gate oxide that insulate with being connected cellular ditch
The side wall of groove is in contact；
On the section of the power MOS (Metal Oxide Semiconductor) device, in connection cellular groove away from the outer wall side for connecting pressure-resistant groove side
Top, which is provided with the second conduction type well region, the second conduction type well region, is provided with the first conductivity type implanted region, and described first leads
Electric type implanted region and the second conduction type well region are in contact with insulation gate oxide, and the bottom of Gate Electrode Conductive polysilicon
Positioned at the lower section of the second conduction type well region, the first conductivity type implanted region and the second conduction type well region with active area
Active area metal ohmic contact on one interarea, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and
Cellular conductive polycrystalline silicon is isolated；Cellular conductive polycrystalline silicon and the pressure-resistant conduction that is connected in pressure-resistant groove in connection cellular groove
Polysilicon keeps equipotential.
On the section of the power MOS (Metal Oxide Semiconductor) device, covered with connection conductive polycrystalline above the notch for connecting pressure-resistant groove
Silicon, the connection conductive polycrystalline silicon and the cellular in the pressure-resistant conductive polycrystalline silicon and connection cellular groove that are connected in pressure-resistant groove
Conductive polycrystalline silicon is electrically connected after being in contact, and insulating medium layer is covered on connection conductive polycrystalline silicon, and the metal of resistance to nip is led with being connected
Electric polysilicon electrical connection.
When having multiple pressure rings in the pressure-resistant protection zone, the pressure ring in pressure-resistant protection zone is parallel to each other.
A kind of utilization Charged Couple realizes the preparation method of pressure-resistant power MOS (Metal Oxide Semiconductor) device, the preparation of the power MOS (Metal Oxide Semiconductor) device
Method comprises the following steps：
The semiconductor substrate of a, offer with two opposing main faces, described two opposing main faces include the first interarea and second
Interarea, includes the first conduction type drift region and positioned at first conduction type drift between the first interarea and the second interarea
The first conductivity type substrate below area；
B, on the first interarea of above-mentioned semiconductor substrate hard mask layer is deposited, optionally shelter and etch and described cover firmly
Film layer, with the hard mask window of insertion hard mask layer needed for obtaining；
C, using above-mentioned hard mask window anisotropic dry etch is carried out to the first interarea of semiconductor substrate, with the
Groove is formed in one conduction type drift region, depth of the groove in the first conduction type drift region is less than the first conduction type
The thickness of drift region, the groove, which includes being located in pressure-resistant protection zone, connects pressure-resistant groove and active in active area
Cellular groove；
D, the hard mask layer removed on above-mentioned first interarea, and in the first interarea and above-mentioned groove of semiconductor substrate
Grow insulating oxide；
E, conductive polycrystalline silicon is deposited on above-mentioned first interarea, the conductive polycrystalline silicon is covered in the insulation on the first interarea
In oxide layer, and it is filled in groove；
F, optionally shelter and etch above-mentioned conductive polycrystalline silicon, obtain being located at the pressure-resistant conduction connected in pressure-resistant groove many
Crystal silicon, the cellular conductive polycrystalline silicon in active cellular groove and be covered on insulating oxide and with pressure-resistant conductive polycrystalline
Silicon, the connection conductive polycrystalline silicon of cellular conductive polycrystalline silicon contact electrical connection；
Insulating oxide on g, the interarea of etching first of selectivity, to remove the insulating oxide on the interarea of active area first
Layer, while removing in active cellular groove away from the insulating oxide and corresponding cellular on connection pressure-resistant groove side side wall
Conductive polycrystalline silicon, to obtain the cellular insulating oxide in active cellular groove, cover on the first interarea of terminal protection area
And connect the pressure-resistant insulating oxide in pressure-resistant groove and the grid hole being formed in active cellular groove；
H, the growth insulation gate oxide in above-mentioned grid hole, the insulation gate oxide is covered in corresponding with grid hole
Active cellular groove side wall, the surface of cellular conductive polycrystalline silicon corresponding with grid hole and the corresponding member of grid hole bottom hole
Born of the same parents' insulating oxide；
I, the deposit Gate Electrode Conductive polysilicon in above-mentioned grid hole, the Gate Electrode Conductive polysilicon, which is filled in growth, insulation
In the grid hole of gate oxide；
J, on above-mentioned first interarea, the second conductive type impurity ion is injected in autoregistration, and is formed by high temperature knot
The second conduction type well region in active area, the second conduction type well region is contacted with insulation gate oxide, and second
Conductive type of trap area is located at the top of Gate Electrode Conductive polysilicon bottom；
K, on above-mentioned first interarea, carry out the first conductive type impurity ion implanting, and pass through high temperature knot formation position
The first conductivity type implanted region in the second conduction type well region, first conductivity type implanted region and insulation gate oxide
It is in contact；
L, on above-mentioned first interarea insulating medium layer is deposited, and optionally etch the insulating medium layer, to be formed
The contact hole of required insertion insulating medium layer, the contact hole includes the contact hole of resistance to nip and active region contact hole；
M, the deposited metal on above-mentioned first interarea, and selective etching sheet metal, to obtain being located in active area
Active area metal and the metal of resistance to nip positioned at pressure-resistant protection zone, the metal of resistance to nip passes through the contact hole of resistance to nip and company
Conductive polycrystalline silicon electrical connection is connect, active area metal is conductive by active region contact hole and the first conductivity type implanted region and second
Type well region Ohmic contact, active area metal is electrically connected with the metal of resistance to nip；
N, metal layer on back, the metal layer on back and the first conduction type are deposited on the second interarea of semiconductor substrate
Substrate Ohmic contact.
Stating the material of semiconductor substrate includes silicon, and the thickness of insulating oxide is the à of 2000 à ~ 10000.
In the step c, obtained groove also includes connection cellular groove annular in shape, and active cellular groove is respectively positioned on ring
In the connection cellular groove of shape, connection cellular groove is on the madial wall of the active upper lateral part of cellular groove one covered with insulated gate
Covered with cellular insulating oxide in oxide layer, and the bottom wall and remaining side wall of connection cellular groove；Connect in cellular groove
Filled with cellular conductive polycrystalline silicon and with the corresponding Gate Electrode Conductive polysilicon of insulation gate oxide, Gate Electrode Conductive polysilicon leads to
Insulation gate oxide is crossed to be in contact with being connected the side wall of cellular groove, and Gate Electrode Conductive polysilicon is distinguished by the gate oxide that insulate
It is isolated with cellular conductive polycrystalline silicon and cellular insulating oxide
On the section of the power MOS (Metal Oxide Semiconductor) device, in connection cellular groove away from the outer wall side for connecting pressure-resistant groove side
Top, which is provided with the second conduction type well region, the second conduction type well region, is provided with the first conductivity type implanted region, and described first leads
Electric type implanted region and the second conduction type well region are in contact with insulation gate oxide, and the bottom of Gate Electrode Conductive polysilicon
Positioned at the lower section of the second conduction type well region, the first conductivity type implanted region and the second conduction type well region with active area
Active area metal ohmic contact on one interarea, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and
Cellular conductive polycrystalline silicon is isolated.
The hard mask layer is LPTEOS, thermal oxide silica adds chemical vapor deposition silica or thermal silicon dioxide
Plus silicon nitride.
In both described " first conduction type " and " the second conduction type ", led for N-type power MOSFET device, first
Electric type refers to N-type, and the second conduction type is p-type；For p-type power MOSFET device, the first conduction type and the second conductive-type
The signified type of type and N-type semiconductor device contrast.
Advantages of the present invention：
1st, formed in active area by cellular conductive polycrystalline silicon, cellular insulating oxide and the first conduction type drift region
Capacitance structure, it is resistance to support that the capacitance structure forms between adjacent trenches depletion layer when pressure-resistant, using Charged Couple principle
Pressure, groove is deeper, and the voltage that can be born is also higher, and the present invention is exactly extended to above-mentioned pressure-resistance structure by active area
Terminal protection area, pressure ring uses groove capacitor structure, the transitional region in active area Yu terminal protection area, connection pressure ring with
Depletion layer is formed when pressure-resistant using Charged Couple principle between connection cellular ring, due to connecting the pressure-resistant conduction in pressure-resistant groove
Polysilicon is connected one with the cellular conductive polycrystalline silicon in connection cellular groove by the connection conductive polycrystalline silicon between them
Rise, keep equipotential, therefore, electricity can be fully achieved with the electric charge in the first conduction type drift region in the electric charge being coupled out herein
Lotus balances, so as to form the pressure-resistant effect consistent with active area, and is connecting the consumption between pressure-resistant groove and connection cellular groove
Before layer is connected together to the greatest extent, due on the first interarea of pressure-resistant protection zone covered with pressure-resistant insulating oxide, it is therefore, thicker
Pressure-resistant insulating oxide can also bear voltage now completely, in addition, can be with according to the difference of the resistance to pressure request of device
The convenient quantity that pressure ring is set, emulation and test result indicates that, for 100V and following device, generally only need to set
The pressure ring of 1-2 circles can ensure resistance to pressure request completely, even for 150V-200V device, also only need to set 3-4 circles resistance to
Pressure ring, because pressure ring is groove structure, therefore, compared to the terminal protection area of traditional field limiting ring and field plate structure, the present invention
The terminal size of structure can be substantially reduced, and wide with bigger resistance to pressure-volume.
The pressure-resistant protection structure of terminal of the present invention is highly suitable for this kind of utilization Charged Couple and realizes pressure-resistant power device,
Drift region material of this kind of device due to having used more low-resistivity under identical resistance to pressure request, therefore, the conducting resistance of device
Substantially reduce, and terminal pressure-resistance structure of the present invention make use of the pressure-resistant mechanism of identical with active area structure, reduce drift region material
Material and influence of the Terminal Design size to voltage endurance capability and reliability, also, terminal pressure-resistance structure is to make simultaneously with active area
Formed, do not increase additional technique, so, the cost performance of product is higher, is suitable for producing in batches.
Brief description of the drawings
Fig. 1 is the structural representation of existing power MOS (Metal Oxide Semiconductor) device.
Fig. 2 is the top view of power MOS (Metal Oxide Semiconductor) device of the present invention.
Fig. 3 is Fig. 2 C-C sectional views.
Fig. 4 ~ Figure 15 is the sectional view of specific implementation process step of the present invention, wherein
Fig. 4 is the sectional view of semiconductor substrate of the present invention.
Fig. 5 obtains the sectional view after hard mask window for the present invention.
Fig. 6 obtains the sectional view after groove for the present invention in N-type drift region.
Fig. 7 obtains the sectional view after insulating oxide for the present invention.
Fig. 8 obtains cuing open after cellular conductive polycrystalline silicon, pressure-resistant conductive polycrystalline silicon and connection conductive polycrystalline silicon for the present invention
View.
Fig. 9 obtains the sectional view after grid hole for the present invention.
Figure 10 obtains the sectional view after Gate Electrode Conductive polysilicon for the present invention.
Figure 11 obtains the sectional view after P type trap zone for the present invention.
Figure 12 obtains the sectional view behind N+ injection regions for the present invention.
Figure 13 obtains the sectional view after contact hole for the present invention.
Figure 14 obtains the sectional view after active area metal and the metal of resistance to nip for the present invention.
Figure 15 obtains the sectional view after metal layer on back for the present invention.
Figure 16 is test result schematic diagram when terminal protection area of the present invention does not have pressure ring.
Figure 17 is test result schematic diagram when terminal protection area of the present invention sets a pressure ring.
Figure 18 is test result schematic diagram when terminal protection area of the present invention sets two pressure rings.
Description of reference numerals：1- active areas, 2- terminal protections area, 3- is pressure-resistant protection zone, 4- active areas metal, the resistance to nips of 5-
Metal, 6- connection cellulars ring, the active cellulars of 7-, 8- pressure rings, 9- connections pressure ring, 10-N types drift region, 11-N types substrate,
12- metal layer on back, 13- connection cellulars groove, 14- connections are pressure-resistant groove, 15- cellulars insulating oxide, 16- cellulars are conductive more
Crystal silicon, 17- insulation gate oxide, 18- Gate Electrode Conductives polysilicon, 19-N+ injection regions, 20-P types well region, 21- is pressure-resistant conductive polycrystalline
Silicon, 22- are pressure-resistant insulating oxide, 23- connections conductive polycrystalline silicon, 24- insulating medium layers, 25- terminals are pressure-resistant groove, 26- first
Interarea, the interareas of 27- second, 28- hard mask layers, the hard mask windows of 29-, 30- insulating oxides, 31- grid holes, the resistance to nips of 32-
Contact hole, 33- active region contacts hole, the active N+ injection regions of 34-, 35- active conductions polysilicon, 36- dielectric layers, 37- source electrodes gold
Category, 38-P well layer, 39- field limiting rings, 40- active grooves and the active insulation gate oxides of 41-.
Embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in Figures 2 and 3：High with pressure-resistant reliability in order to improve voltage endurance capability, reduction terminal protection area takes chip
The proportion of entire area, it is of the invention in the top plan view of the power MOS (Metal Oxide Semiconductor) device by taking N-type power MOS (Metal Oxide Semiconductor) device as an example, including
Active area 1 and terminal protection area 2 positioned at semiconductor substrate, the active area 1 are located at the center of semiconductor substrate, and terminal is protected
Area 2 is protected to be located at the outer ring of active area 1 and include the resistance to of adjacent active area 1 around surrounding in the active area 1, terminal protection area 2
Press protection zone 3；On the section of the power MOS (Metal Oxide Semiconductor) device, the semiconductor substrate include N-type drift region 10 above with
And underlying N-type substrate 11, the adjoining of N-type substrate 11 N-type drift region 10, the upper surface of N-type drift region 10 forms half
First interarea 26 of conductor substrate, the second interarea 27 of the lower surface formation semiconductor substrate of N-type substrate 11；
In the top plan view of the power MOS (Metal Oxide Semiconductor) device, active area 1 includes the connection member positioned at the active area outmost turns
Include the pressure ring 8 of neighbouring connection cellular ring 6 at least one pressure ring 8, pressure-resistant protection zone 3 in born of the same parents' ring 6, pressure-resistant protection zone 2
Connection pressure ring 9 is formed, the connection pressure ring 9 is parallel with connection cellular ring 6；
On the section of the power MOS (Metal Oxide Semiconductor) device, connection pressure ring 9 uses groove structure, the pressure-resistant groove 14 of connection
Extended vertically downward by the first interarea 26, the extension depth for connecting pressure-resistant groove 14 is less than the thickness of N-type drift region 10, connects resistance to
The inwall and bottom wall of groove 14 are pressed covered with pressure-resistant insulating oxide 22, it is pressure-resistant in the connection covered with pressure-resistant insulating oxide 22
Pressure-resistant conductive polycrystalline silicon 21 is filled with groove 14；Insulating medium layer 24 is provided with above the notch for connecting pressure-resistant groove 14, and
The insulating medium layer 24 is also covered on the pressure-resistant insulating oxide 22 on the interarea of terminal protection area 2 first, in the insulation
The metal of resistance to nip 5 is set on dielectric layer 24；
On the section of the power MOS (Metal Oxide Semiconductor) device, connection cellular ring 6 uses groove structure, the connection cellular groove 13
Extended vertically downward by the first interarea 26, the extension depth for connecting pressure-resistant groove 13 is less than the thickness of N-type drift region 10, connection member
Covered with insulated gate oxide layer 17 on side wall of the born of the same parents' groove 13 away from the pressure-resistant upper lateral part of groove 14 1 of connection, and connection cellular groove
Covered with cellular insulating oxide 15 on 13 bottom wall and remaining side wall；Connect conductive many filled with cellular in cellular groove 13
Crystal silicon 16 and the Gate Electrode Conductive polysilicon 18 corresponding with insulation gate oxide 17, Gate Electrode Conductive polysilicon 18 pass through insulated gate
Oxide layer 17 is in contact with being connected the side wall of cellular groove 13, and Gate Electrode Conductive polysilicon 18 is distinguished by the gate oxide 17 that insulate
It is isolated with cellular conductive polycrystalline silicon 16 and cellular insulating oxide 15；
On the section of the power MOS (Metal Oxide Semiconductor) device, in connection cellular groove 13 away from the outer of the pressure-resistant side of groove 14 of connection
It is provided with above wall side in P type trap zone 20, P type trap zone 20 and is provided with N+ injection regions 19, the N+ injection regions 19 and P type trap zone 20 is equal
With insulation gate oxide 17 be in contact, and Gate Electrode Conductive polysilicon 18 bottom be located at P type trap zone 20 lower section, N+ injection regions 19
And P type trap zone 20 with the Ohmic contact of active area metal 4 on the first interarea of active area 26, active area metal 4 pass through insulation
Dielectric layer 24 is isolated with Gate Electrode Conductive polysilicon 18 and cellular conductive polycrystalline silicon 16 respectively；Active area metal 4 and resistance to nip
Metal 5 is electrically connected, and connects the cellular conductive polycrystalline silicon 16 in cellular groove 13 and the pressure-resistant conduction being connected in pressure-resistant groove 14
Polysilicon 21 keeps equipotential.
Specifically, active area 1 is located at center, and terminal protection area 2 is located in the outer ring of active area 1, terminal protection area 2
Pressure-resistant protection zone 3, which abuts the region covered with the metal of resistance to nip 5 in active area 1, terminal protection area 2, to be used to form pressure-resistant protection zone
3, the region of pressure-resistant protection zone 3 and the pressure-resistant outer ring of protection zone 3 is collectively forming terminal protection area 2.
In the embodiment of the present invention, in the outmost turns formation connection cellular ring 6 of active area 1, i.e., active area 1 is by connection cellular ring
6 and it is collectively forming positioned at the region of the inner ring of connection cellular ring 6.In addition, setting at least one pressure-resistant in pressure-resistant protection zone 3
Ring 8, the institute in pressure-resistant protection zone 3 in the formation connection pressure ring 9 of pressure ring 8 of neighbouring connection cellular ring 4, pressure-resistant protection zone 3
There is pressure ring 8 in parallel distribution, that is, to connect pressure ring 9 with connection cellular ring 6 and be parallel to each other with being connected cellular ring 6, and connection
The neighbouring connection cellular ring 6 of pressure ring 5.
In active area 1, there is cellular insulating oxide 15 and insulation gate oxide 17 in connection cellular groove 13, its
In, the thickness of cellular insulating oxide 15 is more than the thickness of insulation gate oxide 17, and insulation gate oxide 17 is covered in connection member
Born of the same parents' groove 13 is away from the side wall for connecting the pressure-resistant upper lateral part of groove 14 1, and cellular insulating oxide 15 is covered in connection cellular groove 13
Bottom wall and remaining side wall on.Cellular conductive polycrystalline silicon 16 is also filled up in connection cellular groove 13 and Gate Electrode Conductive is more
Crystal silicon 18, the Gate Electrode Conductive polysilicon 18 is corresponding with insulation gate oxide 17, except grid is led in connection cellular groove 13
Region outside electric crystal silicon 18 all has cellular conductive polycrystalline silicon 16 to fill.In connection cellular groove 13, Gate Electrode Conductive polysilicon
18 are dielectrically separated from by the gate oxide 17 that insulate with cellular conductive polycrystalline silicon 16, due to Gate Electrode Conductive polysilicon 18 and insulation grid oxygen
Change layer 17 corresponding, therefore side wall phase of the Gate Electrode Conductive polysilicon 18 by the gate oxide 17 that insulate with being connected cellular groove 13
Even, Gate Electrode Conductive polysilicon 18 is also isolated by the gate oxide 17 that insulate with cellular insulating oxide 15.P type trap zone 20 and
N+ injection regions 19 are located at the top of the lateral wall of connection cellular groove 13, and P type trap zone 20 and N+ injection regions 19 pass through the grid oxygen that insulate
Change layer 17 to be connected with Gate Electrode Conductive polysilicon 18, and P type trap zone 20 and N+ injection regions 19 and the Ohmic contact of active area metal 4,
So as to which active area metal 4, insulation gate oxide 17, Gate Electrode Conductive polysilicon 18, N+ injection regions 19 and P type trap zone 20 are formed
MOS structure.N+ injection regions 19 are covered close to the surface of connection cellular groove 13 by insulating medium layer 24, and insulating medium layer 24 is simultaneously
Also it is covered on Gate Electrode Conductive polysilicon 18, so as to which Gate Electrode Conductive polysilicon 18 is dielectrically separated from active area metal 4.
In pressure-resistant protection zone 3, the pressure-resistant conductive polycrystalline silicon 21 connected in pressure-resistant groove 14 passes through pressure-resistant insulating oxide
22 connect with being connected the side wall and bottom wall of pressure-resistant groove 14, and pressure-resistant insulating oxide 22 is also covered in the correspondence of terminal protection area 2
The first interarea 26 on, pressure-resistant insulating oxide 22 is in contact with cellular insulating oxide.Active area metal 4 and the metal of resistance to nip
Realized after 5 contacts in the electrical connection between active area metal 4 and the metal of resistance to nip 5, such as Fig. 2, active area metal 4 is resistance to side
Electrically connected after the contact of nip metal 5.
In active area 1, electric capacity is formed between cellular conductive polycrystalline silicon 16, cellular insulating medium layer 15 and N-type drift region 10
Structure, can support voltage using Charged Couple principle formation depletion layer.Meanwhile, in pressure-resistant protection zone 3, pressure-resistant conductive polycrystalline
Silicon 21, pressure-resistant insulating oxide 22 are similarly formed capacitance structure with N-type drift region 10.Connection cellular ring 6 is with being connected the profit of pressure ring 9
Depletion layer is formed when pressure-resistant with electric charge coupling principle, because the cellular conductive polycrystalline silicon 16 in connection cellular groove 13 is with being connected
Pressure-resistant conductive polycrystalline silicon 21 in pressure-resistant groove 14 keeps equipotential, therefore, the electric charge being coupled out can with N-type drift region 10
Electric charge charge balance is fully achieved, so as to be formed in active area 1 consistent pressure-resistant effect, and connection cellular groove 13 with
Connect before the depletion layer between pressure-resistant groove 14 links together, by thicker resistance on the first interarea 26 of pressure-resistant protection zone 3
Pressure insulating oxide 22 can bear voltage now completely.In the specific implementation, according to pressure-resistant requirement, it can be protected pressure-resistant
Protect in area 3 and the pressure ring 8 of varying number is set.
Further, on the section of the power MOS (Metal Oxide Semiconductor) device, covered with even above the notch for connecting pressure-resistant groove 14
Meet conductive polycrystalline silicon 23, the connection conductive polycrystalline silicon 23 and the pressure-resistant conductive polycrystalline silicon 21 being connected in pressure-resistant groove 14 and company
Connect and electrically connected after the cellular conductive polycrystalline silicon 16 in cellular groove 13 is in contact, insulating medium layer 24 is covered in connection conductive polycrystalline
On silicon 23, the metal of resistance to nip 5 is connected with being connected conductive polycrystalline silicon electricity 23.
In the embodiment of the present invention, the metal of resistance to nip 5 is electrically connected with being connected conductive polycrystalline silicon 23, and connection conductive polycrystalline silicon 23 is same
When contacted with cellular conductive polycrystalline silicon 16 and pressure-resistant conductive polycrystalline silicon 21, therefore, can be reached by connecting conductive polycrystalline silicon 23
Equipotential between cellular conductive polycrystalline silicon 16 and pressure-resistant conductive polycrystalline silicon 21.In the specific implementation, it can also be connected by other
Connect form so that cellular conductive polycrystalline silicon 16 and pressure-resistant conductive polycrystalline silicon 21 keep equipotential, specifically will not enumerate.
The cellular insulating oxide 15, pressure-resistant insulating oxide 22 are same manufacture layer, cellular insulating oxide 15
Thickness is the à of 2000 à ~ 10000.In the embodiment of the present invention, cellular insulating oxide 17, the thickness of pressure-resistant insulating oxide 15 are used for
Ensure that before depletion layer is connected voltage can be born.
Include being located at some rule of inner ring of connection cellular ring 6 in the top plan view of the power MOS (Metal Oxide Semiconductor) device, in active area 1
Then arrange and the distribution that is parallel to each other active cellular 7, the active cellular 7 in active area 1 is connected with being connected cellular ring 6；
On the section of the power MOS (Metal Oxide Semiconductor) device, active cellular 7 uses groove structure, and the active cellular groove is from
One interarea 26 is extended downwardly downward vertically, and the depth of active cellular groove extension is less than the thickness of N-type drift layer 10, in active member
The side wall of born of the same parents' groove internal upper part is covered on the bottom wall of active cellular groove and remaining side wall covered with insulation gate oxide 17
Have cellular insulating oxide 15, and be also filled with active cellular groove cellular conductive polycrystalline silicon 16 and with the insulated gate
The corresponding Gate Electrode Conductive polysilicon 18 of oxide layer 17, Gate Electrode Conductive polysilicon 18 passes through gate insulator oxide layer 17 and active cellular
The side wall connection of groove, cellular conductive polycrystalline silicon 16 is located at the center of active cellular groove, and Gate Electrode Conductive polysilicon 18 passes through
Insulation gate oxide 17 is dielectrically separated from cellular conductive polycrystalline silicon 16, and Gate Electrode Conductive polysilicon 18 and cellular insulating oxide 15
Between be spaced by the gate oxide 17 that insulate；P type trap zone 20 is provided with above the outer wall side of active cellular groove both sides, in the P
N+ injection regions 19 are provided with type well region 20, N+ injection regions 19 and P type trap zone 20 connect with corresponding insulation gate oxide 17 respectively
Connection is touched, the bottom of Gate Electrode Conductive polysilicon 18 is located at the lower section of P type trap zone 20, and N+ injection regions 19 and P type trap zone 20 are with having
The Ohmic contact of source region metal 4.
In the embodiment of the present invention, the concrete structure of active cellular 7 is not showed that, active cellular 7 can in bar shaped or other
In shape, Fig. 2, it is in the schematic diagram that bar shaped is distributed to show active cellular 7.The two ends of active cellular 7 are with being connected the phase of cellular ring 6
Even.When active cellular 7 is using groove structure, the structure of active cellular 7 is similar with the structure for connecting cellular ring 6.In power MOS devices
On the section of part, the top in active cellular groove is set in symmetrical Gate Electrode Conductive polysilicon 18, active cellular groove
Cellular conductive polycrystalline silicon 16 be located at two Gate Electrode Conductive polysilicons 18 between, Gate Electrode Conductive polysilicon 18 passes through the gate oxide 17 that insulate
Be dielectrically separated from cellular conductive polycrystalline silicon 16, the P type trap zone 20 and N+ injection regions 19 above active cellular groove lateral wall with
The Ohmic contact of active area metal 4, so that active area metal 4, insulation gate oxide 17, Gate Electrode Conductive polysilicon 18, N+ injection regions
19 and P type trap zone 20 also form MOS structure.Gate Electrode Conductive polysilicon 18, connection cellular groove 13 in active cellular groove
Interior Gate Electrode Conductive polysilicon 18 is electrically connected, and the connection cellular ring 6 and the MOS of formation in active cellular 7 in active area 1 are tied
Structure is simultaneously joined together.Cellular conductive polycrystalline silicon 16 in active cellular groove and the cellular conductive polycrystalline being connected in cellular groove 13
Silicon 16 is in contact, in parallel so as to the capacitance structure that will be formed in active area 1.
In addition, can also only include some regular arrays in the specific implementation, in active area 1 while the distribution that is parallel to each other
Do not include the connection cellular ring 6 positioned at outmost turns in active cellular 7, i.e. active area 1.Only has active cellular 7 in active area 1
When, covered with insulated gate oxide layer 17, the bottom of active cellular groove on corresponding madial wall between neighboring active cellular groove
Covered with cellular insulating oxide 15 on wall and remaining side wall, and it is conductive more to be also filled with active cellular groove cellular
Crystal silicon 16 and Gate Electrode Conductive polysilicon 18 corresponding with the insulation gate oxide 17, Gate Electrode Conductive polysilicon 18 pass through grid
Insulating oxide 17 is connected with the side wall of active cellular groove, and Gate Electrode Conductive polysilicon 18 is other by the gate oxide point 17 that insulate
It is isolated with cellular conductive polycrystalline silicon 16 and cellular insulating oxide 15；The corresponding outer wall between neighboring active cellular groove
P type trap zone 20 is provided with above side, 20 points of N+ injection regions 19, N+ injection regions 19 and P type trap zone are provided with the P type trap zone 20
Connection is not contacted with corresponding insulation gate oxide 17, the bottom of Gate Electrode Conductive polysilicon 18 is located at the lower section of P type trap zone 20, N+
Injection region 19 and P type trap zone 20 and the Ohmic contact of active area metal 4, active area metal 4 are led by insulating medium layer 4 and grid
Electric polysilicon 18 is isolated；Cellular conductive polycrystalline silicon 16 in active cellular groove and the pressure-resistant conduction being connected in pressure-resistant groove 14
Polysilicon 21 keeps equipotential.
It it is in parallel point when only having in active area 1 because connection pressure ring 9 is around active area 1 is surrounded in the embodiment of the present invention
During the active cellular 7 of cloth, the active cellular 7 of parallel distribution can be parallel with the region of connection pressure ring 9 side.For outermost
Active cellular 7, only away from can be covered with insulated gate on the side wall for connecting the pressure-resistant side of groove 13 in its active cellular groove
Oxide layer 17, meanwhile, P type trap zone 20 and N+ injection regions 19 are just had on the side outer wall of covering insulation gate oxide 17,
Remaining structure is referred to connect the structure of cellular groove 13.In order that obtaining the cellular conductive polycrystalline silicon in active cellular 7
16 keep the cellular conductive polycrystalline silicon in equipotential, active cellular 7 with the pressure-resistant conductive polycrystalline silicon 21 being connected in pressure-resistant groove 14
16 can also be attached by the pressure-resistant conductive polycrystalline silicon 23 for connecting conductive polycrystalline silicon 23 with being connected in pressure-resistant groove 14.
Cellular insulating oxide 15 in active cellular groove and the cellular insulating oxide 15 being connected in cellular groove 13
For same manufacture layer, cellular conductive polycrystalline silicon 16 in active cellular groove and the cellular conductive polycrystalline being connected in cellular groove 13
Silicon 16 is same manufacture layer.
When having multiple pressure rings 8 in the pressure-resistant protection zone 3, the pressure ring 8 in pressure-resistant protection zone 3 is parallel to each other, and
Connect pressure ring 9 equal with the distance between the active cellular 7 that is parallel to each other in active area 1 with the distance between connection cellular ring 6.
It is different according to pressure-resistant requirement in the embodiment of the present invention, the resistance to of varying number can be set in pressure-resistant protection zone 3
It is parallel to each other between pressure ring 8, multiple pressure rings 8, the formation connection pressure ring 9 of pressure ring 8 of neighbouring connection cellular ring 6, remaining
Pressure ring 8 can also use groove structure, including the pressure-resistant groove 25 of terminal, the inwall and bottom wall of the pressure-resistant groove 25 of terminal
Covered with pressure-resistant insulating oxide 22, led in the pressure-resistant groove 25 of terminal covered with pressure-resistant insulating oxide 22 filled with pressure-resistant
Electric polysilicon 21.Connection conductive polycrystalline silicon 23 is also covered in the notch of the pressure-resistant groove 25 of terminal, and connection conductive polycrystalline silicon 23 with
Pressure-resistant conductive polycrystalline silicon 21 in terminal is pressure-resistant groove 25 is electrically connected after contacting, so that by connecting conductive polycrystalline silicon 23 by terminal
Pressure-resistant conductive polycrystalline silicon 21 in pressure-resistant groove 25 also simultaneously with the equipotential link of cellular conductive polycrystalline silicon 16.In Fig. 2 and Fig. 3,
Show there is the structure of two pressure rings 8 in pressure-resistant protection zone 3.Pressure-resistant insulating oxide 22 in terminal is pressure-resistant groove 25 with
It is the pressure-resistant conductive polycrystalline silicon in same manufacture layer, terminal is pressure-resistant groove 25 to connect the pressure-resistant insulating oxide 22 in pressure ring 9
21 be same manufacture layer with the pressure-resistant conductive polycrystalline silicon 21 being connected in pressure ring 9.
As described in Fig. 4 ~ Figure 15, above-mentioned utilization Charged Couple realizes that pressure-resistant power MOS (Metal Oxide Semiconductor) device can be by following techniques
Prepare, the preparation method of the power MOS (Metal Oxide Semiconductor) device specifically includes following steps：
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces include the first interarea 26 and the
Two interareas 27, include N-type drift region 10 and below the N-type drift region 10 between the first interarea 26 and the second interarea 27
N-type substrate 11；
As shown in figure 4, the material of semiconductor substrate includes silicon, the upper surface of N-type drift region 10 forms the first interarea 26, N
Lower surface the second interarea 27 of formation of type substrate 11.
B, the deposit hard mask layer 28 on the first interarea 26 of above-mentioned semiconductor substrate, optionally shelter and etch and be described
Hard mask layer 28, with the hard mask window 29 of insertion hard mask layer 28 needed for obtaining；
As shown in figure 5, the hard mask layer 27 is LPTEOS, thermal oxide silica adds chemical vapor deposition silica
Or thermal silicon dioxide adds silicon nitride.It to obtain by those skilled in the art the process of hard mask window 28 to the etching of hard mask layer 27
Know, repeat herein.
C, using above-mentioned hard mask window 29 anisotropic dry etch is carried out to the first interarea 26 of semiconductor substrate, with
Groove is formed in N-type drift region 10, the groove is less than the thickness of N-type drift region 10 in the depth of N-type drift region 10, described
Groove includes being located at the pressure-resistant groove 14 of connection in pressure-resistant protection zone 3 and the connection cellular groove 13 in active area 1；
As shown in fig. 6, when carrying out anisotropic dry etch using hard 29 pair of first interarea 26 of mask window, with hard
The lower of mask window 26 can form groove, so as to obtain connecting pressure-resistant groove 14 with being connected cellular groove 13.In active area 1 also
With active cellular groove, when pressure-resistant protection zone 3 has multiple pressure rings 8, in addition to the pressure-resistant groove 25 of terminal, it is described active
Cellular groove, connection cellular groove 13, to connect pressure-resistant groove 14 and the pressure-resistant groove 25 of terminal be that same processing step is prepared into
Arrive.
D, the hard mask layer 28 removed on above-mentioned first interarea 26, and in the first interarea 26 of semiconductor substrate and above-mentioned
Growth insulating oxide 30 in groove；
As shown in fig. 7, removing hard mask layer 28 by conventional technique, then the technique such as thermal oxide grows insulating oxide
30, the thickness of the insulating oxide 30 is the à of 2000 à ~ 10000, insulating oxide 30 be grown in simultaneously on the first interarea 26 with
And on the side wall of corresponding groove and bottom wall, required cellular insulating oxide 15 can be formed and resistance to by insulating oxide 30
Press insulating oxide 22.Insulating oxide 30 can be equally covered on the side wall of active cellular groove and bottom wall.
E, conductive polycrystalline silicon is deposited on above-mentioned first interarea 26, the conductive polycrystalline silicon is covered in exhausted on the first interarea
In edge oxide layer 30, and it is filled in groove；
F, optionally shelter and etch above-mentioned conductive polycrystalline silicon, obtain being located at the pressure-resistant conduction connected in pressure-resistant groove 14
Polysilicon 21, positioned at connection cellular groove 13 in cellular conductive polycrystalline silicon 16 and be covered on insulating oxide 30 and with it is resistance to
Press conductive polycrystalline silicon 21, the connection conductive polycrystalline silicon 23 of the contact electrical connection of cellular conductive polycrystalline silicon 16；
As shown in figure 8, after etching conductive polysilicon, pressure-resistant conductive polycrystalline silicon 21 and cellular conductive polycrystalline silicon can be obtained
16, meanwhile, connection conductive polycrystalline silicon 23 is covered on the insulating oxide 30 on the first interarea 26, and connection conductive polycrystalline silicon 23 covers
The notch of lid connection cellular groove 13, to be contacted with the cellular conductive polycrystalline silicon 16 in connection cellular groove 13, connects conductive polycrystalline
Silicon 23 is also covered on the first interarea of pressure-resistant protection zone 3, so as to it is pressure-resistant connection groove 14 in pressure-resistant conductive polycrystalline silicon
21 and the pressure-resistant groove 25 of terminal in pressure-resistant conductive polycrystalline silicon 21 contact after electrically connect, reach cellular conductive polycrystalline silicon 16 with it is resistance to
Press the isopotential electrical connection between conductive polycrystalline silicon 21.
Insulating oxide 30 on g, the first interarea of etching 26 of selectivity, to remove on the interarea 26 of active area 1 first
Insulating oxide 30, while removing in connection cellular groove 13 away from the insulating oxide connected on the pressure-resistant side side wall of groove 14
30 and corresponding cellular conductive polycrystalline silicon 16, with obtain being located in connection cellular groove 13 cellular insulating oxide 15, cover
Pressure-resistant insulating oxide 22 on the interarea 26 of lid terminal protection area 2 first and in the pressure-resistant groove 14 of connection and it is formed at connection
Grid hole 31 in cellular groove 13；
As shown in figure 9, remove the interarea 26 of active area 1 first on insulating oxide 30 while, can also etch covering
Connect the connection conductive polycrystalline silicon 23 on the notch of cellular groove 13, the cellular insulating oxide 15 in connection cellular groove 13 and
Cellular conductive polycrystalline silicon 16, to form grid hole 31 in connection cellular groove 13, grid hole 31 is in connection cellular groove 13
Depth be less than the depth of connection cellular groove 13.In addition, grid hole 31 can be formed simultaneously in active cellular groove, from power
Seen on the section of MOS device, the grid hole 31 in active cellular groove is symmetric.
H, the growth insulation gate oxide 17 in above-mentioned grid hole 31, the insulation gate oxide 17 are covered in and grid
Side wall, the surface of cellular conductive polycrystalline silicon 16 corresponding with grid hole 31 and the grid of the corresponding connection cellular groove 13 in hole 31
The corresponding cellular insulating oxide 15 of the bottom hole of hole 31；
The thin oxide layer of growth in grid hole 31, so that the gate oxide 17 that insulate is obtained, the thickness for the gate oxide 17 that insulate
Degree is less than the thickness of insulating oxide 30, the thickness and the gate oxide thickness phase in existing power MOS (Metal Oxide Semiconductor) device of the gate oxide 17 that insulate
Unanimously, here is omitted.
I, the deposit Gate Electrode Conductive polysilicon 18 in above-mentioned grid hole 31, the Gate Electrode Conductive polysilicon 18 is filled in growth
In the grid hole 31 for having insulation gate oxide 17；
As shown in Figure 10, the deposit Gate Electrode Conductive polysilicon 18 in grid hole 31, Gate Electrode Conductive polysilicon 18 passes through insulation
Gate oxide 17 is dielectrically separated from cellular conductive polycrystalline silicon 16, and Gate Electrode Conductive polysilicon 18 also passes through gate oxide 17 and the member of insulating
Born of the same parents' insulating oxide 15 is isolated.
J, on above-mentioned first interarea 26, autoregistration implanting p-type foreign ion, and by high temperature knot formation be located at it is active
P type trap zone 20 in area 1, the P type trap zone 20 is contacted with insulation gate oxide 17, and P type trap zone 20 is more positioned at Gate Electrode Conductive
The top of the bottom of crystal silicon 18；
As shown in figure 11, implanting p-type foreign ion and high temperature knot formation P type trap zone 20 can use the art
Known to conventional technique, specially those skilled in the art, here is omitted.The P type trap zone 20 of formation is located at connection member
Born of the same parents' groove 13 and the top at active cellular groove corresponding groove bottom, and P type trap zone 20 will also be located at the bottom of Gate Electrode Conductive polysilicon 18
The top at end, the bottom of Gate Electrode Conductive polysilicon 18 refers to Gate Electrode Conductive polysilicon 18 adjacent to the one of cellular insulating oxide 15
End.
K, on above-mentioned first interarea 26, carry out N-type impurity ion implanting, and by high temperature knot formation be located at p-type trap
N+ injection regions 19 in area 20, the N+ injection regions 19 are in contact with insulation gate oxide 17；
As shown in figure 12, injection N-type impurity ion and high temperature knot formation N+ injection regions 19 can also use this technology
The conventional technique in field, specially known to those skilled in the art, here is omitted.N+ injection regions 19 are located at P type trap zone
Top in 20, the depth of N+ injection regions 19 in vertical direction is less than the depth of P type trap zone 20.
L, insulating medium layer 24 is deposited on above-mentioned first interarea 26, and optionally etches the insulating medium layer 24,
With the contact hole of insertion insulating medium layer 24 needed for being formed, the contact hole includes the contact hole of resistance to nip 32 and active region contact
Hole 33；
As shown in figure 13, the technique deposit commonly used using the art obtains insulating medium layer 24, insulating medium layer 24
It is covered in connection conductive polycrystalline silicon 23, the pressure-resistant insulating oxide 22 on the interarea 26 of terminal protection area 2 first and active area 1
On first interarea 26.The contact hole of resistance to nip 32 is located at the surface of connection conductive polycrystalline silicon 23, passes through the energy of active region contact hole 33
So that N+ injection regions 19 and the subregion of P type trap zone 20 are exposed, in order to which active area metal 4 is contacted.
M, the deposited metal on above-mentioned first interarea 26, and selective etching sheet metal, to obtain being located at active area 1
Interior active area metal 4 and the metal of resistance to nip 5 positioned at pressure-resistant protection zone 3, the metal of resistance to nip 5 pass through resistance to nip contact
Hole 32 is electrically connected with being connected conductive polycrystalline silicon 23, and active area metal 4 passes through active region contact hole 33 and N+ injection regions 19 and p-type
The Ohmic contact of well region 20, active area metal 4 is electrically connected with the metal of resistance to nip 5；
As shown in figure 14, using obtaining metal level after conventional technique and material deposit, active area metal 4 and pressure-resistant
Area's metal 5 is contacted by part, and to realize the electrical connection between active area metal 4 and the metal of resistance to nip 5, the metal of resistance to nip 5 passes through
The contact hole of resistance to nip 32 is electrically connected with being connected conductive polycrystalline silicon 23, now, the metal of resistance to nip 5 and cellular conductive polycrystalline silicon 16 and
Pressure-resistant conductive polycrystalline silicon 21 is electrically connected.
N, the deposit metal layer on back 12 on the second interarea 27 of semiconductor substrate, the metal layer on back 12 are served as a contrast with N-type
The Ohmic contact of bottom 11.
As shown in figure 15, metal layer on back 12 and the Ohmic contact of N-type substrate 11, power can be formed by metal layer on back 12
The drain electrode end of MOS device.
The working mechanism of terminal pressure-resistance structure of the present invention is：Connect pressure ring 9 equal with being connected cellular ring 6, active cellular 7
Using groove structure, cellular conductive polycrystalline silicon 16, cellular insulating oxide 15 and N-type drift region 10 in active area 1 are formed
Pressure-resistant conductive polycrystalline silicon 21, pressure-resistant insulating oxide 22 and N-type drift in the capacitance structure of active area 1, pressure-resistant protection zone 3
Area 10 forms the capacitance structure of pressure-resistant protection zone 3.The cellular conductive polycrystalline silicon 16 in cellular ring 6 is connected with being connected in pressure ring 9
Pressure-resistant conductive polycrystalline silicon 21 keep equipotential, in the pressure-resistant work of power MOS (Metal Oxide Semiconductor) device, cellular is conductive more in connection cellular ring 6
The current potential of crystal silicon 16 is zero potential.
By taking N-type MOS device as an example, when the pressure-resistant work of device, the metal layer on back 12 on the second interarea 27 applies one
Positive voltage, the positive voltage to be coupled out positive charge in N-type drift region 10, the positive charge and the electricity in N-type drift region 10
Son is when reaching charge balance, and its depletion layer formed obtains largest extension, is connecting pressure-resistant groove 14 with being connected cellular groove
Before 13 respective neighbouring depletion layers are in contact, voltage is the pressure-resistant insulating oxide on first interarea 26 in pressure-resistant protection zone 3
Layer 22 is undertaken, and after above-mentioned depletion layer is connected, voltage is just undertaken by depletion layer so that the electric field in device active region 1
Laterally it can be extended to the transition of terminal protection area 2, it is to avoid puncture, and by increasing the number of pressure ring 8 in terminal protection area 2
The lifting of the pressure-resistant voltage endurance capability of protection zone 3 can just be realized by measuring, and covered with pressure-resistant on the first interarea 26 in pressure-resistant protection zone 3
Insulating oxide 22, the thickness of pressure-resistant insulating oxide 22 is thicker, its voltage endurance capability generally far above device resistance to pressure request,
Therefore, terminal protection area 2 can realize the voltage endurance capability higher than active area 1.
By taking a 130V power MOSFET device as an example, the drain-source breakdown voltage BVdss of device is tested, test condition is
Drain-source applies a scanning voltage Vds originated from zero volt, while drain-source leakage current Idss is read, when Idss is increased to 250uA
When, Vds now is the breakdown voltage BVdss of device, and the simulation result as shown in Figure 16, Figure 17 and Figure 18, emulation is shown
In intention, abscissa is scanning voltage Vds, and ordinate is drain-source leakage current Idss.When only changing the quantity of its pressure ring 8,
There is no pressure ring 8, set pressure ring 8 to be respectively 128V, 145V, 148V with setting the breakdown voltage of two pressure rings 8, and
When setting a pressure ring 8, the size in its terminal protection area 2 only has 10 μm or so, according to traditional field limiting ring 39 and field
The terminal pressure-resistance structure of plate, at least more than 30 μm of its size, and realize pressure-resistant power for this kind of utilization Charged Couple
Device, the pressure-resistance structure of traditional field limiting ring 39 is different from the pressure-resistant mechanism of active area 1 because of its pressure-resistant mechanism, this two parts for
The concentration requirement of N-type drift region 10 emphasizes particularly on different fields, therefore, structure of the present invention be more suitable for this kind of utilization Charged Couple realize it is pressure-resistant
Power device, with higher superiority of effectiveness, is suitable for producing in batches.
Claims (6)
1. a kind of utilization Charged Couple realizes pressure-resistant power MOS (Metal Oxide Semiconductor) device, in the top plan view of the power MOS (Metal Oxide Semiconductor) device, bag
The active area positioned at semiconductor substrate and terminal protection area are included, the active area is located at the center of semiconductor substrate, and terminal is protected
Area is protected to be located at the outer ring of active area and include the pressure-resistant protection of adjacent active area around surrounding in the active area, terminal protection area
Area；On the section of the power MOS (Metal Oxide Semiconductor) device, the semiconductor substrate include the first conduction type drift region above with
And underlying first conductivity type substrate, the first conduction type drift region of the first conductivity type substrate adjoining, first
The upper surface of conduction type drift region forms the first interarea of semiconductor substrate, the lower surface formation half of the first conductivity type substrate
Second interarea of conductor substrate；It is characterized in that：
In the top plan view of the power MOS (Metal Oxide Semiconductor) device, include in pressure-resistant protection zone at least one pressure ring, pressure-resistant protection zone
The pressure ring formation connection pressure ring of adjacent active regions；
On the section of the power MOS (Metal Oxide Semiconductor) device, connection pressure ring uses groove structure, and the pressure-resistant groove of connection is by the first master
Face extends vertically downward, and the extension depth for connecting pressure-resistant groove is less than the thickness of the first conduction type drift region, connects pressure-resistant ditch
The inwall and bottom wall of groove are filled covered with pressure-resistant insulating oxide in the pressure-resistant groove of connection covered with pressure-resistant insulating oxide
There is pressure-resistant conductive polycrystalline silicon；Insulating medium layer is provided with above the notch for connecting pressure-resistant groove, and the insulating medium layer also covers
Cover on the pressure-resistant insulating oxide on the interarea of terminal protection area first, the metal of resistance to nip is set on the insulating medium layer；
On the section of the power MOS (Metal Oxide Semiconductor) device, the active member including some regular arrays and the distribution that is parallel to each other in active area
Born of the same parents, the active cellular uses groove structure, and the active cellular groove is extended downwardly downward vertically from the first interarea, active member
The depth of born of the same parents' groove extension is less than the thickness of the first conduction type drift layer；The corresponding inner side between neighboring active cellular groove
Covered with insulated gate oxide layer on wall, covered with cellular insulating oxide on the bottom wall of active cellular groove and remaining side wall
Layer, and it is also filled with active cellular groove cellular conductive polycrystalline silicon and grid corresponding with the insulation gate oxide is led
Electric polysilicon, Gate Electrode Conductive polysilicon is connected by gate insulator oxide layer with the side wall of active cellular groove, and Gate Electrode Conductive
Polysilicon is isolated with cellular conductive polycrystalline silicon and cellular insulating oxide respectively by the gate oxide that insulate；In neighboring active
The second conduction type well region is provided between cellular groove above corresponding outer wall side, is provided with the second conduction type well region
First conductivity type implanted region, the first conductivity type implanted region and the second conductive type of trap area respectively with corresponding insulation grid oxygen
Change layer contact connection, the bottom of Gate Electrode Conductive polysilicon is located at the lower section of the second conduction type well region, the injection of the first conduction type
Area and the second conduction type well region and active area metal ohmic contact, active area metal pass through insulating medium layer and Gate Electrode Conductive
Polysilicon is isolated；
Active area metal is electrically connected with the metal of resistance to nip, and the cellular conductive polycrystalline silicon in active cellular groove is with being connected pressure-resistant ditch
Pressure-resistant conductive polycrystalline silicon in groove keeps equipotential；
In the top plan view of the power MOS (Metal Oxide Semiconductor) device, active area includes the connection cellular ring positioned at the active area outmost turns,
Regular array and the active cellular for the distribution that is parallel to each other are located in connection cellular ring in active area, and the connection pressure ring is with being connected
Cellular ring is parallel；Active cellular in active area is connected with being connected cellular ring；The active cellular being parallel to each other in active area it
Between spacing it is equal；
On the section of the power MOS (Metal Oxide Semiconductor) device, connection cellular ring uses groove structure, and the connection cellular groove is by the first master
Face extends vertically downward, and the extension depth for connecting pressure-resistant groove is less than the thickness of the first conduction type drift region, connects cellular ditch
Groove on the madial wall of the active upper lateral part of cellular groove one covered with insulated gate oxide layer, and the bottom wall of connection cellular groove and
Covered with cellular insulating oxide on remaining side wall；Connect in cellular groove filled with cellular conductive polycrystalline silicon and with insulation
The corresponding Gate Electrode Conductive polysilicon of gate oxide, Gate Electrode Conductive polysilicon is by the gate oxide that insulate with being connected cellular groove
Side wall is in contact；
On the section of the power MOS (Metal Oxide Semiconductor) device, in connection cellular groove away from above the outer wall side for connecting pressure-resistant groove side
Provided with the second conduction type well region, the first conductivity type implanted region, first conductive-type are provided with the second conduction type well region
Type injection region and the second conduction type well region are in contact with insulation gate oxide, and the bottom of Gate Electrode Conductive polysilicon is located at
The lower section of second conduction type well region, the first conductivity type implanted region and the second conduction type well region are led with active area first
Active area metal ohmic contact on face, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and cellular
Conductive polycrystalline silicon is isolated；Cellular conductive polycrystalline silicon and the pressure-resistant conductive polycrystalline that is connected in pressure-resistant groove in connection cellular groove
Silicon keeps equipotential；
On the section of the power MOS (Metal Oxide Semiconductor) device, covered with connection conductive polycrystalline silicon, institute above the notch for connecting pressure-resistant groove
State connection conductive polycrystalline silicon and the cellular in the pressure-resistant conductive polycrystalline silicon and connection cellular groove being connected in pressure-resistant groove is conductive
Polysilicon is electrically connected after being in contact, and insulating medium layer is covered on connection conductive polycrystalline silicon, and the metal of resistance to nip is conductive more with being connected
Crystal silicon is electrically connected.
2. utilization Charged Couple according to claim 1 realizes pressure-resistant power MOS (Metal Oxide Semiconductor) device, it is characterized in that：In the work(
On the section of rate MOS device, covered with connection conductive polycrystalline silicon above the notch for connecting pressure-resistant groove, the connection is conductive more
Crystal silicon is in contact with the cellular conductive polycrystalline silicon in the pressure-resistant conductive polycrystalline silicon and active cellular groove that are connected in pressure-resistant groove
After electrically connect, insulating medium layer be covered in connection conductive polycrystalline silicon on, the metal of resistance to nip and be connected conductive polycrystalline silicon electrically connect.
3. utilization Charged Couple according to claim 1 realizes pressure-resistant power MOS (Metal Oxide Semiconductor) device, it is characterized in that：It is described pressure-resistant
When having multiple pressure rings in protection zone, the pressure ring in pressure-resistant protection zone is parallel to each other.
4. a kind of utilization Charged Couple realizes the preparation method of pressure-resistant power MOS (Metal Oxide Semiconductor) device, it is characterized in that, the power MOS devices
The preparation method of part comprises the following steps：
（a）, the semiconductor substrate with two opposing main faces is provided, described two opposing main faces include the first interarea to be led with second
Face, includes the first conduction type drift region and positioned at the first conduction type drift region between the first interarea and the second interarea
First conductivity type substrate of lower section；
（b）, on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch the hard mask
Layer, with the hard mask window of insertion hard mask layer needed for obtaining；
（c）, using above-mentioned hard mask window anisotropic dry etch is carried out to the first interarea of semiconductor substrate, with first
Groove is formed in conduction type drift region, depth of the groove in the first conduction type drift region is floated less than the first conduction type
The thickness in area is moved, the groove includes being located at the pressure-resistant groove of connection in pressure-resistant protection zone and the active member in active area
Born of the same parents' groove；
The step（c）In, obtained groove also includes connection cellular groove annular in shape, and active cellular groove is respectively positioned on ring-type
Connection cellular groove in, connection cellular groove on the madial wall of the active upper lateral part of cellular groove one covered with insulated gate oxygen
Change on layer, and the bottom wall and remaining side wall of connection cellular groove covered with cellular insulating oxide；Filled out in connection cellular groove
Filled with cellular conductive polycrystalline silicon and with the corresponding Gate Electrode Conductive polysilicon of insulation gate oxide, Gate Electrode Conductive polysilicon passes through
Insulation gate oxide be in contact with being connected the side wall of cellular groove, and Gate Electrode Conductive polysilicon by insulate gate oxide respectively with
Cellular conductive polycrystalline silicon and cellular insulating oxide are isolated
On the section of the power MOS (Metal Oxide Semiconductor) device, in connection cellular groove away from above the outer wall side for connecting pressure-resistant groove side
Provided with the second conduction type well region, the first conductivity type implanted region, first conductive-type are provided with the second conduction type well region
Type injection region and the second conduction type well region are in contact with insulation gate oxide, and the bottom of Gate Electrode Conductive polysilicon is located at
The lower section of second conduction type well region, the first conductivity type implanted region and the second conduction type well region are led with active area first
Active area metal ohmic contact on face, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and cellular
Conductive polycrystalline silicon is isolated；
（d）, the hard mask layer that removes on above-mentioned first interarea, it is and raw in the first interarea and above-mentioned groove of semiconductor substrate
Long insulating oxide；
（e）, conductive polycrystalline silicon is deposited on above-mentioned first interarea, the conductive polycrystalline silicon is covered in the insulation oxygen on the first interarea
Change on layer, and be filled in groove；
（f）, optionally shelter and etch above-mentioned conductive polycrystalline silicon, obtain being located at the pressure-resistant conductive polycrystalline connected in pressure-resistant groove
Silicon, the cellular conductive polycrystalline silicon in active cellular groove and be covered on insulating oxide and with pressure-resistant conductive polycrystalline
Silicon, the connection conductive polycrystalline silicon of cellular conductive polycrystalline silicon contact electrical connection；
（g）, selectivity the interarea of etching first on insulating oxide, to remove the insulating oxide on the interarea of active area first
Layer, while removing in active cellular groove away from the insulating oxide and corresponding cellular on connection pressure-resistant groove side side wall
Conductive polycrystalline silicon, to obtain the cellular insulating oxide in active cellular groove, cover on the first interarea of terminal protection area
And connect the pressure-resistant insulating oxide in pressure-resistant groove and the grid hole being formed in active cellular groove；
（h）, in above-mentioned grid hole growth insulation gate oxide, the insulation gate oxide is covered in corresponding with grid hole
The side wall of active cellular groove, the surface of cellular conductive polycrystalline silicon corresponding with grid hole and the corresponding cellular of grid hole bottom hole
Insulating oxide；
（i）, in above-mentioned grid hole deposit Gate Electrode Conductive polysilicon, the Gate Electrode Conductive polysilicon, which is filled in growth, insulated gate
In the grid hole of oxide layer；
（j）, on above-mentioned first interarea, autoregistration inject the second conductive type impurity ion, and pass through high temperature knot formation position
In the second conduction type well region in active area, the second conduction type well region is contacted with insulation gate oxide, and second leads
Electric type well region is located at the top of Gate Electrode Conductive polysilicon bottom；
（k）, on above-mentioned first interarea, carry out the first conductive type impurity ion implanting, and by high temperature knot formation be located at
The first conductivity type implanted region in second conduction type well region, first conductivity type implanted region and insulation gate oxide phase
Contact；
（l）, on above-mentioned first interarea deposit insulating medium layer, and the insulating medium layer is optionally etched, to be formed
The contact hole of insertion insulating medium layer is needed, the contact hole includes the contact hole of resistance to nip and active region contact hole；
（m）, on above-mentioned first interarea deposited metal, and selective etching sheet metal, to obtain being located in active area
Active area metal and the metal of resistance to nip positioned at pressure-resistant protection zone, the metal of resistance to nip is by the contact hole of resistance to nip with being connected
Conductive polycrystalline silicon is electrically connected, and active area metal passes through active region contact hole and the first conductivity type implanted region and the second conductive-type
Type well region Ohmic contact, active area metal is electrically connected with the metal of resistance to nip；
（n）, deposit metal layer on back on the second interarea of semiconductor substrate, the metal layer on back and the first conduction type are served as a contrast
Bottom Ohmic contact.
5. the preparation method of pressure-resistant power MOS (Metal Oxide Semiconductor) device is realized using Charged Couple according to claim 4, it is characterized in that：
Stating the material of semiconductor substrate includes silicon, and the thickness of insulating oxide is the à of 2000 à ~ 10000.
6. the preparation method of pressure-resistant power MOS (Metal Oxide Semiconductor) device is realized using Charged Couple according to claim 4, it is characterized in that：
The hard mask layer is LPTEOS, thermal oxide silica adds chemical vapor deposition silica or thermal silicon dioxide to add nitridation
Silicon.
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| CN106356398A (en) * | 2015-07-16 | 2017-01-25 | 张家港意发功率半导体有限公司 | High-voltage power device with special voltage withstanding ring |
| CN106653836B (en) * | 2016-12-01 | 2023-09-01 | 无锡新洁能股份有限公司 | Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same |
| US10600897B2 (en) * | 2017-11-08 | 2020-03-24 | Fuji Electric Co., Ltd. | Semiconductor device |
| CN108063159B (en) * | 2017-12-08 | 2020-09-18 | 上海芯龙半导体技术股份有限公司 | Terminal structure of semiconductor power device, semiconductor power device and manufacturing method thereof |
| CN107994069B (en) * | 2017-12-29 | 2024-03-15 | 安徽赛腾微电子有限公司 | IGBT device and manufacturing method thereof |
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| CN108767004B (en) * | 2018-08-03 | 2024-02-09 | 江苏捷捷微电子股份有限公司 | Split gate MOSFET device structure and manufacturing method thereof |
| CN113782432A (en) * | 2021-08-05 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Semiconductor device with trench type shielding structure and method of manufacturing the same |
| CN115295627B (en) * | 2022-08-25 | 2023-09-05 | 中国电子科技集团公司第二十四研究所 | High-voltage power semiconductor device and method for manufacturing the same |
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