CN104716192A - Power MOS device capable of achieving voltage resistance by charge coupling and preparation method thereof - Google Patents
Power MOS device capable of achieving voltage resistance by charge coupling and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 230000008878 coupling Effects 0.000 title abstract 2
- 238000010168 coupling process Methods 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 254
- 239000002184 metal Substances 0.000 claims abstract description 96
- 230000001413 cellular effect Effects 0.000 claims description 319
- 239000004065 semiconductor Substances 0.000 claims description 98
- 229920005591 polysilicon Polymers 0.000 claims description 78
- 229910044991 metal oxide Inorganic materials 0.000 claims description 60
- 150000004706 metal oxides Chemical class 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000009826 distribution Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract description 32
- 239000007924 injection Substances 0.000 abstract description 32
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000010923 batch production Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- Engineering & Computer Science (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thyristors (AREA)
Abstract
The invention relates to a power MOS device capable of achieving voltage resistance by charge coupling and a preparation method thereof. The device is characterized in that a connected voltage resisting ring is of a groove structure; a connected voltage resisting groove is filled with voltage-resistant conductive polycrystalline silicon; an active area includes a plurality of active cells; grid electrode conductive polycrystalline silicon is in contact with the sidewall of an active cell groove through an insulated grid oxide layer and is isolated from cell conductive polycrystalline silicon and a cell insulated oxide layer through the insulated grid oxide layer; the bottom part of the grid electrode conductive polycrystalline silicon is positioned below a second conductive type well region; a first conductive type injection area and the second conductive type well region are both in contact with active area metal ohm on the first main surface of the active area; metal in the active area is electrically connected with metal in a voltage resisting area; the cell conductive polycrystalline silicon is kept at equal potential with the voltage resisting conductive polycrystalline silicon. The device is high in voltage resistance and high in voltage resisting reliability; in addition, a terminal protection area occupies a little area of the whole chip area; the device is suitable for mass production.
Description
Technical field
The present invention relates to a kind of power MOS (Metal Oxide Semiconductor) device and preparation method thereof, especially a kind of Charged Couple that utilizes realizes withstand voltage power MOS (Metal Oxide Semiconductor) device and preparation method thereof, belongs to the technical field of power MOS (Metal Oxide Semiconductor) device.
Background technology
Semiconductor power device needs to bear certain voltage usually, voltage range from tens volts to several kilovolts not etc., and the structure of the two large key elements the realizing device withstand voltage material that to be devices use and device.The semiconductor power device be most widely used at present is silicon device, and the material used is silicon materials, is generally epitaxial silicon material, and it has specific resistivity and thickness; And the structure of device includes source structure and terminal protection plot structure; the former be generally break-over of device work time electric current flow through region; when latter is device withstand voltage work, electric field provides by active-surface is outwards extending transversely the region extending and bear, thus guarantees that device is not breakdown in the operating voltage range allowed.
Weigh the area proportion that good Yu the bad major criterion of power device terminal protection plot structure comprises chip shared by withstand voltage limit capacity, withstand voltage reliability and pressure-resistance structure.In general; usually the voltage endurance capability of terminal protection plot structure is needed to be not less than the active area of device; the requirement of withstand voltage of device is higher; then the size of terminal protection plot structure is larger, and the area proportion namely accounting for whole chip is higher, and under the prerequisite that the area that chip is total is fixed; the area of active area will be forced to reduce; thus reduce the current capacity of device, therefore, desirable terminal protection plot structure is that voltage endurance capability is strong and size is little as much as possible.
Usually, terminal protection district comprises withstand voltage protection zone, traditional withstand voltage protection zone many employings field limiting ring structure or field plate structure or both combinations, as shown in Figure 1, be specially the structure chart that a kind of withstand voltage protection zone adopts the trench MOSFET device of field limiting ring structure, it comprises N-type drift region 10 and the N-type substrate 11 adjacent with described N-type drift region 10, groove-shaped cellular and multiple field limiting ring 39 are set in N-type drift region 10, wherein, groove-shaped cellular comprises active groove 40, described active groove 40 is positioned at active P trap 38, the degree of depth stretches in N-type drift region 10, namely the bottom land of active groove 40 is positioned at the below of active P trap 38.The inwall growth of active groove 40 has insulated gate oxide layer 41, have in the active groove 40 of insulated gate oxide layer 41 in growth and fill active conductive polycrystalline silicon 35, active N+ injection region 34 is provided with above neighboring active groove 40 sidewall, described active N+ injection region 34 is positioned at the top of active P trap 38, and contacts with the lateral wall of active groove 40.The notch of active groove 40 is coated with dielectric layer 36, and described dielectric layer 36 also covers the surface of the N-type drift region 10 of withstand voltage protection zone, and active area metal 37 covers on dielectric layer 36, and with active P trap 38 and active N+ injection region 34 ohmic contact.During concrete enforcement, in withstand voltage protection zone, between the field limiting ring 39 formed by P trap and N-type drift region 10, form PN junction.
When said structure is withstand voltage; PN junction in withstand voltage protection zone can exhaust; the region exhausted can support electric field along with the increase of voltage laterally connects together gradually; the quantity of field limiting ring 39 determines withstand voltage height; simultaneously; the concentration of field limiting ring 39, junction depth, spacing all will be determined according to the drift region concentration forming with it PN junction; therefore; need specific technological process to make field limiting ring 39; and easily by the impact of other technique, thus cause the withstand voltage stability of device and reliability to be subject to fluctuation.
In addition, for in some semiconductor device, cellular in active area adopts capacitor board structure, this structure can realize Charged Couple, when the electric charge in the electric charge be coupled and its surrounding drift region reaches balance, the depletion region of two kinds of electric charge formation can support withstand voltage, contrast conventional power devices, the resistivity of the epitaxial silicon material that this kind of device uses is less, lower conducting resistance can be obtained, but the terminal pressure-resistance structure of higher drift region concentration to device is had higher requirement, the number needs of field limiting ring 39 is more, and technique is held wide less, these are all be unfavorable for the reliability of this kind of advanced device and cost performance.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art; a kind of Charged Couple that utilizes is provided to realize withstand voltage power MOS (Metal Oxide Semiconductor) device and preparation method thereof; its voltage endurance capability is strong; withstand voltage reliability is high; manufacture craft is simple; and the proportion that terminal protection district takies chip entire area is lower, there is high cost performance, be suitable for batch production.
According to technical scheme provided by the invention, the described Charged Couple that utilizes realizes withstand voltage power MOS (Metal Oxide Semiconductor) device, in the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise the active area and terminal protection district that are positioned at semiconductor substrate, described active area is positioned at the center of semiconductor substrate, terminal protection district is positioned at the outer ring of active area and around the described active area of encirclement, comprises the withstand voltage protection zone of adjacent active area in terminal protection district; On the cross section of described power MOS (Metal Oxide Semiconductor) device, described semiconductor substrate comprises the first conduction type drift region being positioned at top and the first conductivity type substrate being positioned at below, described first conductivity type substrate adjoins the first conduction type drift region, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate forms the second interarea of semiconductor substrate; Its innovation is:
In the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise at least one pressure ring in withstand voltage protection zone, in withstand voltage protection zone, the pressure ring of adjacent active regions is formed and connects pressure ring;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connect pressure ring and adopt groove structure, described connection is withstand voltage trenched to be extended vertically downward by the first interarea, connect the thickness that the withstand voltage trenched extension degree of depth is less than the first conduction type drift region, connect withstand voltage trenched inwall and diapire is coated with withstand voltage insulating oxide, in the connection being coated with withstand voltage insulating oxide is withstand voltage trenched, is filled with withstand voltage conductive polycrystalline silicon; Above the notch that connection is withstand voltage trenched, be provided with insulating medium layer, and described insulating medium layer also covers on the withstand voltage insulating oxide on terminal protection district first interarea, and described insulating medium layer arranges withstand voltage zone metal;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, some regular array are comprised and the active cellular of the distribution that is parallel to each other in active area, described active cellular adopts groove structure, described active cellular groove is from the first interarea downward vertically to downward-extension, and the degree of depth that active cellular groove extends is less than the thickness of the first conduction type drift layer; Madial wall corresponding between neighboring active cellular groove is coated with insulated gate oxide layer, the diapire of active cellular groove and remaining sidewall are coated with cellular insulating oxide, and in active cellular groove, be also filled with cellular conductive polycrystalline silicon and the Gate Electrode Conductive polysilicon corresponding with described insulated gate oxide layer, Gate Electrode Conductive polysilicon is connected with the sidewall of active cellular groove by gate insulator oxide layer, and Gate Electrode Conductive polysilicon pass through insulated gate oxide layer respectively with cellular conductive polycrystalline silicon and cellular insulating oxide isolated; The second conduction type well region is provided with above outer wall side corresponding between neighboring active cellular groove, the first conductivity type implanted region is provided with in described second conduction type well region, first conductivity type implanted region and the second conductive type of trap district contact with corresponding insulated gate oxide layer respectively and connect, the bottom of Gate Electrode Conductive polysilicon is positioned at the below of the second conduction type well region, first conductivity type implanted region and the second conduction type well region and active area metal ohmic contact, active area metal by insulating medium layer and Gate Electrode Conductive polysilicon isolated;
Active area metal is connected with withstand voltage zone metal electric, and cellular conductive polycrystalline silicon in active cellular groove be connected withstand voltage trenched in withstand voltage conductive polycrystalline silicon keep equipotential.
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connection conductive polycrystalline silicon is coated with above the notch that connection is withstand voltage trenched, described connection conductive polycrystalline silicon is electrically connected after contacting with the cellular conductive polycrystalline silicon be connected in withstand voltage trenched interior withstand voltage conductive polycrystalline silicon and active cellular groove, insulating medium layer covers and connects on conductive polycrystalline silicon, withstand voltage zone metal be connected conductive polycrystalline silicon and be electrically connected.
In the top plan view of described power MOS (Metal Oxide Semiconductor) device, active area comprises the connection cellular ring being positioned at described active area outmost turns, regular array in active area and the active cellular of the distribution that is parallel to each other are positioned at and connect cellular ring, described connection pressure ring be connected cellular ring and parallel; Active cellular in active area be connected cellular ring be connected; Spacing between the active cellular be parallel to each other in active area is equal.
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connect cellular ring and adopt groove structure, described connection cellular groove is extended vertically downward by the first interarea, connect the thickness that the withstand voltage trenched extension degree of depth is less than the first conduction type drift region, the madial wall of contiguous active cellular groove one upper lateral part of connection cellular groove is coated with insulated gate oxide layer, and the diapire of connection cellular groove and remaining sidewall are coated with cellular insulating oxide; Connect in cellular groove and be filled with cellular conductive polycrystalline silicon and the Gate Electrode Conductive polysilicon corresponding with insulated gate oxide layer, Gate Electrode Conductive polysilicon is contacted with the sidewall being connected cellular groove by insulated gate oxide layer;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, the second conduction type well region is provided with connecting cellular groove away from above the outer wall side connecting withstand voltage trenched side, the first conductivity type implanted region is provided with in second conduction type well region, described first conductivity type implanted region and the second conduction type well region all contact with insulated gate oxide layer, and the bottom of Gate Electrode Conductive polysilicon is positioned at the below of the second conduction type well region, first conductivity type implanted region and the second conduction type well region all with the active area metal ohmic contact on the interarea of active area first, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and cellular conductive polycrystalline silicon isolated, connect cellular conductive polycrystalline silicon in cellular groove and be connected withstand voltage trenched interior withstand voltage conductive polycrystalline silicon and keep equipotential.
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connection conductive polycrystalline silicon is coated with above the notch that connection is withstand voltage trenched, described connection conductive polycrystalline silicon is electrically connected after contacting with the cellular conductive polycrystalline silicon be connected in withstand voltage trenched interior withstand voltage conductive polycrystalline silicon and connection cellular groove, insulating medium layer covers and connects on conductive polycrystalline silicon, withstand voltage zone metal be connected conductive polycrystalline silicon and be electrically connected.
When having multiple pressure ring in described withstand voltage protection zone, the pressure ring in withstand voltage protection zone is parallel to each other.
Utilize Charged Couple to realize a preparation method for withstand voltage power MOS (Metal Oxide Semiconductor) device, the preparation method of described power MOS (Metal Oxide Semiconductor) device comprises the steps:
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces comprise the first interarea and the second interarea, comprise the first conduction type drift region and be positioned at the first conductivity type substrate below described first conduction type drift region between the first interarea and the second interarea;
B, on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch described hard mask layer, to obtain the hard mask window of required through hard mask layer;
C, first interarea of above-mentioned hard mask window to semiconductor substrate is utilized to carry out anisotropic dry etch, to form groove in the first conduction type drift region, described groove is less than the thickness of the first conduction type drift region in the degree of depth of the first conduction type drift region, and it is withstand voltage trenched and be positioned at the active cellular groove of active area that described groove comprises the connection being positioned at withstand voltage protection zone;
D, the hard mask layer removed on above-mentioned first interarea, and insulating oxide is grown in first interarea and above-mentioned groove of semiconductor substrate;
E, on above-mentioned first interarea deposit conductive polycrystalline silicon, described conductive polycrystalline silicon covers on the insulating oxide on the first interarea, and is filled in groove;
F, optionally shelter and etch above-mentioned conductive polycrystalline silicon, obtain being positioned at and connect withstand voltage trenched withstand voltage conductive polycrystalline silicon, be positioned at the cellular conductive polycrystalline silicon of active cellular groove and cover on insulating oxide and to contact with withstand voltage conductive polycrystalline silicon, cellular conductive polycrystalline silicon the connection conductive polycrystalline silicon be electrically connected;
G, optionally etch insulating oxide on the first interarea, to remove the insulating oxide on the interarea of active area first, remove the cellular conductive polycrystalline silicon away from the insulating oxide connected on the sidewall of withstand voltage trenched side and correspondence in active cellular groove simultaneously, with obtain being positioned at active cellular groove cellular insulating oxide, cover on terminal protection district first interarea and connect withstand voltage trenched withstand voltage insulating oxide and be formed at the grid hole of active cellular groove;
H, in above-mentioned grid hole, grow insulated gate oxide layer, described insulated gate oxide layer covers cellular insulating oxide corresponding at the bottom of the sidewall of the active cellular groove corresponding with grid hole, the surface of the cellular conductive polycrystalline silicon corresponding with grid hole and grid hole hole;
I, in above-mentioned grid hole deposit Gate Electrode Conductive polysilicon, described Gate Electrode Conductive polysilicon be filled in growth have in the grid hole of insulated gate oxide layer;
J, on above-mentioned first interarea, the second conductive type impurity ion is injected in autoregistration, and the second conduction type well region being positioned at active area is formed by high temperature knot, described second conduction type well region contacts with insulated gate oxide layer, and the second conductive type of trap district is positioned at the top of Gate Electrode Conductive polysilicon bottom;
K, on above-mentioned first interarea, carry out the first conductive type impurity ion implantation, and formed the first conductivity type implanted region being positioned at the second conduction type well region by high temperature knot, described first conductivity type implanted region contacts with insulated gate oxide layer;
L, on above-mentioned first interarea deposit insulating medium layer, and optionally etch described insulating medium layer, to form the contact hole of required through insulating medium layer, described contact hole comprises withstand voltage zone contact hole and active region contact hole;
M, on above-mentioned first interarea deposited metal, and optionally etching sheet metal, to obtain being positioned at the active area metal of active area and being positioned at the withstand voltage zone metal of withstand voltage protection zone, described withstand voltage zone metal by withstand voltage zone contact hole be connected conductive polycrystalline silicon and be electrically connected, active area metal is by active region contact hole and the first conductivity type implanted region and the second conduction type well region ohmic contact, and active area metal is connected with withstand voltage zone metal electric;
N, on the second interarea of semiconductor substrate deposit metal layer on back, described metal layer on back and the first conductivity type substrate ohmic contact.
The material stating semiconductor substrate comprises silicon, and the thickness of insulating oxide is 2000 à ~ 10000 à.
In described step c, the groove obtained also comprises connection cellular groove in the form of a ring, active cellular groove is all positioned at the connection cellular groove of ring-type, the madial wall of contiguous active cellular groove one upper lateral part of connection cellular groove is coated with insulated gate oxide layer, and the diapire of connection cellular groove and remaining sidewall are coated with cellular insulating oxide; Connect in cellular groove and be filled with cellular conductive polycrystalline silicon and the Gate Electrode Conductive polysilicon corresponding with insulated gate oxide layer, Gate Electrode Conductive polysilicon is contacted with the sidewall being connected cellular groove by insulated gate oxide layer, and Gate Electrode Conductive polysilicon by insulated gate oxide layer respectively with cellular conductive polycrystalline silicon and cellular insulating oxide isolated
On the cross section of described power MOS (Metal Oxide Semiconductor) device, the second conduction type well region is provided with connecting cellular groove away from above the outer wall side connecting withstand voltage trenched side, the first conductivity type implanted region is provided with in second conduction type well region, described first conductivity type implanted region and the second conduction type well region all contact with insulated gate oxide layer, and the bottom of Gate Electrode Conductive polysilicon is positioned at the below of the second conduction type well region, first conductivity type implanted region and the second conduction type well region all with the active area metal ohmic contact on the interarea of active area first, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and cellular conductive polycrystalline silicon isolated.
Described hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
In both described " the first conduction type " and " the second conduction type ", for N-type power MOSFET device, the first conduction type refers to N-type, and the second conduction type is P type; For P type power MOSFET device, the first conduction type is just in time contrary with N type semiconductor device with the type of the second conduction type indication.
Advantage of the present invention:
1, by cellular conductive polycrystalline silicon in active area, the capacitance structure that cellular insulating oxide and the first conduction type drift region are formed, this capacitance structure is when withstand voltage, utilize Charged Couple principle between adjacent trenches, form depletion layer withstand voltage to support, groove is darker, the voltage that can bear is also higher, above-mentioned pressure-resistance structure has been extended to terminal protection district by active area by the present invention just, pressure ring adopts groove capacitor structure, in the transitional region in active area and terminal protection district, connecting pressure ring utilizes Charged Couple principle to form depletion layer when withstand voltage with being connected between cellular ring, be connected together by the connection conductive polycrystalline silicon between them with the cellular conductive polycrystalline silicon be connected in cellular groove owing to connecting withstand voltage trenched interior withstand voltage conductive polycrystalline silicon, keep equipotential, therefore, the electric charge be herein coupled out can reach charge balance completely with the electric charge in the first conduction type drift region, thus form the withstand voltage effect consistent with in active area, and before the withstand voltage trenched depletion layer with being connected between cellular groove of connection is connected together, due to the first interarea of withstand voltage protection zone being coated with withstand voltage insulating oxide, therefore, thicker withstand voltage insulating oxide also can bear voltage now completely, in addition, according to the difference that device withstand voltage requires, the quantity of pressure ring can be conveniently set, emulation and experimental result show, for 100V and following device, usually the pressure ring that 1-2 circle is set only is needed can to guarantee requirement of withstand voltage completely, even if for the device of 150V-200V, also only needing, 3-4 is set and encloses pressure ring, because pressure ring is groove structure, therefore, compared to the terminal protection district of traditional field limiting ring and field plate structure, the terminal size of structure of the present invention can reduce greatly, and it is wide to have larger resistance to pressure-volume.
Terminal of the present invention is withstand voltage, and operator guards is highly suitable for this kind of Charged Couple that utilizes realizes withstand voltage power device, this kind of device owing to employing the drift region material of more low-resistivity under identical requirement of withstand voltage, therefore, the conducting resistance of device reduces greatly, and terminal pressure-resistance structure of the present invention and active area structure make use of identical withstand voltage mechanism, reduce the impact on voltage endurance capability and reliability of drift region material and Terminal Design size, and, simultaneously terminal pressure-resistance structure and active area make formation, do not increase additional technique, so, the cost performance of product is higher, be suitable for batch production.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing power MOS (Metal Oxide Semiconductor) device.
Fig. 2 is the vertical view of power MOS (Metal Oxide Semiconductor) device of the present invention.
Fig. 3 is the C-C cutaway view of Fig. 2.
Fig. 4 ~ Figure 15 is the cutaway view of the concrete implementing process step of the present invention, wherein
Fig. 4 is the cutaway view of semiconductor substrate of the present invention.
Fig. 5 is the cutaway view after the present invention obtains hard mask window.
Fig. 6 is the cutaway view after the present invention obtains groove in N-type drift region.
Fig. 7 is the cutaway view after the present invention obtains insulating oxide.
Fig. 8 is that the present invention obtains cellular conductive polycrystalline silicon, withstand voltage conductive polycrystalline silicon and the cutaway view after connecting conductive polycrystalline silicon.
Fig. 9 is the cutaway view after the present invention obtains grid hole.
Figure 10 is the cutaway view after the present invention obtains Gate Electrode Conductive polysilicon.
Figure 11 is the cutaway view after the present invention obtains P type trap zone.
Figure 12 is the cutaway view after the present invention obtains N+ injection region.
Figure 13 is the cutaway view after the present invention obtains contact hole.
Figure 14 is the cutaway view after the present invention obtains active area metal and withstand voltage zone metal.
Figure 15 is the cutaway view after the present invention obtains metal layer on back.
Figure 16 is the test result schematic diagram of terminal protection district of the present invention when not having a pressure ring.
Figure 17 is the test result schematic diagram of terminal protection district of the present invention when arranging a pressure ring.
Figure 18 is the test result schematic diagram of terminal protection district of the present invention when arranging two pressure rings.
Description of reference numerals: 1-active area, 2-terminal protection district, 3-is withstand voltage protection zone, 4-active area metal, 5-withstand voltage zone metal, 6-connects cellular ring, the active cellular of 7-, 8-pressure ring, 9-connects pressure ring, 10-N type drift region, 11-N type substrate, 12-metal layer on back, 13-connects cellular groove, 14-connects withstand voltage trenched, 15-cellular insulating oxide, 16-cellular conductive polycrystalline silicon, 17-insulated gate oxide layer, 18-Gate Electrode Conductive polysilicon, 19-N+ injection region, 20-P type well region, 21-is withstand voltage conductive polycrystalline silicon, 22-is withstand voltage insulating oxide, 23-connects conductive polycrystalline silicon, 24-insulating medium layer, 25-terminal is withstand voltage trenched, 26-first interarea, 27-second interarea, 28-hard mask layer, the hard mask window of 29-, 30-insulating oxide, 31-grid hole, 32-withstand voltage zone contact hole, 33-active region contact hole, the active N+ injection region of 34-, 35-active conduction polysilicon, 36-dielectric layer, 37-source metal, 38-P well layer, 39-field limiting ring, 40-active groove and the active insulated gate oxide layer of 41-.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figures 2 and 3: in order to improve voltage endurance capability and withstand voltage reliability is high, reduce the proportion that terminal protection district takies chip entire area, for N-type power MOS (Metal Oxide Semiconductor) device, the present invention is in the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise the active area 1 and terminal protection district 2 that are positioned at semiconductor substrate, described active area 1 is positioned at the center of semiconductor substrate, terminal protection district 2 is positioned at the outer ring of active area 1 and around the described active area 1 of encirclement, comprises the withstand voltage protection zone 3 of adjacent active area 1 in terminal protection district 2; On the cross section of described power MOS (Metal Oxide Semiconductor) device, described semiconductor substrate comprises the N-type drift region 10 being positioned at top and the N-type substrate 11 being positioned at below, described N-type substrate 11 adjoins N-type drift region 10, the upper surface of N-type drift region 10 forms the first interarea 26 of semiconductor substrate, and the lower surface of N-type substrate 11 forms the second interarea 27 of semiconductor substrate;
In the top plan view of described power MOS (Metal Oxide Semiconductor) device, active area 1 comprises the connection cellular ring 6 being positioned at described active area outmost turns, at least one pressure ring 8 is comprised in withstand voltage protection zone 2, in withstand voltage protection zone 3, the contiguous pressure ring 8 connecting cellular ring 6 is formed and connects pressure ring 9, described connection pressure ring 9 be connected cellular ring 6 and parallel;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connect pressure ring 9 and adopt groove structure, described connection withstand voltage trenched 14 is extended vertically downward by the first interarea 26, the extension degree of depth connecting withstand voltage trenched 14 is less than the thickness of N-type drift region 10, the inwall and the diapire that connect withstand voltage trenched 14 are coated with withstand voltage insulating oxide 22, in the connection withstand voltage trenched 14 being coated with withstand voltage insulating oxide 22, be filled with withstand voltage conductive polycrystalline silicon 21; Above the notch of connection withstand voltage trenched 14, be provided with insulating medium layer 24, and described insulating medium layer 24 also covers on the withstand voltage insulating oxide 22 on terminal protection district 2 first interarea, and described insulating medium layer 24 arranges withstand voltage zone metal 5;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connect cellular ring 6 and adopt groove structure, described connection cellular groove 13 is extended vertically downward by the first interarea 26, the extension degree of depth connecting withstand voltage trenched 13 is less than the thickness of N-type drift region 10, connect on the sidewall of cellular groove 13 away from withstand voltage trenched 14 1 upper lateral parts of connection and be coated with insulated gate oxide layer 17, and the diapire of connection cellular groove 13 and remaining sidewall are coated with cellular insulating oxide 15; Connect in cellular groove 13 and be filled with cellular conductive polycrystalline silicon 16 and the Gate Electrode Conductive polysilicon 18 corresponding with insulated gate oxide layer 17, Gate Electrode Conductive polysilicon 18 is contacted with the sidewall being connected cellular groove 13 by insulated gate oxide layer 17, and Gate Electrode Conductive polysilicon 18 by insulated gate oxide layer 17 respectively with cellular conductive polycrystalline silicon 16 and cellular insulating oxide 15 isolated;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, P type trap zone 20 is provided with connecting cellular groove 13 away from above the outer wall side connecting withstand voltage trenched 14 sides, N+ injection region 19 is provided with in P type trap zone 20, described N+ injection region 19 and P type trap zone 20 all contact with insulated gate oxide layer 17, and the bottom of Gate Electrode Conductive polysilicon 18 is positioned at the below of P type trap zone 20, N+ injection region 19 and P type trap zone 20 all with active area metal 4 ohmic contact on active area first interarea 26, active area metal 4 by insulating medium layer 24 respectively with Gate Electrode Conductive polysilicon 18 and cellular conductive polycrystalline silicon 16 isolated, active area metal 4 is electrically connected with withstand voltage zone metal 5, and the cellular conductive polycrystalline silicon 16 connected in cellular groove 13 keeps equipotential with the withstand voltage conductive polycrystalline silicon 21 be connected in withstand voltage trenched 14.
Particularly; active area 1 is positioned at center; terminal protection district 2 is positioned at the outer ring of active area 1; withstand voltage protection zone 3 in terminal protection district 2 adjoins active area 1; be coated with the region of withstand voltage zone metal 5 in terminal protection district 2 for the formation of withstand voltage protection zone 3, withstand voltage protection zone 3 forms terminal protection district 2 jointly with the region of outer ring, described withstand voltage protection zone 3.
In the embodiment of the present invention, outmost turns in active area 1 is formed and connects cellular ring 6, and namely active area 1 is formed jointly by the region connecting cellular ring 6 and be positioned at described connection cellular ring 6 inner ring.In addition; at least one pressure ring 8 is set in withstand voltage protection zone 3; in withstand voltage protection zone 3, the contiguous pressure ring 8 connecting cellular ring 4 is formed and connects pressure ring 9; all pressure rings 8 in withstand voltage protection zone 3 all with connection cellular ring 6 in parallel distribution; namely connect pressure ring 9 and is connected cellular ring 6 and is parallel to each other, and connect pressure ring 5 and be close to connection cellular ring 6.
In active area 1, connect in cellular groove 13 and there is cellular insulating oxide 15 and insulated gate oxide layer 17, wherein, the thickness of cellular insulating oxide 15 is greater than the thickness of insulated gate oxide layer 17, insulated gate oxide layer 17 covers and connects cellular groove 13 away from the sidewall connecting withstand voltage trenched 14 1 upper lateral parts, cellular insulating oxide 15 cover connect cellular groove 13 diapire and remaining sidewall on.Cellular conductive polycrystalline silicon 16 and Gate Electrode Conductive polysilicon 18 is also filled in connection cellular groove 13, described Gate Electrode Conductive polysilicon 18 is corresponding with insulated gate oxide layer 17, and the region in connection cellular groove 13 except Gate Electrode Conductive crystal silicon 18 all has cellular conductive polycrystalline silicon 16 to fill.In connection cellular groove 13, Gate Electrode Conductive polysilicon 18 is insulated by insulated gate oxide layer 17 and cellular conductive polycrystalline silicon 16 and isolates, because Gate Electrode Conductive polysilicon 18 is corresponding with insulated gate oxide layer 17, therefore Gate Electrode Conductive polysilicon 18 is connected with the sidewall being connected cellular groove 13 by insulated gate oxide layer 17, and Gate Electrode Conductive polysilicon 18 is also isolated by insulated gate oxide layer 17 and cellular insulating oxide 15.P type trap zone 20 and N+ injection region 19 are positioned at the top connecting cellular groove 13 lateral wall, P type trap zone 20 and N+ injection region 19 are connected with Gate Electrode Conductive polysilicon 18 by insulated gate oxide layer 17, and P type trap zone 20 and N+ injection region 19 and active area metal 4 ohmic contact, thus active area metal 4, insulated gate oxide layer 17, Gate Electrode Conductive polysilicon 18, N+ injection region 19 and P type trap zone 20 form MOS structure.N+ injection region 19 is covered by insulating medium layer 24 near the surface connecting cellular groove 13, and insulating medium layer 24 also covers on Gate Electrode Conductive polysilicon 18 simultaneously, thus Gate Electrode Conductive polysilicon 18 and active area metal 4 can be insulated and isolate.
In withstand voltage protection zone 3; the withstand voltage conductive polycrystalline silicon 21 connected in withstand voltage trenched 14 is connected with the sidewall and diapire being connected withstand voltage trenched 14 by withstand voltage insulating oxide 22; withstand voltage insulating oxide 22 also covers on the first interarea 26 of terminal protection district 2 correspondence, and withstand voltage insulating oxide 22 contacts with cellular insulating oxide.Active area metal 4 realizes the electrical connection between active area metal 4 and withstand voltage zone metal 5 after contacting with withstand voltage zone metal 5, as in Fig. 2, active area metal 4 is electrically connected with after the contact of the withstand voltage zone metal 5 of side.
In active area 1, cellular conductive polycrystalline silicon 16, between cellular insulating medium layer 15 and N-type drift region 10, form capacitance structure, Charged Couple principle can be utilized to form depletion layer to support voltage.Meanwhile, in withstand voltage protection zone 3, withstand voltage conductive polycrystalline silicon 21, withstand voltage insulating oxide 22 are same with N-type drift region 10 forms capacitance structure.Connect cellular ring 6 and be connected pressure ring 9 and utilize Charged Couple principle to form depletion layer when withstand voltage, because the cellular conductive polycrystalline silicon 16 connected in cellular groove 13 keeps equipotential with the withstand voltage conductive polycrystalline silicon 21 be connected in withstand voltage trenched 14, therefore, the electric charge be coupled out can reach charge balance completely with the electric charge in N-type drift region 10, thus be formed at withstand voltage effect consistent in active area 1, and before connection cellular groove 13 links together with the depletion layer be connected between withstand voltage trenched 14, voltage now can be born completely by withstand voltage insulating oxide 22 thicker on the first interarea 26 of withstand voltage protection zone 3.In the specific implementation, according to withstand voltage requirement, the pressure ring 8 of varying number can be set in withstand voltage protection zone 3.
Further, on the cross section of described power MOS (Metal Oxide Semiconductor) device, be coated with above the notch of connection withstand voltage trenched 14 and connect conductive polycrystalline silicon 23, described connection conductive polycrystalline silicon 23 is electrically connected after contacting with the withstand voltage conductive polycrystalline silicon 21 be connected in withstand voltage trenched 14 and the cellular conductive polycrystalline silicon 16 connected in cellular groove 13, insulating medium layer 24 covers and connects on conductive polycrystalline silicon 23, withstand voltage zone metal 5 be connected conductive polycrystalline silicon electric 23 and connect.
In the embodiment of the present invention, withstand voltage zone metal 5 be connected conductive polycrystalline silicon 23 and be electrically connected, connect conductive polycrystalline silicon 23 to contact with cellular conductive polycrystalline silicon 16 and withstand voltage conductive polycrystalline silicon 21 simultaneously, therefore, the equipotential between cellular conductive polycrystalline silicon 16 and withstand voltage conductive polycrystalline silicon 21 can be reached by connection conductive polycrystalline silicon 23.In the specific implementation, can also other types of attachment be passed through, make cellular conductive polycrystalline silicon 16 and withstand voltage conductive polycrystalline silicon 21 keep equipotential, specifically will not enumerate.
Described cellular insulating oxide 15, withstand voltage insulating oxide 22 are same fabrication layer, and the thickness of cellular insulating oxide 15 is 2000 à ~ 10000 à.In the embodiment of the present invention, the thickness of cellular insulating oxide 17, withstand voltage insulating oxide 15 is used for ensureing can bear voltage before depletion layer connects.
In the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise being positioned at connect the cellular some regular array of ring 6 inner ring and the active cellular 7 of the distribution that is parallel to each other in active area 1, the active cellular 7 in active area 1 is with to be connected cellular ring 6 connected;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, active cellular 7 adopts groove structure, described active cellular groove is from the first interarea 26 downward vertically to downward-extension, the degree of depth that active cellular groove extends is less than the thickness of N-type drift layer 10, insulated gate oxide layer 17 is coated with at the sidewall of active cellular groove internal upper part, the diapire of active cellular groove and remaining sidewall are coated with cellular insulating oxide 15, and in active cellular groove, be also filled with cellular conductive polycrystalline silicon 16 and the Gate Electrode Conductive polysilicon 18 corresponding with described insulated gate oxide layer 17, Gate Electrode Conductive polysilicon 18 is connected with the sidewall of active cellular groove by gate insulator oxide layer 17, cellular conductive polycrystalline silicon 16 is positioned at the center of active cellular groove, Gate Electrode Conductive polysilicon 18 is insulated by insulated gate oxide layer 17 and cellular conductive polycrystalline silicon 16 and isolates, and by insulated gate oxide layer 17 interval between Gate Electrode Conductive polysilicon 18 and cellular insulating oxide 15, P type trap zone 20 is provided with above the outer wall side of active cellular groove both sides, N+ injection region 19 is provided with in described P type trap zone 20, N+ injection region 19 and P type trap zone 20 contact with corresponding insulated gate oxide layer 17 respectively and connect, the bottom of Gate Electrode Conductive polysilicon 18 is positioned at the below of P type trap zone 20, N+ injection region 19 and P type trap zone 20 and active area metal 4 ohmic contact.
In the embodiment of the present invention, the concrete structure of active cellular 7 is also not shown, and active cellular 7 can be bar shaped or other shapes, in Fig. 2, shows the schematic diagram of active cellular 7 distribution in bar shaped.The two ends of active cellular 7 be connected cellular ring 6 and be connected.When active cellular 7 adopts groove structure, structure and the similar being connected cellular ring 6 of active cellular 7.On the cross section of power MOS (Metal Oxide Semiconductor) device, top in active cellular groove arranges symmetrical Gate Electrode Conductive polysilicon 18, cellular conductive polycrystalline silicon 16 in active cellular groove is positioned between two Gate Electrode Conductive polysilicons 18, Gate Electrode Conductive polysilicon 18 is insulated by insulated gate oxide layer 17 and cellular conductive polycrystalline silicon 16 and isolates, P type trap zone 20 above active cellular groove lateral wall and N+ injection region 19 and active area metal 4 ohmic contact, thus active area metal 4, insulated gate oxide layer 17, Gate Electrode Conductive polysilicon 18, N+ injection region 19 and P type trap zone 20 also form MOS structure.Gate Electrode Conductive polysilicon 18 in active cellular groove, the Gate Electrode Conductive polysilicon 18 connected in cellular groove 13 are electrically connected, the MOS structure formed in the connection cellular ring 6 in active area 1 and active cellular 7 to be joined together.Cellular conductive polycrystalline silicon 16 in active cellular groove contacts with the cellular conductive polycrystalline silicon 16 be connected in cellular groove 13, thus can be in parallel by the capacitance structure formed in active area 1.
In addition, in the specific implementation, also can only comprise some regular array in active area 1 while the active cellular 7 of the distribution that is parallel to each other, namely in active area 1, not comprise the connection cellular ring 6 being positioned at outmost turns.In active area 1 only active cellular 7 time, madial wall corresponding between neighboring active cellular groove is coated with insulated gate oxide layer 17, the diapire of active cellular groove and remaining sidewall are coated with cellular insulating oxide 15, and in active cellular groove, be also filled with cellular conductive polycrystalline silicon 16 and the Gate Electrode Conductive polysilicon 18 corresponding with described insulated gate oxide layer 17, Gate Electrode Conductive polysilicon 18 is connected with the sidewall of active cellular groove by gate insulator oxide layer 17, and Gate Electrode Conductive polysilicon 18 by insulated gate oxide layer divide 17 not and cellular conductive polycrystalline silicon 16 and cellular insulating oxide 15 isolated, P type trap zone 20 is provided with above outer wall side corresponding between neighboring active cellular groove, N+ injection region 19 is provided with in described P type trap zone 20, N+ injection region 19 and P type trap zone 20 contact with corresponding insulated gate oxide layer 17 respectively and connect, the bottom of Gate Electrode Conductive polysilicon 18 is positioned at the below of P type trap zone 20, N+ injection region 19 and P type trap zone 20 and active area metal 4 ohmic contact, active area metal 4 is isolated by insulating medium layer 4 and Gate Electrode Conductive polysilicon 18, cellular conductive polycrystalline silicon 16 in active cellular groove keeps equipotential with the withstand voltage conductive polycrystalline silicon 21 be connected in withstand voltage trenched 14.
In the embodiment of the present invention, owing to connecting pressure ring 9 around being surrounded by source region 1, when only there being the active cellular 7 in parallel distribution in active area 1, the active cellular 7 of parallel distribution can parallel with the region being connected pressure ring 9 side.For outermost active cellular 7, only have in its active cellular groove on the sidewall away from withstand voltage trenched 13 sides of connection and can be coated with insulated gate oxide layer 17, simultaneously, the side outer wall covering insulated gate oxide layer 17 just has P type trap zone 20 and N+ injection region 19, and remaining structure all can with reference to the structure connecting cellular groove 13.In order to make the cellular conductive polycrystalline silicon 16 in active cellular 7 keep equipotential with the withstand voltage conductive polycrystalline silicon 21 be connected in withstand voltage trenched 14, the cellular conductive polycrystalline silicon 16 in active cellular 7 also can connect with the withstand voltage conductive polycrystalline silicon 23 be connected in withstand voltage trenched 14 by connecting conductive polycrystalline silicon 23.
Cellular insulating oxide 15 in active cellular groove is same fabrication layer with the cellular insulating oxide 15 be connected in cellular groove 13, and the cellular conductive polycrystalline silicon 16 in active cellular groove and the cellular conductive polycrystalline silicon 16 be connected in cellular groove 13 are same fabrication layer.
When having multiple pressure ring 8 in described withstand voltage protection zone 3, the pressure ring 8 in withstand voltage protection zone 3 is parallel to each other, and it is equal with the distance be parallel to each other in active area 1 between active cellular 7 with the distance connected between cellular ring 6 to connect pressure ring 9.
In the embodiment of the present invention; different according to withstand voltage requirement; the pressure ring 8 of varying number can be set in withstand voltage protection zone 3; be parallel to each other between multiple pressure ring 8; the contiguous pressure ring 8 connecting cellular ring 6 is formed and connects pressure ring 9; remaining pressure ring 8 also can adopt groove structure; comprise terminal withstand voltage trenched 25; the inwall of described terminal withstand voltage trenched 25 and diapire are coated with withstand voltage insulating oxide 22, in the terminal withstand voltage trenched 25 being coated with withstand voltage insulating oxide 22, be filled with withstand voltage conductive polycrystalline silicon 21.Connect the notch that conductive polycrystalline silicon 23 also covers terminal withstand voltage trenched 25, and connect conductive polycrystalline silicon 23 and contact rear electrical connection with the withstand voltage conductive polycrystalline silicon 21 in terminal withstand voltage trenched 25, thus by connect conductive polycrystalline silicon 23 by the withstand voltage conductive polycrystalline silicon 21 in withstand voltage trenched for terminal 25 also while with cellular conductive polycrystalline silicon 16 equipotential link.In Fig. 2 and Fig. 3, show the structure that there are two pressure rings 8 in withstand voltage protection zone 3.Withstand voltage insulating oxide 22 in terminal withstand voltage trenched 25 is same fabrication layer with the withstand voltage insulating oxide 22 be connected in pressure ring 9, and the withstand voltage conductive polycrystalline silicon 21 in terminal withstand voltage trenched 25 and the withstand voltage conductive polycrystalline silicon 21 be connected in pressure ring 9 are same fabrication layer.
As described in Fig. 4 ~ Figure 15, above-mentionedly utilize Charged Couple to realize withstand voltage power MOS (Metal Oxide Semiconductor) device can be prepared by following technique, the preparation method of described power MOS (Metal Oxide Semiconductor) device specifically comprises the steps:
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces comprise the first interarea 26 and the second interarea 27, comprise N-type drift region 10 and are positioned at the N-type substrate 11 below described N-type drift region 10 between the first interarea 26 and the second interarea 27;
As shown in Figure 4, the material of semiconductor substrate comprises silicon, and the upper surface of N-type drift region 10 forms the first interarea 26, and the lower surface of N-type substrate 11 forms the second interarea 27.
B, on the first interarea 26 of above-mentioned semiconductor substrate deposit hard mask layer 28, optionally shelter and etch described hard mask layer 28, to obtain the hard mask window 29 of required through hard mask layer 28;
As shown in Figure 5, described hard mask layer 27 is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.The process of hard mask window 28 is obtained known by the art personnel to hard mask layer 27 etching, repeats herein.
C, the first interarea 26 of above-mentioned hard mask window 29 pairs of semiconductor substrates is utilized to carry out anisotropic dry etch, to form groove in N-type drift region 10, described groove is less than the thickness of N-type drift region 10 in the degree of depth of N-type drift region 10, and described groove comprises the connection withstand voltage trenched 14 being positioned at withstand voltage protection zone 3 and the connection cellular groove 13 being positioned at active area 1;
As shown in Figure 6, when utilizing hard mask window 29 to carry out anisotropic dry etch to the first interarea 26, can groove be formed having the lower of hard mask window 26, thus obtain connecting withstand voltage trenched 14 and be connected cellular groove 13.Also there is in active area 1 active cellular groove; when withstand voltage protection zone 3 has multiple pressure ring 8; also comprise terminal withstand voltage trenched 25, described active cellular groove, connect cellular groove 13, connect withstand voltage trenched 14 and terminal withstand voltage trenched 25 prepare for same processing step.
D, the hard mask layer 28 removed on above-mentioned first interarea 26, and insulating oxide 30 is grown in first interarea 26 and above-mentioned groove of semiconductor substrate;
As shown in Figure 7, hard mask layer 28 is removed by the technique of routine, then the technique such as thermal oxidation growth insulating oxide 30, the thickness of described insulating oxide 30 is 2000 à ~ 10000 à, insulating oxide 30 grows on the first interarea 26 and on the sidewall of corresponding groove and diapire simultaneously, the cellular insulating oxide 15 needed for being formed by insulating oxide 30 and withstand voltage insulating oxide 22.On the sidewall that insulating oxide 30 can cover active cellular groove equally and diapire.
E, on above-mentioned first interarea 26 deposit conductive polycrystalline silicon, described conductive polycrystalline silicon covers on the insulating oxide 30 on the first interarea, and is filled in groove;
F, optionally shelter and etch above-mentioned conductive polycrystalline silicon, obtain being positioned at connect withstand voltage trenched 14 withstand voltage conductive polycrystalline silicon 21, be positioned at the cellular conductive polycrystalline silicon 16 that connects cellular groove 13 and cover on insulating oxide 30 and to contact with withstand voltage conductive polycrystalline silicon 21, cellular conductive polycrystalline silicon 16 the connection conductive polycrystalline silicon 23 be electrically connected;
As shown in Figure 8, after etching conductive polysilicon, withstand voltage conductive polycrystalline silicon 21 and cellular conductive polycrystalline silicon 16 can be obtained, simultaneously, connecting conductive polycrystalline silicon 23 covers on the insulating oxide 30 on the first interarea 26, connect conductive polycrystalline silicon 23 and cover connection cellular groove 13 notch, to contact with the cellular conductive polycrystalline silicon 16 connected in cellular groove 13, connecting conductive polycrystalline silicon 23 also covers on the first interarea of withstand voltage protection zone 3, thus rear electrical connection can be contacted with the withstand voltage conductive polycrystalline silicon 21 in the withstand voltage conductive polycrystalline silicon 21 in withstand voltage connection groove 14 and terminal withstand voltage trenched 25, the isopotential electrical reached between cellular conductive polycrystalline silicon 16 with withstand voltage conductive polycrystalline silicon 21 is connected.
G, optionally etch insulating oxide 30 on the first interarea 26, to remove the insulating oxide 30 on the interarea 26 of active area 1 first, remove the cellular conductive polycrystalline silicon 16 connected away from the insulating oxide 30 connected on withstand voltage trenched 14 side sidewalls and correspondence in cellular groove 13 simultaneously, with obtain being positioned at connect cellular groove 13 cellular insulating oxide 15, cover on terminal protection district 2 first interarea 26 and connect the withstand voltage insulating oxide 22 of withstand voltage trenched 14 and be formed at the grid hole 31 connecting cellular groove 13;
As shown in Figure 9, while removing the insulating oxide 30 on the interarea 26 of active area 1 first, also can etch and cover the connection conductive polycrystalline silicon 23 on connection cellular groove 13 notch, the cellular insulating oxide 15 in connection cellular groove 13 and cellular conductive polycrystalline silicon 16, to form grid hole 31 in connection cellular groove 13, grid hole 31 is less than the degree of depth of connection cellular groove 13 connecting the degree of depth in cellular groove 13.In addition, in active cellular groove, can form grid hole 31, from the cross section of power MOS (Metal Oxide Semiconductor) device, the grid hole 31 in active cellular groove is symmetric simultaneously.
H, in above-mentioned grid hole 31, grow insulated gate oxide layer 17, described insulated gate oxide layer 17 covers cellular insulating oxide 15 corresponding at the bottom of the sidewall of the connection cellular groove 13 corresponding with grid hole 31, the surface of the cellular conductive polycrystalline silicon 16 corresponding with grid hole 31 and grid hole 31 hole;
The oxide layer that growth is thin in grid hole 31, thus obtain insulated gate oxide layer 17, the thickness of insulated gate oxide layer 17 is less than the thickness of insulating oxide 30, and the thickness of insulated gate oxide layer 17 is consistent with the gate oxide thickness in existing power MOS (Metal Oxide Semiconductor) device, repeats no more herein.
I, in above-mentioned grid hole 31 deposit Gate Electrode Conductive polysilicon 18, described Gate Electrode Conductive polysilicon 18 be filled in growth have in the grid hole 31 of insulated gate oxide layer 17;
As shown in Figure 10, deposit Gate Electrode Conductive polysilicon 18 in grid hole 31, Gate Electrode Conductive polysilicon 18 is insulated by insulated gate oxide layer 17 and cellular conductive polycrystalline silicon 16 and isolates, and Gate Electrode Conductive polysilicon 18 is also isolated by insulated gate oxide layer 17 and cellular insulating oxide 15.
J, on above-mentioned first interarea 26, autoregistration implanting p-type foreign ion, and the P type trap zone 20 being positioned at active area 1 is formed by high temperature knot, described P type trap zone 20 contacts with insulated gate oxide layer 17, and P type trap zone 20 is positioned at the top of Gate Electrode Conductive polysilicon 18 bottom;
As shown in figure 11, implanting p-type foreign ion and high temperature knot form the technique that P type trap zone 20 can adopt the art conventional, are specially known by the art personnel, repeat no more herein.The P type trap zone 20 formed is positioned at and connects cellular groove 13 and the top at the bottom of active cellular groove corresponding groove, and P type trap zone 20 also will be positioned at the top of Gate Electrode Conductive polysilicon 18 bottom, the bottom of Gate Electrode Conductive polysilicon 18 refers to one end of the contiguous cellular insulating oxide 15 of Gate Electrode Conductive polysilicon 18.
K, on above-mentioned first interarea 26, carry out N-type impurity ion implantation, and formed the N+ injection region 19 being positioned at P type trap zone 20 by high temperature knot, described N+ injection region 19 contacts with insulated gate oxide layer 17;
As shown in figure 12, injection N-type impurity ion and high temperature knot form the technique that N+ injection region 19 also can adopt the art conventional, are specially known by the art personnel, repeat no more herein.N+ injection region 19 is positioned at the top of P type trap zone 20, and N+ injection region 19 degree of depth is in vertical direction less than the degree of depth of P type trap zone 20.
L, on above-mentioned first interarea 26 deposit insulating medium layer 24, and optionally etch described insulating medium layer 24, to form the contact hole of required through insulating medium layer 24, described contact hole comprises withstand voltage zone contact hole 32 and active region contact hole 33;
As shown in figure 13; adopt the conventional technique deposit of the art to obtain insulating medium layer 24, insulating medium layer 24 cover connect withstand voltage insulating oxide 22 on conductive polycrystalline silicon 23, terminal protection district 2 first interarea 26 and active area 1 the first interarea 26 on.Withstand voltage zone contact hole 32 is positioned at and connects directly over conductive polycrystalline silicon 23, the subregion of N+ injection region 19 and P type trap zone 20 can be made exposed, so that active area metal 4 contacts by active region contact hole 33.
M, on above-mentioned first interarea 26 deposited metal, and optionally etching sheet metal, to obtain being positioned at the active area metal 4 of active area 1 and being positioned at the withstand voltage zone metal 5 of withstand voltage protection zone 3, described withstand voltage zone metal 5 by withstand voltage zone contact hole 32 be connected conductive polycrystalline silicon 23 and be electrically connected, active area metal 4 is by active region contact hole 33 and N+ injection region 19 and P type trap zone 20 ohmic contact, and active area metal 4 is electrically connected with withstand voltage zone metal 5;
As shown in figure 14, metal level is obtained after adopting conventional technique and deposition of materials, active area metal 4 and withstand voltage zone metal 5 pass through part contact, to realize the electrical connection between active area metal 4 and withstand voltage zone metal 5, withstand voltage zone metal 5 by withstand voltage zone contact hole 32 be connected conductive polycrystalline silicon 23 and be electrically connected, now, withstand voltage zone metal 5 is electrically connected with cellular conductive polycrystalline silicon 16 and withstand voltage conductive polycrystalline silicon 21.
N, on the second interarea 27 of semiconductor substrate deposit metal layer on back 12, described metal layer on back 12 and N-type substrate 11 ohmic contact.
As shown in figure 15, metal layer on back 12 and N-type substrate 11 ohmic contact, can form the drain electrode end of power MOS (Metal Oxide Semiconductor) device by metal layer on back 12.
The working mechanism of terminal pressure-resistance structure of the present invention is: connect pressure ring 9 and be connected cellular ring 6, active cellular 7 all adopts groove structure; cellular conductive polycrystalline silicon 16 in active area 1, cellular insulating oxide 15 and N-type drift region 10 are formed with the capacitance structure in source region 1, and the withstand voltage conductive polycrystalline silicon 21 in withstand voltage protection zone 3, withstand voltage insulating oxide 22 and N-type drift region 10 form the capacitance structure of withstand voltage protection zone 3.The cellular conductive polycrystalline silicon 16 connected in cellular ring 6 keeps equipotential with the withstand voltage conductive polycrystalline silicon 21 be connected in pressure ring 9, and when the withstand voltage work of power MOS (Metal Oxide Semiconductor) device, the current potential connecting cellular conductive polycrystalline silicon 16 in cellular ring 6 is zero potential.
For N-type MOS device, when device withstand voltage works, metal layer on back 12 on second interarea 27 applies a positive voltage, described positive voltage makes to be coupled out positive charge in N-type drift region 10, electronics in described positive charge and N-type drift region 10 is when reaching charge balance, its depletion layer formed obtains largest extension, connect withstand voltage trenched 14 be connected cellular groove 13 respective near depletion layer contact before, voltage born by the withstand voltage insulating oxide 22 on the first interarea 26 in withstand voltage protection zone 3, after above-mentioned depletion layer is connected, voltage just born by depletion layer, electric field in device active region 1 can laterally be expanded to terminal protection district 2 transition, avoid occurring puncturing, and the lifting of withstand voltage protection zone 3 voltage endurance capability just can be realized by the quantity increasing pressure ring 8 in terminal protection district 2, and the first interarea 26 in withstand voltage protection zone 3 is coated with withstand voltage insulating oxide 22, the thickness of withstand voltage insulating oxide 22 is thicker, its voltage endurance capability is generally far above the requirement of withstand voltage of device, therefore, terminal protection district 2 can realize the voltage endurance capability higher than active area 1.
For the power MOSFET device of a 130V, the drain-source breakdown voltage BVdss of test component, test condition is that drain-source applies one from the initial scanning voltage Vds of zero volt, read drain-source leakage current Idss, when Idss is increased to 250uA, Vds is now the puncture voltage BVdss of device simultaneously, simulation result as shown in Figure 16, Figure 17 and Figure 18, in emulation schematic diagram, abscissa is scanning voltage Vds, and ordinate is drain-source leakage current Idss.When only changing the quantity of its pressure ring 8, there is no pressure ring 8, a pressure ring 8 is set and is respectively 128V with the puncture voltage arranging two pressure rings 8, 145V, 148V, and when arranging a pressure ring 8, the size in its terminal protection district 2 only has about 10 μm, according to the terminal pressure-resistance structure of traditional field limiting ring 39 with field plate, its size has more than 30 μm at least, and withstand voltage power device is realized for this kind of Charged Couple that utilizes, the pressure-resistance structure of traditional field limiting ring 39 because of its withstand voltage mechanism different from the withstand voltage mechanism of active area 1, these two parts emphasize particularly on different fields for the concentration requirement of N-type drift region 10, therefore, structure of the present invention is more suitable for this kind of Charged Couple that utilizes and realizes withstand voltage power device, there is higher superiority of effectiveness, be suitable for batch production.
Claims (10)
1. one kind utilizes Charged Couple to realize withstand voltage power MOS (Metal Oxide Semiconductor) device, in the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise the active area and terminal protection district that are positioned at semiconductor substrate, described active area is positioned at the center of semiconductor substrate, terminal protection district is positioned at the outer ring of active area and around the described active area of encirclement, comprises the withstand voltage protection zone of adjacent active area in terminal protection district; On the cross section of described power MOS (Metal Oxide Semiconductor) device, described semiconductor substrate comprises the first conduction type drift region being positioned at top and the first conductivity type substrate being positioned at below, described first conductivity type substrate adjoins the first conduction type drift region, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate forms the second interarea of semiconductor substrate; It is characterized in that:
In the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise at least one pressure ring in withstand voltage protection zone, in withstand voltage protection zone, the pressure ring of adjacent active regions is formed and connects pressure ring;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, connect pressure ring and adopt groove structure, described connection is withstand voltage trenched to be extended vertically downward by the first interarea, connect the thickness that the withstand voltage trenched extension degree of depth is less than the first conduction type drift region, connect withstand voltage trenched inwall and diapire is coated with withstand voltage insulating oxide, in the connection being coated with withstand voltage insulating oxide is withstand voltage trenched, is filled with withstand voltage conductive polycrystalline silicon; Above the notch that connection is withstand voltage trenched, be provided with insulating medium layer, and described insulating medium layer also covers on the withstand voltage insulating oxide on terminal protection district first interarea, and described insulating medium layer arranges withstand voltage zone metal;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, some regular array are comprised and the active cellular of the distribution that is parallel to each other in active area, described active cellular adopts groove structure, described active cellular groove is from the first interarea downward vertically to downward-extension, and the degree of depth that active cellular groove extends is less than the thickness of the first conduction type drift layer; Madial wall corresponding between neighboring active cellular groove is coated with insulated gate oxide layer, the diapire of active cellular groove and remaining sidewall are coated with cellular insulating oxide, and in active cellular groove, be also filled with cellular conductive polycrystalline silicon and the Gate Electrode Conductive polysilicon corresponding with described insulated gate oxide layer, Gate Electrode Conductive polysilicon is connected with the sidewall of active cellular groove by gate insulator oxide layer, and Gate Electrode Conductive polysilicon pass through insulated gate oxide layer respectively with cellular conductive polycrystalline silicon and cellular insulating oxide isolated; The second conduction type well region is provided with above outer wall side corresponding between neighboring active cellular groove, the first conductivity type implanted region is provided with in described second conduction type well region, first conductivity type implanted region and the second conductive type of trap district contact with corresponding insulated gate oxide layer respectively and connect, the bottom of Gate Electrode Conductive polysilicon is positioned at the below of the second conduction type well region, first conductivity type implanted region and the second conduction type well region and active area metal ohmic contact, active area metal by insulating medium layer and Gate Electrode Conductive polysilicon isolated;
Active area metal is connected with withstand voltage zone metal electric, and cellular conductive polycrystalline silicon in active cellular groove be connected withstand voltage trenched in withstand voltage conductive polycrystalline silicon keep equipotential.
2. the Charged Couple that utilizes according to claim 1 realizes withstand voltage power MOS (Metal Oxide Semiconductor) device, it is characterized in that: on the cross section of described power MOS (Metal Oxide Semiconductor) device, connection conductive polycrystalline silicon is coated with above the notch that connection is withstand voltage trenched, described connection conductive polycrystalline silicon is electrically connected after contacting with the cellular conductive polycrystalline silicon be connected in withstand voltage trenched interior withstand voltage conductive polycrystalline silicon and active cellular groove, insulating medium layer covers and connects on conductive polycrystalline silicon, withstand voltage zone metal be connected conductive polycrystalline silicon and be electrically connected.
3. the Charged Couple that utilizes according to claim 1 realizes withstand voltage power MOS (Metal Oxide Semiconductor) device, it is characterized in that: in the top plan view of described power MOS (Metal Oxide Semiconductor) device, active area comprises the connection cellular ring being positioned at described active area outmost turns, regular array in active area and the active cellular of the distribution that is parallel to each other are positioned at and connect cellular ring, described connection pressure ring be connected cellular ring and parallel; Active cellular in active area be connected cellular ring be connected; Spacing between the active cellular be parallel to each other in active area is equal.
4. the Charged Couple that utilizes according to claim 3 realizes withstand voltage power MOS (Metal Oxide Semiconductor) device, it is characterized in that: on the cross section of described power MOS (Metal Oxide Semiconductor) device, connect cellular ring and adopt groove structure, described connection cellular groove is extended vertically downward by the first interarea, connect the thickness that the withstand voltage trenched extension degree of depth is less than the first conduction type drift region, the madial wall of contiguous active cellular groove one upper lateral part of connection cellular groove is coated with insulated gate oxide layer, and the diapire of connection cellular groove and remaining sidewall are coated with cellular insulating oxide; Connect in cellular groove and be filled with cellular conductive polycrystalline silicon and the Gate Electrode Conductive polysilicon corresponding with insulated gate oxide layer, Gate Electrode Conductive polysilicon is contacted with the sidewall being connected cellular groove by insulated gate oxide layer;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, the second conduction type well region is provided with connecting cellular groove away from above the outer wall side connecting withstand voltage trenched side, the first conductivity type implanted region is provided with in second conduction type well region, described first conductivity type implanted region and the second conduction type well region all contact with insulated gate oxide layer, and the bottom of Gate Electrode Conductive polysilicon is positioned at the below of the second conduction type well region, first conductivity type implanted region and the second conduction type well region all with the active area metal ohmic contact on the interarea of active area first, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and cellular conductive polycrystalline silicon isolated, connect cellular conductive polycrystalline silicon in cellular groove and be connected withstand voltage trenched interior withstand voltage conductive polycrystalline silicon and keep equipotential.
5. the Charged Couple that utilizes according to claim 4 realizes withstand voltage power MOS (Metal Oxide Semiconductor) device, it is characterized in that: on the cross section of described power MOS (Metal Oxide Semiconductor) device, connection conductive polycrystalline silicon is coated with above the notch that connection is withstand voltage trenched, described connection conductive polycrystalline silicon is electrically connected after contacting with the cellular conductive polycrystalline silicon be connected in withstand voltage trenched interior withstand voltage conductive polycrystalline silicon and connection cellular groove, insulating medium layer covers and connects on conductive polycrystalline silicon, withstand voltage zone metal be connected conductive polycrystalline silicon and be electrically connected.
6. the Charged Couple that utilizes according to claim 4 realizes withstand voltage power MOS (Metal Oxide Semiconductor) device, it is characterized in that: when having multiple pressure ring in described withstand voltage protection zone, the pressure ring in withstand voltage protection zone is parallel to each other.
7. utilize Charged Couple to realize a preparation method for withstand voltage power MOS (Metal Oxide Semiconductor) device, it is characterized in that, the preparation method of described power MOS (Metal Oxide Semiconductor) device comprises the steps:
(a), the semiconductor substrate with two opposing main faces is provided, described two opposing main faces comprise the first interarea and the second interarea, comprise the first conduction type drift region and be positioned at the first conductivity type substrate below described first conduction type drift region between the first interarea and the second interarea;
(b), on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch described hard mask layer, to obtain the hard mask window of required through hard mask layer;
(c), utilize first interarea of above-mentioned hard mask window to semiconductor substrate to carry out anisotropic dry etch, to form groove in the first conduction type drift region, described groove is less than the thickness of the first conduction type drift region in the degree of depth of the first conduction type drift region, and it is withstand voltage trenched and be positioned at the active cellular groove of active area that described groove comprises the connection being positioned at withstand voltage protection zone;
(d), the hard mask layer removed on above-mentioned first interarea, and insulating oxide is grown in first interarea and above-mentioned groove of semiconductor substrate;
(e), on above-mentioned first interarea deposit conductive polycrystalline silicon, described conductive polycrystalline silicon covers on the insulating oxide on the first interarea, and is filled in groove;
(f), optionally shelter and etch above-mentioned conductive polycrystalline silicon, obtain being positioned at and connect withstand voltage trenched withstand voltage conductive polycrystalline silicon, be positioned at the cellular conductive polycrystalline silicon of active cellular groove and cover on insulating oxide and to contact with withstand voltage conductive polycrystalline silicon, cellular conductive polycrystalline silicon the connection conductive polycrystalline silicon be electrically connected;
(g), optionally etch insulating oxide on the first interarea, to remove the insulating oxide on the interarea of active area first, remove the cellular conductive polycrystalline silicon away from the insulating oxide connected on the sidewall of withstand voltage trenched side and correspondence in active cellular groove simultaneously, with obtain being positioned at active cellular groove cellular insulating oxide, cover on terminal protection district first interarea and connect withstand voltage trenched withstand voltage insulating oxide and be formed at the grid hole of active cellular groove;
(h), in above-mentioned grid hole, grow insulated gate oxide layer, described insulated gate oxide layer covers cellular insulating oxide corresponding at the bottom of the sidewall of the active cellular groove corresponding with grid hole, the surface of the cellular conductive polycrystalline silicon corresponding with grid hole and grid hole hole;
, in above-mentioned grid hole deposit Gate Electrode Conductive polysilicon, described Gate Electrode Conductive polysilicon be filled in growth have in the grid hole of insulated gate oxide layer;
(j), on above-mentioned first interarea, the second conductive type impurity ion is injected in autoregistration, and the second conduction type well region being positioned at active area is formed by high temperature knot, described second conduction type well region contacts with insulated gate oxide layer, and the second conductive type of trap district is positioned at the top of Gate Electrode Conductive polysilicon bottom;
(k), on above-mentioned first interarea, carry out the first conductive type impurity ion implantation, and formed by high temperature knot and be positioned at the first conductivity type implanted region of the second conduction type well region, described first conductivity type implanted region contacts with insulated gate oxide layer;
(l), on above-mentioned first interarea deposit insulating medium layer, and optionally etch described insulating medium layer, to form the contact hole of required through insulating medium layer, described contact hole comprises withstand voltage zone contact hole and active region contact hole;
(m), on above-mentioned first interarea deposited metal, and optionally etching sheet metal, to obtain being positioned at the active area metal of active area and being positioned at the withstand voltage zone metal of withstand voltage protection zone, described withstand voltage zone metal by withstand voltage zone contact hole be connected conductive polycrystalline silicon and be electrically connected, active area metal is by active region contact hole and the first conductivity type implanted region and the second conduction type well region ohmic contact, and active area metal is connected with withstand voltage zone metal electric;
(n), on the second interarea of semiconductor substrate deposit metal layer on back, described metal layer on back and the first conductivity type substrate ohmic contact.
8. utilize Charged Couple to realize the preparation method of withstand voltage power MOS (Metal Oxide Semiconductor) device according to claim 6, it is characterized in that: the material stating semiconductor substrate comprises silicon, the thickness of insulating oxide is 2000 à ~ 10000 à.
9. utilize Charged Couple to realize the preparation method of withstand voltage power MOS (Metal Oxide Semiconductor) device according to claim 6, it is characterized in that: in described step (c), the groove obtained also comprises connection cellular groove in the form of a ring, active cellular groove is all positioned at the connection cellular groove of ring-type, the madial wall of contiguous active cellular groove one upper lateral part of connection cellular groove is coated with insulated gate oxide layer, and the diapire of connection cellular groove and remaining sidewall are coated with cellular insulating oxide; Connect in cellular groove and be filled with cellular conductive polycrystalline silicon and the Gate Electrode Conductive polysilicon corresponding with insulated gate oxide layer, Gate Electrode Conductive polysilicon is contacted with the sidewall being connected cellular groove by insulated gate oxide layer, and Gate Electrode Conductive polysilicon by insulated gate oxide layer respectively with cellular conductive polycrystalline silicon and cellular insulating oxide isolated
On the cross section of described power MOS (Metal Oxide Semiconductor) device, the second conduction type well region is provided with connecting cellular groove away from above the outer wall side connecting withstand voltage trenched side, the first conductivity type implanted region is provided with in second conduction type well region, described first conductivity type implanted region and the second conduction type well region all contact with insulated gate oxide layer, and the bottom of Gate Electrode Conductive polysilicon is positioned at the below of the second conduction type well region, first conductivity type implanted region and the second conduction type well region all with the active area metal ohmic contact on the interarea of active area first, active area metal by insulating medium layer respectively with Gate Electrode Conductive polysilicon and cellular conductive polycrystalline silicon isolated.
10. utilize Charged Couple to realize the preparation method of withstand voltage power MOS (Metal Oxide Semiconductor) device according to claim 6, it is characterized in that: described hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
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