CN106653836B - Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same - Google Patents
Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to an insulated gate bipolar transistor device with low on-voltage drop and a manufacturing method thereof, wherein the insulated gate bipolar transistor device comprises an active region and a terminal protection region which are positioned on a semiconductor substrate, and on the section of the insulated gate bipolar transistor device, the active cells of the active region adopt a groove structure, and the active cells comprise active cells and inactive cells; the bottom of the active cell groove and the bottom of the inactive cell groove are both provided with second conductive floating regions, the second conductive floating regions below the active cell groove cover the bottom of the active cell groove, and the second conductive floating regions below the inactive cell groove cover the bottom of the inactive cell groove. The invention has extremely low on-voltage drop and extremely fast off-speed, and has lower current-voltage oscillation under the condition of ensuring voltage resistance, thereby greatly improving the working reliability.
Description
Technical Field
The invention relates to an insulated gate bipolar transistor device and a manufacturing method thereof, in particular to an insulated gate bipolar transistor device with low on-voltage drop and a manufacturing method thereof, belonging to the technical field of semiconductor devices.
Background
The IGBT is commonly referred to as Insulate Gate Bipolar Transistor, i.e. an insulated gate bipolar transistor. The power semiconductor device has the advantages of the MOSFET and the GTR, and greatly expands the application field of the power semiconductor device. As a main representative of the novel power semiconductor device, IGBTs are widely used in the fields of industry, information, new energy, medicine, traffic, military, and aviation. IGBTs are one of the most important power devices at present, and the IGBTs have the advantages of high input impedance, low on-state voltage drop, simple driving circuit, wide safe working area, strong current processing capability and the like, so that the IGBTs are increasingly valued in various power switch applications. It has wide application in motor control, medium frequency switching power supply and inverter, robot, air conditioner and many fields requiring fast and low loss.
Since the IGBT invention, efforts have been made to improve the performance of IGBTs. Through development for twenty years, a plurality of IGBT device structures are sequentially provided, so that the device performance is steadily improved. By employing dummy trench gate electrodes, IEGT device structures have been proposed in the industry. The dummy trench gate electrode of the IEGT device increases the distance between trench gates, reduces the extraction channel of minority carriers at the emitter end, introduces the carrier enhancement effect at the emitter end of the device, and enhances the carrier injection of the drift region, thereby improving the conductivity modulation of the N-type drift region, improving the carrier concentration distribution of the whole N-type drift region, and ensuring that the IGBT obtains low forward conduction voltage drop and improved forward conduction voltage drop and turn-off loss.
However, for IEGT device structures, 1), due to the adoption of dummy trench gate electrodes, results in: the grid capacitance (especially the grid-collector capacitance) of the device is large, however, the switching process of the IGBT device is the process of flushing and discharging the grid capacitance, the larger the grid capacitance is, the longer the flushing and discharging time is, the larger the grid capacitance (especially the grid-collector capacitance) is, the switching speed of the device is reduced, the switching loss of the device is increased, and the forward conduction voltage drop and the compromise characteristic of the switching loss of the device are affected; 2) Due to the presence of the floating body region, this results in: in-vivo potential inconsistency in the on-off process of the device shows larger voltage and current oscillation, so that serious EMI (electromagnetic interference) problems are caused, and the reliability of the system is seriously affected.
In view of the above drawbacks of the prior art, a new structure that effectively improves the performance of IGBTs and a method of manufacturing the same are highly desirable.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide an insulated gate bipolar transistor device with low on-voltage drop and a manufacturing method thereof, which have compact structure, extremely low on-voltage drop and extremely high off-speed under the condition of ensuring voltage resistance, lower current-voltage oscillation and greatly improve the reliability of work.
According to the technical scheme provided by the invention, the insulated gate bipolar transistor device with low on-voltage drop comprises an active region and a terminal protection region, wherein the active region is positioned on a semiconductor substrate, the terminal protection region is positioned on the outer ring of the active region and surrounds the active region; in the cross section of the insulated gate bipolar transistor device, the semiconductor substrate is provided with a first main surface and a second main surface corresponding to the first main surface, and a first conduction type drift region is arranged between the first main surface and the second main surface;
on the cross section of the insulated gate bipolar transistor device, the active region cell adopts a groove structure, and the active region cell comprises an active cell and an inactive cell; an insulated gate oxide layer grows on the inner wall and the bottom wall of a groove of each active cell, active cell conductive polysilicon is filled in the groove of each active cell growing with the insulated gate oxide layer, and the notch of each active cell groove is covered by a first insulating medium layer; a second conductive type body region is arranged between adjacent active cell grooves, and a first conductive type carrier storage layer is arranged at the bottom of the second conductive type body region; a first conductive type emission region and a second conductive type active ohmic contact region are arranged in the second conductive type body region, the first conductive type emission region is contacted with the outer side wall of the active cell groove, and the second conductive type active ohmic contact region is positioned between the first conductive type emission regions and is contacted with the first conductive type emission regions at two sides; the first conductive type emission region and the second conductive type active ohmic contact region are in ohmic contact with the first emitter metal above the first main surface; active cell conductive polysilicon is in ohmic contact with the gate electrode metal above the first main surface;
An insulated gate oxide layer grows on the inner wall and the bottom wall of a groove of the non-active cell, the non-active cell groove growing with the insulated gate oxide layer is filled with non-active cell conductive polysilicon, second conductive type pseudo-body regions are arranged on two sides of the non-active cell groove, second conductive type non-active ohmic contact regions are arranged in the second conductive type pseudo-body regions, the second conductive type non-active ohmic contact regions are in contact with the outer side wall of the non-active cell groove, and the second conductive type non-active ohmic contact regions and the non-active cell conductive polysilicon are in ohmic contact with second emitter metal on the first main surface; the second emitter metal is insulated and isolated from the first emitter metal;
the bottom of the active cell groove and the bottom of the inactive cell groove are both provided with second conductive floating regions, the second conductive floating regions below the active cell groove cover the bottom of the active cell groove, and the second conductive floating regions below the inactive cell groove cover the bottom of the inactive cell groove.
The first emitter metal is connected with the second emitter metal through a diode, the first emitter metal is connected with the anode end of the diode, and the second emitter metal is connected with the cathode end of the diode.
The first emitter metal is connected with the second emitter metal through an external diode or connected with the second emitter metal through an integrated diode arranged on the first main surface; the integrated diode is positioned on the first main surface of the terminal protection area and comprises a diode P-type conductive area and a diode N-type conductive area adjacent to the diode P-type conductive area.
The terminal protection area comprises a transition area, a field limiting ring structure and a stop ring structure, wherein the transition area is adjacent to the active area, the stop ring structure is positioned on the outer ring of the terminal protection area, and the field limiting ring structure is positioned between the transition area and the stop ring structure.
And a second conduction type collector region is arranged on the second main surface of the semiconductor substrate, a first conduction type electric field cut-off region is arranged between the second conduction type collector region and the first conduction type drift region, and the second conduction type collector region is in ohmic contact with the collector metal.
A method of fabricating an insulated gate bipolar transistor device having a low on-voltage drop, the method comprising the steps of:
a. providing a semiconductor substrate having two opposing main faces including a first main face and a second main face corresponding to the first main face, and including a first conductivity type drift region between the first main face and the second main face;
b. Depositing a field oxide layer on the first main surface of the semiconductor substrate, wherein the field oxide layer covers the first main surface of the semiconductor substrate;
c. selectively masking and etching the field oxide layer to form an ion implantation window, implanting impurities of a second conductivity type by using the ion implantation window, and forming a main junction, a field limiting ring structure and a second conductivity type pseudo body region in the semiconductor substrate after well pushing;
d. removing the field oxide layer on the active region of the semiconductor substrate, and after removing the required field oxide layer, depositing a hard mask layer on the first main surface, wherein the hard mask layer covers the first main surface of the active region and covers the first main surface of the terminal protection region and the field oxide layer;
e. selectively masking and etching the hard mask layer to obtain a required hard mask window, and etching the semiconductor substrate by using the hard mask window to form a plurality of grooves in the first conductivity type drift region of the semiconductor substrate; injecting second conductivity type impurities above the first main surface of the semiconductor substrate with the grooves, and forming a required second conductivity type floating region after pushing the well, wherein the second conductivity type floating region covers the bottoms of the grooves;
f. Removing the hard mask layer on the first main surface of the semiconductor substrate, growing an insulating gate oxide layer on the inner wall and the bottom wall of the groove after removing the hard mask layer, and filling conductive polysilicon in the groove with the insulating gate oxide layer;
g. coating a first photoresist layer on a first main surface of the semiconductor substrate, and injecting first conductivity type impurities above the first main surface after the first photoresist layer is subjected to required etching so as to form a required first conductivity type carrier storage layer in a first conductivity type drift region of the semiconductor substrate;
h. removing the first photoresist layer, coating a second photoresist layer on the first main surface of the semiconductor substrate, and after the second photoresist layer is etched to be required, injecting second conductivity type impurities above the first main surface to form a second conductivity type body region in the first conductivity type drift region of the semiconductor substrate, wherein the second conductivity type body region is positioned right above the first conductivity type carrier storage layer and is in contact with the first conductivity type carrier storage layer;
i. removing the second photoresist layer, coating a third photoresist layer on the first main surface of the semiconductor substrate, and implanting first conductivity type impurities above the first main surface after the third photoresist layer is subjected to required etching so as to form a first conductivity type emission region and a first conductivity type cut-off region in the semiconductor substrate;
k. Depositing a first insulating dielectric layer on the first main surface of the semiconductor substrate, etching the first insulating dielectric layer, and implanting second conductivity type impurities above the etched first insulating dielectric layer to form a required second conductivity type ohmic contact region in the active region of the semiconductor substrate;
providing a second emitter metal on the first main surface of the semiconductor substrate, wherein the second emitter metal is in ohmic contact with the corresponding second conductive type ohmic contact area and the conductive polysilicon in the corresponding groove so as to form a required inactive cell;
n, depositing a second insulating dielectric layer on the first main surface of the semiconductor substrate, and etching the second insulating dielectric layer to form a required second insulating dielectric layer contact hole;
depositing a metal layer on the first main surface of the semiconductor substrate, etching the obtained metal layer to form required first emitter metal, gate electrode metal and stop ring metal, wherein the first emitter metal is in ohmic contact with the first conductive type emitter region and the corresponding second conductive type ohmic contact region so as to form required active cells, conductive polysilicon in the first conductive type drift region except for ohmic contact with the second emitter metal is in ohmic contact with the gate electrode metal, and the stop ring metal is in ohmic contact with the first conductive type stop region;
p, forming a first conductive type electric field cut-off region and a second conductive type collector region on the second main surface of the semiconductor substrate, wherein the first conductive type electric field cut-off region is positioned between the first conductive type drift region and the second conductive type collector region, and the second conductive type collector region is adjacent to the first conductive type electric field cut-off region;
q, depositing the required collector metal on the second conduction type collector region, wherein the collector metal is in ohmic contact with the second conduction type collector region.
The material of the semiconductor substrate includes silicon.
In the step g, when the first conductive type carrier storage layer is formed, a diode N-type conductive region is also formed on the first main surface of the semiconductor substrate; in step h, forming a diode P-type conductive region on the first main surface of the semiconductor substrate while forming the second conductivity type body region, the diode P-type conductive region being adjacent to the diode N-type conductive region to form an integrated diode; the second emitter metal is in ohmic contact with the diode N-type conductive region, and the first emitter metal is in ohmic contact with the diode P-type conductive region.
In the two types of the first conductivity type and the second conductivity type, for an N-type insulated gate bipolar transistor device, the first conductivity type refers to N type, and the second conductivity type refers to P type; for a P-type insulated gate bipolar transistor device, the first conductivity type and the second conductivity type refer to opposite types from the N-type semiconductor device.
The invention has the advantages that:
1. when the device is conducted, the first conductive type carrier storage layer positioned at the bottom of the second conductive type body region can obstruct the flow of minority carriers to the emitter due to the existence of built-in potential, so that accumulation of minority carriers can be formed, and the conductivity modulation effect is enhanced; meanwhile, the accumulation of minority carriers in the B region of the inactive cell further strengthens the conductivity modulation effect of the device, so that the saturation voltage drop of the IGBT device can be obviously reduced, and the conduction loss is reduced.
2. When the device is blocked, the floating region of the second conductivity type is arranged to shield the body region of the active cell region A, so that the withstand voltage of the device is not influenced when the concentration of the carrier storage layer of the first conductivity type is adjusted.
3. The existence of the inactive cell B region reduces the effective gate electrode area, greatly reduces the capacitance between the gate electrode and the emitter and the capacitance between the gate electrode and the collector, reduces the switching loss and improves the switching speed of the device.
4. And the inactive cell B region, the second emitter metal and the inactive cell conductive polysilicon are in ohmic contact and are connected with the cathode end of the diode, so that the voltage unbalance in the IGBT structure is reduced, and the current and voltage oscillation in the switching process of the device can be reduced.
Drawings
Fig. 1 is a cross-sectional view of an active region of the present invention.
Fig. 2 is a top view of the present invention.
FIG. 3 is a cross-sectional view of A1-A1' of FIG. 2 in accordance with the present invention.
FIG. 4 is a cross-sectional view of B1-B1' of FIG. 2 in accordance with the present invention.
FIG. 5 is a cross-sectional view of B2-B2' of FIG. 2 in accordance with the present invention.
FIG. 6 is a cross-sectional view of the C1-C1' of FIG. 2 in accordance with the present invention.
FIGS. 7-19 are cross-sectional views illustrating steps of a process embodying the present invention, wherein
Fig. 7 is a cross-sectional view of a semiconductor substrate of the present invention.
Fig. 8 is a cross-sectional view of the present invention after a field oxide layer is formed.
Fig. 9 is a cross-sectional view of the P-type dummy body region obtained in accordance with the present invention.
Fig. 10 is a cross-sectional view of the present invention after a hard mask layer is formed.
Fig. 11 is a cross-sectional view of a P-type floating region according to the present invention.
Fig. 12 is a cross-sectional view of the invention after filling with conductive polysilicon.
Fig. 13 is a cross-sectional view of the present invention after an N-type carrier storage layer is obtained.
Fig. 14 is a cross-sectional view of the present invention after a P-type ohmic contact region is made.
Fig. 15 is a cross-sectional view of the present invention after a second emitter metal is obtained.
Fig. 16 is a cross-sectional view of the present invention after a second dielectric layer is formed.
Fig. 17 is a cross-sectional view of the present invention after a first emitter metal is obtained.
Fig. 18 is a cross-sectional view of the P-type collector region of the present invention.
Fig. 19 is a cross-sectional view of the present invention after collector metal is obtained.
Reference numerals illustrate: 1-N type drift region, 2-P type dummy body region, 3-P type floating region, 4-N type carrier storage layer, 5-P type body region, 6-insulated gate oxide layer, 7-active cell conductive polysilicon, 7-1-diode N type conductive region, 7-2-diode P type conductive region, 8-N+ emission region, 9-P type active ohmic contact region, 10-first insulating dielectric layer, 11-second emitter metal, 12-second insulating dielectric layer, 13-first emitter metal, 14-field oxide layer, 15-P type transition region, 16-gate electrode metal, 17-cut-off ring metal, 18-N+ electric field cut-off region, 19-P+ collector region, 20-collector metal, 21-N+ cut-off region, 22-P type field limiting ring, 23-inactive cell conductive polysilicon, 24-insulating isolation layer, 25-active cell extraction conductive polysilicon, 26-P type inactive ohmic contact region, 27-hard mask layer, 100-active terminal region and 200-terminal protection region.
Description of the embodiments
The invention will be further described with reference to the following specific drawings and examples.
As shown in fig. 1, 2, 3, 4, 5, 6 and 19: in order to ensure the voltage withstand, have extremely low on-voltage drop and extremely fast off-speed, and have lower current-voltage oscillation, greatly improve the reliability of operation, take the N-type insulated gate bipolar transistor device as an example, the invention specifically comprises: the insulated gate bipolar transistor device comprises an active region 100 and a terminal protection region 200 which are positioned on a semiconductor substrate, wherein the active region 100 is positioned in a central region of the semiconductor substrate, and the terminal protection region 200 is positioned on the outer ring of the active region 100 and surrounds the active region 100; in the cross section of the insulated gate bipolar transistor device, the semiconductor substrate has a first main surface and a second main surface corresponding to the first main surface, and an N-type drift region 1 is arranged between the first main surface and the second main surface;
On the cross section of the insulated gate bipolar transistor device, the active region 100 unit cell adopts a groove structure, and the active region unit cell comprises an active unit cell A and an inactive unit cell B; an insulated gate oxide layer 6 grows on the inner wall and the bottom wall of the groove of the active cell A, active cell conductive polysilicon 7 is filled in the groove of the active cell grown with the insulated gate oxide layer 6, and the notch of the groove of the active cell A is covered by a first insulating medium layer 10; a P-type body region 5 is arranged between adjacent active cell grooves, and an N-type carrier storage layer 4 is arranged at the bottom of the P-type body region 5; an N+ emission region 8 and a P-type active ohmic contact region 9,N + emission region 8 are arranged in the P-type body region 5, the P-type active ohmic contact region 9 is positioned between the N+ emission regions 8 and is in contact with the N+ emission regions 8 at two sides; the N+ emission region 8 and the P-type active ohmic contact region 9 are in ohmic contact with the first emitter metal 13 above the first main surface; the active cell conductive polysilicon 7 is in ohmic contact with the gate electrode metal 16 above the first main surface;
an insulated gate oxide layer 6 grows on the inner wall and the bottom wall of a groove of the non-active cell, an inactive cell conductive polysilicon 23 is filled in the groove of the non-active cell growing with the insulated gate oxide layer 6, P-type dummy body regions 2 are arranged on two sides of the groove of the non-active cell, P-type inactive ohmic contact regions 26 are arranged in the P-type dummy body regions 2, the P-type inactive ohmic contact regions 26 are contacted with the outer side wall of the groove of the non-active cell, and the P-type inactive ohmic contact regions 26 and the inactive cell conductive polysilicon 23 are in ohmic contact with second emitter metal 11 on the first main surface; the second emitter metal 11 is insulated from the first emitter metal 13;
The bottom of the active cell groove and the bottom of the inactive cell groove are both provided with P-type floating regions 3, the P-type floating regions 3 below the active cell groove cover the bottom of the active cell groove, and the P-type floating regions 3 below the inactive cell groove cover the bottom of the inactive cell groove.
Specifically, the semiconductor substrate may be a silicon substrate, and the active area 100 can be effectively protected by the terminal protection area 200, and the specific matching relationship between the active area 100 and the terminal protection area 200 is well known to those skilled in the art, and will not be described herein. In the embodiment of the invention, the grooves of the active cell A and the grooves of the inactive cell B are the same process manufacturing layer, namely, the depths of the grooves of the active cell A and the grooves of the inactive cell B are the same, the insulating gate oxide layer 6 in the grooves of the active cell A and the insulating gate oxide layer 6 in the grooves of the inactive cell B are the same process layer, and the active cell conductive polysilicon 7 in the grooves of the active cell A and the inactive cell conductive polysilicon 23 in the grooves of the inactive cell B are the same process layer.
In fig. 3, A1-A1' is taken in a cross-section perpendicular to the trenches, in fig. 4, parallel to the trenches and in a cross-section along the direction of the active cell conductive polysilicon 7, and in fig. 5, parallel to the trenches and in a cross-section along the direction of the inactive cell conductive polysilicon 7.
The notch of the active cell a groove is covered by a first insulating medium layer 10, so that the active cell conductive polysilicon 7 in the active cell a groove is insulated and isolated from the first emitter metal 13 and the second emitter metal 11, the first emitter metal 13 is isolated from the P-type body region 5 through the n+ emission region 8 and the P-type active ohmic contact region 9, the n+ emission region 8 is contacted with the upper side wall of the active cell a groove, the N-type carrier storage layer 4 is positioned below the P-type body region 5, generally, the N-type carrier storage layer 4 is positioned above the bottom of the active cell a groove, the N-type carrier storage layer 4 is not contacted with the P-type floating region 3, and the P-type body region 5 is isolated from the N-type drift region 1 through the N-type carrier storage layer 4. When the device is turned on, holes accumulate at the bottom of the N-type carrier storage layer 4 and form built-in potential with the N-type carrier storage layer 4; the accumulation of holes reduces the resistivity of the N-type drift region 1, thereby effectively reducing the on-voltage drop.
The conductive polysilicon in direct ohmic contact with the second emitter metal 11 forms inactive cell conductive polysilicon 23, and P-type dummy body regions 2 are formed on both sides of the inactive cell B trench, and the P-type dummy body regions 2 are in contact with the P-type floating regions 3. The P-type inactive ohmic contact region 26 is connected to the upper side of the outer sidewall of the inactive cell B trench. On the cross section of the insulated gate bipolar transistor device, the P-type floating regions 3 at the bottom of the groove of the active cell A are mutually separated, and the P-type floating regions 3 at the bottom of the groove of the inactive cell B can be mutually contacted or mutually separated.
In the embodiment of the invention, the first emitter metal 13 is insulated from the second emitter metal 11 by the second insulating dielectric layer 12, the emitter terminal of the insulated gate bipolar transistor device can be formed by the first emitter metal 13, and the gate electrode terminal of the insulated gate bipolar transistor device can be formed by the gate electrode metal 16.
In the embodiment of the invention, when the device is conducted, minority carriers of the inactive cell B are accumulated, so that the conductivity modulation effect of the device is further enhanced, and therefore, the saturation voltage drop of the IGBT device can be obviously reduced, and the conduction loss is reduced; the existence of the inactive cell B reduces the effective gate electrode area, greatly reduces the capacitance between the gate and the emitter of the device and the capacitance between the gate and the collector of the device, reduces the switching loss and improves the switching speed of the device. In particular, the number of active cells a and the number of inactive cells B in the active region 100 may be adjusted according to the specific requirements of the igbt device.
Further, the first emitter metal 13 is connected with the second emitter metal 11 through a diode, the first emitter metal 13 is connected with the anode terminal of the diode, and the second emitter metal 11 is connected with the cathode terminal of the diode.
In the embodiment of the invention, after the first emitter metal 13 is connected with the second emitter metal 11 through the diode, the unbalance of the internal voltage of the device can be reduced, so that the current and voltage oscillation in the switching process of the device can be reduced. In specific implementation, the first emitter metal 13 is connected with the second emitter metal through an external diode, or is connected with the second emitter metal 11 through an integrated diode arranged on the first main surface; an integrated diode is located on the first main surface of the termination protection region 200, the integrated diode comprising a diode P-type conductive region 7-2 and a diode N-type conductive region 7-1 adjacent to the diode P-type conductive region 7-2.
Further, the terminal protection region 200 includes a transition region C, a field limiting ring structure D, and a stop ring structure E, where the transition region C abuts the active region 100, the stop ring structure E is located on the outer ring of the terminal protection region 200, and the field limiting ring structure D is located between the transition region C and the stop ring structure E.
In the embodiment of the invention, the transition region C, the field limiting ring structure D and the stop ring structure E are all annular, the transition region C includes a P-type transition region 15 disposed in the N-type drift region 1, and the P-type transition region 15 contacts with the sidewall of the outermost trench of the active region 100 and the P-type floating region 3 at the bottom of the trench. On the first main surface corresponding to the transition region C, an insulating isolation layer 24 and active cell leading-out conductive polysilicon 25 disposed on the insulating isolation layer 24 are disposed, the active cell leading-out conductive polysilicon 25 is isolated from the P-type transition region 15 by the insulating isolation layer 24, the active cell leading-out conductive polysilicon 25 and the active cell conductive polysilicon 7 in the active region 100 are connected into a whole, and the active cell conductive polysilicon 7 in the active region 100 is in ohmic contact with the gate electrode metal 16 by the active cell leading-out conductive polysilicon 25. The active cell extraction conductive polysilicon 25 is insulated from the second emitter metal 11 by a first insulating dielectric layer 10. The gate electrode metal 16 is insulated from the second emitter metal 11 by a second insulating dielectric layer 12.
The field limiting ring structure D includes a P-type field limiting ring 22 disposed in the N-type drift region 1, where the P-type field limiting ring 22 and the P-type transition region 15 are manufactured by the same process. The first main surface above the P-type field limiting ring 22 is further provided with a first insulating medium layer 10, etc., and the field limiting ring structure D may be in a structure commonly used in the art, and is specifically well known in the art, and will not be described herein.
The cut-off ring structure E includes an n+ cut-off region 21, where the n+ cut-off region 21 is in ohmic contact with the cut-off ring metal 17 on the first main surface, and the n+ cut-off region 21 and the n+ emission region 8 are the same process manufacturing layer, and the specific structure and function of the chang cut-off ring structure E are the same as those of the prior art, and are well known to the local operators, and are not described herein.
Further, a p+ collector region 19 is disposed on the second main surface of the semiconductor substrate, an n+ electric field cut-off region 18 is disposed between the p+ collector region 19 and the N-type drift region 1, and the p+ collector region 19 is in ohmic contact with the collector metal 20. In the embodiment of the present invention, the doping concentration of the n+ electric field cut-off region 18 is greater than that of the N-type drift region 1, and the p+ collector region 19 may be continuous or discontinuous, and when the p+ collector region 19 is discontinuous, the collector metal 20 is in ohmic contact with the n+ electric field cut-off region 18, and the collector end of the device can be formed through the collector metal 20.
As shown in fig. 7 to 19, the insulated gate bipolar transistor device with low on-voltage drop can be manufactured by the following manufacturing method, and specifically, the manufacturing method of the insulated gate bipolar transistor device includes the following steps:
a. providing a semiconductor substrate having two opposite main surfaces, the two opposite main surfaces including a first main surface and a second main surface corresponding to the first main surface, and an N-type drift region 1 being provided between the first main surface and the second main surface;
as shown in fig. 7, the material of the semiconductor substrate includes silicon, however, other materials commonly used in the art may be used for the semiconductor substrate, which is not listed here.
b. Depositing a field oxide layer 14 on the first main surface of the semiconductor substrate, wherein the field oxide layer 14 covers the first main surface of the semiconductor substrate;
as shown in fig. 8, the field oxide layer 14 is a silicon dioxide layer, and the specific process of depositing the field oxide layer 14 is well known to those skilled in the art and will not be described herein.
c. Selectively masking and etching the field oxide layer 14 to form an ion implantation window, implanting P-type impurities by using the ion implantation window, and forming a main junction, a field limiting ring structure D and a P-type dummy body region 2 in the semiconductor substrate after well pushing;
As shown in fig. 9, the ion implantation window penetrates through the field oxide layer 14, and P-type impurities can be implanted into the N-type drift region 1 by using the ion implantation window, and specific processes of P-type impurity implantation and well-pushing are well known to those skilled in the art and will not be described herein. The main junction is a PN junction formed by the P-type transition region 15 and the N-type drift region 1 below the P-type transition region 15, the P-type dummy body region 2 is located in the active region 100, and the main junction and the field limiting ring structure D are both located in the terminal protection region 200.
d. Removing the field oxide layer 14 on the active region 100 of the semiconductor substrate, and after removing the required field oxide layer 14, depositing a hard mask layer 27 on the first main surface, wherein the hard mask layer 27 covers the first main surface of the active region 100 and covers the first main surface of the termination protection region 200 and the field oxide layer 14;
as shown in fig. 10, the field oxide layer 14 on the active region 100 is removed by using a photoresist masking method, etc., and the specific process of removing the field oxide layer 14 is well known in the art and will not be described herein. The hard mask layer 27 is LPTEOS, thermal oxide silicon dioxide plus chemical vapor deposited silicon dioxide, or thermal silicon dioxide plus silicon nitride. Since the field oxide layer 14 on the active region 100 has been completely removed, the field oxide layer 14 on the termination protection region 200 remains, and thus the hard mask layer 27 directly covers the first main surface of the active region 100 and covers the field oxide layer 14 on the termination protection region 200 and a portion of the first main surface of the termination protection region 200.
e. Selectively masking and etching the hard mask layer 27 to obtain a desired hard mask window, and etching the semiconductor substrate by using the hard mask window to form a plurality of trenches in the N-type drift region 1 of the semiconductor substrate; injecting P-type impurities above the first main surface of the semiconductor substrate with the grooves, forming a required P-type floating region 3 after pushing a well, wherein the P-type floating region 3 covers the bottoms of the grooves;
as shown in fig. 11, the hard mask layer 27 can be etched by using a technical means commonly used in the art to obtain a hard mask window, the hard mask window penetrates through the hard mask layer 27, and the N-type drift region 1 is anisotropically etched by using the hard mask window, so as to obtain a plurality of trenches, and the trenches extend from the first main surface vertically into the N-type drift region 1. After forming the trench, P-type impurities are implanted to obtain the P-type floating region 3, and specific processes of P-type impurity implantation and well-push are well known to those skilled in the art and will not be described herein.
f. Removing the hard mask layer 27 on the first main surface of the semiconductor substrate, growing an insulating gate oxide layer 6 on the inner wall and the bottom wall of the groove after removing the hard mask layer 27, and filling conductive polysilicon in the groove with the insulating gate oxide layer 6;
Specifically, the removal of the hard mask layer 27 can be achieved by using a technical means commonly used in the art, the insulated gate oxide layer 6 can be obtained by thermal oxidation growth, and after the insulated gate oxide layer 6 is grown, the conductive polysilicon can be filled in the trench by depositing the conductive polysilicon on the first main surface. After filling the trenches, the conductive polysilicon in the corresponding regions on the first major surface need to be etched away for subsequent processing. The etching removal of the corresponding conductive polysilicon is realized by adopting the technical means commonly used in the technical field, which is particularly well known in the technical field, and is not repeated here.
g. Coating a first photoresist layer on a first main surface of the semiconductor substrate, and after the first photoresist layer is subjected to required etching, injecting an N-type impurity above the first main surface to form a required N-type carrier storage layer 4 in an N-type drift region 1 of the semiconductor substrate;
specifically, after the first main surface is coated with the first photoresist layer and the first photoresist layer is etched, N-type impurities are conveniently injected to form the required N-type carrier storage layer 4 in the active region 100, as shown in fig. 12, and specific process steps are well known to those skilled in the art and are not repeated herein.
In addition, when the first emitter metal 13 and the second emitter metal 11 are connected by using an integrated diode, when the N-type carrier storage layer 4 is formed, the diode N-type conductive region 7-1 can also be formed on the first main surface of the transition region C, and the diode N-type conductive region 7-1 can be obtained by performing N-type impurity implantation through conductive polysilicon on the first main surface of the transition region C.
h. Removing the first photoresist layer, coating a second photoresist layer on the first main surface of the semiconductor substrate, and after the second photoresist layer is etched to be required, injecting P-type impurities above the first main surface to form a P-type body region 5 in an N-type drift region 1 of the semiconductor substrate, wherein the P-type body region 5 is positioned right above an N-type carrier storage layer 4, and the P-type body region 5 is in contact with the N-type carrier storage layer;
as shown in fig. 13, the first photoresist layer can be removed by a conventional technique in the art, and P-type impurities can be conveniently performed after etching the second photoresist layer, so as to obtain the P-type body region 5. Furthermore, a diode P-type conductive region 7-2 can be formed on the first main surface of the transition region C, and the diode P-type conductive region 7-2 is connected with the diode N-type conductive region 71-to form a diode structure.
i. Removing the second photoresist layer, coating a third photoresist layer on the first main surface of the semiconductor substrate, and implanting N-type impurities above the first main surface after the third photoresist layer is subjected to required etching to form an N+ emission region 8 and an N+ cut-off region 21 in the semiconductor substrate;
specifically, the second photoresist layer is removed by adopting a technical means commonly used in the technical field; after the third photoresist layer is coated and lithographically etched, N-type impurity implantation is performed to obtain n+ emitter region 8 and n+ stop region 21, n+ emitter region 8 being located within active region 100. After the n+ emitter region 8 and the n+ stop region 21 are obtained, the third photoresist layer is removed.
k. Depositing a first insulating dielectric layer 10 on a first main surface of the semiconductor substrate, etching the first insulating dielectric layer 10, and implanting P-type impurities above the etched first insulating dielectric layer 10 to form a required P-type ohmic contact region in an active region 100 of the semiconductor substrate;
as shown in fig. 14, after etching the first insulating dielectric layer 10, the first insulating dielectric layer 10 can cover the notch of a part of the trench in the active region 100, and in addition, P-type impurity injection can be implemented by using the etched first insulating dielectric layer 10 to obtain a P-type ohmic contact region, specifically, the P-type ohmic contact region includes a P-type active ohmic contact region 9 and a P-type inactive ohmic contact region 26, the P-type active ohmic contact region 9 contacts with the n+ emission region 8, and the first insulating dielectric layer 10 above the P-type active ohmic contact region 9 is etched. The P-type inactive ohmic contact region 26 is flanked by no N + emitter regions 8.
Providing a second emitter metal 11 on the first main surface of the semiconductor substrate, wherein the second emitter metal 11 is in ohmic contact with the corresponding P-type ohmic contact area and the conductive polysilicon in the corresponding groove so as to form a required inactive cell B;
as shown in fig. 15, since the notch of a part of the trench is in an open state when etching the first insulating dielectric layer 10, when depositing the second emitter metal 11, the second emitter metal 11 is in ohmic contact with the P-type inactive ohmic contact region 26 and the conductive polysilicon directly under, so as to form an inactive cell B, and after the inactive cell B is formed, the conductive polysilicon becomes the inactive cell conductive polysilicon 23. When the second emitter metal 11 is obtained, the second emitter metal 11 may be in ohmic contact with the diode N-type conductive region 7-1.
n, depositing a second insulating dielectric layer 12 on the first main surface of the semiconductor substrate, and etching the second insulating dielectric layer 12 to form a required second insulating dielectric layer contact hole;
as shown in fig. 16, after the second insulating dielectric layer 12 is deposited, a second insulating dielectric layer contact hole is formed in a desired position area, and the position of the second insulating dielectric layer contact hole may be selected according to needs, which is well known in the art, and will not be described herein.
o, depositing a metal layer on the first main surface of the semiconductor substrate, etching the obtained metal layer to form a first emitter metal 13, a gate electrode metal 16 and a stop ring metal 17, wherein the first emitter metal 13 is in ohmic contact with the N+ emitter region 8 and the corresponding P-type ohmic contact region to form a required active cell A, conductive polysilicon except for ohmic contact with the second emitter metal 11 in the N-type drift region 1 is in ohmic contact with the gate electrode metal 16, and the stop ring metal 17 is in ohmic contact with the N+ stop region 21;
as shown in fig. 17, after the metal layer is deposited and etched, the first emitter metal 13 can be in ohmic contact with the n+ emitter 8 and the P-type active ohmic contact region 9, and the stop ring metal 17 can be in ohmic contact with the n+ stop region 21 by using the second insulating dielectric layer contact hole. In the active region 100, the conductive polysilicon in ohmic contact with the second emitter metal 11 forms inactive cell conductive polysilicon 23, the conductive polysilicon in the remaining trenches forms active cell conductive polysilicon 7, the active cell conductive polysilicon 7 is connected in parallel, and the active cell extraction conductive polysilicon 25 on the transition region is in ohmic contact with the gate electrode metal 16, and the active cell extraction conductive polysilicon 25 and the active cell conductive polysilicon 7 are in the same process layer, i.e. step f, the specific preparation process is well known to those skilled in the art, and is not repeated herein.
P, forming a required N+ electric field cut-off region 18 and a P+ collector region 19 on the second main surface of the semiconductor substrate, wherein the N+ electric field cut-off region 18 is positioned between the N-type drift region 1 and the P+ collector region 19, and the P+ collector region 19 is adjacent to the N+ electric field cut-off region 18;
as shown in fig. 18, the doping concentration of the n+ electric field cut-off region 18 is greater than that of the N-type drift region 1, and generally, the second main surface of the semiconductor substrate may be thinned, and the specific thinning process is well known to those skilled in the art and will not be described herein.
q, depositing the required collector metal 20 on the p+ collector region 19, said collector metal 20 being in ohmic contact with the p+ collector region.
As shown in fig. 19, the collector terminal of the device can be formed by collector metal 20.
When the device is conducted, the N-type carrier storage layer 4 positioned at the bottom of the P-type body region 5 can prevent minority carriers from flowing to the emitter due to the existence of built-in potential, so that accumulation of the minority carriers can be formed, and the conductivity modulation effect is enhanced; meanwhile, the accumulation of minority carriers in the B region of the inactive cell further strengthens the conductivity modulation effect of the device, so that the saturation voltage drop of the IGBT device can be obviously reduced, and the conduction loss is reduced; when the device is blocked, the existence of the P-type floating region 3 shields the body region of the active cell region A, so that the withstand voltage of the device is not influenced when the concentration of the N-type carrier storage layer 4 is regulated.
The existence of the inactive cell B region reduces the area of the effective gate electrode, greatly reduces the capacitance between the gate electrode and the emitter and the capacitance between the gate electrode and the collector, reduces the switching loss and improves the switching speed of the device; in the inactive cell B region, the second emitter metal 11 is in ohmic contact with the inactive cell conductive polysilicon 23 and is connected with the cathode end of the diode, so that the voltage unbalance in the IGBT structure is reduced, and the current and voltage oscillation in the switching process of the device can be reduced.
Claims (8)
1. An insulated gate bipolar transistor device with low on-voltage drop comprises an active region and a terminal protection region on a semiconductor substrate on a top plane of the insulated gate bipolar transistor device, wherein the active region is positioned in a central region of the semiconductor substrate, and the terminal protection region is positioned at the outer ring of the active region and surrounds the active region; in the cross section of the insulated gate bipolar transistor device, the semiconductor substrate is provided with a first main surface and a second main surface corresponding to the first main surface, and a first conduction type drift region is arranged between the first main surface and the second main surface; the method is characterized in that:
on the cross section of the insulated gate bipolar transistor device, the cell of the active region adopts a groove structure, and the cell of the active region comprises an active cell and an inactive cell; an insulated gate oxide layer grows on the inner wall and the bottom wall of a groove of each active cell, active cell conductive polysilicon is filled in the groove of each active cell growing with the insulated gate oxide layer, and the notch of each active cell groove is covered by a first insulating medium layer; a second conductive type body region is arranged between adjacent active cell grooves, and a first conductive type carrier storage layer is arranged at the bottom of the second conductive type body region; a first conductive type emission region and a second conductive type active ohmic contact region are arranged in the second conductive type body region, the first conductive type emission region is contacted with the outer side wall of the active cell groove, and the second conductive type active ohmic contact region is positioned between the first conductive type emission regions and is contacted with the first conductive type emission regions at two sides; the first conductive type emission region and the second conductive type active ohmic contact region are in ohmic contact with the first emitter metal above the first main surface; active cell conductive polysilicon is in ohmic contact with the gate electrode metal above the first main surface;
An insulated gate oxide layer grows on the inner wall and the bottom wall of a groove of the non-active cell, the non-active cell groove growing with the insulated gate oxide layer is filled with non-active cell conductive polysilicon, second conductive type pseudo-body regions are arranged on two sides of the non-active cell groove, second conductive type non-active ohmic contact regions are arranged in the second conductive type pseudo-body regions, the second conductive type non-active ohmic contact regions are in contact with the outer side wall of the non-active cell groove, and the second conductive type non-active ohmic contact regions and the non-active cell conductive polysilicon are in ohmic contact with second emitter metal on the first main surface; the second emitter metal is insulated and isolated from the first emitter metal;
the bottom of the active cell groove and the bottom of the inactive cell groove are both provided with second conductive floating regions, the second conductive floating regions below the active cell groove cover the bottom of the active cell groove, and the second conductive floating regions below the inactive cell groove cover the bottom of the inactive cell groove.
2. The insulated gate bipolar transistor device with low on-voltage drop of claim 1, wherein: the first emitter metal is connected with the second emitter metal through a diode, the first emitter metal is connected with the anode end of the diode, and the second emitter metal is connected with the cathode end of the diode.
3. The insulated gate bipolar transistor device with low on-voltage drop of claim 2, wherein: the first emitter metal is connected with the second emitter metal through an external diode or connected with the second emitter metal through an integrated diode arranged on the first main surface; the integrated diode is positioned on the first main surface of the terminal protection area and comprises a diode P-type conductive area and a diode N-type conductive area adjacent to the diode P-type conductive area.
4. The insulated gate bipolar transistor device with low on-voltage drop of claim 1, wherein: the terminal protection area comprises a transition area, a field limiting ring structure and a stop ring structure, wherein the transition area is adjacent to the active area, the stop ring structure is positioned on the outer ring of the terminal protection area, and the field limiting ring structure is positioned between the transition area and the stop ring structure.
5. The insulated gate bipolar transistor device with low on-voltage drop of claim 1, wherein: and a second conduction type collector region is arranged on the second main surface of the semiconductor substrate, a first conduction type electric field cut-off region is arranged between the second conduction type collector region and the first conduction type drift region, and the second conduction type collector region is in ohmic contact with the collector metal.
6. A method of fabricating an insulated gate bipolar transistor device having a low on-state voltage drop, the method comprising the steps of:
(a) Providing a semiconductor substrate having two opposing main faces including a first main face and a second main face corresponding to the first main face, and including a first conductivity type drift region between the first main face and the second main face;
(b) Depositing a field oxide layer on the first main surface of the semiconductor substrate, wherein the field oxide layer covers the first main surface of the semiconductor substrate;
(c) Selectively masking and etching the field oxide layer to form an ion implantation window, implanting impurities of a second conductivity type by using the ion implantation window, and forming a main junction, a field limiting ring structure and a second conductivity type pseudo body region in the semiconductor substrate after well pushing;
(d) Removing the field oxide layer on the active region of the semiconductor substrate, and after removing the required field oxide layer, depositing a hard mask layer on the first main surface, wherein the hard mask layer covers the first main surface of the active region and covers the first main surface of the terminal protection region and the field oxide layer;
(e) Selectively masking and etching the hard mask layer to obtain a required hard mask window, and etching the semiconductor substrate by using the hard mask window to form a plurality of grooves in the first conductivity type drift region of the semiconductor substrate; injecting second conductivity type impurities above the first main surface of the semiconductor substrate with the grooves, and forming a required second conductivity type floating region after pushing the well, wherein the second conductivity type floating region covers the bottoms of the grooves;
(f) Removing the hard mask layer on the first main surface of the semiconductor substrate, growing insulating gate oxide layers on the inner wall and the bottom wall of the groove after removing the hard mask layer, and filling conductive polysilicon in the groove with the insulating gate oxide layers;
(g) Coating a first photoresist layer on a first main surface of the semiconductor substrate, and injecting first conductivity type impurities above the first main surface after the first photoresist layer is etched to form a first conductivity type carrier storage layer in a first conductivity type drift region of the semiconductor substrate;
(h) Removing the first photoresist layer, coating a second photoresist layer on the first main surface of the semiconductor substrate, and injecting second conductivity type impurities above the first main surface after the second photoresist layer is etched to form a second conductivity type body region in the first conductivity type drift region of the semiconductor substrate, wherein the second conductivity type body region is positioned right above the first conductivity type carrier storage layer and is in contact with the first conductivity type carrier storage layer;
(i) Removing the second photoresist layer, coating a third photoresist layer on the first main surface of the semiconductor substrate, and implanting first conductivity type impurities above the first main surface after the third photoresist layer is subjected to required etching so as to form a first conductivity type emission region and a first conductivity type cut-off region in the semiconductor substrate;
(k) Depositing a first insulating dielectric layer on the first main surface of the semiconductor substrate, etching the first insulating dielectric layer, and implanting second conductivity type impurities above the etched first insulating dielectric layer to form a required second conductivity type ohmic contact region in the active region of the semiconductor substrate;
(l) Providing a second emitter metal on the first main surface of the semiconductor substrate, wherein the second emitter metal is in ohmic contact with the corresponding second conductive type ohmic contact area and the conductive polysilicon in the corresponding groove so as to form a required inactive cell;
(n) depositing a second insulating dielectric layer on the first main surface of the semiconductor substrate, and etching the second insulating dielectric layer to form a required second insulating dielectric layer contact hole;
(o) depositing a metal layer on the first main surface of the semiconductor substrate, etching the obtained metal layer to form a required first emitter metal, a gate electrode metal and a stop ring metal, wherein the first emitter metal is in ohmic contact with the first conductive type emitter region and the corresponding second conductive type ohmic contact region so as to form a required active cell, conductive polysilicon in the first conductive type drift region except the ohmic contact with the second emitter metal is in ohmic contact with the gate electrode metal, and the stop ring metal is in ohmic contact with the first conductive type stop region;
(p) forming a first conductivity type electric field stop region and a second conductivity type collector region on the second main surface of the semiconductor substrate, wherein the first conductivity type electric field stop region is positioned between the first conductivity type drift region and the second conductivity type collector region, and the second conductivity type collector region is adjacent to the first conductivity type electric field stop region;
(q) depositing a desired collector metal on the second conductivity type collector region, the collector metal in ohmic contact with the second conductivity type collector region.
7. The method of manufacturing an insulated gate bipolar transistor device with low on-state voltage drop according to claim 6, wherein: the material of the semiconductor substrate includes silicon.
8. The method of manufacturing an insulated gate bipolar transistor device with low on-state voltage drop according to claim 6, wherein: in the step (g), when the first conductivity type carrier storage layer is formed, a diode N-type conductive region is also formed on the first main surface of the semiconductor substrate; in step (h), forming a diode P-type conductive region on the first main surface of the semiconductor substrate while forming the second conductivity type body region, the diode P-type conductive region being contiguous with the diode N-type conductive region to form an integrated diode; the second emitter metal is in ohmic contact with the diode N-type conductive region, and the first emitter metal is in ohmic contact with the diode P-type conductive region.
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