CN107658343B - Semiconductor structure for optimizing device characteristics and manufacturing method thereof - Google Patents
Semiconductor structure for optimizing device characteristics and manufacturing method thereof Download PDFInfo
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- CN107658343B CN107658343B CN201711043510.7A CN201711043510A CN107658343B CN 107658343 B CN107658343 B CN 107658343B CN 201711043510 A CN201711043510 A CN 201711043510A CN 107658343 B CN107658343 B CN 107658343B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 44
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 210000000746 body region Anatomy 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention relates to a semiconductor structure for optimizing device characteristics and a manufacturing method thereof, which are characterized in that: a first conductive type region is arranged below the groove in the active region, and the first conductive type region covers the bottom of the groove; according to the invention, the first conductive type region is arranged at the bottom of the groove of the active region, so that the voltage resistance of the active region is lower than that of the terminal protection region, the breakdown point is positioned in the active region when the device is in voltage resistance, and meanwhile, the on-resistance of the device is reduced.
Description
Technical Field
The invention relates to a power semiconductor device and a manufacturing method thereof, in particular to a semiconductor structure for optimizing the characteristics of the device and a manufacturing method thereof, belonging to the technical field of manufacturing of semiconductor devices.
Background
In the field of power semiconductor devices, the design of the power semiconductor device generally requires lower on-resistance, and requires that the breakdown point of the device fall in the active region, rather than the termination protection region, and the deep trench MOSFET can significantly improve the channel density and reduce the characteristic on-resistance, so that the deep trench MOSFET has been widely adopted. At present, the terminal voltage resistance of the deep trench MOSFET limits the overall voltage resistance of the device, and the terminal voltage resistance is lower than the cell voltage resistance, so that the on-resistance of the device is higher, and the reliability is reduced.
As shown in fig. 12, in the conventional deep trench MOSFET power semiconductor device structure, the first conductivity type region 14 does not exist at the bottoms of the trenches 4 in the active region 01 and the termination protection region 02, and when the device is voltage-resistant, the electric field at the bottom of the trench 4 closest to the active region 01 in the termination protection region 02 is significantly higher than the electric field at the bottom of the trench 4 in the active region 01, resulting in the voltage-resistant of the termination protection region 02 being lower than the voltage-resistant of the active region 01.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a semiconductor structure for optimizing the characteristics of a device and a manufacturing method thereof.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: a semiconductor structure for optimizing device characteristics, on the top plane of the semiconductor device, the semiconductor structure comprises an active region and a terminal protection region, wherein the active region is positioned on a semiconductor substrate, the active region is positioned in a central region of the semiconductor substrate, the terminal protection region is positioned on an outer ring of the active region and surrounds the active region, the semiconductor substrate comprises drain metal connected with a drain, a first conductive type silicon substrate is arranged on the drain metal, a first conductive type epitaxial layer is arranged on the first conductive type silicon substrate, a second conductive type body region is arranged on the upper surface of the first conductive type epitaxial layer, a groove is arranged in the second conductive type body region, the groove extends into the first conductive type epitaxial layer below the second conductive type body region from the surface of the second conductive type body region, the central region in the groove is filled with conductive polysilicon and a first type insulating dielectric body positioned on the outer ring of the conductive polysilicon, a gate oxide layer grows in the inner groove is filled with the gate oxide layer, and an epitaxial layer is arranged on the first conductive type insulating dielectric body; in the active region, two first conductivity type source regions are arranged in the second conductivity type body region, the first conductivity type source regions are contacted with the outer wall of the groove, source metal connected with a source is arranged above the second type insulating dielectric body, and the source metal is in ohmic contact with the first conductivity type source regions and the second conductivity type body region through holes in the second type insulating dielectric body, and the active region is characterized in that: and a first conductive type region is arranged below the groove in the active region, and the first conductive type region covers the bottom of the groove.
Further, for an N-type power semiconductor device, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type power semiconductor device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Further, the first conductivity type region is formed by implanting a first conductivity type impurity at a dose ranging from 10 12 ~10 16 The implantation energy ranges from 10keV to 200keV.
Further, the opening width and the depth of the trench in the active region may be consistent or inconsistent with the opening width and the depth of the trench in the termination protection region.
Further, in the terminal protection region, the gate conductive polysilicon in the trench may be set to be floating, may not be set to be floating, may be set to be a second conductive type body region, and may not be set.
In order to further achieve the above technical object, the present invention further provides a method for manufacturing a semiconductor structure for optimizing device characteristics, which is characterized by comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer grown on the first conductive type substrate, the upper surface of the first conductive type epitaxial layer is a first main surface, and the lower surface of the first conductive type substrate is a second main surface;
secondly, carrying out groove etching on the first main surface of the semiconductor substrate through shielding of the patterned mask layer, forming grooves in the first conductive type epitaxial layers of the active region and the terminal protection region, and removing the patterned mask layer;
injecting first conductivity type impurities into the bottom of the groove of the active region through shielding of the patterned photoresist to form a first conductivity type region, and removing the patterned photoresist;
forming insulating medium layers in the grooves and on the first main surface, wherein the insulating medium layers in the grooves form a first type insulating medium body;
depositing polysilicon in the groove formed by the first type of insulating dielectric body, and etching the polysilicon to form source electrode conductive polysilicon;
step six, etching the insulating medium layer to form an inner groove at the upper part of the groove;
step seven, thermally growing an oxide layer in the inner groove to form a gate oxide layer;
depositing polysilicon in the groove formed by the gate oxide layer, and etching the polysilicon to form gate conductive polysilicon;
step nine, implanting second conductivity type impurity ions on the first main surface of the semiconductor substrate and performing thermal annealing to form a second conductivity type body region;
step ten, selectively implanting first conductivity type impurity ions on the first main surface of the semiconductor substrate and activating the first conductivity type impurity ions, and forming a first conductivity type source region in the second conductivity type body region of the active region;
step eleven, depositing an insulating dielectric layer on the first main surface of the semiconductor substrate to form a second type insulating dielectric body, etching contact holes on the second type insulating dielectric body, and forming contact holes at the junctions of the active area and the terminal protection area;
a metal layer is deposited in the contact hole, etching and patterning are carried out on the metal layer, and source electrode metal and grid electrode metal are formed on the first main surface of the semiconductor substrate;
and thirteenth, disposing drain metal on the second main surface of the semiconductor substrate, wherein the drain metal is in ohmic contact with the first conductive type substrate.
Further, in the step twelve, the source metal is electrically contacted with the source conductive polysilicon through the contact hole, and the gate metal is electrically contacted with the gate conductive polysilicon through the contact hole.
Compared with the traditional power semiconductor device, the invention has the following advantages:
1) According to the structure, the first conductive type impurities are injected into the bottom of the groove in the active region, so that the impurity concentration of the bottom of the groove in the active region is higher than that of the terminal protection region, the electric field strength of the bottom of the groove in the active region can be obviously improved, the withstand voltage of the terminal protection region is higher than that of the active region, and breakdown occurs at the bottom of the groove in the active region when the device is withstand voltage;
2) According to the invention, the doping concentration of the first conductive type epitaxial layer is improved by injecting the first conductive type impurity into the bottom of the active region trench, so that the on-resistance of the device can be reduced;
3) The device manufacturing method is compatible with the existing semiconductor technology, has low manufacturing cost and wide application range, and is safe and reliable.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench formed according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a first conductivity type region formed according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional structure of a first type of insulating dielectric body according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of forming source conductive polysilicon according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of an embodiment of the present invention for forming an inner trench.
Fig. 6 is a schematic cross-sectional view of a thermally grown gate oxide layer according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of forming a gate conductive polysilicon according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of a second conductivity type body region formed according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional structure of forming a first conductivity type source region according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of forming gate metal and source metal according to an embodiment of the invention.
Fig. 11 is a schematic cross-sectional view of a drain metal formed according to an embodiment of the invention.
Fig. 12 is a schematic cross-sectional structure of an active region and a terminal protection region of a conventional structure.
Reference numerals illustrate: 01-an active region; 02—a terminal protection area; 1-drain metal; 2-a first conductivity type silicon substrate; 3-an epitaxial layer of the first conductivity type; 4-grooves; 5-a first type of insulating dielectric body; 6-source conductive polysilicon; 7-an inner trench; 8-gate oxide; 9-gate conductive polysilicon; 10-a body region of a second conductivity type; 11-a source region of a first conductivity type; 12-a second type of insulating dielectric body; 13-source metal; 14-regions of the first conductivity type.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
As shown in fig. 10, a semiconductor structure for optimizing the device characteristics is taken as an example of an N-type deep trench power semiconductor device, on the top plane of the semiconductor device, the semiconductor structure comprises an active region 01 and a terminal protection region 02 which are positioned on a semiconductor substrate, the active region 01 is positioned in the central region of the semiconductor substrate, the terminal protection region 02 is positioned on the outer ring of the active region and surrounds the active region 01, the semiconductor substrate comprises a drain metal 1 connected with a drain electrode, an N-type silicon substrate 2 is arranged on the drain metal 1, an N-type epitaxial layer 3 is arranged on the N-type silicon substrate 2, a P-type body region 10 is arranged on the upper surface of the N-type epitaxial layer 3, a trench 4 is arranged in the P-type epitaxial layer 10, the trench 4 extends into the N-type epitaxial layer 3 below the P-type body region 10 from the surface of the P-type body region 10, the central region in the trench 4 is filled with conductive polysilicon 6 and a first type insulator 5 positioned on the outer ring of the polysilicon 6, inner trench 7 is arranged on two sides of the upper part of the conductive polysilicon 6, a gate oxide layer 8 is grown in the inner trench 7, and a gate oxide layer 12 is grown in the gate oxide layer 8 is arranged on the inner trench layer 12; in the active region 01, two N-type source regions 11 are disposed in the P-type body region 10, the N-type source regions 11 are in contact with the outer wall of the trench 4, a source metal 13 connected with a source is disposed above the second type insulating dielectric body 12, and the source metal 13 is connected with the N-type source regions 11 and the P-type body regions through the through holes on the second type insulating dielectric body 1210 ohmic contact, characterized by: in the active region 01, an N-type region 14 is arranged below the trench 4, the N-type region 14 covers the bottom of the trench 4, the N-type region 14 is formed by N-type impurity implantation, and the implantation dosage range of the N-type impurity is 10 12 ~10 16 The implantation energy ranges from 10keV to 200keV.
In the embodiment of the invention, the opening width and the depth of the groove 4 in the active region 01 are consistent with the opening width and the depth of the groove 4 in the terminal protection region 02.
In the embodiment of the present invention, in the termination protection region 02, the gate conductive polysilicon 9 in the trench 4 is provided to be floating and a P-type body region 10 is provided.
The power semiconductor device structure of the above embodiment can be manufactured by the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type substrate 2 and a first conductive type epitaxial layer 3 grown on the first conductive type substrate 2, the upper surface of the first conductive type epitaxial layer 3 is a first main surface 001, and the lower surface of the first conductive type substrate 2 is a second main surface 002;
step two, as shown in fig. 1, trench etching is performed on the first main surface 001 of the semiconductor substrate by shielding the patterned mask layer, a trench 4 is formed in the first conductive type epitaxial layer 3 of the active region 01 and the terminal protection region 02, and the patterned mask layer is removed;
step three, as shown in fig. 2, implanting first conductivity type impurities into the bottom of the trench 4 of the active region 01 through the shielding of the patterned photoresist to form a first conductivity type region 14, and removing the patterned photoresist;
step four, as shown in fig. 3, forming an insulating dielectric layer in the trench 4 and on the first main surface 001, wherein the insulating dielectric layer in the trench 4 forms a first type insulating dielectric body 5;
step five, as shown in fig. 4, depositing polysilicon in the grooves formed by the first type insulating dielectric body 5, and etching the polysilicon to form source electrode conductive polysilicon 6;
step six, etching the insulating dielectric layer to form an inner trench 7 at the upper part of the trench 4 as shown in fig. 5;
step seven, as shown in fig. 6, thermally growing an oxide layer in the inner trench 7 to form a gate oxide layer 8;
step eight, as shown in fig. 7, depositing polysilicon in the grooves formed by the gate oxide layer 8, and etching the polysilicon to form gate conductive polysilicon 9;
in the embodiment of the invention, an insulating gate oxide layer is firstly grown in the inner groove 7, and gate conductive polysilicon 6 is filled in the groove after the insulating gate oxide layer is grown, and insulating isolation is carried out between the gate conductive polysilicon 6 and the source conductive polysilicon 6 through the gate oxide layer 8 and the first type insulating dielectric body 5;
as shown in fig. 8, step nine, implanting second conductivity type impurity ions on a first main surface 001 of a semiconductor substrate and thermally annealing to form a second conductivity type body region 10;
as shown in fig. 9, step ten, first conductivity type impurity ions are selectively implanted and activated on the first main surface 001 of the semiconductor substrate, forming a first conductivity type source region 11 in the second conductivity type body region 10 of the active region 100;
as shown in fig. 10, step eleven, an insulating dielectric layer is deposited on a first main surface 001 of a semiconductor substrate to form a second type insulating dielectric body 12, contact hole etching is performed on the second type insulating dielectric body 12, and contact holes are formed at the junctions of an active region 01 and a terminal protection region 02;
the second type of insulating dielectric body 12 may be a silicon dioxide layer, and the insulating dielectric layer covers the first main surface 001 of the semiconductor substrate, and the process of depositing the insulating dielectric layer and the process of etching the contact hole of the insulating dielectric layer are well known in the art and will not be described herein.
A metal layer is deposited in the contact hole, etching and patterning are carried out on the metal layer, and source electrode metal 13 and grid electrode metal are formed on the first main surface 001 of the semiconductor substrate;
the front metal layer is supported on the second type insulating dielectric body 12, after patterning the front metal layer, source metal 13 and grid metal are respectively obtained, the source metal 13 is positioned in the active region 01, the source metal 13 is electrically contacted with the source conductive polysilicon 6 through a contact hole, and the grid metal is electrically contacted with the grid conductive polysilicon 9 through the contact hole;
the source metal 11 can be in ohmic contact with the P-type first well region 8, the N-type source region 9 and the first type conductor 5 through the contact hole of the active region 100, and the gate metal is electrically connected with the gate conductive polysilicon 6 in the active region 100, so that the cells in the active region 100 can be connected in parallel into a whole. The gate metal is not shown in fig. 10, and the specific connection is well known to those skilled in the art, and will not be described here.
As shown in fig. 11, step thirteenth, a drain metal 1 is provided on the second main face 002 of the semiconductor substrate, the drain metal 1 being in ohmic contact with the first conductivity type substrate 2.
The working principle of the invention is as follows:
when the device is voltage-resistant, the drain metal 1 is connected with high voltage, the gate metal and the source metal 13 are connected with low voltage, and as the impurity of the first conductivity type is injected into the bottom of the groove 4 of the active region 01, the impurity concentration of the bottom of the groove 4 of the active region 01 is higher than that of the bottom of the groove 4 of the terminal protection region 02, so that the electric field intensity at the bottom of the groove 4 of the active region 01 is stronger than that at the bottom of the groove 4 of the terminal protection region 02, and the breakdown position of the device is in the active region 01;
when the device is conducted, the gate metal is connected with high potential, the device is started, and when current flows through the bottom of the groove 4 of the active region 01, the impurity of the first conductivity type is injected into the bottom of the groove 4 of the active region 01, so that the impurity concentration is higher, the resistivity is smaller, the on-resistance of the device is reduced, and the loss power consumption is smaller.
The invention and its embodiments have been described above with no limitation, and the actual construction is not limited to the embodiments of the invention as shown in the drawings. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution should not be creatively devised without departing from the gist of the present invention.
Claims (7)
1. A semiconductor structure for optimizing device characteristics comprises a semiconductor device, wherein the semiconductor device comprises an active region (01) and a terminal protection region (02) which are arranged on a semiconductor substrate, the active region (01) is arranged in the central region of the semiconductor substrate, the terminal protection region (02) is arranged on the outer ring of the active region and surrounds the active region (01), the semiconductor substrate comprises a drain metal (1) connected with a drain, a first conductive type silicon substrate (2) is arranged on the drain metal (1), a first conductive type epitaxial layer (3) is arranged on the first conductive type silicon substrate (2), a second conductive type epitaxial layer (10) is arranged on the upper surface of the first conductive type epitaxial layer (3), a groove (4) is arranged in the second conductive type epitaxial layer (10), the groove (4) extends into the first conductive type epitaxial layer (3) below the second conductive type epitaxial layer (10) from the surface of the second conductive type epitaxial layer (10), the central region in the groove (4) is filled with silicon (6) and polycrystalline silicon (7) is arranged on the inner sides of the polycrystalline silicon (7) in the polycrystalline silicon (7), a grid conductive polysilicon (9) is filled in the inner groove (7) growing with the grid oxide layer (8), and a second type insulating dielectric body (12) is arranged above the first conductivity type epitaxial layer (3); in the active region (01), two first conductivity type source regions (11) are arranged in the second conductivity type body region (10), the first conductivity type source regions (11) are in contact with the outer wall of the groove (4), source metal (13) connected with a source is arranged above the second type insulating dielectric body (12), and the source metal (13) is in ohmic contact with the first conductivity type source regions (11) and the second conductivity type body region (10) through holes in the second type insulating dielectric body (12), and the active region is characterized in that: in the active region (01), a first conductive type region (14) is arranged below the groove (4), and the first conductive type region (14) covers the bottom of the groove (4).
2. A semiconductor structure for optimizing device characteristics as defined in claim 1, wherein: for an N-type power semiconductor device, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity; for a P-type power semiconductor device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
3. A semiconductor structure for optimizing device characteristics as defined in claim 1, wherein: the first conductivity type region (14) is formed by first conductivity type impurity implantation, and the implantation energy of the first conductivity type impurity ranges from 10keV to 200keV.
4. A semiconductor structure for optimizing device characteristics as defined in claim 1, wherein: the opening width and the depth of the groove (4) in the active region (01) are consistent with those of the groove (4) in the terminal protection region (02).
5. A semiconductor structure for optimizing device characteristics as defined in claim 1, wherein: in the termination protection region (02), the gate conductive polysilicon (9) in the trench (4) is set to float, and a second conductivity type body region (10) is set.
6. A method of fabricating a semiconductor structure that optimizes device characteristics, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type substrate (2) and a first conductive type epitaxial layer (3) grown on the first conductive type substrate (2), the upper surface of the first conductive type epitaxial layer (3) is a first main surface (001), and the lower surface of the first conductive type substrate (2) is a second main surface (002);
secondly, carrying out groove etching on a first main surface (001) of the semiconductor substrate through shielding of the patterned mask layer, forming a groove (4) in the first conductive type epitaxial layer (3) of the active region (01) and the terminal protection region (02), and removing the patterned mask layer;
injecting first conductivity type impurities into the bottom of the groove (4) of the active region (01) through shielding of the patterned photoresist to form a first conductivity type region (14), and removing the patterned photoresist;
forming an insulating medium layer in the groove (4) and on the first main surface (001), wherein the insulating medium layer in the groove (4) forms a first type insulating medium body (5);
depositing polysilicon in the groove formed by the first type insulating dielectric body (5), and etching the polysilicon to form source electrode conductive polysilicon (6);
step six, etching the insulating medium layer, and forming an inner groove (7) at the upper part of the groove (4);
step seven, thermally growing an oxide layer in the inner groove (7) to form a gate oxide layer (8);
depositing polysilicon in the groove formed by the gate oxide layer (8), and etching the polysilicon to form gate conductive polysilicon (9);
step nine, implanting second conductivity type impurity ions on a first main surface (001) of the semiconductor substrate and performing thermal annealing to form a second conductivity type body region (10);
step ten, selectively implanting first conductivity type impurity ions on a first main surface (001) of the semiconductor substrate and activating, and forming a first conductivity type source region (11) in a second conductivity type body region (10) of the active region;
step eleven, depositing an insulating dielectric layer on a first main surface (001) of the semiconductor substrate to form a second type insulating dielectric body (12), etching contact holes on the second type insulating dielectric body (12), and forming contact holes at the junction of the active region (01) and the terminal protection region (02);
a metal layer is deposited in the contact hole, etching and patterning are carried out on the metal layer, and source electrode metal (13) and grid electrode metal are formed on the first main surface (001) of the semiconductor substrate;
and thirteenth step, disposing a drain metal (1) on the second main surface (002) of the semiconductor substrate, wherein the drain metal (1) is in ohmic contact with the first conductive type substrate (2).
7. A method of manufacturing a semiconductor structure for optimizing device characteristics according to claim 6, wherein in said step twelve, the source metal (13) is in electrical contact with the source conductive polysilicon (6) through the contact hole and the gate metal is in electrical contact with the gate conductive polysilicon (9) through the contact hole.
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| CN114613667B (en) * | 2022-05-16 | 2022-08-26 | 广州粤芯半导体技术有限公司 | Preparation method of semiconductor structure |
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