CN114068331B - SGT terminal structure for improving BV stability and preparation method thereof - Google Patents
SGT terminal structure for improving BV stability and preparation method thereof Download PDFInfo
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- CN114068331B CN114068331B CN202210030400.1A CN202210030400A CN114068331B CN 114068331 B CN114068331 B CN 114068331B CN 202210030400 A CN202210030400 A CN 202210030400A CN 114068331 B CN114068331 B CN 114068331B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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Abstract
The invention discloses an SGT terminal structure for improving BV stability and a preparation method thereof. The method comprises the steps of depositing and forming polycrystalline silicon of a second conduction type on the upper side of a gate oxide layer, then carrying out etching operation on the polycrystalline silicon, and carrying out first conduction type element injection and annealing operation on the inner end portions of the polycrystalline silicon reserved in the body area and on the upper side of the gate oxide layer through etching to manufacture a first well region arranged in the body area of an active area, a second well region arranged at the outer end of the body area of a terminal area, a diode and a resistor arranged on the upper side of the gate oxide layer, wherein the outer end of the diode is connected with the inner end of the resistor. According to the invention, by increasing the bias voltage in the terminal trench, the defect density of oxide layer interface holes during avalanche breakdown is reduced, so that the problems of BV walk-in and walk-out are effectively improved, the BV stability is improved, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SGT terminal structure for improving BV stability and a preparation method thereof.
Background
A conventional SGT termination structure is shown in fig. 1, a combination of floating and grounding is adopted in a trench of a termination region in the structure, and in a process of applying a reverse bias voltage to a device, a polysilicon electrode in the trench acts as a field plate, so that a depletion line is more easily expanded outwards.
As shown in fig. 2, the voltage withstanding level of the conventional SGT termination structure is limited by the thickness of the trench oxide layer and the trench morphology, and the trench oxide layer is completely depleted at a position far from the stop ring, so that the depletion line cannot be expanded continuously, and the voltage withstanding cannot be improved continuously.
Meanwhile, when the device is subjected to avalanche breakdown, the oxide layer on the side wall of the trench is easy to form a hole defect, so that the BVDSS of the device has the problem of walk-in (BV reduction) or walk-out (BV increase), BV instability is caused, and the reliability of the device is influenced.
In addition, some free metal ions and trap charges exist in the silicon surface dielectric layer, which has certain influence on the breakdown voltage and reliability of the device.
Disclosure of Invention
The invention aims to provide an SGT terminal structure for improving BV stability and a preparation method thereof aiming at the defects in the prior art.
To achieve the above object, in a first aspect, the present invention provides a method for manufacturing an SGT termination structure that improves BV stability, comprising:
providing a first conductive type substrate, and manufacturing an epitaxial layer on the upper side of the substrate;
etching to form a plurality of grooves on the epitaxial layer;
growing a field oxide layer on the upper side of the epitaxial layer and the inner side of the groove;
respectively manufacturing and forming a first conductive type shield grid polycrystalline silicon and a polycrystalline silicon field plate in the grooves in the active region and the terminal region;
manufacturing a first oxide layer in the grooves on the upper sides of the shield grid polycrystalline silicon and the polycrystalline silicon field plate, and etching the first oxide layer on the upper side of the shield grid polycrystalline silicon to form an isolation oxide layer;
growing a gate oxide layer in the groove on the upper side of the isolation oxide layer and on the upper side of the epitaxial layer;
manufacturing a control gate polysilicon of a first conductive type in the trench on the inner side of the gate oxide layer, and manufacturing and forming a second oxide layer on the upper side of the control gate polysilicon;
manufacturing a body region of a second conduction type on the epitaxial layer;
depositing and forming polycrystalline silicon of a second conductive type on the upper side of the gate oxide layer, then carrying out etching operation on the polycrystalline silicon, and carrying out first conductive type element injection and annealing operation on the inner end part of the polycrystalline silicon reserved in the body region and etching to manufacture and form a first well region arranged in the body region of the active region, a second well region arranged at the outer end of the body region of the terminal region, a diode and a resistor arranged on the upper side of the gate oxide layer, wherein the outer end of the diode is connected with the inner end of the resistor;
depositing to form a first dielectric layer, and etching the first dielectric layer to form a first connecting hole;
sputtering a first metal layer on the upper side of the first dielectric layer and in the first connecting hole, and etching the first metal layer to form a first source electrode metal connected with the first well region, a capacitor field plate metal respectively connected with the polysilicon field plate and the inner end of the diode, a stop ring metal respectively connected with the outer end of the resistor, the polysilicon field plate and the second well region, and a gate metal;
depositing to form a second dielectric layer, etching to form a second connecting hole on the second dielectric layer, sputtering to form a second metal layer on the upper side of the second dielectric layer and in the second connecting hole, etching to form a second source electrode metal connected with the first source electrode metal, and extending the second source electrode metal outwards to the upper side of the capacitor field plate metal to form a capacitor structure in cooperation with the capacitor field plate metal.
Furthermore, a vacant region is formed in the epitaxial layer between two adjacent trenches in the terminal region, and the diode and the resistor are arranged on the upper side of the vacant region.
Further, the element implanted into the body region and the inner end part of the polysilicon remained by etching is arsenic element, and the implantation dosage is 5E15-1E16atom/cm2The implantation energy was 60KeV, the annealing temperature was 950 ℃ and the annealing time was 60 min.
Further, depositing a passivation layer on the upper sides of the second source metal and the second dielectric layer, and etching the passivation layer to form opening regions of the source and the grid.
Further, a back gold layer is formed on the lower side of the substrate.
In a second aspect, the invention provides an SGT terminal structure for improving BV stability, which comprises a first conductive type substrate and an epitaxial layer arranged on the upper side of the substrate, wherein a plurality of trenches are arranged on the epitaxial layer, a field oxide layer is arranged on the inner side of each trench, a shielded gate polysilicon and a polysilicon field plate of the first conductive type are respectively manufactured and formed in the trenches in an active region and a terminal region, an isolation oxide layer and a first oxide layer are respectively arranged in the trenches on the upper sides of the shielded gate polysilicon and the polysilicon field plate, a gate oxide layer is arranged in the trench on the upper side of the isolation oxide layer, a control gate polysilicon of the first conductive type is arranged in the trench on the inner side of the gate oxide layer, a second oxide layer is arranged on the upper side of the control gate polysilicon, a body region of the second conductive type is arranged on the epitaxial layer, a first well region is arranged in the body region of the active region, and a second well region is arranged at the outer end of the body region of the terminal region, the diode comprises a diode and a resistor on the upper side of a gate oxide layer, the outer end of the diode is connected with the inner end of the resistor, a first dielectric layer is arranged on the upper sides of the gate oxide layer, the diode and the resistor, a first connecting hole is arranged on the first dielectric layer, first source electrode metal connected with a well region in a source region, capacitor field plate metal connected with a polysilicon field plate and the inner end of the diode, stop ring metal connected with the outer end of the resistor, the polysilicon field plate and a second well region and gate metal are arranged on the upper side of the dielectric layer, a second connecting hole is arranged on the second dielectric layer, second source electrode metal connected with the first source electrode metal is arranged on the upper side of the second dielectric layer, and the second source electrode metal extends outwards to the upper side of the capacitor field plate metal, so as to form a capacitor structure by matching with the capacitor field plate metal.
Furthermore, a vacant region is formed between two adjacent trenches in the terminal region, and the diode and the resistor are arranged on the upper side of the vacant region.
Further, depositing a passivation layer on the upper sides of the second source metal and the second dielectric layer, and etching the passivation layer to form opening regions of the source and the grid.
Further, a back gold layer is formed on the lower side of the substrate.
Further, the resistor is arranged in a surrounding mode.
Has the advantages that: compared with the prior art, the invention has the following advantages:
1) according to the invention, the resistor, the diode and the capacitor structure are manufactured in the terminal area, when a forward voltage is applied to the drain electrode of the device, the voltage sequentially passes through the winding and the diode to charge the capacitor, and meanwhile, the metal of the capacitor field plate is connected with the polysilicon field plate in the terminal groove, so that the polysilicon field plate in the groove and the metal of the capacitor field plate are in the same potential, a forward bias voltage is applied to the polysilicon field plate in the terminal groove, the defect density of oxide layer interface cavities during avalanche breakdown is reduced, the problems of BV walk-in and walk-out are effectively improved, the BV stability is improved, and the reliability of the device is improved; from the simulation pull bias result, the bias voltage in the trench is between 6V and 17V, and the BVDSS of the device is relatively stable;
2) because the forward bias voltage exists in the terminal groove, the electric field distribution of the terminal area can be adjusted, so that the depletion line can extend transversely, the voltage resistance of the device is improved, and meanwhile, the avalanche breakdown point moves from the terminal to the active area, so that the high-temperature stability is better;
3) compared with the traditional SGT terminal structure, the invention can obviously improve the electric field distribution, and the terminal groove bears more voltage, thereby improving the voltage withstanding level of the device; meanwhile, the electric field intensity near the periphery of the terminal area is higher by the electric field distribution vertical to the bottom of the groove;
4) parallel plate capacitors and polysilicon diodes are integrated in the terminal structure, and the breakdown voltage of the device is improved by applying the potential of a stop ring to a terminal groove;
5) the second layer of metal induces negative charges when the second layer of metal is resistant to voltage, so that free charges in the dielectric layer, such as sodium ions and the like, can be effectively adsorbed, the effect of shielding the charges is achieved, and the reliability of the device is improved;
6) the process is simple in implementation process, is compatible with the existing process, realizes integration of the power device and the self-bias structure on the premise of not increasing the processing cost obviously, and effectively improves the BV stability and reliability of the device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional SGT terminal structure;
fig. 2 is a simulation structure diagram of a conventional SGT terminal structure;
FIG. 3 is a schematic diagram of a structure after an epitaxial layer is fabricated on a substrate;
FIG. 4 is a schematic diagram of the structure after trenches have been etched in the epitaxial layer;
FIG. 5 is a schematic diagram of the structure after a field oxide layer is grown in the trench and on the upper side of the epitaxial layer;
FIG. 6 is a schematic structural diagram of a structure after a shield gate polysilicon and a polysilicon field plate are manufactured in a trench;
FIG. 7 is a schematic diagram of the structure after etching the first oxide layer;
FIG. 8 is a schematic diagram of the structure after growing a gate oxide layer;
fig. 9 is a schematic structural diagram of the control gate polysilicon and the second oxide layer after being manufactured in the trench of the active region;
figure 10 is a schematic diagram of the structure after body regions have been formed in the epitaxial layer;
FIG. 11 is a schematic structural diagram of the first well region, the second well region, the diode and the resistor after being fabricated;
fig. 12 is a schematic structural diagram after a first connection hole is etched in the first dielectric layer;
FIG. 13 is a schematic diagram of the structure after etching the first metal layer;
fig. 14 is a schematic cross-sectional structure diagram of an SGT terminal structure for improving BV stability according to an embodiment of the present invention;
fig. 15 is a schematic top view of an SGT termination structure for improving BV stability according to an embodiment of the present invention;
fig. 16 is a simulation structure diagram of an SGT terminal structure for improving BV stability according to an embodiment of the present invention;
FIG. 17 is a comparison of simulated electric field distribution of an SGT termination structure for improving BV stability with an existing SGT termination structure;
fig. 18 is a graph of the variation trend of the bias voltage and BV of the SGT termination structure for improving BV stability.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 3 to 15, an embodiment of the present invention provides a method for manufacturing an SGT termination structure that improves BV stability, including:
referring to fig. 3, a first conductivity type substrate 1 is provided, and an epitaxial layer 2 is formed on the upper side of the substrate 1. The technical scheme of the invention is described by taking the first conductive type as an N type and the second conductive type as a P type as an example. The substrate 1 is typically doped with arsenic or phosphorus, and the epitaxial layer 2 is typically 3-15um thick and has a resistivity of 0.1-1 Ω.
Referring to fig. 4, a plurality of trenches 3 are etched in the epitaxial layer 2. Specifically, a SiO2/SiN/SiO2 layer structure can be deposited on the upper side of the epitaxial layer 2, the total thickness is about 4000 angstroms, the thickness can be finely adjusted according to the groove etching morphology, and then groove photoetching and etching are sequentially carried out to form the structure of the groove 3. The depth of the groove 3 is 0.6-5um, the width of the groove is 0.2-1.2um, and the inclination angle of the side wall is 88-89 degrees.
Referring to fig. 5, a field oxide layer 4 is grown on the upper side of the epitaxial layer 2 and inside the trench. The field oxide layer 4 may be formed by dry-wet-dry oxidation and CVD methods, and the thickness of the field oxide layer is 3500-7000 angstroms.
Referring to fig. 6, N-type shield gate polysilicon 5 and polysilicon field plate 6 are formed in trenches 3 in the active and termination regions, respectively. Specifically, polysilicon doped with N-type element is deposited in the trench 3, and the doping concentration of the polysilicon is 1E19-6E19atom/cm2And the doping element is phosphorus, and then the polysilicon in the trenches 3 in the active region and the terminal region is respectively subjected to photoetching and etching operations, so that the N-type shielding gate polysilicon 5 and the polysilicon field plate 6 are formed.
Referring to fig. 7, a first oxide layer 7 is formed in the trench 3 on the upper side of the shield gate polysilicon 5 and the polysilicon field plate 6, wherein the first oxide layer 7 on the upper side of the shield gate polysilicon 5 is etched to form an isolation oxide layer 8. The thickness of the isolation oxide layer 8 is 5000-10000 angstroms.
Referring to fig. 8, a gate oxide layer 9 is grown in the trench 3 on the upper side of the isolation oxide layer 8 and on the upper side of the epitaxial layer 2. Specifically, the thickness of the gate oxide layer 9 is 500-1000 angstroms, the growth temperature is 950-1050 ℃, and the thicker the thickness of the gate oxide layer 9, the higher the temperature is required for growth. Before growing the gate oxide layer 9, a sacrificial oxide layer can be grown in the trench 3, the sacrificial oxide layer is formed by dry oxidation, the growth oxidation temperature of the sacrificial oxide layer is 1000-1100 ℃, and then a part of the sacrificial oxide layer can be removed by wet rinsing.
Referring to fig. 9, an N-type control gate polysilicon 10 is formed in the trench 3 inside the gate oxide 9, and a second oxide layer 11 is formed on the upper side of the control gate polysilicon 10. The control gate polysilicon 10 is also formed by doped poly deposition, lithography and etching with a doping concentration of 1E19-6E19atom/cm2The doping element is phosphorus. It should be noted that the control gate polysilicon 10 is preferably not formed in the trench 3 in the active region closest to the termination region.
Referring to fig. 10, a body region 12 of P-type is fabricated on the epitaxial layer 2. Specifically, the body region 12 is formed by a body implantation operation and a body annealing operation, wherein the body implantation operation implants boron, the implantation energy is 60KEV-120Kev, and the implantation dose is adjusted according to the VTH parameter requirement, generally 5E12-1.8E13atom/cm2About, the temperature of the body region annealing operation is 1100 ℃, and the time is 60 min.
Referring to fig. 11 and fig. 15, P-type polysilicon is deposited on the upper side of the gate oxide layer 9, then the polysilicon is etched, N-type element implantation and annealing operations are performed on the body region 12 to produce a first well region 13 arranged in the body region 12 of the active region and a second well region 14 arranged at the outer end of the body region 12 of the terminal region, when the N-type element implantation is performed on the body region 12, the N-type element is also synchronously implanted into the inner end of the polysilicon remained after the etching operation, so that the polysilicon remained after the etching is produced to form a diode 15 and a resistor 16 arranged on the upper side of the gate oxide layer 9, the resistor 16 is arranged in a surrounding manner, and the outer end of the diode 15 is connected with the inner end of the resistor 16. The N element implanted in the step is preferably arsenic element, the implantation energy is 60KeV, the annealing temperature is 950 ℃, and the annealing time is 60 min.
Referring to fig. 12, a first dielectric layer 17 is deposited on the upper side of the gate oxide layer 9, the diode 15 and the resistor 16, and a first connection hole 18 is etched on the first dielectric layer 17. After the first connection holes 18 are formed, a hole implantation and annealing operation may be performed on the first connection holes 18 to reduce contact resistance. Specifically, the hole implantation is carried out in two times, the elements implanted in the two times are boron difluoride and boron respectively, and the implantation dosage is 2E14-5E14atom/cm2The implantation energy is 30-40KeV, and then rapid annealing is carried out, the annealing temperature is 950 ℃, and the annealing time is 30 s. The first contact hole 18 may also be deposited with titanium/titanium nitride and then filled with tungsten metal and etched back to form an ohmic contact hole.
Referring to fig. 13 and 15, a first metal layer is formed on the upper side of the first dielectric layer 17 and in the first connection hole 18 by sputtering, and the first metal layer is etched to form a first source metal 19 connected to the first well region 13, a capacitor field plate metal 20 connected to the polysilicon field plate 6 and the inner end of the diode 15, a stop ring metal 21 connected to the outer end of the resistor 16, the polysilicon field plate 6 and the second well region 14, and a gate metal 26.
Referring to fig. 14 and 15, a second dielectric layer 22 is deposited on the first source metal 19, the capacitor field plate metal 20, the stop ring metal 21, the gate metal 26 and the exposed upper side of the first dielectric layer 17, a second connection hole 23 is etched on the second dielectric layer 22, a second metal layer is sputtered on the upper side of the second dielectric layer 22 and in the second connection hole 23, the second metal layer is etched to form a second source metal 24 connected with the first source metal 19, and the second source metal 24 extends outward to the upper side of the capacitor field plate metal 20 to form a capacitor structure in cooperation with the capacitor field plate metal 20. The first metal layer and the second metal layer are preferably 4um aluminum layers, and the aluminum can be doped with Cu in a certain proportion to prevent aluminum and silicon from being mutually soluble.
A vacant region 25 is formed in the epitaxial layer 2 between two adjacent trenches 3 in the termination region, and the diode 15 and the resistor 16 are disposed on the upper side of the vacant region 25.
A passivation layer may also be deposited on the upper side of the second source metal 24 and the second dielectric layer 22 and the opening regions for the source and gate electrodes are etched on the passivation layer. The passivation layer is preferably a silicon nitride passivation layer, and the thickness of the passivation layer is 7000-12000 angstroms, so that the passivation layer can reduce device leakage caused by mobile ions on the surface of the chip. And a back gold layer can be formed on the lower side of the substrate 1, before the back gold layer is formed, the device can be thinned from the lower side of the substrate 1 to the residual thickness of about 150um, and then Ti-Ni-Ag (titanium-nickel-silver) is sequentially evaporated to form the back gold layer.
Referring to fig. 3 to 15, based on the above embodiments, it can be easily understood by those skilled in the art that the present invention also provides an SGT termination structure for improving BV stability, which includes a first conductive type substrate 1 and an epitaxial layer 2 disposed on the upper side of the substrate 1. The technical scheme of the invention is described by taking the first conductive type as an N type and the second conductive type as a P type as an example. The substrate 1 is typically doped with arsenic or phosphorus, and the epitaxial layer 2 is typically 3-15um thick and has a resistivity of 0.1-1 Ω.
A plurality of grooves 3 are arranged on the epitaxial layer, the depth of each groove 3 is 0.6-5um, the width of each groove is 0.2-1.2um, and the inclination angle of the side wall of each groove is 88-89 degrees. A field oxide layer 4 is provided on the inner side of the trench 3, the field oxide layer 4 can be formed by dry-wet-dry oxidation and CVD methods, and the thickness of the field oxide layer is 3500-7000 angstroms.
N-type shielding grid polycrystalline silicon 5 and a polycrystalline silicon field plate 6 are respectively manufactured and formed in a groove 3 in an active region and a terminal region, an isolation oxide layer 8 and a first oxide layer 7 are respectively arranged in the groove 3 on the upper sides of the shielding grid polycrystalline silicon 5 and the polycrystalline silicon field plate 6, a gate oxide layer 9 is arranged in the groove 3 on the upper side of the isolation oxide layer 8 and on the upper side of an epitaxial layer 2, N-type control grid polycrystalline silicon 10 is arranged in the groove 3 on the inner side of the gate oxide layer 9, and a second oxide layer 11 is arranged on the upper side of the control grid polycrystalline silicon 10.
The epitaxial layer 2 is provided with a body region 12 of a second conduction type, a first well region 13 is arranged in the body region 12 of the active region, a second well region 14 is arranged at the outer end of the body region 12 of the terminal region, the first well region 13 and the second well region 14 are both of an N type, a diode 15 and a resistor 16 are arranged on the upper side of the gate oxide layer 9 of the terminal region, and the outer end of the diode 15 is connected with the inner end of the resistor 16. During manufacturing, P-type polycrystalline silicon is deposited and formed on the upper side of the gate oxide layer 9, then etching operation is performed on the polycrystalline silicon at the position, N-type element injection and annealing operation are performed on the body region 12, so that a first well region 13 arranged in the body region 12 of the active region and a second well region 14 arranged at the outer end of the body region 12 of the terminal region are manufactured and formed, when the N-type element injection is performed on the body region 12, N-type elements are synchronously injected into the inner end of the polycrystalline silicon reserved through the etching operation, and therefore the polycrystalline silicon reserved after etching is manufactured and formed into a diode 15 and a resistor 16 arranged on the upper side of the gate oxide layer 9. Wherein, the resistor 16 is arranged in a surrounding way, and the outer end of the diode 15 is connected with the inner end of the resistor 16. The N element implanted in the step is preferably arsenic element, the implantation energy is 60KeV, the annealing temperature is 950 ℃, and the annealing time is 60 min.
A first dielectric layer 17 is arranged on the upper side of the gate oxide layer 9, the diode 15 and the resistor 16, and a first connection hole 18 is arranged on the first dielectric layer 17. After the first connection holes 18 are formed, a hole implantation and annealing operation may be performed on the first connection holes 18 to reduce contact resistance. Specifically, the hole implantation is carried out in two times, the elements implanted in the two times are boron difluoride and boron respectively, and the implantation dosage is 2E14-5E14atom/cm2The implantation energy is 30-40KeV, and then rapid annealing is carried out, the annealing temperature is 950 ℃, and the annealing time is 30 s. The first contact hole 18 may also be deposited with titanium/titanium nitride and then filled with tungsten metal and etched back to form an ohmic contact hole.
On the upper side of the dielectric layer 17, there are a first source metal 19 connected to the first well region 13, a capacitor field plate metal 20 connected to the polysilicon field plate 6 and the inner end of the diode 15, respectively, a stop ring metal 21 connected to the outer end of the resistor 16, the polysilicon field plate 6 and the second well region 14, and a gate metal 26. The upper sides of the first source electrode metal 19, the capacitor field plate metal 20, the stop ring metal 21 and the gate electrode metal 26 and the upper side of the second dielectric layer 22 of the first dielectric layer 17 between the first source electrode metal and the gate electrode metal are respectively provided with a second connecting hole 23 on the second dielectric layer 22, the upper side of the second dielectric layer 22 is provided with a second source electrode metal 24 connected with the first source electrode metal 19, and the second source electrode metal 24 extends outwards to the upper side of the capacitor field plate metal 20 so that the second source electrode metal 24 and the capacitor field plate metal 20 are matched to form a capacitor structure.
A vacant region 25 is formed between adjacent two trenches 3 in the termination region, and the diode 15 and the resistor 16 are disposed on the upper side of the vacant region 25.
A passivation layer may also be deposited on the upper side of the second source metal 24 and the second dielectric layer 22 and the opening regions for the source and gate electrodes are etched on the passivation layer. The passivation layer is preferably a silicon nitride passivation layer, and the thickness of the passivation layer is 7000-12000 angstroms, so that the passivation layer can reduce device leakage caused by mobile ions on the surface of the chip. And a back gold layer can be formed on the lower side of the substrate 1, before the back gold layer is formed, the device can be thinned from the lower side of the substrate 1 to the residual thickness of about 150um, and then Ti-Ni-Ag (titanium-nickel-silver) is sequentially evaporated to form the back gold layer.
The working principle is as follows: according to the invention, through a bias structure formed by the resistor 16, the diode 15 and the capacitor structure, when a reverse bias voltage is applied to a device, a high potential is generated on the stop ring metal 21, after voltage is divided by the resistor 16 and the diode 15, a parallel plate capacitor formed by the capacitor field plate metal 20 and the second source electrode metal 24 is charged, when the reverse bias voltage is reduced, the voltage on the capacitor field plate metal 20 can be kept stable and unchanged due to the reverse clamping action of the diode 15, and therefore, a stable voltage is provided for the polysilicon field plate in the trench 3 of the terminal region. Since the potential at the position of the stop ring metal 21 is large, the voltage applied to the termination region trench 3 is reduced by the resistor 16. The resistance of the resistor 16 can be adjusted linearly by the implantation dose, and different voltage division functions can be realized, so that the resistor is applied to devices with different voltage withstanding levels. The capacitor field plate metal 20 and the second source electrode metal 24 form a parallel plate capacitor, when the device is resistant to voltage, the capacitor field plate metal 20 induces positive charges, and the second source electrode metal 24 is connected with the source electrode to provide negative charges so as to keep the potential difference in the capacitor stable. The capacitance of the capacitor can be adjusted according to the magnitude of the applied voltage to adjust the thickness of the first dielectric layer 17.
Referring to fig. 16, due to the presence of the forward bias voltage in the trench of the termination region, the electric field distribution of the termination region can be adjusted, so that the depletion line extends laterally, the voltage endurance of the device is improved, and meanwhile, the avalanche breakdown point moves from the termination to the active region, and the high-temperature stability is better. Referring to fig. 17, compared with the conventional SGT termination structure, the present invention can significantly improve the electric field distribution, and the trench of the termination region bears more voltage, thereby increasing the voltage withstanding level of the device; meanwhile, the electric field intensity near the periphery of the terminal region is higher in the invention as seen by the electric field distribution (parallel to the X axis) perpendicular to the bottom of the trench. Referring to fig. 18, the invention reduces the density of oxide layer interface hole defects during avalanche breakdown by increasing bias voltage in the trench of the termination region, thereby effectively improving BV walk-in and walk-out problems, thereby improving BV stability and increasing device reliability; from the simulation pull bias result, the bias voltage in the trench is between 6V and 17V, and the BVDSS of the device is stable.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Without departing from the principle of the invention, several improvements and modifications can be made, and these improvements and modifications should also be construed as the scope of the invention.
Claims (8)
1. A manufacturing method of an SGT terminal structure for improving BV stability is characterized by comprising the following steps:
providing a first conductive type substrate, and manufacturing an epitaxial layer on the upper side of the substrate;
etching to form a plurality of grooves on the epitaxial layer;
growing a field oxide layer on the upper side of the epitaxial layer and the inner side of the groove;
respectively manufacturing and forming a first conductive type shield grid polycrystalline silicon and a polycrystalline silicon field plate in the grooves in the active region and the terminal region;
manufacturing a first oxide layer in the grooves on the upper sides of the shield grid polycrystalline silicon and the polycrystalline silicon field plate, and etching the first oxide layer on the upper side of the shield grid polycrystalline silicon to form an isolation oxide layer;
growing a gate oxide layer in the groove on the upper side of the isolation oxide layer and on the upper side of the epitaxial layer;
manufacturing a control gate polysilicon of a first conductive type in the trench on the inner side of the gate oxide layer, and manufacturing and forming a second oxide layer on the upper side of the control gate polysilicon;
manufacturing a body region of a second conduction type on the epitaxial layer;
depositing and forming polycrystalline silicon of a second conductive type on the upper side of the gate oxide layer, then carrying out etching operation on the polycrystalline silicon, and carrying out first conductive type element injection and annealing operation on the inner end part of the polycrystalline silicon reserved in the body region and the upper side of the gate oxide layer through etching so as to manufacture and form a first well region arranged in the body region of the active region, a second well region arranged at the outer end of the body region of the terminal region, a diode and a resistor arranged on the upper side of the gate oxide layer, wherein the outer end of the diode is connected with the inner end of the resistor, a vacant region is formed in an epitaxial layer between two adjacent grooves in the terminal region, and the diode and the resistor are arranged on the upper side of the vacant region;
depositing to form a first dielectric layer, and etching the first dielectric layer to form a first connecting hole;
sputtering a first metal layer on the upper side of the first dielectric layer and in the first connecting hole, and etching the first metal layer to form a first source electrode metal connected with the first well region, a capacitor field plate metal respectively connected with the polysilicon field plate and the inner end of the diode, a stop ring metal respectively connected with the outer end of the resistor, the polysilicon field plate and the second well region, and a gate metal;
depositing to form a second dielectric layer, etching to form a second connecting hole on the second dielectric layer, sputtering to form a second metal layer on the upper side of the second dielectric layer and in the second connecting hole, etching to form a second source electrode metal connected with the first source electrode metal, and extending the second source electrode metal outwards to the upper side of the capacitor field plate metal to form a capacitor structure in cooperation with the capacitor field plate metal.
2. The method of claim 1, wherein the implantation of arsenic as an element at the inner end of polysilicon left by etching in the body region and on the gate oxide layer is performed at a dose of 5E15-1E16atom/cm2The implantation energy was 60KeV, the annealing temperature was 950 ℃ and the annealing time was 60 min.
3. The method of claim 1, wherein a passivation layer is deposited on the second source metal and the upper side of the second dielectric layer, and the passivation layer is etched to form the source and gate openings.
4. The method of claim 1, wherein a backside gold layer is formed on the underside of the substrate.
5. An SGT terminal structure for improving BV stability is characterized by comprising a first conductive type substrate and an epitaxial layer arranged on the upper side of the substrate, wherein a plurality of grooves are formed in the epitaxial layer, a field oxide layer is arranged on the inner side of each groove, a shielding grid polysilicon and a polysilicon field plate of a first conductive type are respectively manufactured and formed in the grooves in an active area and a terminal area, an isolation oxide layer and a first oxide layer are respectively arranged in the grooves on the upper sides of the shielding grid polysilicon and the polysilicon field plate, a gate oxide layer is arranged in the groove on the upper side of the isolation oxide layer, a control grid polysilicon of the first conductive type is arranged in the groove on the inner side of the gate oxide layer, a second oxide layer is arranged on the upper side of the control grid polysilicon, a body area of a second conductive type is arranged on the epitaxial layer, a first well area is arranged in the body area of the active area, and a second well area is arranged at the outer end of the body area of the terminal area, the upper side of the gate oxide layer is connected with the inner end of the resistor, a vacant region is formed between two adjacent grooves in the terminal region, the diode and the resistor are arranged on the upper side of the vacant region, a first dielectric layer is arranged on the upper sides of the gate oxide layer, the diode and the resistor, a first connecting hole is formed in the first dielectric layer, first source electrode metal connected with a well region in the source region, capacitor field plate metal connected with the inner ends of the polysilicon field plate and the diode respectively, stop ring metal and gate metal connected with the outer end of the resistor, the polysilicon field plate and a second well region respectively are arranged on the upper side of the dielectric layer, a second connecting hole is formed in the second dielectric layer, the upper sides of the first source electrode metal, the capacitor field plate metal, the stop ring metal and the gate metal and the upper side of the first dielectric layer therebetween, and a second source electrode metal connected with the first source electrode metal is arranged on the upper side of the second dielectric layer, and the second source electrode metal extends outwards to the upper side of the capacitor field plate metal so as to form a capacitor structure by matching with the capacitor field plate metal.
6. The SGT terminal structure for improving BV stability of claim 5, wherein a passivation layer is deposited on the top side of the second source metal and the second dielectric layer, and the opening regions of the source and the gate are etched on the passivation layer.
7. An SGT termination structure to improve BV stability according to claim 5, wherein a back gold layer is fabricated on the underside of the substrate.
8. An SGT termination structure to improve BV stability according to claim 5, wherein the resistors are placed in a circumferential arrangement.
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