CN113921401B - Super junction and SGT novel composite MOSFET and manufacturing method thereof - Google Patents

Super junction and SGT novel composite MOSFET and manufacturing method thereof Download PDF

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CN113921401B
CN113921401B CN202111496386.6A CN202111496386A CN113921401B CN 113921401 B CN113921401 B CN 113921401B CN 202111496386 A CN202111496386 A CN 202111496386A CN 113921401 B CN113921401 B CN 113921401B
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epitaxial layer
layer
upper side
etching
oxide layer
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CN113921401A (en
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薛璐
陶瑞龙
李加洋
胡兴正
刘海波
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Nanjing Huaruiwei Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The invention discloses a super junction and SGT novel composite MOSFET and a manufacturing method thereof. The method comprises the steps of manufacturing an epitaxial layer on the upper side of a substrate, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer which are sequentially arranged on the upper side of the substrate, and the doping concentration of the first epitaxial layer is greater than that of the second epitaxial layer; etching the epitaxial layer to form a plurality of first grooves, wherein the lower ends of the first grooves are arranged in the first epitaxial layer; growing a first oxide layer on the upper side of the second epitaxial layer and in the first groove; etching the first epitaxial layer at the lower side of the first groove to form a second groove; and manufacturing a second conductive type silicon column in the first groove and the second groove. The invention can realize charge balance by adjusting the doping concentration of the silicon column, reduce the resistivity of the epitaxial layer, reduce the on resistance, reduce the stress of the wafer, increase the Coss of the device and enhance the EMI resistance of the device.

Description

Super junction and SGT novel composite MOSFET and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a super junction and SGT novel composite MOSFET and a manufacturing method thereof.
Background
Poly-S of a traditional top-bottom type SGT MOS structure is formed by depositing polysilicon in a groove, the region is connected with a source electrode, when a device is in reverse bias, a transverse electric field is formed in a drift region, and a field plate of an oxide layer on the side wall of the groove shares the withstand voltage, so that a charge balance result is formed. However, the structure has a certain limitation, because the thickness of the oxide layer on the side wall of the trench cannot be continuously increased, when the voltage resistance of the device direction needs to be 200V or more, the partial pressure effect of oxygen on the side of the trench is gradually weakened, and higher voltage can be borne only by adjusting the doping concentration and thickness of the epitaxial layer.
Disclosure of Invention
The invention aims to provide a super junction and SGT novel composite MOSFET and a manufacturing method thereof, aiming at the defects in the prior art.
To achieve the above object, in a first aspect, the present invention provides a method for manufacturing a super junction and SGT novel composite MOSFET, comprising:
providing a substrate of a first conduction type, and manufacturing an epitaxial layer on the upper side of the substrate, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer which are sequentially arranged on the upper side of the substrate, and the doping concentration of the first epitaxial layer is greater than that of the second epitaxial layer;
etching the epitaxial layer to form a plurality of first grooves, wherein the lower ends of the first grooves are arranged in the first epitaxial layer;
growing a first oxide layer on the upper side of the second epitaxial layer and in the first groove;
etching the first epitaxial layer at the lower side of the first groove to form a second groove;
manufacturing silicon columns of a second conduction type in the first trench and the second trench, and etching the silicon columns in the upper end of the first trench, the first oxide layer on the periphery of the silicon columns and the first oxide layer on the upper side of the second epitaxial layer;
manufacturing an isolation oxide layer in the first groove on the upper side of the silicon column;
growing a gate oxide layer on the inner side of the first groove on the upper side of the isolation oxide layer;
manufacturing a polysilicon gate of a first conductive type in a first groove on the upper side of the isolation oxide layer, and growing a second oxide layer on the upper side of the polysilicon gate;
performing body region injection operation and body region annealing operation in the second epitaxial layer around the gate oxide layer to manufacture and form a body region of a second conduction type;
performing source region photoetching operation, source region injection operation and source region annealing operation on the upper end of the body region to manufacture and form a source region of the first conduction type;
depositing a dielectric layer on the upper side of the second epitaxial layer, and etching the dielectric layer and the second epitaxial layer to form a connecting hole;
and depositing a metal layer on the upper side of the dielectric layer and in the connecting hole, etching the metal layer to form source metal and grid metal, and respectively connecting the source metal with the source region, the body region and the silicon column.
Furthermore, the doping concentration of the first epitaxial layer is 4E16-7E16, and the doping concentration of the second epitaxial layer is 1E16-2E 16.
Further, after the first groove is formed through etching, elements of a second conductive type are implanted into the first epitaxial layer on the lower side of the first groove, the implantation energy is 20keV-30keV, and the implantation dosage is 1E12-3E 12.
Further, the method also comprises the following steps:
after the connection hole is formed, performing connection hole injection operation and connection hole annealing operation on the second epitaxial layer on the lower side of the connection hole, wherein the connection hole injection operation comprises two times of element injection, the elements injected twice are BF2 and B respectively, the injection dosage is 2E14-5E14, the injection energy is 30-40KeV, and the annealing condition of the connection hole annealing operation is 950 ℃/30 s;
and sequentially depositing Ti and TiN layers on the second epitaxial layer on the lower side of the connecting hole, and finally filling and back-etching the tungsten metal to form an ohmic contact hole.
Further, the depth of the first groove is 0.6-5um, and the width of the first groove is 0.2-1.2 um.
In a second aspect, the invention provides a super-junction and SGT novel composite MOSFET, which includes a substrate of a first conductivity type and an epitaxial layer disposed on the substrate, wherein the epitaxial layer includes a first epitaxial layer and a second epitaxial layer sequentially disposed on the substrate, the doping concentration of the first epitaxial layer is greater than that of the second epitaxial layer, a plurality of first trenches and second trenches are etched on the epitaxial layer, the lower ends of the first trenches are disposed in the first epitaxial layer, the lower end of each first trench is connected with the upper end of one second trench, the lower ends of the first trenches and a silicon pillar of a second conductivity type in the second trench are etched, a first oxide layer is disposed between the silicon pillar and the epitaxial layer, an isolation oxide layer is disposed in the first trench on the upper side of the silicon pillar, a polysilicon gate is formed on the upper side of the isolation oxide layer, and a gate oxide layer is disposed between the polysilicon gate and the second epitaxial layer, and a second oxidation layer is arranged on the upper side of the gate oxide layer, a body region of a second conduction type is formed in the second epitaxial layer on the periphery of the gate oxide layer, a source region of a first conduction type is formed at the upper end of the body region, a dielectric layer is deposited on the upper side of the second epitaxial layer, connecting holes are formed in the dielectric layer and the second epitaxial layer in an etching mode, metal layers are deposited on the upper side of the dielectric layer and in the connecting holes, a source electrode metal and a gate electrode metal are formed by etching the metal layers, and the source electrode metal is connected with the source region, the body region and the silicon column respectively.
Furthermore, the doping concentration of the first epitaxial layer is 4E16-7E16, and the doping concentration of the second epitaxial layer is 1E16-2E 16.
Further, after the first groove is formed through etching, elements of a second conductive type are implanted into the first epitaxial layer on the lower side of the first groove, the implantation energy is 20keV-30keV, and the implantation dosage is 1E12-3E 12.
Further, the method also comprises the following steps:
after the connection hole is formed, performing connection hole injection operation and connection hole annealing operation on the second epitaxial layer on the lower side of the connection hole, wherein the connection hole injection operation comprises two times of element injection, the elements injected twice are BF2 and B respectively, the injection dosage is 2E14-5E14, the injection energy is 30-40KeV, and the annealing condition of the connection hole annealing operation is 950 ℃/30 s;
and sequentially depositing Ti and TiN layers on the second epitaxial layer on the lower side of the connecting hole, and finally filling and back-etching the tungsten metal to form an ohmic contact hole.
Further, the depth of the first groove is 0.6-5um, and the width of the first groove is 0.2-1.2 um.
Has the advantages that: 1. the charge balance can be realized by adjusting the doping concentration of the silicon column, the resistivity of the epitaxial layer is reduced, and the on-resistance is reduced;
2. compared with the deep groove and thick oxide layer process, the method has the advantages that the super junction structure is formed by manufacturing the silicon column, so that the stress of the wafer can be reduced;
3. the invention increases the Coss of the device and enhances the EMI resistance of the device.
Drawings
FIG. 1 is a schematic diagram of a structure after an epitaxial layer is fabricated on a substrate;
fig. 2 is a schematic structural view after a first trench is formed in the epitaxial layer;
FIG. 3 is a schematic structural diagram of a first oxide layer after being formed;
FIG. 4 is a schematic diagram of the structure after a second trench is formed in the first epitaxial layer;
FIG. 5 is a schematic structural diagram of a silicon pillar fabricated in the first trench and the second trench;
FIG. 6 is a schematic structural diagram of a silicon pillar with an isolation oxide layer formed thereon;
FIG. 7 is a schematic structural diagram of a gate oxide layer formed in the first trench;
fig. 8 is a schematic structural view after a polysilicon gate and a second oxide layer are formed on the upper side of the isolation oxide layer;
figure 9 is a schematic diagram of the structure after body and source regions have been formed in the second epitaxial layer;
FIG. 10 is a schematic structural diagram after a connection hole is etched in a dielectric layer;
FIG. 11 is a schematic diagram of the structure after etching to form source metal;
fig. 12 is a schematic diagram of a simulated structure of a superjunction and SGT novel composite MOSFET;
FIG. 13 is a graph comparing simulated electric field distributions of a MOSFET of an embodiment of the present invention with a conventional MOSFET;
fig. 14 is a simulated doping concentration profile of a superjunction and SGT novel composite MOSFET;
fig. 15 is a simulated potential line profile of a superjunction and SGT novel composite MOSFET.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1 to 11, an embodiment of the present invention provides a method for manufacturing a super junction and SGT novel composite MOSFET, including:
referring to fig. 1, a substrate 1 of a first conductivity type is provided, an epitaxial layer being produced on the upper side of the substrate. The following describes the technical solution of the present invention by taking the first conductive type as an N-type and the second conductive type as a P-type as an example. The substrate 1 is doped with arsenic or phosphorus, and the thickness of the epitaxial layer is determined by different device withstand voltages, and is generally 3-15 um. The epitaxial layers preferably include a first epitaxial layer 2 and a second epitaxial layer 3, the first epitaxial layer 2 being disposed on an upper side of the substrate 1, the second epitaxial layer 3 being disposed on an upper side of the first epitaxial layer 2. The doping concentration of the first epitaxial layer 2 is greater than the doping concentration of the second epitaxial layer 3, the doping concentration of the first epitaxial layer 2 is preferably 4E16-7E16, and the doping concentration of the second epitaxial layer 3 is preferably 1E16-2E 16.
Referring to fig. 2, a plurality of first trenches 4 are etched into the epitaxial layer, and the lower ends of the first trenches 4 are disposed in the first epitaxial layer 2. Specifically, a silicon dioxide layer is deposited on the surface of the epitaxial layer, the thickness of the silicon dioxide layer is about 4000 angstroms, and the thickness of the silicon dioxide layer can be finely adjusted according to the etching morphology of the first groove 4. And then, performing groove photoetching and etching to form a first groove 4, wherein the depth of the first groove 4 is preferably 0.6-5um, the width of the first groove 4 is preferably 0.2-1.2um, and the inclination angle of the side wall of the first groove 4 is preferably 89 degrees.
Referring to fig. 3, a first oxide layer 5 is grown on the upper side of the second epitaxial layer 3 and within the first trenches 4. The first oxide layer 5 may be formed by dry-wet-dry oxidation and CVD (chemical deposition) methods, and the thickness of the first oxide layer 5 is about 3500-.
Referring to fig. 4, a second trench 6 is etched in the first epitaxial layer 2 on the lower side of the first trench 4. The depth of the second trench 6 is generally above 1 um, and the depth depends on the dielectric strength to be achieved, and the higher the dielectric strength to be achieved, the deeper the depth of the second trench 6 needs to be.
Referring to fig. 5, a silicon pillar 7 of the second conductivity type is formed in the first trench 4 and the second trench 6, and the silicon pillar 7 in the upper end of the first trench 4, the first oxide layer 5 around the silicon pillar, and the first oxide layer 5 on the upper side of the second epitaxial layer 3 are etched away. Specifically, the silicon pillars 7 are preferably formed by a CVD process. Referring to fig. 12, in the simulation result, the silicon pillars 7 are distributed in a wide upper portion and a narrow lower portion, and the morphology can be adjusted by adjusting the concentration of the epitaxial layer at the position and the doping concentration of the silicon pillars 7.
Referring to fig. 6, an isolation oxide layer 8 is formed in the first trench 4 on the upper side of the silicon pillar 7. Specifically, an isolation oxide layer 8 may be formed in the first trench 4 by a deposition method, and then the isolation oxide layer is etched to have a thickness of 5000-.
Referring to fig. 7, a gate oxide layer 9 is grown inside the first trench 4 on the upper side of the isolation oxide layer 8. The thickness of the gate oxide layer 9 is preferably 500-1000 angstroms, the growth temperature is 950-1050 ℃, and the thicker the thickness of the gate oxide layer 9 is, the higher the temperature is required for growth. Before growing the gate oxide layer 9, a sacrificial oxide layer with a thickness of 500-.
Referring to fig. 8, a polysilicon gate 10 of the first conductivity type is formed in the first trench 4 on the upper side of the isolation oxide layer 8, and a second oxide layer 11 is grown on the upper side of the polysilicon gate 10. The thickness of the polysilicon gate 10 is preferably 0.8-1.2um, the doping concentration is 1E19-6E19, and the doping element is preferably phosphorus.
Referring to fig. 9, a body implantation operation and a body annealing operation are performed in the second epitaxial layer 3 around the gate oxide layer 9 to fabricate a body region 12 of the second conductivity type. Specifically, the element implanted by the body region implantation operation is preferably boron, the implantation energy is 60KEV-120KEV, the implantation dose is adjusted according to the requirements of VTH parameters, and is generally about 5E12-1.8E13, and the annealing conditions of the body region annealing operation are as follows: 1100 ℃/60min, a certain amount of oxygen needs to be introduced in the annealing process, an oxide layer is formed on the surface of the second epitaxial layer 3, and the uniformity of the doping concentration of the P well can be improved by adopting double injection.
Referring to fig. 9, a source region photolithography operation, a source region implantation operation, and a source region annealing operation are performed on the upper end of the body region 12 to fabricate a source region 13 forming the first conductive type. The element implanted by the source region implantation operation is preferably arsenic, the implantation energy is preferably 60KeV, and the annealing condition of the source region annealing operation is 950 ℃/60 min.
Referring to fig. 10, a dielectric layer 14 is deposited on the upper side of the second epitaxial layer 3 and a connection hole 15 is etched in the dielectric layer 14 and the second epitaxial layer 3. After the formation of the connection hole 15, a connection hole implantation operation and a connection hole annealing operation are preferably performed on the second epitaxial layer 3 on the lower side of the connection hole 15, wherein the connection hole implantation operation comprises two element implantations, the two element implantations are BF2 and B respectively, the implantation dosage is 2E14-5E14, the implantation energy is 30-40KeV, and the annealing condition of the connection hole annealing operation is 950 ℃/30 s. And then sequentially depositing Ti and TiN layers on the second epitaxial layer 3 on the lower side of the connecting hole 15, and finally filling and back-etching tungsten metal to form an ohmic contact hole.
Referring to fig. 11, a metal layer is deposited on the upper side of the dielectric layer 14 and in the connection hole 15, and the metal layer is etched to form a source metal 16 and a gate metal (not shown in the figure), and the source metal 16 is connected to the source region 13, the body region 12 and the silicon pillar 7, respectively. In particular, the silicon pillars 7 may be led out from the edge of the device through wire holes laterally arranged in the first epitaxial layer 2 and then connected to the source metal 16 from the outside. The metal layer of the device is preferably an aluminum layer, SiCu can be doped in the aluminum in a certain proportion to prevent mutual dissolution of aluminum and silicon, and the thickness of the metal layer is preferably 4 um.
It is also possible to deposit a passivation layer on the upper side of the device and etch the passivation layer to form Gate and Source opening regions. The passivation layer is preferably a silicon nitride passivation layer, and the thickness of the passivation layer is preferably 7000-12000 angstroms, and the passivation layer can reduce device leakage caused by mobile ions on the surface of the chip. It is also possible to thin the substrate 1 from the underside to a remaining thickness of around 150um and then to form a back gold layer 17 by evaporation on the underside of the substrate 1, the back gold layer 17 preferably being a Ti-Ni-Ag (titanium-nickel-silver) layer.
Referring to fig. 15, the present invention can effectively improve the electric field distribution, except that the interface between the silicon pillar 7 and the bottom of the first oxide layer 5 is a potential-dense region (breakdown weak point), and the concentration distribution at this position can be adjusted by increasing the implantation at the bottom of the first trench 4 to achieve a better electric potential distribution. Specifically, after the first trench 4 is formed by etching, the first epitaxial layer 2 on the lower side of the first trench 4 is implanted with an element of the second conductivity type, preferably boron, at an implantation energy of 20keV to 30keV, in a dose of 1E12 to 3E 12.
With reference to fig. 1 to 11, based on the above embodiments, those skilled in the art can understand that the present invention further provides a super junction and SGT novel composite MOSFET, which includes a substrate 1 of a first conductivity type and an epitaxial layer 2 disposed on an upper side of the substrate 1, and the technical solutions of the present invention are described below by taking the first conductivity type as an N-type and the second conductivity type as a P-type as examples. The substrate 1 is doped with arsenic or phosphorus, and the thickness of the epitaxial layer is determined by different device withstand voltages, and is generally 3-15 um. The epitaxial layers preferably include a first epitaxial layer 2 and a second epitaxial layer 3, the first epitaxial layer 2 being disposed on an upper side of the substrate 1, the second epitaxial layer 3 being disposed on an upper side of the first epitaxial layer 2. The doping concentration of the first epitaxial layer 2 is greater than the doping concentration of the second epitaxial layer 3, the doping concentration of the first epitaxial layer 2 is preferably 4E16-7E16, and the doping concentration of the second epitaxial layer 3 is preferably 1E16-2E 16.
A plurality of first trenches 4 and second trenches 6 are etched on the epitaxial layer, wherein the lower ends of the first trenches 4 are arranged in the first epitaxial layer 2, the lower end of each first trench 4 is connected with the upper end of one second trench 6, second conductive type silicon columns 7 are arranged at the lower ends of the first trenches 4 and in the second trenches 6, a first oxide layer 5 is arranged between the silicon columns 7 and the epitaxial layer, the first oxide layer 5 can be formed by a dry-wet-dry oxidation and CVD (chemical deposition) method, and the thickness of the first oxide layer 5 is about 3500-5000 angstroms. An isolation oxide layer 8 is disposed in the first trench on the upper side of the silicon pillar 7, and the thickness of the isolation oxide layer 8 is preferably 5000-. A polysilicon gate 10 is formed on the upper side of the isolation oxide layer 8, a gate oxide layer 9 is arranged between the polysilicon gate 10 and the second epitaxial layer 3, the thickness of the gate oxide layer 9 is preferably 500-1000 angstroms, the growth temperature is 950-1050 ℃, and the thicker the gate oxide layer 9 is. A second oxide layer 11 is disposed on the upper side of the polysilicon gate 10, a body region 12 of a second conductivity type is formed in the second epitaxial layer 3 around the gate oxide layer 9, specifically, the body region 12 is formed by a body region implantation operation and a body region annealing operation, the element implanted by the body region implantation operation is preferably boron, the implanted energy is 60KEV-120KEV, the implanted dose is adjusted according to the requirement of VTH parameters, generally about 5E12-1.8E13, and the annealing condition of the body region annealing operation is as follows: 1100 ℃/60min, a certain amount of oxygen needs to be introduced in the annealing process, an oxide layer is formed on the surface of the second epitaxial layer 3, and the uniformity of the doping concentration of the P well can be improved by adopting double injection.
A source region 13 of the first conductivity type is formed at the upper end of the body region 12, specifically, the source region 13 is formed by a source region implantation operation and a source region annealing operation, wherein the element implanted by the source region implantation operation is preferably arsenic, the implantation energy is preferably 60KeV, and the annealing condition of the source region annealing operation is 950 ℃/60 min. Depositing a dielectric layer 14 on the upper side of the second epitaxial layer 3, etching a connecting hole 15 on the dielectric layer 14 and the second epitaxial layer 3, preferably performing a connecting hole injection operation and a connecting hole annealing operation on the second epitaxial layer 3 on the lower side of the connecting hole 15 after the connecting hole 15 is formed, wherein the connecting hole injection operation comprises two times of element injection, the two times of element injection are BF2 and B respectively, the injection dosage is 2E14-5E14, the injection energy is 30-40KeV, and the annealing condition of the connecting hole annealing operation is 950 ℃/30 s. And then sequentially depositing Ti and TiN layers on the second epitaxial layer 3 on the lower side of the connecting hole 15, and finally filling and back-etching tungsten metal to form an ohmic contact hole. And depositing a metal layer on the upper side of the dielectric layer 14 and in the connecting hole 15, and etching the metal layer to form a source metal 16 and a gate metal. The source metal 16 is connected to the source region 13, the body region 12 and the silicon pillar 7, respectively.
It is also possible to deposit a passivation layer on the upper side of the device and etch the passivation layer to form Gate and Source opening regions. The passivation layer is preferably a silicon nitride passivation layer, and the thickness of the passivation layer is preferably 7000-12000 angstroms, and the passivation layer can reduce device leakage caused by mobile ions on the surface of the chip. It is also possible to thin the substrate 1 from the underside to a remaining thickness of around 150um and then to form a back gold layer 17 by evaporation on the underside of the substrate 1, the back gold layer 17 preferably being a Ti-Ni-Ag (titanium-nickel-silver) layer.
The invention forms a deep groove by etching a first groove 4 and a second groove 6, and a P-type silicon column 7 is manufactured in the groove. The P-type silicon column 7 is led out to be connected with the source metal 16. The P-type silicon column 7 and the N-type epitaxial layer form a super junction structure, and simultaneously form a field plate structure with the first oxide layer 5 in the first trench 4. Referring to fig. 13, when the device is in reverse bias during operation, except for the action of the flattening electric field of the first oxide layer 5 on the sidewall of the first trench 4, meanwhile, since the silicon pillar 7 is connected to the source electrode with a low potential and forms a PN junction with the epitaxial layer in a reverse bias state, the lateral electric field of the device is increased, so that the device is flattened from a triangular electric field to a trapezoidal electric field, thereby playing a role in balancing electric charges and improving the withstand voltage capability of the device. Referring to fig. 14, the invention uses a two-layer epitaxy technique, which can better achieve the charge balance between the epitaxial layer and the silicon pillar 7, and reduce the on-resistance of the device. Referring to fig. 15, the present invention can effectively improve the electric field distribution, except that the interface between the silicon pillar 7 and the bottom of the first oxide layer 5 is a potential-dense region (breakdown weak point), and the concentration distribution at this position can be adjusted by increasing the implantation at the bottom of the first trench 4 to achieve a better electric potential distribution. Specifically, after the first trench 4 is formed by etching, the first epitaxial layer 2 on the lower side of the first trench 4 is implanted with an element of the second conductivity type, preferably boron, at an implantation energy of 20keV to 30keV, in a dose of 1E12 to 3E 12.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Without departing from the principle of the invention, several improvements and modifications can be made, and these improvements and modifications should also be construed as the scope of the invention.

Claims (10)

1. A method for manufacturing a super junction and SGT novel composite MOSFET is characterized by comprising the following steps:
providing a substrate of a first conduction type, and manufacturing an epitaxial layer on the upper side of the substrate, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer which are sequentially arranged on the upper side of the substrate, and the doping concentration of the first epitaxial layer is greater than that of the second epitaxial layer;
etching the epitaxial layer to form a plurality of first grooves, wherein the lower ends of the first grooves are arranged in the first epitaxial layer;
growing a first oxide layer on the upper side of the second epitaxial layer and in the first groove;
etching the first epitaxial layer at the lower side of the first groove to form a second groove;
manufacturing silicon columns of a second conduction type in the first trench and the second trench, and etching the silicon columns in the upper end of the first trench, the first oxide layer on the periphery of the silicon columns and the first oxide layer on the upper side of the second epitaxial layer;
manufacturing an isolation oxide layer in the first groove on the upper side of the silicon column;
growing a gate oxide layer on the inner side of the first groove on the upper side of the isolation oxide layer;
manufacturing a polysilicon gate of a first conductive type in a first groove on the upper side of the isolation oxide layer, and growing a second oxide layer on the upper side of the polysilicon gate;
performing body region injection operation and body region annealing operation in the second epitaxial layer around the gate oxide layer to manufacture and form a body region of a second conduction type;
performing source region photoetching operation, source region injection operation and source region annealing operation on the upper end of the body region to manufacture and form a source region of the first conduction type;
depositing a dielectric layer on the upper side of the second epitaxial layer, and etching the dielectric layer and the second epitaxial layer to form a connecting hole;
and depositing a metal layer on the upper side of the dielectric layer and in the connecting hole, etching the metal layer to form source metal and grid metal, and respectively connecting the source metal with the source region, the body region and the silicon column.
2. The method of manufacturing a superjunction and SGT novel composite MOSFET of claim 1, wherein the doping concentration of the first epitaxial layer is 4E16-7E16 and the doping concentration of the second epitaxial layer is 1E16-2E 16.
3. The method for manufacturing a super-junction and SGT novel composite MOSFET as claimed in claim 1, wherein after the first trench is formed by etching, the first epitaxial layer under the first trench is implanted with the second conductivity type element at an implantation energy of 20keV to 30keV in a dose of 1E12 to 3E 12.
4. The method of manufacturing a superjunction and SGT novel composite MOSFET of claim 1, further comprising:
after the connection hole is formed, performing connection hole injection operation and connection hole annealing operation on the second epitaxial layer on the lower side of the connection hole, wherein the connection hole injection operation comprises two times of element injection, the elements injected twice are BF2 and B respectively, the injection dosage is 2E14-5E14, the injection energy is 30-40KeV, and the annealing condition of the connection hole annealing operation is 950 ℃/30 s;
and sequentially depositing Ti and TiN layers on the second epitaxial layer on the lower side of the connecting hole, and finally filling and back-etching the tungsten metal to form an ohmic contact hole.
5. The method for manufacturing a super junction and SGT novel composite MOSFET according to claim 1, wherein the depth of the first trench is 0.6 to 5um, and the width thereof is 0.2 to 1.2 um.
6. A super-junction and SGT novel composite MOSFET is characterized by comprising a substrate of a first conductivity type and an epitaxial layer arranged on the upper side of the substrate, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer which are sequentially arranged on the upper side of the substrate, the doping concentration of the first epitaxial layer is greater than that of the second epitaxial layer, a plurality of first grooves and second grooves are formed in the epitaxial layer in an etching mode, the lower ends of the first grooves are arranged in the first epitaxial layer, the lower end of each first groove is connected with the upper end of one second groove, silicon columns of the second conductivity type are arranged in the first grooves and the second grooves, a first oxide layer is arranged between the silicon columns and the epitaxial layer, an isolation oxide layer is arranged in the first grooves on the upper sides of the silicon columns, a polysilicon gate is formed on the upper sides of the isolation oxide layers, and a gate oxide layer is arranged between the polysilicon gate oxide and the second epitaxial layer, and a second oxidation layer is arranged on the upper side of the gate oxide layer, a body region of a second conduction type is formed in the second epitaxial layer on the periphery of the gate oxide layer, a source region of a first conduction type is formed at the upper end of the body region, a dielectric layer is deposited on the upper side of the second epitaxial layer, connecting holes are formed in the dielectric layer and the second epitaxial layer in an etching mode, metal layers are deposited on the upper side of the dielectric layer and in the connecting holes, a source electrode metal and a gate electrode metal are formed by etching the metal layers, and the source electrode metal is connected with the source region, the body region and the silicon column respectively.
7. The superjunction and SGT novel composite MOSFET as claimed in claim 6, wherein the doping concentration of the first epitaxial layer is 4E16-7E16 and the doping concentration of the second epitaxial layer is 1E16-2E 16.
8. The superjunction and SGT novel composite MOSFET as claimed in claim 6, wherein after the first trench is etched to form, the first epitaxial layer under said first trench is implanted with the element of the second conductivity type at an implantation energy of 20keV to 30keV with an implantation dose of 1E12 to 3E 12.
9. The superjunction and SGT novel composite MOSFET as claimed in claim 6, further comprising:
after the connection hole is formed, performing connection hole injection operation and connection hole annealing operation on the second epitaxial layer on the lower side of the connection hole, wherein the connection hole injection operation comprises two times of element injection, the elements injected twice are BF2 and B respectively, the injection dosage is 2E14-5E14, the injection energy is 30-40KeV, and the annealing condition of the connection hole annealing operation is 950 ℃/30 s;
and sequentially depositing Ti and TiN layers on the second epitaxial layer on the lower side of the connecting hole, and finally filling and back-etching the tungsten metal to form an ohmic contact hole.
10. The superjunction and SGT novel composite MOSFET as claimed in claim 6, wherein the first trench has a depth of 0.6-5um and a width of 0.2-1.2 um.
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CN107331706A (en) * 2017-05-27 2017-11-07 上海华虹宏力半导体制造有限公司 Groove grid super node device and its manufacture method
CN107919399A (en) * 2017-12-13 2018-04-17 深圳市晶特智造科技有限公司 Half superjunction devices and its manufacture method
CN107994069A (en) * 2017-12-29 2018-05-04 安徽赛腾微电子有限公司 A kind of IGBT device and its manufacture method

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CN107331706A (en) * 2017-05-27 2017-11-07 上海华虹宏力半导体制造有限公司 Groove grid super node device and its manufacture method
CN107919399A (en) * 2017-12-13 2018-04-17 深圳市晶特智造科技有限公司 Half superjunction devices and its manufacture method
CN107994069A (en) * 2017-12-29 2018-05-04 安徽赛腾微电子有限公司 A kind of IGBT device and its manufacture method

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