CN111900089B - Method for manufacturing super junction device - Google Patents
Method for manufacturing super junction device Download PDFInfo
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- CN111900089B CN111900089B CN202010867057.7A CN202010867057A CN111900089B CN 111900089 B CN111900089 B CN 111900089B CN 202010867057 A CN202010867057 A CN 202010867057A CN 111900089 B CN111900089 B CN 111900089B
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention discloses a manufacturing method of a super junction device, which is realized by adopting a full-flat process and comprises the following steps: forming a zeroth layer alignment mark; forming a super junction, forming a super junction groove in the first epitaxial layer, filling a second epitaxial layer in the super junction groove, and flattening; forming a gate structure, forming a gate groove, refilling a polysilicon gate and flattening, wherein the width of the gate groove at the leading-out position of the gate structure meets the requirement of forming a contact hole; forming a body region by adopting ion implantation and annealing advancing processes; and thirdly, forming flat field oxygen without climbing. The invention can reduce the photoetching level and the process cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction device.
Background
The super junction is composed of alternately arranged P-type thin layers also called P-type pillars (pilar) and N-type thin layers also called N-type pillars (N-type pillars) formed in a semiconductor substrate, and the device using the super junction is a super junction device such as a super junction MOSFET. The in vivo surface electric field (Resurf) reduction technology utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and keep smaller on-resistance.
The PN-spaced pilar structure of the superjunction is the biggest feature of the superjunction. There are two main methods for manufacturing the PN-spaced pilar structure, one is obtained by multiple epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxial (EPI) filling. The latter method is to manufacture a super junction device by a trench process, and it is necessary to etch a trench with a certain depth and width on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then fill a P-type doped silicon epitaxial layer on the etched trench by using an epitaxial Filling (EPI) method.
FIG. 1 is a schematic diagram of a prior art superjunction; the super junction mainly comprises:
the N-type epitaxial layer 102 formed on the surface of an N-type semiconductor substrate such as the silicon substrate 101, the super junction trench 103 is formed in the N-type epitaxial layer 102, the trench corresponding to the super junction is referred to as a super junction trench in the present application, the P-type epitaxial layer is filled in the super junction trench 103 and the P-type epitaxial layer filled in the super junction trench 103 forms a P-type column 104, the N-type column is formed by the N-type epitaxial layer 102 between the P-type columns 104, and the P-type columns 104 and the N-type columns are alternately arranged to form a super junction.
As shown in fig. 2, a flow chart of a method of manufacturing a prior art superjunction device; the process flow of the fabrication method of the superjunction device is illustrated in fig. 2 by using photolithography steps, wherein a Mask is used and photolithography is performed on each layer of the photolithography process. The manufacturing method of the existing super junction device comprises the following steps:
and forming a zeroth layer alignment mark by a first layer photoetching process. And forming a zero layer alignment mark on the scribing channel, wherein the zero layer alignment mark is required to be adopted for alignment in a subsequent second layer photoetching process corresponding to the formation body region. The zeroth layer alignment mark is defined by a zeroth layer Mask (ZM), and the zeroth layer Mask is also denoted by Mask 1.
And (3) a second layer photoetching process, body region implantation and promotion. Sampling of body implant is required to be defined using Mask 2.
And etching and filling the super junction groove by a third layer of photoetching process. The formation area of the super structure trench needs to be defined by Mask 3.
And a fourth layer photoetching process, namely, depositing and etching field oxygen. The etching area of the field oxide needs to be defined by Mask 4. The field oxide is typically formed on the surface of a termination region that surrounds the periphery of the device cell region, i.e., the current flow region, i.e., the active region. The field oxide of the device cell region needs to be removed prior to forming the structure of the device cell region.
And a fifth photoetching process, namely etching the grid groove and forming a grid oxide layer and a polysilicon grid. The trench corresponding to the trench gate is called a gate trench in the invention, and the gate trench needs to be defined by Mask 5.
And a sixth layer photoetching process, namely photoetching and etching polysilicon, and injecting and advancing a body region. The Mask6 is used for defining an etching area of the polysilicon, and after the polysilicon is subjected to photoetching and etching, a polysilicon gate extraction structure of the trench gate can be formed. The polysilicon gate extraction structure is typically located in the termination region, so the polysilicon of the extraction structure needs to climb the slope between the field oxide and the active region.
The body implant here does not require further photolithographic definition.
And a seventh layer photoetching process, wherein the source region is implanted and advanced. The implantation area of the source region is defined by Mask 7.
And eighth layer photoetching process, interlayer film deposition and contact hole (CT) etching, and body region leading-out region injection and promotion. The etched area of the contact hole is defined by Mask 8.
And a ninth layer photoetching process, namely depositing and etching the front metal layer. The etched area of the front side metal layer is defined by Mask 9.
A tenth layer of lithography process, deposition and etching of Contact PADs (CP); the etched area of the contact pad is defined using Mask 10.
As can be seen from the above, in the conventional method, 10 photolithography processes are required, and the process cost is high.
Disclosure of Invention
The invention aims to provide a manufacturing method of a super junction device, which can reduce photoetching layers and reduce process cost.
In order to solve the technical problems, the manufacturing method of the super junction device provided by the invention is realized by adopting a full Flat (All Flat) process and comprises the following steps:
and step one, photoetching by adopting a zeroth layer photomask and forming a zeroth layer alignment mark.
Step two, performing a super junction forming process, including:
a first epitaxial layer with a first conductivity type is provided, and a photoetching process is performed to define a forming area of the super junction groove.
And etching the first epitaxial layer to form a super junction groove.
And filling a second epitaxial layer of a second conductivity type in the super junction groove, forming second conductivity type columns by the second epitaxial layer filled in the super junction groove, forming first conductivity type columns by the first epitaxial layer between the second conductivity type columns, and alternately arranging the first conductivity type columns and the second conductivity type columns to form the super junction.
A first planarization is performed such that the surface of the first epitaxial layer on which the super junction is formed is a planar surface.
Step three, forming the gate structure, wherein the gate structure is a trench gate, and the formation process of the trench gate comprises the following steps:
and carrying out a photoetching process on the first epitaxial layer with the super junction formed and the flat surface to define a forming area of the grid groove.
And etching the first epitaxial layer to form the gate groove, wherein the width of the gate groove at the leading-out position of the gate structure meets the requirement of forming a contact hole.
And forming a gate oxide layer on the side surface of the gate trench, and forming a bottom oxide layer on the bottom surface of the gate trench.
And filling the polysilicon gate in the gate trench, wherein the trench gate is formed by the gate oxide layer, the bottom oxide layer and the polysilicon gate which are formed in the gate trench.
And carrying out planarization for the second time to enable the surface of the first epitaxial layer formed with the trench gate to be a flat surface.
And fourthly, forming a body region by adopting ion implantation and annealing advancing processes, wherein the formed region of the body region is defined by photoetching.
And fifthly, forming field oxide, wherein the field oxide is covered on the first epitaxial layer which is formed with the super junction and the trench gate and has a flat surface, and the field oxide has a flat structure without climbing.
A further improvement is that after the body region is formed in step four and before the field oxide is formed in step five, the step of forming a heavily doped source region of the first conductivity type is further included as follows:
and forming a source region by adopting an ion implantation and annealing advancing process, wherein a forming region of the source region is defined by photoetching, and in the device unit region, the source region and the corresponding side face of the grid structure are self-aligned.
Further improvement is that after the step five is completed, the method further comprises the steps of:
and forming an interlayer film and a contact hole, wherein the forming area of the contact hole is defined by photoetching, and the corresponding contact hole is formed at the leading-out position of the grid structure.
And forming a front metal layer, patterning the front metal layer by adopting a photoetching definition and etching process, wherein an electrode formed by the patterned front metal layer comprises a gate electrode structure, and the gate electrode structure is contacted with the polysilicon gate through the contact hole at the leading-out position of the gate structure.
Contact pads are formed, and the forming areas of the contact pads are defined by lithography.
And finishing the back surface process of the super junction device.
The further improvement is that the contact holes are realized by tungsten bolts.
Further improvements are that the field oxygen consists of a thermal oxide layer or an oxide layer formed by a thermal oxide layer-on-TEOS oxidation process.
A further improvement is that the interlayer film covers the planar surface of the field oxide.
The interlayer film is formed by adopting a USG oxidation process or a TEOS oxidation process.
In the second step, a first hard mask layer is adopted in the formation process of the super junction, the first hard mask layer is formed by laminating a second bottom oxide layer, a middle nitride layer and a top oxide layer, and the formation process of the super junction when the first hard mask layer is adopted comprises the following steps:
and forming the first hard mask layer.
And defining a forming area of the super junction groove by adopting a photoetching process.
And etching the first hard mask layer and the first epitaxial layer in sequence to form the super junction groove.
And removing the top oxide layer of the first hard mask layer, forming a first sacrificial oxide layer by adopting a thermal oxidation process, and then removing the first sacrificial oxide layer.
And removing the middle nitride layer of the first hard mask layer.
And performing epitaxial filling in the super junction groove to form the second epitaxial layer.
And carrying out chemical mechanical polishing on the second epitaxial layer to realize the first planarization, so that the second epitaxial layer is only filled in the super junction groove.
And completely removing the second bottom oxide layer of the first hard mask layer or removing only part of the thickness.
In a further improvement, the first epitaxial layer is formed on a semiconductor substrate, and the back side process of the super junction device includes:
and thinning the back surface of the semiconductor substrate.
The semiconductor substrate is heavily doped with the first conduction type, and the thinned semiconductor substrate is directly used as a heavily doped drain region of the first conduction type; or carrying out back injection of the first conductivity type heavy doping on the thinned semiconductor substrate to form a drain region.
And forming a back metal layer on the back of the drain region.
In the third step, the step of forming a second hard mask layer on the surface of the first epitaxial layer is further included before the photoetching process for defining the gate trench, and then the second hard mask layer is etched first and then the first epitaxial layer is etched to form the gate trench.
The second planarization stops on the second hard mask layer and then the second hard mask layer is removed.
In the third step, after the etching of the gate trench is completed and before the forming of the gate oxide layer, the method further comprises the step of rounding the gate trench, wherein the rounding comprises:
and forming a second sacrificial oxide layer by adopting a thermal oxidation process.
And removing the second sacrificial oxide layer.
The further improvement is that the gate oxide layer is formed on the side surface of the gate trench by adopting a thermal oxidation process.
A further improvement is that the bottom oxide layer and the gate oxide layer are formed simultaneously using the same process.
Alternatively, the thickness of the bottom oxide layer is greater than the thickness of the gate oxide layer, and the bottom oxide layer and the gate oxide layer are formed separately.
A further improvement is that the second planarization is achieved by a back etching process or a chemical mechanical polishing process.
A further improvement is that the superjunction device includes a charge flow region, a transition region, and a termination region; the body region is formed in the charge flow region, the formation of the body region being simultaneous with the formation of the body region also forming a second conductivity type ring in the transition region.
In the fourth step, the junction depth of the body region is adjusted by controlling the thermal budget of the annealing promotion, and the greater the thermal budget, the deeper the junction depth of the body region; alternatively, the junction depth of the body region is adjusted by multiple ion implants and controlling the implant energy of each ion implant to reduce the thermal budget.
The super junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the super junction device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
The key of the invention is to adopt the full-flat technology, the invention mainly adopts the contact hole and the field oxide patterning technology is cancelled to realize the full-flat technology by combining the grid electrode leading-out structure, and the photoetching plates used for defining the grid electrode leading-out structure and the field oxide patterning can be respectively saved in the full-flat technology, so compared with the prior art, the invention can reduce two layers of photoetching layers, thereby reducing the technology cost.
In addition, although the field oxide is not patterned, the active region, namely the charge flow region, is not required to be defined by the field oxide patterning, the active region is directly defined by the formation process of the body region, and the body region of the active region and the second conductive type ring of the transition region can be formed together, so that the cost caused by independently forming the second conductive type ring can be saved.
The body region is formed after the gate structure is formed, so that segregation of doped impurities of the body region during the growth process of the gate oxide layer when the body region is formed before the gate structure is formed can be prevented, for example, for an N-type device, the body region is doped in a P type, the body region is formed after the gate structure to prevent segregation of the P type impurities, and therefore the durability of the gate structure can be improved, and potential risks in high-end applications can be prevented.
The body region can realize deeper junction depth by adopting an annealing advancing process with larger thermal budget, but the larger thermal budget can generate adverse effect on PN impurity interdiffusion on a super junction, which can increase on-resistance; the body region of the invention can also adopt an annealing advancing process with lower thermal budget, but deeper junction depths such as 2 microns are realized through multiple times of high-energy ion implantation, so that the influence on the forward conduction capacity of the device is smaller.
In the prior art, field oxide is used for passivation of the surface of a terminal area on the periphery of an active area besides the function of defining the active area, and in the invention, the field oxide is not required to be patterned and is directly used on the whole first epitaxial layer, so that the field oxide has a flat structure without climbing, and the field oxide with a flat structure without climbing is a necessary condition for realizing the full-flat process.
In the prior art, a gate extraction structure is usually realized by adopting a polysilicon pattern formed outside a gate groove, the polysilicon pattern often needs to climb over a step of field oxygen, the polysilicon pattern can cause the surface of a first epitaxial layer to be uneven, and the surface of the first epitaxial layer can not be even due to the combination of the step structure of the field oxygen, so that the prior art cannot realize a full-flat process; the invention is connected to the gate electrode structure formed by the front metal layer by directly forming the contact hole at the leading-out position of the gate structure, so that the invention does not need to adopt uneven polysilicon patterns for leading out the gate structure, the polysilicon patterns for leading out the gate structure are another necessary condition for realizing the full-flat process, and finally, the invention can realize the full-flat process by combining field oxygen of a flat structure without climbing and the polysilicon patterns for leading out the gate structure.
In addition, the grid electrode lead-out structure does not need to adopt a structure that polysilicon climbs out of the grid electrode groove and climbs up field oxygen, and the polysilicon climbs out of the grid electrode groove and climbs up field oxygen to have a weak (weak) structure that polysilicon climbs over steps, so the invention can eliminate the weak structure brought by the polysilicon climbs over steps, thereby improving the reliability of the grid electrode structure.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of a prior art superjunction structure;
FIG. 2 is a flow chart of a method of manufacturing a prior art superjunction device;
FIG. 3 is a flow chart of a method of fabricating a superjunction device according to an embodiment of the present invention;
fig. 4A-4N are schematic device structure diagrams at various steps in a method of fabricating a superjunction device according to an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a method of fabricating a superjunction device according to an embodiment of the present invention; fig. 3 illustrates a photolithography process level including a plurality of specific process steps, wherein only one photomask is used for the photolithography process. As shown in fig. 4A to 4N, a schematic device structure of the super junction device in each step of the method for manufacturing the super junction device according to the embodiment of the present invention is shown; the manufacturing method of the super junction device provided by the embodiment of the invention is realized by adopting a full-flat process and comprises the following steps:
step one, as shown in fig. 4A, a first epitaxial layer 2 having a first conductivity type is provided, the first epitaxial layer 2 being formed on a semiconductor substrate 1.
The doping concentration of the first epitaxial layer 2 is 1e14cm -3 ～1e17cm -3 . The thickness of the first epitaxial layer 2 is 5 micrometers to 100 micrometers.
Photolithography is performed using a zeroth layer mask and zeroth layer alignment marks are formed, which corresponds to the first layer photolithography process in fig. 3.
Step two, performing a super junction forming process, including:
as shown in fig. 4B, a photolithographic process is performed to define the formation region of the super junction trench 202.
As shown in fig. 4B, the first epitaxial layer 2 is etched to form a super junction trench 202.
As shown in fig. 4C, the second epitaxial layer 4 of the second conductivity type is filled in the super junction trench 202, the second epitaxial layer 4 filled in the super junction trench 202 forms second conductivity type pillars, the first epitaxial layer 2 between the second conductivity type pillars forms first conductivity type pillars, and the first conductivity type pillars and the second conductivity type pillars are alternately arranged to form the super junction.
The first planarization is performed so that the surface of the first epitaxial layer 2 on which the super junction is formed is a flat surface.
In the embodiment of the present invention, a first hard mask layer 201 is adopted in the process of forming the super junction, the first hard mask layer 201 is formed by stacking a second bottom oxide layer 201a, a middle nitride layer 201b and a top oxide layer 201c, and the process of forming the super junction when the first hard mask layer 201 is adopted includes the steps of:
as shown in fig. 4B, the first hard mask layer 201 is formed.
As shown in fig. 4B, a photolithographic process is used to define the formation region of the super junction trench 202.
As shown in fig. 4B, the first hard mask layer 201 and the first epitaxial layer 2 are etched in sequence to form the super junction trench 202.
The top oxide layer 201c of the first hard mask layer 201 is removed, a first sacrificial oxide layer is formed using a thermal oxidation process, and then the first sacrificial oxide layer is removed.
As shown in fig. 4C, the intermediate nitride layer 201b of the first hard mask layer 201 is removed.
As shown in fig. 4C, the second epitaxial layer 4 is formed by performing epitaxial filling in the super junction trench 202.
As shown in fig. 4D, the first planarization is performed by performing a chemical mechanical polishing process on the second epitaxial layer 4, so that the second epitaxial layer 4 is only filled in the super junction trench 202.
The second bottom oxide layer 201a of the first hard mask layer 201 is removed entirely or only partially.
Step two corresponds to the second layer photolithography process in fig. 3.
Step three, forming the gate structure, wherein the gate structure is a trench gate, and the formation process of the trench gate comprises the following steps:
as shown in fig. 4E, a photolithography process is performed on the first epitaxial layer 2, on which the super junction is formed and the surface of which is flat, to define a formation region of the gate trench 203.
As shown in fig. 4E, the first epitaxial layer 2 is etched to form the gate trench 203, and the width of the gate trench 203 at the extraction position of the gate structure meets the requirement of forming the contact hole 10. The cross-sectional views corresponding to the extraction positions of the gate structures are shown in fig. 4K and 4N.
As shown in fig. 4E, a gate oxide layer 5 is formed on the side surface of the gate trench 203, and a bottom oxide layer is formed on the bottom surface of the gate trench 203.
As shown in fig. 4F, the gate trench 203 is filled with the polysilicon gate 6, and the trench gate is composed of the gate oxide layer 5, the bottom oxide layer, and the polysilicon gate 6 formed in the gate trench 203. In fig. 4K and 4N, the polysilicon gate at the exit position of the gate structure is denoted by reference numeral 6a alone.
A second planarization is performed so that the surface of the first epitaxial layer 2 on which the trench gate is formed is a flat surface.
Step three corresponds to the third layer photolithography process in fig. 3.
In this embodiment of the present invention, the photolithography process for defining the gate trench 203 further includes a step of forming a second hard mask layer on the surface of the first epitaxial layer 2, and then etching the second hard mask layer and then etching the first epitaxial layer 2 to form the gate trench 203.
The second planarization stops on the second hard mask layer and then the second hard mask layer is removed.
The method further comprises the step of rounding the gate trench 203 after the etching of the gate trench 203 is completed and before the forming of the gate oxide layer 5, wherein the rounding comprises:
and forming a second sacrificial oxide layer by adopting a thermal oxidation process.
And removing the second sacrificial oxide layer.
The gate oxide layer 5 is formed on the side surface of the gate trench 203 by a thermal oxidation process. The gate oxide layer 5 will also extend to the surface of the first epitaxial layer 2 outside the gate trench 203.
The bottom oxide layer and the gate oxide layer 5 are formed simultaneously by the same process. The thickness of the bottom oxide layer is greater than that of the gate oxide layer 5, and the bottom oxide layer and the gate oxide layer 5 are formed separately.
The second planarization is realized by adopting a back etching process or a chemical mechanical polishing process.
The thickness of the gate oxide layer 5 on the surface of the first epitaxial layer 2 after the second planarization is required to be kept about
Step four, as shown in fig. 4G, an ion implantation and annealing advancing process is used to form a body region 3, where a formation region of the body region 3 is defined by photolithography, and this step corresponds to the fourth layer photolithography process in fig. 3.
The superjunction device includes a charge flow region, a transition region, and a termination region; the body region 3 is formed in the charge flow region, and a second conductivity type ring is also formed in the transition region at the same time as the body region 3 is formed.
In the embodiment of the invention, the junction depth of the body region 3 is adjusted by controlling the thermal budget of the annealing promotion, and the greater the thermal budget, the deeper the junction depth of the body region 3; alternatively, the junction depth of the body region 3 is adjusted by ion implantation a plurality of times and controlling the implantation energy of each ion implantation, such as adjusting the junction depth of the body region 3 to 2 μm, to reduce the thermal budget.
The step of forming a heavily doped source region 7 of the first conductivity type then further comprises the steps of:
as shown in fig. 4H, an ion implantation and annealing promotion process is used to form a source region 7, where a formation region of the source region 7 is defined by photolithography, and in the device unit region, the source region 7 and a corresponding side surface of the gate structure are self-aligned.
The step of forming the source region 7 corresponds to the fifth layer lithography process in fig. 3.
Step five, as shown in fig. 4H, a field oxide 8 is formed, the field oxide 8 is covered on the first epitaxial layer 2 formed with the super junction and the trench gate and having a flat surface, and the field oxide 8 has a flat structure without climbing.
The field oxide 8 is composed of an oxide layer 8b formed by a thermal oxide layer 8a superimposed with a TEOS oxidation process, for example, the thermal oxide layer 8a has a thickness ofThe thickness of the oxide layer 8b is +.>Typical value is +.>In other embodiments can also be: the field oxide 8 consists of a thermal oxide layer 8a, in which case a large thermal process occurs.
After the fifth step is completed, the method further comprises the steps of:
as shown in fig. 4J, an interlayer film 9 is formed. The interlayer film 9 covers the flat surface of the field oxide 8.
The interlayer film 9 is formed by using USG oxidation process or TEOS oxidation process. The thickness of the interlayer film 9 isTypical value is +.>
A contact hole 10 is formed, the contact hole 10 penetrating the interlayer film 9 and the field oxide 8. The formation area of the contact hole 10 is defined by photolithography, and the corresponding contact hole 10 is formed at the extraction position of the gate structure.
The contact hole 10 is formed on top of the source region 7. As shown in fig. 4K, the contact hole 10 is also formed on top of the polysilicon gate 6a serving as the lead-out of the gate structure.
Generally, after the opening of the contact hole 10 is opened, a step of performing a second conductive type heavily doped ion implantation to form a body region leading-out region is further included, and then, a metal such as tungsten is filled in the opening of the contact hole 10 to form the contact hole 10, wherein the tungsten-filled contact hole 10 is also called a tungsten plug.
The process of forming the contact hole 10 corresponds to the sixth layer photolithography process in fig. 3.
As shown in fig. 4L, a front metal layer 11 is formed, and the front metal layer 11 is patterned by using a photolithography definition and etching process, and an electrode formed by the patterned front metal layer 11 includes a gate electrode structure and a source electrode, where the gate electrode structure contacts the polysilicon gate 6 through the contact hole 10 at the lead-out position of the gate structure. The gate electrode structure includes a gate bus and a gate pad, the gate bus being shown in fig. 4M. The front side metal layer 11 and the corresponding patterning process correspond to the seventh layer lithography process in fig. 3.
As shown in fig. 4L, a contact pad is formed, and a formation region of the contact pad is defined by photolithography. The contact pad includes a source pad and the gate pad. The formation process of the contact pad corresponds to the eighth layer photolithography process in fig. 3.
And finishing the back surface process of the super junction device.
As shown in fig. 4M, the semiconductor substrate 1 is thinned on the back side.
The semiconductor substrate 1 is heavily doped with the first conductivity type, and the thinned semiconductor substrate 1 is directly used as a heavily doped drain region of the first conductivity type; or the thinned semiconductor substrate 1 is subjected to back implantation of first conductivity type heavy doping to form a drain region.
As shown in fig. 4L, a back metal layer 12 is formed on the back of the drain region.
In the embodiment of the invention, the super junction device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments can also be: the super junction device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.
The key point of the embodiment of the invention is that the full-flat process is adopted, the full-flat process is realized mainly by adopting the contact hole 10 in combination with the grid electrode lead-out structure and the patterning process of the field oxide 8 is omitted, and the photoetching plates for defining the grid electrode lead-out structure and the patterning of the field oxide 8 can be respectively saved in the full-flat process, so that compared with the prior art, the embodiment of the invention can reduce two layers of photoetching layers, thereby reducing the process cost.
In addition, although the field oxide 8 is not patterned in the embodiment of the present invention, the active region 7, that is, the charge flow region, is not required to be defined by patterning the field oxide 8, and the active region 7 in the embodiment of the present invention is directly defined by the formation process of the body region 3, and the body region 3 of the active region 7 and the second conductivity type ring of the transition region can be formed together, so that the cost caused by separately forming the second conductivity type ring can be saved.
The body region 3 is formed after the gate structure is formed, so that segregation of impurities doped in the body region 3 during the growth process of the gate oxide layer when the body region 3 is formed before the gate structure is formed can be prevented, for example, for an N-type device, the body region 3 is doped in a P-type mode, segregation of the impurities in the P-type can be prevented when the body region 3 is formed after the gate structure is formed, the durability of the gate structure can be improved, and potential risks in high-end applications can be prevented.
The body region 3 of the embodiment of the invention can realize deeper junction depth by adopting an annealing advancing process with larger thermal budget, but the larger thermal budget can generate adverse effect of PN impurity interdiffusion on the super junction, which can increase on-resistance; the body region 3 of the embodiment of the invention can also adopt an annealing advancing process with lower thermal budget, but a deeper junction depth such as 2 micrometers is realized through multiple times of high-energy ion implantation, so that the influence on the forward conduction capability of the device is smaller.
In the prior art, the field oxide 8 is used for passivation of the surface of the termination area on the peripheral side of the active area 7 in addition to the function of defining the active area 7, and in the embodiment of the invention, the field oxide 8 is not required to be patterned because the field oxide 8 is not required to define the active area 7, and the field oxide 8 formed on the whole first epitaxial layer 2 is directly adopted, so that the field oxide 8 has a flat structure without climbing, and the field oxide 8 with a flat structure without climbing is a necessary condition for realizing the full-leveling process in the embodiment of the invention.
In the prior art, the gate lead-out structure is usually implemented by a polysilicon pattern formed outside the gate trench 203, and the polysilicon pattern often needs to climb over the step of the field oxide 8, the polysilicon pattern itself can make the surface of the first epitaxial layer 2 uneven, and the combination of the step structure of the field oxide 8 can make the surface of the first epitaxial layer 2 more unable to be flat, so that the prior art cannot implement a full-flat process; the embodiment of the invention is connected to the gate electrode structure formed by the front metal layer 11 by directly forming the contact hole 10 at the lead-out position of the gate structure, so that the embodiment of the invention does not need to adopt uneven polysilicon patterns for leading out the gate structure, does not adopt the polysilicon patterns for leading out the gate structure as another necessary condition for realizing the full-flat process of the embodiment of the invention, combines the field oxygen 8 of the flat structure without climbing and does not adopt the polysilicon patterns for leading out the gate structure, and finally can realize the full-flat process.
In addition, the gate lead-out structure in the embodiment of the invention does not need to adopt a structure that polysilicon climbs out of the gate groove and climbs up field oxygen, and the polysilicon climbs out of the gate groove and climbs up field oxygen to have a weak (weak) structure that polysilicon climbs over steps, so the embodiment of the invention can eliminate the weak structure brought by the polysilicon climbs over steps, thereby improving the reliability of the gate structure.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. The manufacturing method of the super junction device is characterized by adopting a full-flat process, and comprises the following steps:
step one, photoetching by adopting a zeroth layer photomask and forming a zeroth layer alignment mark;
step two, performing a super junction forming process, including:
providing a first epitaxial layer with a first conductivity type, and defining a forming area of a super junction groove by performing a photoetching process;
etching the first epitaxial layer to form a super junction groove;
filling a second epitaxial layer of a second conductivity type in the super junction trench, forming second conductivity type columns by the second epitaxial layer filled in the super junction trench, forming first conductivity type columns by the first epitaxial layer between the second conductivity type columns, and alternately arranging the first conductivity type columns and the second conductivity type columns to form the super junction;
performing first planarization to make the surface of the first epitaxial layer with the super junction formed be a flat surface;
step three, forming a gate structure, wherein the gate structure is a trench gate, and the formation process of the trench gate comprises the following steps:
performing a photoetching process on the first epitaxial layer with the super junction formed and the flat surface to define a forming area of a grid groove;
etching the first epitaxial layer to form the gate groove, wherein the width of the gate groove at the leading-out position of the gate structure meets the requirement of forming a contact hole;
forming a gate oxide layer on the side surface of the gate trench, and forming a bottom oxide layer on the bottom surface of the gate trench;
filling a polysilicon gate in the gate trench, wherein the gate oxide layer, the bottom oxide layer and the polysilicon gate formed in the gate trench form the trench gate;
performing second planarization to make the surface of the first epitaxial layer formed with the trench gate be a flat surface;
forming a body region by adopting ion implantation and annealing propulsion processes, wherein the formation region of the body region is defined by photoetching;
the superjunction device includes a charge flow region, a transition region, and a termination region; the body region is formed in the charge flow region, the body region being formed simultaneously with the formation of the body region and also forming a second conductivity type ring in the transition region;
and fifthly, forming field oxide, wherein the field oxide is covered on the first epitaxial layer which is formed with the super junction and the trench gate and has a flat surface, and the field oxide has a flat structure without climbing.
2. The method of fabricating a superjunction device according to claim 1, wherein: the method further comprises the following steps of forming a first conductive type heavily doped source region after the body region is formed in the fourth step and before the field oxide is formed in the fifth step:
and forming a source region by adopting an ion implantation and annealing advancing process, wherein a forming region of the source region is defined by photoetching, and the source region and the corresponding side surface of the grid structure are self-aligned in the device unit region.
3. The method of fabricating a superjunction device according to claim 1, wherein: after the fifth step is completed, the method further comprises the steps of:
forming an interlayer film and a contact hole, wherein the forming area of the contact hole is defined through photoetching, and the corresponding contact hole is formed at the leading-out position of the grid structure;
forming a front metal layer, patterning the front metal layer by adopting a photoetching definition and etching process, wherein an electrode formed by the patterned front metal layer comprises a gate electrode structure, and the gate electrode structure is contacted with the polysilicon gate through the contact hole at the leading-out position of the gate structure;
forming a contact pad, wherein a forming area of the contact pad is defined by lithography;
and finishing the back surface process of the super junction device.
4. A method of fabricating a superjunction device according to claim 3, wherein: the contact holes are realized by tungsten bolts.
5. A method of fabricating a superjunction device according to claim 3, wherein: the field oxygen consists of a thermal oxide layer or an oxide layer formed by a thermal oxide layer laminating TEOS oxidation process.
6. The method of fabricating a superjunction device according to claim 5, wherein: the interlayer film covers the flat surface of the field oxide;
the interlayer film is formed by adopting a USG oxidation process or a TEOS oxidation process.
7. The method of fabricating a superjunction device according to claim 1, wherein: in the second step, a first hard mask layer is adopted in the formation process of the super junction, the first hard mask layer is formed by laminating a second bottom oxide layer, a middle nitride layer and a top oxide layer, and the formation process of the super junction when the first hard mask layer is adopted comprises the following steps:
forming the first hard mask layer;
defining a forming area of the super junction groove by adopting a photoetching process;
etching the first hard mask layer and the first epitaxial layer in sequence to form the super junction groove;
removing the top oxide layer of the first hard mask layer, forming a first sacrificial oxide layer by adopting a thermal oxidation process, and then removing the first sacrificial oxide layer;
removing the middle nitride layer of the first hard mask layer;
performing epitaxial filling in the super junction groove to form a second epitaxial layer;
carrying out chemical mechanical polishing on the second epitaxial layer to realize the first planarization, so that the second epitaxial layer is only filled in the super junction groove;
and completely removing the second bottom oxide layer of the first hard mask layer or removing only part of the thickness.
8. A method of fabricating a superjunction device according to claim 3, wherein: the first epitaxial layer is formed on a semiconductor substrate, and the back side process of the super junction device comprises the following steps:
thinning the back surface of the semiconductor substrate;
the semiconductor substrate is heavily doped with the first conduction type, and the thinned semiconductor substrate is directly used as a heavily doped drain region of the first conduction type; or carrying out back injection of first conductivity type heavy doping on the thinned semiconductor substrate to form a drain region;
and forming a back metal layer on the back of the drain region.
9. The method of fabricating a superjunction device according to claim 1, wherein: step three, the step of forming a second hard mask layer on the surface of the first epitaxial layer before the photoetching process for defining the gate trench is carried out, and then etching the second hard mask layer and then etching the first epitaxial layer to form the gate trench;
the second planarization stops on the second hard mask layer and then the second hard mask layer is removed.
10. The method of fabricating a superjunction device according to claim 1, wherein: in the third step, after the etching of the gate trench is completed and before the forming of the gate oxide layer, the method further includes a step of rounding the gate trench, where the rounding includes:
forming a second sacrificial oxide layer by adopting a thermal oxidation process;
and removing the second sacrificial oxide layer.
11. The method of fabricating a superjunction device according to claim 10, wherein: the gate oxide layer is formed on the side surface of the gate groove by adopting a thermal oxidation process.
12. The method of fabricating a superjunction device of claim 11, wherein: the bottom oxide layer and the gate oxide layer are formed simultaneously by adopting the same process;
alternatively, the thickness of the bottom oxide layer is greater than the thickness of the gate oxide layer, and the bottom oxide layer and the gate oxide layer are formed separately.
13. The method of fabricating a superjunction device according to claim 1, wherein: the second planarization is realized by adopting a back etching process or a chemical mechanical polishing process.
14. The method of fabricating a superjunction device according to claim 1, wherein: in the fourth step, the junction depth of the body region is adjusted by controlling the thermal budget of the annealing propulsion, and the greater the thermal budget, the deeper the junction depth of the body region; alternatively, the junction depth of the body region is adjusted by multiple ion implants and controlling the implant energy of each ion implant to reduce the thermal budget.
15. A method of fabricating a superjunction device according to any of claims 1-14, characterised in that: the super junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the super junction device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
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