CN112447844A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN112447844A
CN112447844A CN201910825434.8A CN201910825434A CN112447844A CN 112447844 A CN112447844 A CN 112447844A CN 201910825434 A CN201910825434 A CN 201910825434A CN 112447844 A CN112447844 A CN 112447844A
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layer
gate
forming
grid
etching
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曾大杰
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The invention discloses a manufacturing method of a semiconductor device, which comprises the following steps: step one, forming a grid groove in a semiconductor substrate; step two, forming a gate dielectric layer; step three, forming a grid conductive material layer; fourthly, carrying out back etching on the grid conductive material layer to form a first self-aligned back etching groove at the top of the grid groove area; step five, forming a channel region; sixthly, forming a source region; step seven, filling a first dielectric layer in the first self-aligned etching-back groove; eighthly, back-etching the semiconductor material in the semiconductor platform area by taking the first dielectric layer as a self-alignment condition to form a second self-alignment back-etching groove; step nine, forming a side wall for defining the source contact hole in a self-alignment manner on the inner side surface of the second self-alignment back-etching groove; and step ten, forming an interlayer film, a contact hole and a front metal layer and patterning to form a grid electrode and a source electrode. The invention can define the contact hole on the top of the source region in a self-alignment way, thereby reducing the step of the device and reducing the specific on-resistance of the device.

Description

Method for manufacturing semiconductor device
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a semiconductor device.
Background
As shown in fig. 1, a schematic structural diagram of a conventional trench gate MOSFET device includes: highly doped semiconductor substrates such as silicon substrate 1, the resistivity of silicon substrate 1 is typically between 0.001 Ω cm and 0.002 Ω cm, and the thickness of silicon substrate 1 is also desirably as thin as possible to reduce the substrate resistance.
An epitaxial layer such as a silicon epitaxial layer 2 is formed on the surface of the silicon substrate 1, and the thickness and doping concentration of the silicon epitaxial layer 2 determine the device voltage of the device. The higher the breakdown voltage of the device, the thicker the required thickness of the silicon epitaxial layer 2 and the lower the doping concentration. Typically, the thickness of the silicon epitaxial layer 2 is between 2 μm and 15 μm and the resistivity of the silicon epitaxial layer 2 is between 0.1 Ω cm and 2 Ω cm. The silicon epitaxial layer 2 can be a single-layer structure, and the resistivity is consistent in the whole epitaxial layer; the silicon epitaxial layer 2 may also be a two-layer structure with a Buffer layer (Buffer) located in the contact area between the silicon epitaxial layer 2 and the silicon substrate 1, the Buffer layer typically having a relatively low resistivity. The silicon epitaxial layer 2 may also be a multilayer structure.
The trench gate includes a gate dielectric layer such as a gate oxide layer 3 and a gate conductive material layer such as a polysilicon gate 9 formed in a gate trench. The lower the breakdown voltage of the device, the thinner the thickness of the gate oxide layer 3. For an N-type trench gate MOSFET, the polysilicon gate 9 is typically heavily N-doped; for a P-type trench gate MOSFET, the polysilicon gate 9 is typically formed with a P-type heavy doping.
A channel region 4 is formed on the surface of the silicon epitaxial layer 2, and the doping concentration of the channel region 4 determines the threshold voltage of the device. In practice, the depth of the gate trench is typically between 0.1 μm and 0.2 μm deeper than the depth of the channel region 4.
A heavily doped source region 5 is formed at the surface of the channel region 4.
An interlayer film 6 and a front metal layer 7, the interlayer film 6 typically being an oxide layer. In order to reduce the on-resistance of the power MOSFET, the top metal layer 7 is usually thicker, and is currently more than 4 μm.
Via or contact holes 8, typically the front-side metal layer 7 comprises a plurality of layers, the connections of the first front-side metal layer 7 to the bottom doped regions, such as the source region 5 and the channel region 4, being connected via the contact holes; the connections between the front metal layers 7 are connected through vias, only one front metal layer 7 is shown in fig. 1, and the corresponding marks 8 are contact holes. The front metal layer 7, after patterning, forms a source and a gate, the source being connected to the source region 5 and the channel region 4 via corresponding contact holes 8.
The current flowing area of the trench gate MOSFET device is formed by a plurality of original cells which are periodically arranged, the trench gate usually extends to a gate lead-out area outside the current flowing area, and is connected to a gate formed by a front metal layer 7 through a contact hole 8 formed at the top of a polysilicon gate 9 in the gate lead-out area.
The on-resistance of a trench-gate MOSFET is strongly correlated with the density of trenches, i.e. gate trenches, the larger the trench density, the lower the on-resistance of the trench-gate MOSFET. Therefore, it is desirable to increase the trench density as much as possible in the process. The trench density is determined by:
the width of the trench is mainly related to the accuracy of the lithography and the etching depth of the trench.
The trench-to-trench distance is also known as the width of the Mesa region (Mesa). The width of Mesa is determined by the size of the contact hole and the distance between the contact hole and the trench. The size of the contact hole is determined by the accuracy of photolithography, i.e., the top width d1 of the trench in fig. 1, and the distance between the contact hole and the trench, i.e., the distance d2 in fig. 1, needs to be ensured. In addition, the position of the contact hole is also affected by the lithographic alignment accuracy. This all results in a relatively wide Mesa width.
For a typical trench-gate MOSFET, the width of the trench can be made 0.2 μm at the minimum, the width of Mesa can be 0.6 μm, the width of the contact hole can be 0.2 μm, and the corresponding step (Pitch), i.e. the sum of the width of one trench and the Pitch of one trench, can be made 0.8 μm.
Disclosure of Invention
The present invention provides a method for fabricating a semiconductor device, which can define a contact hole at the top of a source region in a self-aligned manner, thereby reducing the step size of the device and reducing the specific on-resistance of the device.
In order to solve the above technical problem, the method for manufacturing a semiconductor device provided by the present invention comprises the steps of:
providing a semiconductor substrate, wherein the top surface of the semiconductor substrate is a first surface; forming a plurality of grid grooves in the semiconductor substrate by adopting a photoetching definition and etching process, wherein the region between every two adjacent grid grooves is a semiconductor platform region; in a current flowing region of the semiconductor device, a forming region of one cell is composed of one of the gate trenches and an adjacent one of the semiconductor mesa regions, and the current flowing region is composed of a plurality of cells arranged periodically.
And step two, forming a gate dielectric layer, wherein the gate dielectric layer is formed on the bottom surface and the side surface of the gate groove and extends to the surface outside the gate groove.
And step three, forming a gate conductive material layer, wherein the gate conductive material layer completely fills the gate trench and extends to the surface outside the gate trench.
And fourthly, carrying out first self-alignment back-etching on the grid conductive material layer, wherein the first self-alignment back-etching completely removes the grid conductive material layer on the outer surface of the grid groove, back-etches the top surface of the grid conductive material layer in the grid groove area to be lower than the first surface and forms a first self-alignment back-etching groove.
And step five, forming a channel region in the semiconductor platform region.
And sixthly, forming a source region on the surface of the channel region, wherein the channel region at the bottom of the source region is covered by the side surface of the gate conductive material layer, and the surface of the channel region covered by the side surface of the gate conductive material layer is used for forming a channel.
And step seven, filling a first dielectric layer in the first self-aligned back-etching groove.
And eighthly, carrying out back etching on the semiconductor material in the semiconductor platform area by taking the first dielectric layer as a self-alignment condition to form a second self-alignment back etching groove, wherein the bottom surface of the second self-alignment back etching groove is lower than the first surface, and the source area is positioned below the bottom surface of the second self-alignment back etching groove.
And ninthly, forming a side wall consisting of the second dielectric layer on the inner side surface of the second self-aligned etching-back groove, and defining a source contact hole at the top of the source region by self-alignment of the side wall.
Forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a grid electrode and a source electrode; the grid electrode is connected with the grid conductive material layer through the grid contact hole, and the source electrode is connected with the source region through the source contact hole.
In a further improvement, in the first step, the semiconductor material composing the semiconductor substrate comprises silicon and silicon carbide.
In the second step, the gate dielectric layer is a gate oxide layer; the gate dielectric layer is formed by adopting a thermal oxidation process.
The grid conductive material layer is a polysilicon grid.
In a further improvement, the sub-step of forming the gate trench includes:
and forming a hard mask layer on the surface of the semiconductor substrate.
And defining a forming area of the gate trench by photoetching.
And sequentially carrying out anisotropic etching on the hard mask layer and the semiconductor substrate to form the gate groove.
The further improvement is that after the gate trench is formed, isotropic etching is performed to process the gate trench so as to round the corners of the gate trench; or, after the gate trench is formed, a process of forming a sacrificial oxide layer and removing the sacrificial oxide layer is further included to round corners of the gate trench.
In a further improvement, the hard mask layer is made of an oxide layer, a nitride layer or a oxynitride layer; the hard mask layer is removed after the gate trench is formed and before the channel region is formed in step five.
In a further improvement, in step five, a channel implantation plus annealing drive-in process is used to form the channel region.
In a further improvement, the material of the first dielectric layer includes an oxide layer, a nitride layer or a oxynitride layer.
The further improvement is that in the ninth step, the material of the second dielectric layer and the material of the interlayer film have an etching rate difference and meet the condition of selective etching; the sub-steps of forming the side wall in the ninth step include:
and comprehensively depositing to form a second dielectric layer.
And comprehensively etching the second dielectric layer to form the side wall on the inner side surface of the second self-aligned back-etching groove.
In a further improvement, the interlayer film is made of an oxide layer; the material of the second dielectric layer comprises a nitride layer.
In a further improvement, the trench gate MOSFET further has a shielding layer, and the step of forming the shielding layer before forming the gate dielectric layer and the gate conductive material layer is further included, and the steps are respectively:
and forming a shielding dielectric layer.
And forming the shielding layer by adopting a deposition and etch-back process.
And forming an inter-gate isolation dielectric layer on the top surface of the shielding layer.
The shielding layer is formed in the grid groove at the bottom of the grid conductive material layer, the material of the shielding layer is the same as that of the grid conductive material layer, a shielding dielectric layer is isolated between the shielding layer and the bottom surface and the side face of the grid groove, and an inter-grid isolation dielectric layer is isolated between the shielding layer and the grid conductive material layer.
In a ninth step, after the forming of the side walls, the semiconductor substrate at the bottoms of the source contact holes is etched under the self-alignment condition of the side walls, so that the bottoms of the source contact holes penetrate through the source regions and are connected with the channel regions, and the source regions and the channel regions are simultaneously connected to the source electrodes through the source contact holes.
In a further improvement, a gate lead-out region is further formed outside the current flowing region, the trench gate of the current flowing region further extends into the gate lead-out region, a gate contact hole is formed at the top of the gate conductive material layer in the gate lead-out region, and the gate conductive material layer and the gate composed of the front metal layer are connected through the gate contact hole.
The further improvement is that the semiconductor device is a MOSFET device, and after the step ten is completed, the following back surface process is also included:
step eleven, thinning the back surface of the semiconductor substrate, forming a drain region on the back surface of the semiconductor substrate, and forming a drift region by the semiconductor substrate between the drain region and the channel region.
And step twelve, forming a back metal layer on the back of the drain region and forming a drain electrode by the back metal layer.
The semiconductor device is an N-type device, the channel region is doped in a P type manner, and the source region is heavily doped in an N type manner; the semiconductor device is a P-type device, the channel region is N-type doped, and the source region is P-type heavily doped.
Aiming at the defects that the size of a source contact hole is reduced and the reduction of the space between the source contact hole and an adjacent groove grid is limited when the contact hole at the top of a source region, namely the source contact hole, is defined by photoetching in the prior art, the invention utilizes the fact that the top of a grid conductive material layer of the groove grid can be self-aligned back-etched so as to form a first self-aligned back-etched groove at the top of the grid conductive material layer, and conversely, after a first dielectric layer is filled in the first self-aligned back-etched groove, the self-aligned etching can be carried out on a semiconductor platform region to form a second self-aligned back-etched groove; a side wall process is adopted to form side walls on the inner side surfaces of the second self-alignment back-etching grooves, the side walls can be self-aligned to open the middle part of the source region, so that the self-alignment definition of the source contact hole is realized, the width of the source contact hole is self-aligned to be defined by the width of the side walls on the two inner side surfaces of the second self-alignment back-etching grooves, and meanwhile, the distance between the source contact hole and the groove gate is self-aligned to be defined by the width of the side walls; since the width of the source contact hole and the distance between the source contact hole and the trench gate are defined by self-alignment, the invention can reduce the step size of the device and further reduce the specific on-resistance of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art trench gate MOSFET device;
fig. 2 is a flowchart of a method of manufacturing a semiconductor device according to a first embodiment of the present invention;
fig. 3A to 3I are schematic views of device structures in respective steps of a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
Detailed Description
As shown in fig. 2, is a flowchart of a method of manufacturing a semiconductor device according to a first embodiment of the present invention; fig. 3A to 3I are schematic views of the device structure in the steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. The method for manufacturing a semiconductor device according to the first embodiment of the present invention includes the steps of:
step one, as shown in fig. 3A, providing a semiconductor substrate 101, wherein a top surface of the semiconductor substrate 101 is a first surface; forming a plurality of gate trenches 201 in the semiconductor substrate 101 by using a lithography definition and etching process, wherein a region between every two adjacent gate trenches 201 is a semiconductor platform region; in the current flowing region of the semiconductor device, a cell forming region is composed of one of the gate trenches 201 and an adjacent one of the semiconductor mesa regions, and the current flowing region is composed of a plurality of cells arranged periodically.
The semiconductor material constituting the semiconductor substrate 101 includes silicon, silicon carbide.
The sub-steps of forming the gate trench 201 include:
and forming a hard mask layer on the surface of the semiconductor substrate 101.
The formation region of the gate trench 201 is defined by photolithography.
And sequentially carrying out anisotropic etching on the hard mask layer and the semiconductor substrate 101 to form the gate trench 201.
After the gate trench 201 is formed, performing isotropic etching to process the gate trench 201 to round corners of the gate trench 201; alternatively, after the gate trench 201 is formed, a process of forming a sacrificial oxide layer and removing the sacrificial oxide layer is further included to round the corners of the gate trench 201.
The hard mask layer is made of an oxide layer, a nitride layer or a oxynitride layer; the hard mask layer is removed after the gate trench 201 is formed and before the channel region 105 is formed in the next step five.
Step two, as shown in fig. 3B, a gate dielectric layer 102 is formed, where the gate dielectric layer 102 is formed on the bottom surface and the side surface of the gate trench 201 and extends to the surface outside the gate trench 201.
The gate dielectric layer 102 is a gate oxide layer; the gate dielectric layer 102 is grown by a thermal oxidation process.
Step three, as shown in fig. 3B, forming a gate conductive material layer 103, wherein the gate conductive material layer 103 completely fills the gate trench 201 and extends to the surface outside the gate trench 201.
The gate conductive material layer 103 is a polysilicon gate.
Step four, as shown in fig. 3B, performing a first self-aligned etchback on the gate conductive material layer 103, where the first self-aligned etchback completely removes the gate conductive material layer 103 on the outer surface of the gate trench 201, and etchback the top surface of the gate conductive material layer 103 in the region of the gate trench 201 to a position lower than the first surface to form a first self-aligned etchback 202.
Step five, as shown in fig. 3C, a channel region 105 is formed in the semiconductor mesa region.
A channel implant plus anneal drive-in process is used to form the channel region 105.
Sixthly, as shown in fig. 3D, forming a source region 106 on the surface of the channel region 105, wherein the channel region 105 at the bottom of the source region 106 is covered by the side surface of the gate conductive material layer 103, and the surface of the channel region 105 covered by the side surface of the gate conductive material layer 103 is used for forming a channel.
Step seven, as shown in fig. 3E, the first dielectric layer 104 is filled in the first self-aligned back-etching trench 202.
The material of the first dielectric layer 104 includes an oxide layer, a nitride layer, or an oxynitride layer.
Step eight, as shown in fig. 3F, performing a back etching on the semiconductor material in the semiconductor platform region under the self-aligned condition of the first dielectric layer 104 to form a second self-aligned back etching trench 203, where a bottom surface of the second self-aligned back etching trench 203 is lower than the first surface and the source region 106 is located below the bottom surface of the second self-aligned back etching trench 203.
Step nine, as shown in fig. 3G, a sidewall 107 composed of the second dielectric layer is formed on the inner side surface of the second self-aligned back-etching trench 203, and the source contact hole 109 at the top of the source region 106 is defined by self-alignment of the sidewall 107.
The sub-steps of forming the side wall 107 include:
and comprehensively depositing to form a second dielectric layer.
And comprehensively etching the second dielectric layer to form the side wall 107 on the inner side surface of the second self-aligned back-etching trench 203.
And step nine, the material of the second dielectric layer and the material of the interlayer film 108 formed subsequently have an etching rate difference and meet the condition of selective etching. Preferably, the material of the interlayer film 108 is an oxide layer; the material of the second dielectric layer comprises a nitride layer.
In the first embodiment of the present invention, after the forming of the sidewall 107, etching the semiconductor substrate 101 at the bottom of the source contact 109 under the self-aligned condition of the sidewall 107 to make the bottom of the source contact 109 penetrate through the source region 106 and connect with the channel region 105, and the source region 106 and the channel region 105 are simultaneously connected to the source electrode through the source contact 109.
Step ten, as shown in fig. 3H, forming an interlayer film 108, a contact hole 109 and a front metal layer 110, and patterning the front metal layer 110 to form a gate and a source; the gate is connected to the gate conductive material layer 103 through a gate contact hole 109, and the source is connected to the source region 106 through a source contact hole 109.
A gate lead-out region is further formed outside the current flow region, the trench gate of the current flow region further extends into the gate lead-out region, a gate contact hole is formed at the top of the gate conductive material layer 103 in the gate lead-out region, and the gate conductive material layer 103 and the gate composed of the front metal layer 110 are connected through the gate contact hole.
In the method according to the first embodiment of the present invention, the contact hole formed in the tenth step includes forming the top portion of the source contact hole 109 and the gate contact hole. The bottom portion of the source contact hole 109 is defined by the self-alignment of the sidewall formed in the ninth step, the top portion of the source contact hole 109 passes through the interlayer film 108, and the gate contact hole also passes through the interlayer film 108.
The semiconductor device is an MOSFET device, and the step ten is completed and then the following back surface process is included:
step eleven, as shown in fig. 3I, thinning the back surface of the semiconductor substrate 101, forming a drain region 111 on the back surface of the semiconductor substrate 101, and forming a drift region by the semiconductor substrate 101 between the drain region 111 and the channel region 105.
Step twelve, forming a back metal layer 112 on the back of the drain region 111 and forming a drain electrode by the back metal layer 112.
In the method according to the first embodiment of the present invention, the semiconductor device is an N-type device, the channel region 105 is P-type doped, the source region 106 and the drain region 111 are both N-type heavily doped, and the drift region is N-type doped. In other embodiments the method can also be: the semiconductor device is a P-type device, the channel region 105 is doped in an N-type manner, the source region 106 and the drain region 111 are both doped in a P-type manner, and the drift region is doped in a P-type manner.
Aiming at the defects that the size of a source contact hole 109 is reduced and the reduction of the distance between the source contact hole 109 and an adjacent trench gate is limited when the contact hole 109 at the top of a source region 106, namely the source contact hole 109, is defined by photoetching in the prior art, the first embodiment of the invention utilizes the fact that the top of a gate conductive material layer 103 of the trench gate can be self-aligned and etched back so as to form a first self-aligned back-etched trench 202 at the top of the gate conductive material layer 103, and conversely, after a first dielectric layer 104 is filled in the first self-aligned back etched trench 202, the self-aligned etching can be carried out on a semiconductor platform region so as to form a second self-aligned back etched trench 203; the sidewall 107 can be formed on the inner side surface of the second self-aligned back-etching trench 203 by using a sidewall 107 process, the sidewall 107 can be self-aligned to open the middle part of the source region 106, so that the self-aligned definition of the source contact hole 109 is realized, that is, the width of the source contact hole 109 is self-aligned defined by the widths of the sidewalls 107 on the two inner side surfaces of the second self-aligned back-etching trench 203, and meanwhile, the distance between the source contact hole 109 and the trench gate is self-aligned defined by the width of the sidewall 107; since the width of the source contact hole 109 and the pitch of the trench gate are defined by self-alignment, the first embodiment of the present invention can reduce the step size of the device and thus reduce the specific on-resistance of the device.
To more clearly illustrate the method of the first embodiment of the present invention, the method of the first embodiment of the present invention will now be further described with reference to specific parameters:
take a semiconductor device with a breakdown voltage of 20V and a cell step of 0.5 μm, i.e., a MOSFET device corresponding to the first embodiment of the present invention as an example: for low voltage MOSFETs, a highly doped phosphorous semiconductor substrate 101 is typically used, rather than a highly doped arsenic semiconductor substrate, because phosphorous doped semiconductor substrates achieve a lower minimum resistivity than arsenic doped semiconductor substrates. Currently, phosphorus doped semiconductor substrates can have a minimum resistivity of 0.7 to 0.9m Ω cm, while arsenic substrates have a minimum resistivity of 1.0 to 1.5m Ω cm. Low voltage devices have a large proportion of the total on-resistance of the substrate because of their lower on-resistance, and lower substrate resistance becomes more important.
An epitaxial layer is formed on the semiconductor substrate 101. to reduce the back-diffusion of the high concentration phosphorus substrate, an epitaxial layer is sometimes added, the thickness of the epitaxial layer is usually between 1 μm and 2 μm, and the corresponding resistivity is usually between 0.02 Ω cm and 0.05 Ω cm. The resistivity and thickness of the epitaxial layer is related to the desired breakdown voltage of the device. The higher the breakdown voltage of the device, the lower the doping concentration of the epitaxial layer and the thicker the epitaxial layer. For a MOSFET with a breakdown voltage of 20V, the epitaxial layer is typically between 2 μm and 4 μm thick, with a corresponding doping concentration, i.e. a corresponding resistivity, in the vicinity of 0.15 Ω cm.
The width of the gate trench 201 of the semiconductor device is 0.2 μm, the distance between the gate trench 201 and the gate trench 201 is 0.3 μm, and the corresponding Pitch is 0.5 μm. The side slope angle of the gate trench 201 is typically between 88 and 89 degrees, and the depth of the gate trench 201 is typically around 1 μm.
The gate trench 201 is formed by photolithography and etching, and anisotropic etching is used, and in order to ensure that the bottom of the trench is as smooth as possible (because of the large electric field to be borne), the etching is adjusted to isotropic etching towards the end of the anisotropic etching. Or after the etching is finished, the sacrificial oxide with a longer and thicker length makes the top as smooth as possible. The width of the opening, i.e., the top, of the finally formed gate trench 201 is typically greater than 0.2 μm.
Before growing the gate dielectric layer 102, a sacrificial oxidation is usually required to repair the sidewall defect caused by etching the gate trench 201, and the thickness of the sacrificial oxidation is usually equal to
Figure BDA0002188866630000091
The temperature of growth is typically between 900 ℃ and 950 ℃. For a 20V device, the thickness of the gate dielectric layer 102 is usually within
Figure BDA0002188866630000092
To
Figure BDA0002188866630000093
In the meantime.
The gate conductive material layer 103 is N-type polysilicon. For P-type devices, the gate conductive material layer 103 is typically P-type polysilicon.
The channel region 105 is formed by channel ion implantation, typically through a masking oxide layer, which prevents tunneling of the ion implantation and thus prevents implantation to too deep a depth. The thickness of the masking oxide layer is usually
Figure BDA0002188866630000094
The masking oxide layer may be deposited or grown by thermal oxygen.
The implantation voltage of the channel ion implantation of the channel region 105 is usually 60 keV-150 keV, the implantation dosage is 5e12cm-2 e13cm-2, and the implantation impurity is boron. After the channel ion implantation is finished, the channel region 105 is subjected to Drive-In by thermal annealing. The Drive-In conditions are typically between 1000 ℃ and 1100 ℃ for a period of from 30 minutes to 100 minutes.
The implantation voltage of the source region 106 is usually 40keV to 80keV, the implantation dose is usually 2e15cm-2 to 6e15cm-2, and the implanted ions are usually Arsenic (Arsenic).
In the ninth step, the thickness of the second dielectric layer deposited comprehensively is
Figure BDA0002188866630000101
In the ninth step, the etching angle of etching the semiconductor substrate 101 at the bottom of the source contact hole 109 is usually 87 to 89 degrees with the sidewall 107 as a self-aligned condition, the etching depth is greater than 0.3 μm and the semiconductor substrate is ensured to pass through the source region 106.
In step ten, the thickness of the interlayer film 108 is
Figure BDA0002188866630000102
The source contact hole 109 and the gate contact hole are typically implemented by filling Ti, TiN, and W in the opening of the contact hole; the front-side metal layer 110 is typically implemented by depositing Al, and the thickness of the front-side metal layer 110 is typically 4 μm.
Whether or not an opening is required for a passivation layer and a passivation layer on top of the topmost front metal layer 110 depends on the breakdown voltage. Typically, for power MOSFET devices with breakdown voltages less than 40V, the use of a passivation layer may not be required.
A method for manufacturing a semiconductor device according to a second embodiment of the present invention:
the method according to an embodiment of the present invention is characterized in that the method for manufacturing a semiconductor device according to a second embodiment of the present invention further includes:
the semiconductor device further has a shielding layer, that is, the semiconductor device is an SGT MOSFET, and the steps of forming the shielding layer before forming the gate dielectric layer 102 and the gate conductive material layer 103 are respectively as follows:
and forming a shielding dielectric layer.
And forming the shielding layer by adopting a deposition and etch-back process.
And forming an inter-gate isolation dielectric layer on the top surface of the shielding layer.
The shielding layer is formed in the gate trench 201 at the bottom of the gate conductive material layer 103, the material of the shielding layer is the same as that of the gate conductive material layer 103, a shielding dielectric layer is isolated between the shielding layer and the bottom surface and the side surface of the gate trench 201, and an inter-gate isolation dielectric layer is isolated between the shielding layer and the gate conductive material layer 103.
For the SGT MOSFET, the significance of reducing the width of Mesa is greater. This is because for SGT, the drift region is laterally depleted by the shield layer as the source field plate, and the smaller the Mesa width, the higher the doping concentration of the drift region can be, and the lower the specific on-resistance of the device can be.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein the top surface of the semiconductor substrate is a first surface; forming a plurality of grid grooves in the semiconductor substrate by adopting a photoetching definition and etching process, wherein the region between every two adjacent grid grooves is a semiconductor platform region; in a current flowing region of the semiconductor device, a forming region of a cell is formed by one gate trench and an adjacent one of the semiconductor platform regions, and the current flowing region is formed by a plurality of cells which are periodically arranged;
forming a gate dielectric layer, wherein the gate dielectric layer is formed on the bottom surface and the side surface of the gate groove and extends to the surface outside the gate groove;
step three, forming a gate conductive material layer, wherein the gate conductive material layer completely fills the gate trench and extends to the surface outside the gate trench;
fourthly, carrying out first self-alignment back-etching on the grid conductive material layer, wherein the first self-alignment back-etching completely removes the grid conductive material layer on the outer surface of the grid groove and back-etches the top surface of the grid conductive material layer in the grid groove area to be lower than the first surface to form a first self-alignment back-etching groove;
fifthly, forming a channel region in the semiconductor platform region;
sixthly, forming a source region on the surface of the channel region, wherein the channel region at the bottom of the source region is covered by the side surface of the gate conductive material layer, and the surface of the channel region covered by the side surface of the gate conductive material layer is used for forming a channel;
step seven, filling a first dielectric layer in the first self-aligned back-etching groove;
eighthly, back-etching the semiconductor material in the semiconductor platform area by taking the first dielectric layer as a self-alignment condition to form a second self-alignment back-etching groove, wherein the bottom surface of the second self-alignment back-etching groove is lower than the first surface, and the source area is positioned below the bottom surface of the second self-alignment back-etching groove;
forming a side wall consisting of the second dielectric layer on the inner side surface of the second self-aligned etching-back groove, and defining a source contact hole at the top of the source region by self-alignment of the side wall;
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a grid electrode and a source electrode; the grid electrode is connected with the grid conductive material layer through the grid contact hole, and the source electrode is connected with the source region through the source contact hole.
2. A method for manufacturing a semiconductor device according to claim 1, wherein: in the first step, the semiconductor material composing the semiconductor substrate comprises silicon and silicon carbide.
3. A method for manufacturing a semiconductor device according to claim 2, wherein: in the second step, the gate dielectric layer is a gate oxide layer; the gate dielectric layer is grown by adopting a thermal oxidation process;
the grid conductive material layer is a polysilicon grid.
4. A method for manufacturing a semiconductor device according to claim 1, wherein: the sub-steps of forming the gate trench include:
forming a hard mask layer on the surface of the semiconductor substrate;
defining a forming area of the grid groove by photoetching;
and sequentially carrying out anisotropic etching on the hard mask layer and the semiconductor substrate to form the gate groove.
5. A method for manufacturing a semiconductor device according to claim 4, wherein: after the gate trench is formed, carrying out isotropic etching to process the gate trench so as to round the corner of the gate trench; or, after the gate trench is formed, a process of forming a sacrificial oxide layer and removing the sacrificial oxide layer is further included to round corners of the gate trench.
6. A method for manufacturing a semiconductor device according to claim 4, wherein: the hard mask layer is made of an oxide layer, a nitride layer or a oxynitride layer; the hard mask layer is removed after the gate trench is formed and before the channel region is formed in step five.
7. A method for manufacturing a semiconductor device according to claim 1, wherein: and step five, forming the channel region by adopting a channel injection and annealing propulsion process.
8. A method for manufacturing a semiconductor device according to claim 1, wherein: the first dielectric layer is made of an oxide layer, a nitride layer or a oxynitride layer.
9. A method for manufacturing a semiconductor device according to claim 8, wherein: in the ninth step, an etching rate difference exists between the material of the second dielectric layer and the material of the interlayer film, and the condition of selective etching is met; the sub-steps of forming the side wall in the ninth step include:
comprehensively depositing to form a second dielectric layer;
and comprehensively etching the second dielectric layer to form the side wall on the inner side surface of the second self-aligned back-etching groove.
10. A method for manufacturing a semiconductor device according to claim 9, wherein: the interlayer film is made of an oxide layer; the material of the second dielectric layer comprises a nitride layer.
11. A method for manufacturing a semiconductor device according to claim 1, wherein: the trench gate MOSFET further comprises a shielding layer, and the steps of forming the shielding layer before the gate dielectric layer and the gate conductive material layer are respectively as follows:
forming a shielding dielectric layer;
forming the shielding layer by adopting a deposition and etch-back process;
forming an inter-gate isolation dielectric layer on the top surface of the shielding layer;
the shielding layer is formed in the grid groove at the bottom of the grid conductive material layer, the material of the shielding layer is the same as that of the grid conductive material layer, a shielding dielectric layer is isolated between the shielding layer and the bottom surface and the side face of the grid groove, and an inter-grid isolation dielectric layer is isolated between the shielding layer and the grid conductive material layer.
12. A method for manufacturing a semiconductor device according to claim 1, wherein: in the ninth step, after the side walls are formed, etching is performed on the semiconductor substrate at the bottoms of the source contact holes by taking the side walls as self-alignment conditions, so that the bottoms of the source contact holes penetrate through the source region and are connected with the channel region, and the source region and the channel region are simultaneously connected to the source electrode through the source contact holes.
13. A method for manufacturing a semiconductor device according to claim 1, wherein: and a grid electrode leading-out area is further formed outside the current flowing area, the trench grid of the current flowing area further extends into the grid electrode leading-out area, a grid electrode contact hole is formed at the top of the grid electrode conductive material layer in the grid electrode leading-out area, and the grid electrode consisting of the grid electrode conductive material layer and the front metal layer is connected through the grid electrode contact hole.
14. A method for manufacturing a semiconductor device according to claim 1, wherein: the semiconductor device is an MOSFET device, and the step ten is completed and then the following back surface process is included:
step eleven, thinning the back surface of the semiconductor substrate, forming a drain region on the back surface of the semiconductor substrate, and forming a drift region by the semiconductor substrate between the drain region and the channel region;
and step twelve, forming a back metal layer on the back of the drain region and forming a drain electrode by the back metal layer.
15. A method for manufacturing a semiconductor device according to any one of claims 1 to 14, wherein: the semiconductor device is an N-type device, the channel region is doped in a P type manner, and the source region is heavily doped in an N type manner; the semiconductor device is a P-type device, the channel region is N-type doped, and the source region is P-type heavily doped.
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