CN112750897A - Groove type field effect transistor structure and preparation method thereof - Google Patents

Groove type field effect transistor structure and preparation method thereof Download PDF

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Publication number
CN112750897A
CN112750897A CN201911038094.0A CN201911038094A CN112750897A CN 112750897 A CN112750897 A CN 112750897A CN 201911038094 A CN201911038094 A CN 201911038094A CN 112750897 A CN112750897 A CN 112750897A
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layer
gate
trench
groove
forming
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陈雪萌
王艳颖
杨林森
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China Resources Microelectronics Chongqing Ltd
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China Resources Microelectronics Chongqing Ltd
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Priority to CN201911038094.0A priority Critical patent/CN112750897A/en
Priority to PCT/CN2019/130496 priority patent/WO2021082273A1/en
Publication of CN112750897A publication Critical patent/CN112750897A/en
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

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Abstract

The invention provides a groove type field effect transistor and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate and forming an epitaxial layer; forming a first device trench; forming a side wall oxidation layer; etching the epitaxial layer based on the side wall oxide layer to form a second device groove; removing the side wall oxide layer to form a gate dielectric layer, a gate layer and a body region; filling a shielding medium layer in the first device groove, and forming a source region and a self-aligned source contact hole based on the shielding medium layer; and forming a source electrode structure and a lower electrode structure. When the grid groove is formed and etched, the first device groove with a larger opening is formed first, the second device groove with a smaller opening is formed by continuous etching, the shielding dielectric layer is formed in the first device groove, the self-aligned source contact hole is formed in the active region of the device through process design, the transverse size of the cell can be reduced, the cell density of the device can be increased, the on-resistance of the device can be reduced, and the method is suitable for groove type devices such as groove type MOSFET (metal-oxide-semiconductor field effect transistor), groove type IGBT and the like.

Description

Groove type field effect transistor structure and preparation method thereof
Technical Field
The invention relates to the technical field of integrated circuit design and manufacture, in particular to a trench type field effect transistor structure and a preparation method thereof.
Background
The trench type device has wide application as an important power device, and has low on-resistance, fast switching speed, good avalanche impact resistance and the like. The requirements of energy conservation, emission reduction and market competition further reduce the on-resistance of the device under the condition of ensuring that other performance parameters of the device are not changed. It is known that decreasing the lateral spacing of the cells of the trench device and increasing the cell density is an effective method for decreasing the on-resistance of the source and drain electrodes. However, the lateral spacing of the cells cannot always be reduced due to the capability of the lithography tool and the etching tool.
Therefore, it is necessary to provide a trench field effect transistor structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a trench field effect transistor structure and a method for fabricating the same, which are used to solve the problems in the prior art that the lateral spacing of the unit cell is difficult to be continuously reduced due to the capability limitations of the lithography machine and the etching machine, and the on-resistance of the device is difficult to be continuously reduced.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a trench type field effect transistor structure, the method comprising the steps of:
providing a substrate of a first doping type, and forming an epitaxial layer of the first doping type on the substrate;
forming a plurality of first device grooves in the epitaxial layer;
forming a side wall oxidation layer on the side wall of the first device groove;
etching the epitaxial layer based on the side wall oxide layer to form a second device groove communicated with the first device groove, wherein the width of the second device groove is smaller than that of the first device groove;
removing the side wall oxide layer to expose the first device groove and the second device groove, wherein the corresponding first device groove and the second device groove form a grid groove;
forming a gate dielectric layer on at least the inner wall of the second device groove, and forming a gate layer on the surface of the gate dielectric layer, wherein the gate layer is filled in the second device groove;
forming a body region of a second doping type in the epitaxial layer, wherein the body region is positioned between the adjacent gate trenches;
filling a shielding dielectric layer in the first device groove, and forming a source region in the body region based on the shielding dielectric layer, wherein the source region is adjacent to the grid groove;
forming a self-aligned source contact hole in the epitaxial layer based on the shielding dielectric layer, wherein the source contact hole penetrates through the source region to the body region and exposes the body region; and
at least the source contact hole is filled with a conductive material layer to form a source electrode structure, and a lower electrode structure electrically connected with the substrate is formed on one side of the substrate far away from the epitaxial layer.
Optionally, the forming a plurality of first device trenches in the epitaxial layer further includes:
forming a mask material layer on the surface of the epitaxial layer, wherein the mask material layer comprises a silicon oxide layer, and the thickness of the mask material layer ranges from 8000 angstroms to 15000 angstroms;
patterning the mask material layer based on a first reticle to form a first mask, wherein the first mask defines the first device groove to be formed; and
and etching the epitaxial layer based on the first mask to form the first device groove in the epitaxial layer, wherein the width range of the first device groove is 0.2-0.4 micrometer, and the depth range of the first device groove is 0.2-0.4 micrometer.
Optionally, the forming a sidewall oxide layer on the sidewall of the first device trench further includes: and forming a surface oxidation layer on the inner wall of the first device groove, and removing the surface oxidation layer at the bottom of the first device groove to form the side wall oxidation layer.
Optionally, the forming a gate dielectric layer on at least the inner wall of the second device trench further includes: the gate dielectric layer further extends to the inner wall of the first device trench and the surface of the epitaxial layer around the first device trench, and/or a gate layer is formed on the surface of the gate dielectric layer and filled in the second device trench, and the method further includes: and depositing a grid electrode material layer on the surface of the grid electrode medium layer, carrying out back etching on the grid electrode material layer by adopting an over-etching process, and removing the grid electrode material layer on the epitaxial layer in the first device groove and around the first device groove to form the grid electrode layer.
Optionally, the filling a shielding dielectric layer in the first device trench, and forming a source region in the body region based on the shielding dielectric layer, further includes: forming a shielding medium material layer on the first device groove and the epitaxial layer around the first device groove, patterning the shielding medium material layer based on a second photolithography mask to define an active region, performing ion implantation on the active region to form the active region, and forming the shielding medium layer by the shielding medium material layer which is remained and filled in the first device groove after patterning, wherein the implantation energy range of the ion implantation is 60Kev to 120Kev, and the implantation angle range is 7 degrees to 30 degrees.
Optionally, the method for manufacturing the trench field effect transistor structure further includes a step of manufacturing a lead-out gate structure, and a termination region is further defined in the epitaxial layer, wherein, an extraction grid groove is prepared in the terminal area while the grid groove is formed, the extraction grid groove comprises a first extraction groove and a second extraction groove which is communicated with the first extraction groove up and down, and forming the first device groove and the first lead-out groove simultaneously, forming the second device groove and the second lead-out groove simultaneously, forming the gate dielectric layer and the lead-out gate dielectric layer on the inner wall of the second lead-out groove simultaneously, forming the gate layer and the lead-out gate layer in the second lead-out groove simultaneously, forming the shielding dielectric layer and the shielding lead-out dielectric layer in the first lead-out groove simultaneously, and preparing the lead-out gate structure.
The invention also provides a trench field effect transistor structure, wherein the trench field effect transistor structure is preferably prepared by the preparation method of the invention, and the trench field effect transistor structure comprises:
a substrate of a first doping type;
the epitaxial layer of the first doping type is formed on the substrate, a plurality of grid grooves are formed in the epitaxial layer, each grid groove comprises a first device groove and a second device groove which are communicated up and down, and the width of each second device groove is smaller than that of each first device groove;
the grid oxide layer is formed on the inner wall of the second device groove;
the gate layer is formed on the surface of the gate oxide layer and fills the second device groove;
the shielding dielectric layer is filled in the first device groove;
a body region of a second doping type formed in the epitaxial layer between adjacent gate trenches;
the source region of the first doping type is formed in the body region and is adjacent to the grid groove, and a source contact hole penetrating through the source region and exposing the body region is formed in the source region;
the source electrode structure is at least filled in the source contact hole; and
and the lower electrode structure is formed on one side of the substrate, which is far away from the epitaxial layer, and is electrically connected with the substrate.
Optionally, the depth of the source region is greater than the depth of the first device trench; the depth of the body region is less than or equal to the depth of the second device trench.
Optionally, a width of the source contact hole is equal to a distance between adjacent first device trenches, and a cross-sectional shape of the source contact hole includes an inverted trapezoid.
Optionally, the trench field effect transistor structure further includes an extraction gate structure, and a termination region is defined in the epitaxial layer, where the extraction gate structure is formed in the termination region, and the extraction gate structure includes: the lead-out grid groove comprises a first lead-out groove and a second lead-out groove which is communicated with the first lead-out groove up and down; the lead-out gate dielectric layer is formed on the inner wall of the second lead-out groove; the lead-out gate layer is formed on the surface of the lead-out gate dielectric layer and fills the second lead-out groove; and the shielding lead-out dielectric layer is filled in the first lead-out groove.
Optionally, an intermediate dielectric layer is further formed on the shielding lead-out dielectric layer, the trench field effect transistor structure further includes a gate contact hole and a gate electrode structure, wherein the gate contact hole sequentially penetrates through the intermediate dielectric layer and the shielding lead-out dielectric layer to the lead-out gate layer, and the gate electrode structure is at least filled in the gate contact hole.
As mentioned above, in the invention, when the gate trench is formed and etched, a first device trench with a larger opening is formed first, and a second device trench with a smaller opening is formed by continuous etching, and a shielding dielectric layer is formed in the first device trench, a self-aligned source contact hole is formed in an active region of the device through process design, and the transverse size of a cell can be reduced to below 1 micron, so that the cell density of the device can be increased, the on-resistance of the device can be reduced, and the invention is suitable for trench type devices such as a trench MOSFET and a trench IGBT.
Drawings
FIG. 1 is a flow chart of a process for fabricating a trench FET according to the present invention.
Fig. 2 is a schematic diagram illustrating the formation of an epitaxial layer in the fabrication of a trench field effect transistor according to the present invention.
Fig. 3 is a schematic diagram illustrating the formation of a first device trench and a second extraction trench in the fabrication of a trench fet in accordance with the present invention.
FIG. 4 is a schematic representation of the formation of a surface oxide layer in the fabrication of a trench FET in accordance with the present invention.
FIG. 5 is a schematic diagram illustrating the formation of a sidewall oxide layer in the fabrication of a trench FET in accordance with the present invention.
Fig. 6 is a schematic diagram illustrating the formation of a second device trench and a second extraction trench in the fabrication of a trench fet in accordance with the present invention.
Fig. 7 is a diagram illustrating the formation of gate trenches and extraction gate trenches in the fabrication of a trench field effect transistor in accordance with the present invention.
Fig. 8 is a schematic representation of the formation of a gate dielectric layer and a lead-out gate dielectric layer in the fabrication of a trench field effect transistor in accordance with the present invention.
Fig. 9 is a schematic representation of the formation of a gate material layer in the fabrication of a trench field effect transistor in accordance with the present invention.
Fig. 10 shows a schematic representation of the formation of a gate layer and a lead-out gate layer in the fabrication of a trench field effect transistor according to the present invention.
Fig. 11 is a schematic representation of the formation of a body region in the fabrication of a trench field effect transistor in accordance with the present invention.
FIG. 12 is a schematic representation of the formation of a masking dielectric material layer in the fabrication of a trench FET in accordance with the present invention.
FIG. 13 is a schematic representation of the formation of a shield dielectric layer, a shield extraction dielectric layer, and an intermediate dielectric layer in the fabrication of a trench FET in accordance with the present invention.
Fig. 14 is a schematic diagram illustrating the formation of a source region in the fabrication of a trench field effect transistor according to the present invention.
FIG. 15 is a schematic representation of source contact hole formation in the fabrication of a trench FET in accordance with the present invention.
FIG. 16 is a diagram illustrating the formation of a gate contact hole in the fabrication of a trench FET in accordance with the present invention.
Fig. 17 is a schematic representation of the formation of a source electrode structure and a gate electrode structure in the fabrication of a trench field effect transistor in accordance with the present invention.
Description of the element reference numerals
100 substrate
101 epitaxial layer
102 first mask
103 first device trench
104 first lead-out groove
105 surface oxide layer
106 sidewall oxide layer
107 second device trench
108 gate trench
109 second lead-out groove
110 lead-out gate trench
111 gate dielectric layer
112 lead-out gate dielectric layer
113 a layer of gate material
114 grid layer
115 lead-out gate layer
116 body region
117 layer of masking dielectric material
118 masking dielectric layer
119 shielding leading-out medium layer
120 interlayer dielectric layer
121 source region
122 source contact hole
123 gate contact hole
124 source electrode structure
125 grid electrode structure
S1-Sn step
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1, the present invention provides a method for manufacturing a trench field effect transistor structure, the method comprising the steps of:
providing a substrate of a first doping type, and forming an epitaxial layer of the first doping type on the substrate;
forming a plurality of first device grooves in the epitaxial layer;
forming a side wall oxidation layer on the side wall of the first device groove;
etching the epitaxial layer based on the side wall oxide layer to form a second device groove communicated with the first device groove, wherein the width of the second device groove is smaller than that of the first device groove;
removing the side wall oxide layer to expose the first device groove and the second device groove, wherein the corresponding first device groove and the second device groove form a grid groove;
forming a gate dielectric layer on at least the inner wall of the second device groove, and forming a gate layer on the surface of the gate dielectric layer, wherein the gate layer is filled in the second device groove;
forming a body region of a second doping type in the epitaxial layer, wherein the body region is positioned between the adjacent gate trenches;
filling a shielding dielectric layer in the first device groove, and forming a source region in the body region based on the shielding dielectric layer, wherein the source region is formed between the adjacent grid grooves and is in contact with the grid grooves;
forming a self-aligned source contact hole in the epitaxial layer based on the shielding dielectric layer, wherein the source contact hole penetrates through the source region to the body region and exposes the body region; and
at least the source contact hole is filled with a conductive material layer to form a source electrode structure, and a lower electrode structure electrically connected with the substrate is formed on one side of the substrate far away from the epitaxial layer.
The following will explain the fabrication process of the trench field effect transistor of the present invention in detail with reference to the accompanying drawings.
As shown in S1 of fig. 1 and fig. 2, a substrate 100 of a first doping type is provided, and an epitaxial layer 101 of the first doping type is formed on the substrate 100.
Specifically, the first doping type (i.e., the first conductivity type) may be P-type doping or N-type doping, and may be the substrate 100 formed by implanting ions of the first doping type (P-type or N-type) into the substrate 100 by an ion implantation process, which is set by actual device requirements, in this example, the substrate 100 is selected to be N-type doping, and in addition, in an example, the substrate 100 may be heavily doped, for example, the concentration of the ions of the first doping type doped in the substrate 100 may be greater than or equal to 1 × 1016/cm3. It should be noted that the substrate 100 may be a silicon substrate 100, a silicon germanium substrate 100, a silicon carbide substrate 100, etc., in this example, the substrate 100 is a silicon substrate 100 doped with N + + type, and may have a resistivity ranging from 0.001ohm-cm to 0.003ohm-cm, for example. The first doping type and the second doping type (namely, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (the first conductivity type) semiconductor is an N-type semiconductor and the second doping type (the second conductivity type) semiconductor is a P-type semiconductor, the trench MOSFET device is an N-type device; in contrast, the trench MOSFET device of the present invention is a P-type device.
Specifically, the doping type of the epitaxial layer 101 is the same as the doping type of the substrate 100, in an example, the doping concentration of the epitaxial layer 101 is lower than the doping concentration of the substrate 100, wherein an epitaxial process may be first used to form a characteristic epitaxial layer 101 on the upper surface of the substrate 100 of the first doping type, and then an ion implantation process is used to implant ions of the first doping type into the intrinsic epitaxial layer 101 to form the epitaxial layer 101 of the first doping type; in another example, the epitaxial layer 101 of the first doping type may also be epitaxially formed directly on the upper surface of the substrate 100 of the first doping type using an epitaxial process. In this example, the epitaxial layer 101 is selected to be an N-type monocrystalline silicon epitaxial layer 101.
As shown in S2 of fig. 1 and fig. 3, a plurality of first device trenches 103 are formed in the epitaxial layer 101.
As an example, the method of forming the first device trench 103 includes the steps of:
forming a mask material layer on the surface of the epitaxial layer 101, wherein the mask material layer includes a silicon oxide layer, and in one example, the thickness of the mask material layer ranges from 8000 a to 15000 a;
patterning the mask material layer based on a first reticle to form a first mask 102, wherein the first mask 102 defines the first device trench 103 to be formed; and
the epitaxial layer 101 is etched based on the first mask 102 to form the first device trench 103 in the epitaxial layer 101.
As an example, the width of the first device trench 103 ranges from 0.2 micrometers to 0.4 micrometers, and the depth of the first device trench 103 ranges from 0.2 micrometers to 0.4 micrometers.
Specifically, in an example, a forming manner of the first device trench 103 is provided, the first device trench 103 may be formed by a photolithography-etching process, for example, a mask material layer is formed on the surface of the epitaxial layer 101 first, the mask material layer may be formed by a chemical vapor deposition process, for example, the deposition thickness may be 10000 angstroms, 12000 angstroms, and then a photolithography process is performed by using the first photolithography mask to form a pattern of the first device trench 103, the epitaxial layer 101 is etched based on the first mask 102 obtained after patterning to form the first device trench 103, for example, the epitaxial layer 101 is etched by a dry etching process, wherein in an example, the width of the first device trench 103 may be between 0.3 microns, the depth of the first device trench 103 may be 0.25 micron, and the width here refers to a lateral dimension, as indicated by w in fig. 3, the depth refers to the dimension of the first device trench 103 buried in the epitaxial layer 101, as indicated by d in fig. 3. In addition, the number and layout of the first device trenches 103 may be selected according to actual requirements.
As shown in S3 of fig. 1 and fig. 4-5, a sidewall oxide layer 106 is formed on the sidewalls of the first device trench 103.
As an example, the method of forming the sidewall oxide layer 106 includes: forming a surface oxide layer 105 on the inner wall of the first device trench 103, and removing the surface oxide layer 105 at the bottom of the first device trench 103 to form the sidewall oxide layer 106.
As an example, before forming the surface oxide layer 105, an etching mask of the first device trench 103 is reserved, the surface oxide layer 105 is formed based on a thermal oxidation process, and the surface oxide layer 105 at the bottom of the first device trench 103 is removed based on the etching mask by a dry etching process.
Specifically, in this step, a sidewall oxide layer 106 is formed on the sidewall of the first device trench 103 for etching the second device trench 107, in an example, a surface oxide layer 105 is formed on the inner wall of the first device trench 103, that is, the surface oxide layer 105 is formed on both the bottom and the sidewall of the first device trench 103, in an alternative example, the surface oxide layer 105 is formed by a thermal oxidation process, which includes but is not limited to silicon oxide, in an example, the thickness of the surface oxide layer 105 is between 0.2 microns and 0.3 microns, so that the subsequent formation of the second device trench 107 can be facilitated without causing damage to the device structure, after the surface oxide layer 105 is formed, in an example, the surface oxide layer 105 on the bottom of the first device trench 103 is removed by a dry etching process, thereby forming the sidewall oxide layer 106, optionally while retaining an etch mask used in forming the first device trench 103, which, as an example, may be the first mask 102 mentioned above, for use in a subsequent etch.
As shown in S4 in fig. 1 and fig. 6, the epitaxial layer 101 is etched based on the sidewall oxide layer 106 to form a second device trench 107 communicating with the first device trench 103, and a width of the second device trench 107 is smaller than a width of the first device trench 103.
As shown in S5 of fig. 1 and fig. 7, the sidewall oxide layer 106 is removed to expose the first device trench 103 and the second device trench 107, and the corresponding first device trench 103 and the second device trench 107 constitute a gate trench 108.
As an example, before removing the sidewall oxide layer 106, a step of forming a sacrificial layer (not shown in fig. 6 and 7) on an inner wall of the second device trench 107 is further included, wherein the sacrificial layer and the sidewall oxide layer 106 are removed by using a wet etching process.
Specifically, the gate trench 108 is formed in this step, and the formed gate trench 108 includes the first device trench 103 and the second device trench 107, that is, a structure similar to a bowl opening with a large top and a small bottom is formed, so as to facilitate the implementation of the subsequent self-aligned process, the gate trench 108 of the device with the "bowl opening" structure can be formed by using only one photolithography mask in the present invention, wherein, in the formation process of the second device trench 107, the previously formed sidewall oxide layer 106 is directly used as an etching mask, and the etching mask formed on the basis of the first device trench 103 is used as a protection, so as to simplify the process, improve the utilization rate of materials and save the cost, the formation of the second device trench 107 adopts a dry etching process, and in addition, after the second device trench 107 is formed, the sidewall oxide layer 106 is removed, when the etching mask formed by the first device trench 103 is remained, for example, when the first mask 102 is remained, the first mask 102 is also removed at the same time, so as to finally obtain the gate trench 108. Additionally, in an example, the depth of the first device trench 103 is less than the depth of the second device trench 107.
In an example, after the second device trench 107 is formed by etching, a sacrificial layer is further formed on the sidewall of the second device trench 107, and damage in the etching process is repaired, in an example, the sacrificial layer may be an oxide layer, such as a silicon oxide layer, optionally, the sacrificial layer is formed by a thermal oxidation process, in an example, the thickness of the sacrificial layer is between 500 angstroms and 1250 angstroms, and may be 800 angstroms and 1000 angstroms, and then the sacrificial layer and the sidewall oxide layer 106 on the sidewall of the first device trench 103 may be simultaneously removed, for example, by a wet etching process, so as to finally obtain the gate trench 108 with a large top and a small bottom, similar to a bowl.
As shown in S8 of fig. 1 and fig. 8-10, a gate dielectric layer 111 is formed at least on the inner wall of the second device trench 107, and a gate layer 114 is formed on the surface of the gate dielectric layer 111, wherein the gate layer 114 fills the second device trench 107.
As an example, the gate dielectric layer 111 further extends to the inner wall of the first device trench 103 and the surface of the epitaxial layer 101 around the first device trench 103;
as an example, the step of forming the gate layer 114 includes: depositing a gate material layer 113 on the surface of the gate dielectric layer 111, and performing an over-etching process on the gate material layer 113 to remove the gate material layer 113 in the first device trench 103 and on the epitaxial layer 101 around the first device trench 103, thereby forming the gate layer 114.
Specifically, the gate dielectric layer 111 is formed after the gate trench 108 is formed, wherein the gate dielectric layer 111 may be formed only on the inner wall of the second device trench 107, may also be formed on the entire inner wall of the gate trench 108, and may further extend to the epitaxial layer 101 around the gate trench 108, preferably, the gate dielectric layer 111 is continuously formed on the inner wall of the gate trench 108 and the epitaxial layer 101 around the gate trench 108, where the inner wall includes a sidewall and a bottom, and in an example, the gate dielectric layer 111 may be formed by using a high temperature thermal oxidation process, and has a thickness ranging from 150 angstroms to 500 angstroms, such as 200 angstroms, 300 angstroms, and the like.
Specifically, the gate layer 114 is formed on the surface of the gate dielectric layer 111 of the second device trench 107, and fills the second device trench 107, the material of the gate layer 114 includes, but is not limited to, polysilicon, the gate layer 114 may be formed by a chemical vapor deposition process, in one example, the gate dielectric layer 111 also extends onto the epitaxial layer 101 around the gate trench 108, the gate layer 114 may be formed by depositing a gate material layer 113 on the surface of the dielectric layer, as shown in fig. 9, for example by a chemical vapor deposition process, in one example, the gate material layer 113 is formed to a thickness of between 0.1 microns and 1 micron, such as 0.5 microns or 0.8 microns, the thickness here refers to the thickness of the gate material layer 113 formed over the epitaxial layer 101, as indicated by s in fig. 9. In an example, an excess gate material layer 113 is removed by a dry etching process to form the gate layer 114, wherein the gate layer 114 (e.g., polysilicon) fills a deep trench (the second device trench 107), an upper surface of the gate layer 114 is flush with an upper opening of the second device trench 107, and in this example, the polysilicon surface is flush with the upper opening of the deep trench, optionally, the dry etching of the gate material layer 113 is substantially stopped at the bottom of the first device trench 103 by over-etching, where the over-etching refers to setting a main etching, and performing a subsequent etching after the main etching, for example, increasing an etching time to continue etching by using the same etching parameters, for example, in an example, the gate dielectric layer 111 is formed on the epitaxial layer 101, and the gate material layer 113 is etched by the over-etching process, when a signal of the gate dielectric layer 111 (such as silicon oxide) is detected, the purpose that etching is stopped at the bottom of the first device groove 103 is achieved by setting an over-etching time, so that the gate layer 114 is formed, and the upper surface of the gate layer 114 is flush with the upper opening of the second device groove 107.
As shown in S9 of fig. 1 and fig. 11, a body region 116 of the second doping type is formed in the epitaxial layer 101, and the body region 116 is located between the adjacent gate trenches 108.
As an example, the depth of the body region 116 does not exceed the depth of the second device trench 107.
In particular, in this step, an ion implantation is carried out in said epitaxial layer 101 to form a body region 116, wherein, specifically, the second doping type represents a doping type opposite to the first doping type, and if the first doping type is an N type, the second doping type is P-type, if the first doping type is P-type, the second doping type is N-type, the doping type of the body region 116 is opposite to the doping type of the epitaxial layer 101 and the substrate 100, in one example, the depth of the body regions 116 is less than the depth of the gate trenches 108, there is a height difference between the bottom of the body region 116 and the bottom of the gate layer 114, that is, the bottom of the body region 116 is further from the bottom of the epitaxial layer 101 than the bottom of the gate trench 108 is from the bottom of the epitaxial layer 101. in this example, the body region 116 is selected to be lightly P-doped. Additionally, forming body region 116 may further include performing a high temperature anneal after ion implantation, wherein the implant dose is adjusted according to performance parameter requirements, such as threshold voltage, breakdown voltage, etc., of the device, in one example, 5E12/CM ^2 to 1E13/CM ^ 2.
As shown in S10 of fig. 1 and fig. 12 to 14, the first device trench 103 is filled with a shielding dielectric layer 118, and a source region 121 is formed in the body region 116 based on the shielding dielectric layer 118, wherein the source region 121 is formed between adjacent gate trenches 108, i.e., the edge of the source region 121 abuts the edge of the gate trench 108.
As an example, the step of forming the shielding dielectric layer 118 and the source region 121 includes: forming a shielding dielectric material layer 117 on the first device trench 103 and the epitaxial layer 101 around the first device trench 103, patterning the shielding dielectric material layer 117 based on a second reticle to define an active region, performing ion implantation on the active region to form the active region 121, and forming the shielding dielectric layer 118 by the shielding dielectric material layer 117 filled in the first device trench 103 after patterning.
As an example, the ion implantation is performed at an implantation energy of 60Kev to 120Kev and at an implantation angle of 7 degrees to 30 degrees.
As an example, the depth of the source region 121 is greater than the depth of the first device trench 103.
Specifically, after the body region 116 is formed, a source region 121 of a device is formed in the body region 116, that is, a source of a trench field effect transistor is prepared, wherein the source region 121 is formed between adjacent gate trenches 108, an edge of the source region 121 abuts an edge of the gate trench 108, in an example, ion implantation for forming the source region 121 is performed on the body region 116, the source region 121 is formed in the body region 116, and an upper surface of the source region 121 is flush with an upper surface of the body region 116. In an alternative example, the implantation energy for performing the ion implantation is between 60Kev and 120Kev, for example, 70Kev, 80Kev or 100Kev, and the implantation angle is between 7 degrees and 30 degrees, for example, 10 degrees, 20 degrees or 25 degrees, so as to facilitate the formation of the source region, and the design of the angle is favorable for the ions to diffuse to the lower part of the shielding dielectric layer to form the source region 121 after the ion implantation and the subsequent activation. In addition, in an example, the depth of the source region 121 is greater than the depth of the first device trench 103, which is beneficial to prevent the problem that the device cannot be turned on or the on-resistance is relatively large when the source region of the device is not connected to the channel, for example, the depth of the source region 121 is greater than the depth of the first device trench 103, that is, the height of the overlapping portion of the two may be 0.08 micrometers to 0.12 micrometers, and may be 0.1 micrometer.
In an example, a forming manner of the source region 121 is provided, and after the body region 116 is formed, a shielding dielectric material layer 117 is formed on the entire surface of the device, and may be formed by using a chemical vapor deposition process, in an example, the thickness of the shielding dielectric material layer 117 is between 0.5 microns and 1 micron, and may be 0.6 microns or 0.8 microns, where the thickness refers to the thickness of the shielding dielectric layer 118 formed above the epitaxial layer 101, as shown by m in fig. 12. Next, the masking dielectric material layer 117 is patterned based on a second reticle to define an active region, as shown in fig. 13. The active region is exposed at a position where the source region 121 needs to be formed, the corresponding shielding dielectric material layer 117 above the epitaxial layer 101 is removed, the shielding dielectric layer 118 filled in the first device trench 103 is formed at the same time, and then ion implantation is performed under the shielding of the shielding dielectric layer 118 to form the source region 121, as shown in fig. 14. In one example, the step of annealing to form the source region 121 is further included after the ion implantation, and in this example, the heavily doped (e.g., n +) device source region 121 is formed.
As shown in S11 of fig. 1 and fig. 15, a self-aligned source contact hole 122 is formed in the epitaxial layer 101 based on the masking dielectric layer 118, the source contact hole 122 penetrates the source region 121 to the body region 116, and the bottom of the source contact hole 122 exposes the body region 116.
As an example, the opening edge of the source contact hole 122 abuts against the edge of the corresponding source region 121, that is, the width of the source contact hole 122 is equal to the distance between two adjacent first device trenches 103, the sidewall of the contact hole 122 is an inclined sidewall, and the cross-sectional shape of the source contact hole 122 includes an inverted trapezoid.
Specifically, as shown in fig. 15, a source contact hole 122 of the trench field effect transistor of the present invention is formed, in this step, the gate trench 108 with a large top and a small bottom is formed, and a shielding dielectric layer 118 is formed in the first device trench 103, so that the epitaxial layer 101 can be etched by using the shielding dielectric layer 118 as a mask, and a self-aligned source contact hole 122 is formed in the active region, so that the lateral distance of the device can be reduced, for example, to less than 1 micron, the density of device unit cells is increased, and the source-drain on-resistance of the device is reduced, in the present invention, the source region 121 and the source contact hole 122 can be simultaneously formed based on the same shielding dielectric layer 118, the process is simplified, and the cost is saved, as shown in fig. 15, a structure in which the first device trench 103 and the source contact hole 102 are alternately arranged is formed, and the first device trench 103 and the source contact hole 102 are closely adjacent, such as the right edge of the first device trenches 103 abutting the left edge of the first of the source contact openings 102, the right edge of the first of the source contact openings 102 abutting the left edge of the second of the first device trenches 103, and so on. Alternatively, the source contact hole 122 may have an inverted trapezoid shape in a longitudinal cross section, and in an alternative example, the source contact hole 122 extends through the source region 121 into the body region 116, so that the electrical stability of the device may be improved.
As shown in S12 of fig. 1 and fig. 17, at least the source contact hole 122 is filled with a conductive material layer to form a source electrode structure 124, and a bottom electrode structure electrically connected to the substrate 100 is formed on a side of the substrate 100 away from the epitaxial layer 101.
Specifically, after the source contact hole 122 is formed, a conductive material layer is filled therein to form the source electrode, so as to electrically extract the source region 121 and the body region 116, and in an example, the conductive material layers filled in the source contact hole 122 are further connected to realize a common connection between the sources. In addition, a lower electrode structure is formed on the other side of the substrate 100, so as to be led out as a drain of the device, wherein the material of the conductive material layer may be, but is not limited to, polysilicon or metal.
Referring to fig. 3 to 17, as an example, the method for manufacturing a trench field effect transistor structure further includes a step of manufacturing an extraction gate structure, and a termination region is further defined in the epitaxial layer 101, wherein an extraction gate trench 110 is also manufactured in the termination region while forming the gate trench 108, the extraction gate trench 110 includes a first extraction trench 104 and a second extraction trench 109 vertically communicated with the first extraction trench 104, the first extraction trench 104 is formed while forming the first device trench 103, the second extraction trench 109 is formed while forming the second device trench 107, an extraction gate dielectric layer 112 is formed on an inner wall of the second extraction trench 109 while forming the gate dielectric layer 111, an extraction gate layer 115 is formed in the second extraction trench 109 while forming the gate layer 114, and a shielding extraction dielectric layer 119 is formed in the first extraction trench 104 while forming the shielding dielectric layer 118, to prepare the extraction gate structure.
As an example, the forming of the shielding dielectric layer 118 and the shielding extraction dielectric layer 119 and the forming of the intermediate dielectric layer 120 on at least the shielding extraction dielectric layer 119 further include the following steps: a gate contact hole 123 exposing the extraction gate layer 115 is formed on the extraction gate layer 115 based on a third photolithography mask, and the gate contact hole 123 penetrates through the intermediate dielectric layer 120 and the shielding extraction dielectric layer 119, as shown in fig. 16.
Specifically, referring to fig. 3, in one example, the extraction gate trench 110 is also fabricated in the epitaxial layer 101, in an alternative example, the region corresponding to the epitaxial layer 101 is divided into a device region B and a termination region a in advance, wherein the gate trench 108 is formed in the device region, the extraction trench is formed in the termination region, both of which may be formed based on the same process and mask, that is, in one example, the pattern of these two trenches is formed on the trench first mask 102, and etching is performed based on the pattern, that is, when the first device trench 103 is formed based on the first mask 102, the first lead-out trench 104 is also formed, in addition, the sidewall oxide layer 106 is formed on the sidewall of the first extraction trench 104 at the same time, the second extraction trench 109 may be formed based thereon, see the preparation of the gate trench 108 for a related description. Further, referring to fig. 8, while forming the gate dielectric layer 111, a lead-out gate dielectric layer 112 is formed on the bottom and the sidewall of the lead-out trench, referring to fig. 9, a gate material layer 113 used for forming the gate layer 114 is simultaneously formed in the lead-out gate trench 110 to prepare a lead-out gate layer 115, and related preparation processes refer to the description of the gate layer 114 and are not repeated herein. In addition, when the shielding dielectric layer 118 is formed, the shielding extraction dielectric layer 119 and the intermediate dielectric layer 120 are simultaneously prepared and formed in the first extraction groove 104, in an example, when the second photolithography mask is used for etching, the shielding dielectric material layer 117 corresponding to the active region is removed, so that the shielding dielectric layer 118 is formed in the first device groove 103 in the core region, the shielding dielectric material layer 117 in the terminal region is retained, the shielding extraction dielectric layer 119 is formed by the material layer filled in the first extraction groove 104, the shielding material layer located above the epitaxial layer 101 in the terminal region forms the intermediate dielectric layer 120, and it should be noted that, as can be understood by those skilled in the art, the etching of the shielding dielectric layer 118 in the interface range between the core region and the terminal region may be actually selected, as illustrated in fig. 13, the removal of the masking material layer resides over the outermost gate trench 108 within the boundary.
Illustratively, the conductive material layer is further filled in the gate contact hole 123 and extends onto the intermediate dielectric layer 120 around the gate contact hole 123 and extends onto the shielding dielectric layer 118 around the source contact hole 122, wherein the preparation method further comprises a step of patterning the conductive material layer based on a fourth reticle to form a gate electrode structure 125 and the source electrode structure 124.
Specifically, in an example, a step of preparing a gate contact hole 123 based on a third photolithography is further included, where a bottom of the gate contact hole 123 may be flush with a bottom of the first lead-out trench 104, just expose the lead-out gate layer 115, or extend into the lead-out gate layer 115. In addition, as shown in fig. 16, terminal contact holes, such as vias formed beside the terminal gate contact holes, may be formed in the termination region, extending into the epitaxial layer to serve as connecting vias for termination to the substrate. In addition, referring to fig. 17, in an example, the source electrode structure 124 and the gate electrode structure 125 are formed by depositing a whole conductive material layer on the core region and the termination region, and when the whole conductive material layer is deposited, etching is performed based on the fourth photolithography mask to define the source electrode structure 124 and the gate electrode structure 125 which are separated from each other, in an example, the thickness of the conductive material layer is between 0.8 micrometers and 2 micrometers, and may be 1 micrometer or 1.5 micrometers, where the thickness refers to a thickness of the conductive material layer formed on the epitaxial layer 101, as shown by n in fig. 17.
Example two:
as shown in fig. 17 and referring to fig. 1 to 16, the present invention further provides a trench field effect transistor structure, wherein the trench field effect transistor structure is preferably prepared by the trench field effect transistor preparation method of the present invention, and the trench field effect transistor structure includes:
a substrate 100 of a first doping type;
the epitaxial layer 101 of the first doping type is formed on the substrate 100, a plurality of gate trenches 108 are formed in the epitaxial layer 101, each gate trench 108 includes a first device trench 103 and a second device trench 107 which are vertically communicated, and the width of each second device trench 107 is smaller than that of each first device trench 103;
a gate oxide layer formed on an inner wall of the second device trench 107;
a gate layer 114 formed on a surface of the gate oxide layer, wherein the gate layer 114 fills the second device trench 107;
a shielding dielectric layer 118 filled in the first device trench 103;
a body region 116 of the second doping type formed in the epitaxial layer 101 between adjacent gate trenches 108;
a source region 121 of the first doping type formed in the body region 116 between adjacent gate trenches 108 and contacting the gate trenches 108, the source region 121 having a source contact hole 122 formed therein, the source contact hole penetrating the source region 121 and exposing the body region 116;
a source electrode structure 124 at least filled in the source contact hole 122; and
and the lower electrode structure is formed on one side of the substrate 100 far away from the epitaxial layer 101 and is electrically connected with the substrate 100.
Specifically, the first doping type (i.e., the first conductivity type) may be P-type doping or N-type doping, and may be the substrate 100 formed by implanting ions of the first doping type (P-type or N-type) into the substrate 100 by an ion implantation process, which is set by actual device requirements, in this example, the substrate 100 is selected to be N-type doping, and in addition, in an example, the substrate 100 may be heavily doped, for example, the concentration of the ions of the first doping type doped in the substrate 100 may be greater than or equal to 1 × 1016/cm3. It should be noted that the substrate 100 may be a silicon substrate 100, a silicon germanium substrate 100, a silicon carbide substrate 100, or the like, and in this example, the substrate 100 is a silicon substrate 100 doped with N + +. The first doping type and the second doping type (namely, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (the first conductivity type) semiconductor is an N-type semiconductor and the second doping type (the second conductivity type) semiconductor is a P-type semiconductor, the trench MOSFET device is an N-type device; in contrast, the trench MOSFET device of the present invention is a P-type device.
Specifically, the doping type of the epitaxial layer 101 is the same as the doping type of the substrate 100, in an example, the doping concentration of the epitaxial layer 101 is lower than the doping concentration of the substrate 100, wherein an epitaxial process may be first used to form a characteristic epitaxial layer 101 on the upper surface of the substrate 100 of the first doping type, and then an ion implantation process is used to implant ions of the first doping type into the intrinsic epitaxial layer 101 to form the epitaxial layer 101 of the first doping type; in another example, the epitaxial layer 101 of the first doping type may also be epitaxially formed directly on the upper surface of the substrate 100 of the first doping type using an epitaxial process. In this example, the epitaxial layer 101 is selected to be an N-type monocrystalline silicon epitaxial layer 101.
Specifically, in an example, the width of the first device trench 103 may be 0.3 microns, and the depth of the first device trench 103 may be 0.25 microns, where the width refers to a lateral dimension, such as w in fig. 3, and the depth refers to a dimension of the first device trench 103 buried in the epitaxial layer 101, such as d in fig. 3. In addition, the number and layout of the first device trenches 103 may be selected according to actual requirements. It should be noted that the gate trench 108 formed in the present invention, including the first device trench 103 and the second device trench 107, is formed with a structure having a large top and a small bottom, which is similar to a bowl mouth, so as to facilitate the implementation of the subsequent self-aligned process.
Specifically, for the gate dielectric layer 111, the gate dielectric layer 111 may be formed only on the inner wall of the second device trench 107, may also be formed on the entire inner wall of the gate trench 108, and may further extend to the epitaxial layer 101 around the gate trench 108, and preferably, the gate dielectric layer 111 is continuously formed on the inner wall of the gate trench 108 and the epitaxial layer 101 around the gate trench 108, where the inner wall includes a sidewall and a bottom, and the thickness of the inner wall may be 150 angstroms to 500 angstroms, such as 200 angstroms, 300 angstroms, and the like. In addition, the gate layer 114 is formed on the surface of the gate dielectric layer 111 of the second device trench 107 and fills the second device trench 107, the gate layer 114 (e.g., polysilicon) fills the deep trench (the second device trench 107), the upper surface of the gate layer 114 is flush with the upper opening of the second device trench 107, in this example, the polysilicon surface is flush with the upper opening of the deep trench, and the material of the gate layer 114 includes, but is not limited to, polysilicon.
As an example, the depth of the body region 116 does not exceed the depth of the second device trench 107.
As an example, the depth of the source region 121 is greater than the depth of the first device trench 103.
In particular, an ion implantation is performed in said epitaxial layer 101 to form a body region 116, wherein, in particular, the second doping type represents a doping type opposite to the first doping type, if the first doping type is N-type, the second doping type is P-type, if the first doping type is P-type, the second doping type is N-type, the doping type of the body region 116 is opposite to the doping type of the epitaxial layer 101 and the substrate 100, in one example, the depth of the body regions 116 is less than the depth of the gate trenches 108, there is a height difference between the bottom of the body region 116 and the bottom of the gate layer 114, that is, the bottom of the body region 116 is further from the bottom of the epitaxial layer 101 than the bottom of the gate trench 108 is from the bottom of the epitaxial layer 101. in this example, the body region 116 is selected to be lightly P-doped. In addition, after the body region 116 is formed, a source region 121 of a device is formed in the body region 116, that is, a source of a trench field effect transistor is prepared, wherein the source region 121 is formed between adjacent gate trenches 108 and is in contact with the gate trenches 108, in an example, ion implantation for forming the source region 121 is performed on the body region 116, the source region 121 is formed in the body region 116, and an upper surface of the source region 121 is flush with an upper surface of the body region 116, in this example, a heavily doped (e.g., n +) device source region 121 is formed.
As an example, the opening edge of the source contact hole 122 abuts against the edge of the corresponding source region 121, that is, the width of the source contact hole 122 is equal to the distance between two adjacent first device trenches 103, the sidewall of the contact hole 122 is an inclined sidewall, and the cross-sectional shape of the source contact hole 122 includes an inverted trapezoid.
The gate trenches 108 with a large top and a small bottom are formed, and the shielding dielectric layer 118 is formed in the first device trench 103, so that the epitaxial layer 101 can be etched by using the shielding dielectric layer 118 as a mask, so that the lateral distance of the device can be reduced, for example, to be less than 1 micron, the density of device cells is increased, and the on-resistance of the source and drain electrodes of the device is reduced, in an example, the openings of the source contact holes 122 are in contact with the corresponding edges of the source regions 121, that is, the size of the opening of the source contact hole 122 is the additional distance between the adjacent first device trenches 103, as shown in fig. 15, a structure is formed in which the first device trenches 103 and the source contact holes 102 are alternately arranged, and the first device trenches 103 are closely adjacent to the source contact holes 102, for example, the right edge of the first device trench 103 is adjacent to the left edge of the first source contact hole 102, the right edge of the first source contact hole 102 abuts the left edge of the second first device trench 103, and so on, optionally the source contact hole 122 may have an inverted trapezoidal longitudinal cross-sectional shape, and in an alternative example, the source contact hole 122 extends through the source region 121 into the body region 116, so that the electrical stability of the device may be improved.
Specifically, after the source contact hole 122 is formed, a conductive material layer is filled therein to form the source electrode, so as to electrically extract the source region 121 and the body region 116, and in an example, the conductive material layers filled in the source contact hole 122 are further connected to realize a common connection between the sources. In addition, a lower electrode structure is formed on the other side of the substrate 100, so as to be led out as a drain of the device, wherein the material of the conductive material layer may be, but is not limited to, polysilicon or metal.
As an example, the trench field effect transistor structure further includes an extraction gate structure, and a termination region is defined in the epitaxial layer 101, where the extraction gate structure is formed in the termination region, and the extraction gate structure includes: the extraction grid groove 110, wherein the extraction grid groove 110 comprises a first extraction groove 104 and a second extraction groove 109 which is vertically communicated with the first extraction groove; an extraction gate dielectric layer 112 formed on the inner wall of the second extraction trench 109; a lead-out gate layer 115 formed on the surface of the lead-out gate dielectric layer 112, wherein the lead-out gate layer 115 fills the second lead-out groove 109; and a shielding extraction dielectric layer 119 filled in the first extraction groove 104.
As an example, an intermediate dielectric layer 120 is further formed on the shielding extraction dielectric layer 119, and the trench field effect transistor structure further includes a gate contact hole 123 and a gate electrode structure 125, wherein the gate contact hole 123 sequentially penetrates through the intermediate dielectric layer 120, the shielding extraction dielectric layer 119 to the extraction gate layer 115, and exposes the extraction gate layer 115, and the gate electrode structure 125 is at least filled in the gate contact hole 123.
Specifically, referring to fig. 3, in an example, the extraction gate trench 110 is further prepared in the epitaxial layer 101, and in an optional example, a region corresponding to the epitaxial layer 101 is divided into a device region B and a terminal region a in advance, wherein the gate trench 108 is prepared in the device region, and the extraction trench is prepared in the terminal region, wherein the first extraction trench 104 and the first device trench 103, the second extraction trench 109 and the second device trench 107, the gate dielectric layer 111 and the extraction gate dielectric layer 112, the gate layer 114 and the extraction gate layer 115, the shielding dielectric layer 118 and the shielding extraction dielectric layer 119 may be formed based on the same process and have the same size and dimension, and it should be noted that, as can be understood by those skilled in the art, the core etching of the shielding dielectric layer 118 in the interface range between the terminal region and the terminal region may be actually selected, as illustrated in fig. 13, the removal of the masking material layer resides over the outermost gate trench 108 within the boundary.
Specifically, in an example, the semiconductor device further includes a gate contact hole 123, and a bottom of the gate contact hole 123 may be flush with a bottom of the first lead-out trench 104, and just expose the lead-out gate layer 115, or may extend into the lead-out gate layer 115. In addition, referring to fig. 17, in an example, the source electrode structure 124 and the gate electrode structure 125 are formed by depositing a whole conductive material layer on the core region and the termination region, and when the whole conductive material layer is deposited, etching is performed based on the fourth photolithography mask to define the source electrode structure 124 and the gate electrode structure 125 which are separated from each other, in an example, the thickness of the conductive material layer is between 0.8 micrometers and 2 micrometers, and may be 1 micrometer or 1.5 micrometers, where the thickness refers to a thickness of the conductive material layer formed on the epitaxial layer 101, as shown by n in fig. 17.
In summary, when the gate trench is formed and etched, a first device trench with a larger opening is formed first, a second device trench with a smaller opening is formed by etching continuously, a shielding dielectric layer is formed in the first device trench, a self-aligned source contact hole is formed in an active region of the device through process design, and the lateral size of a cell can be reduced to below 1 micron, so that the cell density of the device can be increased, the on-resistance of the device can be reduced, and the method is suitable for trench type devices such as a trench MOSFET and a trench IGBT. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. A preparation method of a trench type field effect transistor is characterized by comprising the following steps:
providing a substrate of a first doping type, and forming an epitaxial layer of the first doping type on the substrate;
forming a plurality of first device grooves in the epitaxial layer;
forming a side wall oxidation layer on the side wall of the first device groove;
etching the epitaxial layer based on the side wall oxide layer to form a second device groove communicated with the first device groove, wherein the width of the second device groove is smaller than that of the first device groove;
removing the side wall oxide layer to expose the first device groove and the second device groove, wherein the corresponding first device groove and the second device groove form a grid groove;
forming a gate dielectric layer on at least the inner wall of the second device groove, and forming a gate layer on the surface of the gate dielectric layer, wherein the gate layer is filled in the second device groove;
forming a body region of a second doping type in the epitaxial layer, wherein the body region is positioned between the adjacent gate trenches;
filling a shielding dielectric layer in the first device groove, and forming a source region in the body region based on the shielding dielectric layer, wherein the source region is adjacent to the grid groove;
forming a self-aligned source contact hole in the epitaxial layer based on the shielding dielectric layer, wherein the source contact hole penetrates through the source region to the body region and exposes the body region; and
at least the source contact hole is filled with a conductive material layer to form a source electrode structure, and a lower electrode structure electrically connected with the substrate is formed on one side of the substrate far away from the epitaxial layer.
2. The method of claim 1, wherein forming a plurality of first device trenches in the epitaxial layer further comprises:
forming a mask material layer on the surface of the epitaxial layer, wherein the mask material layer comprises a silicon oxide layer, and the thickness of the mask material layer ranges from 8000 angstroms to 15000 angstroms;
patterning the mask material layer based on a first reticle to form a first mask, wherein the first mask defines the first device groove to be formed; and
and etching the epitaxial layer based on the first mask to form the first device groove in the epitaxial layer, wherein the width range of the first device groove is 0.2-0.4 micrometer, and the depth range of the first device groove is 0.2-0.4 micrometer.
3. The method of claim 1, wherein forming a sidewall oxide layer on sidewalls of the first device trench further comprises: and forming a surface oxidation layer on the inner wall of the first device groove, and removing the surface oxidation layer at the bottom of the first device groove to form the side wall oxidation layer.
4. The method of claim 1, wherein a gate dielectric layer is formed on at least the inner wall of the second device trench, and further comprising: the gate dielectric layer further extends to an inner wall of the first device trench and a surface of the epitaxial layer around the first device trench, and/or,
and form the gate layer on the surface of said gate dielectric layer, said gate layer is packed in the said second device ditch groove, also include:
and depositing a gate material layer on the surface of the gate dielectric layer, etching back the gate material layer, and removing the gate material layer on the epitaxial layer in and around the first device groove to form the gate layer.
5. The method of claim 1, wherein the first device trench is filled with a masking dielectric layer, and a source region is formed in the body region based on the masking dielectric layer, further comprising: forming a shielding medium material layer on the first device groove and the epitaxial layer around the first device groove, patterning the shielding medium material layer based on a second photolithography mask to define an active region, performing ion implantation on the active region to form the active region, and forming the shielding medium layer by the shielding medium material layer which is remained and filled in the first device groove after patterning, wherein the implantation energy range of the ion implantation is 60Kev to 120Kev, and the implantation angle range is 7 degrees to 30 degrees.
6. The method according to any one of claims 1 to 5, wherein the method further comprises a step of forming a lead-out gate structure, and a termination region is further defined in the epitaxial layer, wherein the lead-out gate trench is formed in the termination region while forming the gate trench, the lead-out gate trench includes a first lead-out trench and a second lead-out trench vertically communicating with the first lead-out trench, the first lead-out trench is formed while forming the first device trench, the second lead-out trench is formed while forming the second device trench, a lead-out gate dielectric layer is formed on an inner wall of the second lead-out trench while forming the gate dielectric layer, and a lead-out gate layer is formed in the second lead-out trench while forming the gate layer, and forming a shielding extraction medium layer in the first extraction groove while forming the shielding medium layer so as to prepare the extraction gate structure.
7. A trench field effect transistor structure, the trench field effect transistor structure comprising:
a substrate of a first doping type;
the epitaxial layer of the first doping type is formed on the substrate, a plurality of grid grooves are formed in the epitaxial layer, each grid groove comprises a first device groove and a second device groove which are communicated up and down, and the width of each second device groove is smaller than that of each first device groove;
the grid oxide layer is formed on the inner wall of the second device groove;
the gate layer is formed on the surface of the gate oxide layer and fills the second device groove;
the shielding dielectric layer is filled in the first device groove;
a body region of a second doping type formed in the epitaxial layer between adjacent gate trenches;
the source region of the first doping type is formed in the body region and is adjacent to the grid groove, and a source contact hole penetrating through the source region and exposing the body region is formed in the source region;
the source electrode structure is at least filled in the source contact hole; and
and the lower electrode structure is formed on one side of the substrate, which is far away from the epitaxial layer, and is electrically connected with the substrate.
8. The trench field effect transistor structure of claim 7 wherein the depth of the source region is greater than the depth of the first device trench; the depth of the body region is less than or equal to the depth of the second device trench.
9. The trench fet structure of claim 7, wherein the source contact opening has a width equal to a distance between adjacent first device trenches, and wherein the source contact opening has a cross-sectional shape comprising an inverted trapezoid.
10. The trench field effect transistor structure of any of claims 7-9, further comprising an extraction gate structure and a termination region defined in the epitaxial layer, wherein the extraction gate structure is formed in the termination region, and wherein the extraction gate structure comprises: the lead-out grid groove comprises a first lead-out groove and a second lead-out groove which is communicated with the first lead-out groove up and down; the lead-out gate dielectric layer is formed on the inner wall of the second lead-out groove; the lead-out gate layer is formed on the surface of the lead-out gate dielectric layer and fills the second lead-out groove; and the shielding lead-out dielectric layer is filled in the first lead-out groove.
11. The trench fet structure of claim 10, further comprising an intermediate dielectric layer formed on the shield extraction dielectric layer, and further comprising a gate contact hole and a gate electrode structure, wherein the gate contact hole sequentially penetrates through the intermediate dielectric layer and the shield extraction dielectric layer to the extraction gate layer, and the gate electrode structure is at least filled in the gate contact hole.
CN201911038094.0A 2019-10-29 2019-10-29 Groove type field effect transistor structure and preparation method thereof Pending CN112750897A (en)

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