CN113284953B - Shielding gate groove type MOSFET structure and manufacturing method thereof - Google Patents
Shielding gate groove type MOSFET structure and manufacturing method thereof Download PDFInfo
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- CN113284953B CN113284953B CN202110822237.8A CN202110822237A CN113284953B CN 113284953 B CN113284953 B CN 113284953B CN 202110822237 A CN202110822237 A CN 202110822237A CN 113284953 B CN113284953 B CN 113284953B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention discloses a shielded gate trench type MOSFET structure, comprising: a semiconductor substrate; an epitaxial semiconductor layer formed over the semiconductor substrate; the well region is formed above the epitaxial semiconductor layer; the source region is formed inside the well region; a first trench and a second trench formed inside the epitaxial semiconductor layer, the source region and the well region; and a second source conductive channel formed inside the source region and the well region and between the first trench and the second trench; wherein a shortest distance between the first trench and the second trench defines a maximum width of the second source conductive channel. The MOSFET structure can realize self-alignment of etching, and solves the technical problem that the prior photoetching machine can not meet the required resolution when the space between two unit cells is too small; and simplifies the MOSFET manufacturing process to save manufacturing time and cost.
Description
Technical Field
The present invention relates to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating the same, and more particularly, to a shielded gate trench type MOSFET structure and a method of fabricating the same.
Background
Metal-Oxide Semiconductor Field Effect transistors (MOSFETs), which are referred to as Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs), are widely used in switching elements of power devices, such as power supplies, rectifiers, or low-voltage motor controllers. The conventional MOSFET is designed with a vertical structure, such as a trench MOSFET, to increase the device density. In power MOSFETs, the higher the cell density, the lower the on-resistance, especially for MOSFETs with operating voltages less than 40 volts. Generally, a shielded gate trench type (shielded gate with trench type) MOSFET can reduce the resistance value of an epitaxial (epitaxiy) semiconductor by increasing the cell density. However, when the spacing between two cells is less than 0.8 μm, the conventional photolithography (photo) tool is easily misaligned to meet the required resolution, which may affect the conductive characteristics of the MOSFET to different degrees, and in severe cases may cause the MOSFET to fail.
Furthermore, in the development of the power type shielded gate trench MOSFET, the width of the trench is limited by the capability of the photolithography tool and is difficult to be made smaller, so that the cell density is difficult to be further improved, and the performance of the MOSFET is limited. Therefore, how to provide a self-aligned contact MOSFET and a method for manufacturing the same are a technical problem of concern in the art.
In addition, the conventional shielded gate trench MOSFET requires multiple masks (masks) to establish the corresponding structures. Therefore, how to simplify the manufacturing process of the MOSFET to save time and cost is also a technical issue of concern in the art.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a shielded gate trench MOSFET structure and a method for manufacturing the same.
The invention provides a shielded gate trench type MOSFET structure, which is characterized by comprising: a semiconductor substrate; an epitaxial semiconductor layer formed over the semiconductor substrate; the well region is formed above the epitaxial semiconductor layer; the source region is formed inside the well region; a first trench and a second trench formed inside the epitaxial semiconductor layer, the source region and the well region; and a second source conductive channel formed inside the source region and the well region and between the first trench and the second trench; wherein a shortest distance between the first trench and the second trench defines a maximum width of the second source conductive channel.
Preferably, a well region recess is formed between the first trench and the second trench.
Preferably, the trench sidewalls of each of the first trench and the second trench have a stepped shape or a raised edge such that the width of each of the first trench and the second trench increases stepwise from the bottom to the top.
Preferably, in at least one of the first and second trenches, the depth from the trench top to the raised edge bottom of the trench sidewalls is Da, the depth from the trench top to the raised edge top of the trench sidewalls is Db, and the depth from the raised edge bottom of the trench sidewalls to the trench bottom is Dc, where Da > Db, Da > Dc, and Db ≈ Dc.
Preferably, the depth Db from the top of the trench to the top of the raised edge of the trench sidewall is greater than 0.2 microns.
Preferably, in at least one of the first trench and the second trench, a maximum width of a trench top is Wa, a width of a protruding edge of a trench sidewall is Wb, and a maximum width of a trench bottom is Wc, where Wa > Wb > Wc, Wa = Wb +2 × Ws, Ws is a width of a spacer.
Preferably, the width of the spacer is greater than 300A, and the material of the spacer is nitride.
Preferably, the shielded gate trench type MOSFET structure further comprises: a third trench formed inside the epitaxial semiconductor layer, the source region and the well region; a first insulating layer formed inside the first trench, the second trench, and the third trench; a source electrode formed over the first trench, the second trench, and the second source conductive channel; and a gate electrode formed over the third trench, wherein an opening is formed between the source electrode and the gate electrode.
Preferably, inside the first trench, a source conductor, a dielectric layer and a first source conductive channel are formed inside the first insulating layer, and the first source conductive channel electrically connects the source electrode and the source conductor; inside the second trench, a first gate oxide, a first shield conductor, and the dielectric layer are formed inside the first insulating layer; and in the third groove, a second grid oxide, a second shielding conductor, a grid contact area and a grid conductive channel are formed in the first insulating layer, the grid conductive channel is electrically connected with the grid electrode and the grid contact area, and the grid contact area is connected with the grid conductive channel and the second shielding conductor.
Preferably, the shielded gate trench type MOSFET structure further comprises: and the body contact region is formed on the well region, the second source electrode conductive channel is formed on the body contact region, the second source electrode conductive channel is electrically connected with the source electrode and the body contact region, and the body contact region is electrically connected with the second source electrode conductive channel and the well region.
In another aspect of the present invention, there is also provided a method for manufacturing a shielded gate trench MOSFET, including the steps of: forming an epitaxial semiconductor layer over a semiconductor substrate; forming a hard mask oxide layer over the epitaxial semiconductor layer; forming spacers over the epitaxial semiconductor layer and between sidewalls of the hard mask oxide layer; forming a source region over the epitaxial semiconductor layer under the coverage of the hard mask oxide layer and the spacer; forming a well region inside the epitaxial semiconductor layer; forming a first trench and a second trench in the epitaxial semiconductor layer, the source region and the well region by using the hard mask oxide layer and the spacer as hard masks; and forming a second source conductive channel inside the source region and the well region and between the first trench and the second trench; wherein a shortest distance between the first trench and the second trench defines a maximum width of the second source conductive channel.
Preferably, the step of forming the source region over the epitaxial semiconductor layer under the coverage of the hard mask oxide layer and the spacer comprises: under the coverage of the hard mask oxide layer and the spacer, performing inclined angle comprehensive well region ion implantation on the epitaxial semiconductor layer to form the source region; wherein a well region recess is formed between the first trench and the second trench.
Preferably, the step of forming the first trench and the second trench inside the epitaxial semiconductor layer, the source region, and the well region using the hard mask oxide layer and the spacer as a hard mask includes: etching the source region and the well region by using the hard mask oxide layer and the spacer as hard masks, thereby forming a part of the first trench and the second trench; removing the spacer; etching the epitaxial semiconductor layer, the source region and the well region by using the hard mask oxide layer to form the first groove and the second groove completely; wherein a trench sidewall of each of the first trench and the second trench has a stepped shape or a raised edge such that a width of each of the first trench and the second trench increases stepwise from a bottom to a top.
Preferably, in at least one of the first and second trenches, the depth from the trench top to the raised edge bottom of the trench sidewalls is Da, the depth from the trench top to the raised edge top of the trench sidewalls is Db, and the depth from the raised edge bottom of the trench sidewalls to the trench bottom is Dc, where Da > Db, Da > Dc, and Db ≈ Dc.
Preferably, the depth Db from the top of the trench to the top of the raised edge of the trench sidewall is greater than 0.2 microns.
Preferably, in at least one of the first trench and the second trench, a maximum width of a trench top is Wa, a width of a protruding edge of a trench sidewall is Wb, and a maximum width of a trench bottom is Wc, where Wa > Wb > Wc, Wa = Wb +2 × Ws, Ws is a width of the spacer.
Preferably, the width of the spacer is greater than 300A, and the material of the spacer is nitride.
The shielding gate groove type MOSFET structure and the manufacturing method thereof provided by the invention have the following advantages: (1) different materials can be formed on the interface (or surface) of the MOSFET structure, the etching sequence is arranged and a proper resist is selected according to the chemical characteristics of the different materials, so that the etching self-alignment can be realized, and the technical problem that when the space between two unit cells is too small, the conventional photoetching machine is easy to be out of alignment and cannot meet the required resolution is solved; (2) since self-alignment can be achieved without the need for defining an etch pattern through a mask, and without the need for defining an ion implantation range through a mask, steps of a semiconductor manufacturing process are simplified and corresponding manufacturing time and cost are saved.
Drawings
Fig. 1 is a schematic cross-sectional view of a shielded gate trench MOSFET according to an embodiment of the invention.
Fig. 2 to 11 are schematic views of a method of manufacturing a shielded gate trench MOSFET according to an embodiment of the present invention.
Detailed Description
The technical means adopted by the invention to achieve the predetermined object of the invention are further described below with reference to the drawings and the preferred embodiments of the invention. Like reference numerals are used to refer to like elements throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, some well-known elements may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
Fig. 1 is a schematic cross-sectional view of a shielded gate trench MOSFET according to an embodiment of the invention. As shown in fig. 1, the shielded gate trench MOSFET of the present invention includes a semiconductor substrate 100, an epitaxial semiconductor layer 101, a first insulating layer 102, a source region 103, a well region 104, a first trench 105, a second trench 106, a third trench 107, a source conductor 1100, a first shielding conductor 1080, a second shielding conductor 1090, a first gate oxide 108, a second gate oxide 109, a dielectric layer 110, a first source conductive channel 111, a second source conductive channel 112, a gate conductive channel 113, a source electrode 114, a gate electrode 115, a body contact region 121, and a gate contact region 122.
Structurally, an epitaxial semiconductor layer 101 is formed over a semiconductor substrate 100; well region 104 is formed over epitaxial semiconductor layer 101; source regions 103 are formed inside well regions 104; a first trench 105, a second trench 106, and a third trench 107 are formed inside the epitaxial semiconductor layer 101, the source region 103, and the well region 104; and the first insulating layer 102 is formed inside the first trench 105, the second trench 106, and the third trench 107. Inside the first trench 105, a source conductor 1100, a dielectric layer 110 and a first source conductive channel 111 are formed inside the first insulating layer 102, and the first source conductive channel 111 electrically connects the source electrode 114 and the source conductor 1100. Inside the second trench 106, a first gate oxide 108, a first shield conductor 1080 and a dielectric layer 110 are formed inside the first insulating layer 102. Inside the third trench 107, a second gate oxide 109, a second shielding conductor 1090, a gate contact region 122, and a gate conductive channel 113 are formed inside the first insulating layer 102, the gate conductive channel 113 electrically connects the gate electrode 115 and the gate contact region 122, and the gate contact region 122 connects the gate conductive channel 113 and the second shielding conductor 1090. Body contact regions 121 are formed over well regions 104; a second source conductive channel 112 is formed over the body contact region 121, inside the source region 103 and the well region 104, and between the two trenches; the second source conductive via 112 is electrically connected to the source electrode 114 and the body contact region 121, and the body contact region 121 is electrically connected to the second source conductive via 112 and the well region 104. A source electrode 114 is formed over the first trench 105 and the second trench 106, and a gate electrode 115 is formed over the third trench 107. An opening 116 is formed between the source electrode 114 and the gate electrode 115. A well region recess 1040 is formed between the two trenches; for example, well region recess 1040 is formed between first trench 105 and second trench 106, well region recess 1040 is formed between second trench 106 and third trench 107, and so on.
In one embodiment, each trench sidewall has a stepped shape such that the width of the trench increases stepwise from the bottom to the top; specifically, the first trench sidewall 1050 of the first trench 105, the second trench sidewall 1060 of the second trench 106, and the third trench sidewall 1070 of the third trench 107 have a stepped shape. In one embodiment, each trench sidewall has a raised edge; for example, the first trench sidewall 1050, the second trench sidewall 1060, and the third trench sidewall 1070 have raised edges. In one embodiment, the width of the gate oxide in the raised edges of the trench sidewalls is greater than the width of the shield conductor in the trench bottom; specifically, the width of first gate oxide 108 within the raised edges of second trench sidewalls 1060 is greater than the width of first shield conductor 1080 within the bottom of second trench 106, and the width of second gate oxide 109 within the raised edges of third trench sidewalls 1070 is greater than the width of second shield conductor 1090 within the bottom of third trench 107.
In the shielded gate trench MOSFET structure of fig. 1, the shortest distance between two trenches defines the maximum width W of the conductive channel, so that the present invention does not need to define the maximum width W of the conductive channel through a mask in a semiconductor manufacturing process for forming the conductive channel, thus simplifying the steps of the semiconductor manufacturing process and saving the corresponding manufacturing time and cost. In other words, since the shortest distance between two trenches defines the maximum width W of the conductive channel, the present invention can realize self-aligned contact (self-aligned contact) of the conductive channel, thus solving the technical problem that the existing photolithography tool is easily misaligned and cannot satisfy the required resolution when the space between two unit cells is too small.
Fig. 2 to 11 are schematic views of a method of manufacturing a shielded gate trench MOSFET according to an embodiment of the present invention. As shown in fig. 2, an epitaxial semiconductor layer 101 is formed over a semiconductor substrate 100, and a hard mask oxide layer 118 is formed over the epitaxial semiconductor layer 101. The patterning of the hard mask oxide layer 118 may be achieved by: a photoresist layer is formed over the epitaxial semiconductor layer 101 and then etched, and in the above etching process, dry etching may be employed. The semiconductor substrate 100 may be composed of silicon and be of a first doping type. The first doping type is one of an N-type and a P-type, and the second doping type is the other of the N-type and the P-type. An epitaxial semiconductor layer 101 is formed over a semiconductor substrate 100.
As shown in fig. 3, spacers 119 are formed over the epitaxial semiconductor layer 101 and adjacent to the hard mask oxide layer 118; for example, the hard mask oxide layer 118 is adjacent to one spacer 119 on both sides. In an embodiment, the width Ws of each spacer 119 is greater than 300A (1A = 10A)-10Rice). In one embodiment, the spacer 119 is made of a material such as nitride (SiN). Patterning of the spacers 119 may be achieved by: on the epitaxial semiconductorA photoresist layer is formed over layer 101 and between the sidewalls of hard mask oxide layer 118 and then etched, during which a wet etch may be used.
It is noted that pattern refinement can be achieved by forming a spacer 119 on each side of the hard mask oxide layer 118. Specifically, in the absence of the spacers 119, the distance between the two hard mask oxide layers 118 is the width Wa; in the case of the spacers 119, the distance between the two hard mask oxide layers 118 is the width Wb, where Wa = Wb +2 × Ws, Wa > Wb. Therefore, by forming one spacer 119 on both sides of the hard mask oxide layer 118, respectively, the distance between the two hard mask oxide layers 118 can be further reduced from the width Wa to the width Wb, thus achieving pattern refinement. In other words, the present invention achieves pattern refinement by forming a spacer 119 on each side of the hard mask oxide layer 118, thereby solving the problem that the conventional photolithography tool is easily misaligned and cannot satisfy the required resolution.
As shown in fig. 4, a source region 103 is formed in the epitaxial semiconductor layer 101. The formation of the source region 103 may be achieved by: blanket source region ion implantation (Blanket source implantation) is performed on epitaxial semiconductor layer 101 under the coverage of hard mask oxide layer 118 and spacers 119, followed by annealing (Anneal) to allow ion diffusion. In one embodiment, the ions implanted in the epitaxial semiconductor layer 101 are, for example, arsenic (As) or phosphorus (P). It is noted that the step of forming the source region 103 does not require a mask to define the ion implantation range, which simplifies the steps of the semiconductor manufacturing process and saves the corresponding manufacturing time and cost.
As shown in fig. 5, a well region 104 is formed over the epitaxial semiconductor layer 101, a source region 103 is formed inside the well region 104, and a first trench 105, a second trench 106, and a third trench 107 are formed inside the source region 103 and the well region 104. The formation of the well region 104 may be achieved by: using the hard mask oxide layer 118 and the spacer 119 as a hard mask (exposed width Wb), tilt angle global well implantation (Blanket well implantation with tilting angle) is performed on the epitaxial semiconductor layer 101 anddrive-in, the depth of the ion implantation and drive of well region 104 is Dp. In one embodiment, the ions implanted into the epitaxial semiconductor layer 101 are, for example, boron (B) or boron difluoride (BF)2). The first etching of the first trench 105, the second trench 106 and the third trench 107 may be achieved by: source region 103 and well region 104 are etched using hard mask oxide layer 118 and spacers 119 as a hard mask, thereby forming portions of first trench 105, second trench 106, and third trench 107. It is noted that the steps of forming well region 104, first trench 105, second trench 106, and third trench 107 do not require additional masks to define the ion implantation range and the trench range, which simplifies the steps of the semiconductor manufacturing process and saves corresponding manufacturing time and cost. In addition, because the present invention uses tilt-angle global well ion implantation to form the well 104, a well recess 1040 is formed between the two trenches; for example, a well region recess 1040 is formed between first trench 105 and second trench 106, and a well region recess 1040 is formed between second trench 106 and third trench 107.
As shown in fig. 6, the spacers 119 are removed, and the method of removing the spacers 119 may be dry or wet etching.
As shown in fig. 7, the bottoms of the first trench 105, the second trench 106, and the third trench 107 are formed inside the epitaxial semiconductor layer 101. In one embodiment, the depth from the top of the trench to the bottom of the raised edge of the trench sidewalls is Da, the depth from the top of the trench to the top of the raised edge of the trench sidewalls is Db, and the depth from the bottom of the raised edge of the trench sidewalls to the bottom of the trench is Dc, where Da > Db, Da > Dc, and Db ≈ Dc. In one embodiment, the depth Db from the top of the trench to the top of the raised edge of the trench sidewall is greater than 0.2 microns; experiments show that the reliability requirement of the existing MOSFET device can be met on the premise of meeting the characteristics. Further, the depth Dc from the bottom of the ridge edge of the trench sidewall to the bottom of the trench directly affects the source-drain voltage Vds or the source-drain capacitance Cds of the MOSFET device, so the depth Db, Dc needs to be considered at the same time.
In one embodiment, the maximum width of the trench top is Wa, the width of the raised edge of the trench sidewall is Wb, and the maximum width of the trench bottom is Wc, where Wa > Wb > Wc, Wa = Wb +2 Ws, and Ws is the width of the spacer 119 of fig. 7. The maximum width Wa of the top of the trench controls the maximum width of the second source conductive channel 112 and thus further controls the product operating characteristics of the MOSFET device. The second etching of the first trench 105, the second trench 106 and the third trench 107 may be achieved by: the source region 103, the well region 104 and the epitaxial semiconductor layer 101 are etched using the hard mask oxide layer 118 as a hard mask, thereby forming the complete first trench 105, the second trench 106 and the third trench 107. In one embodiment, the source region 103 and well region 104 not covered by the hard mask oxide layer 118 are etched to a depth Db.
As shown in fig. 8, the first insulating layer 102 is formed inside the first trench 105, the second trench 106, and the third trench 107. Inside the first trench 105, a source conductor 1100 is formed inside the first insulating layer 102. Inside the second trench 106, a first gate oxide 108 and a first shield conductor 1080 are formed inside the first insulating layer 102. Inside the third trench 107, a second gate oxide 109 and a second shield conductor 1090 are formed inside the first insulating layer 102. A first insulating layer 102 may be formed over the well region 104, the first trench 105, the second trench 106, and the third trench 107 through a thermal oxidation process. The fabrication process for forming the structure of fig. 8 should be familiar to those skilled in the art and will not be described herein.
As shown in fig. 9, a dielectric layer 110 is formed on top of the first trench 105, the second trench 106 and the third trench 107, and the first insulating layer 102 over the well region 104 is removed. The method of removing the excess first insulating layer 102 and the dielectric layer 110 may be Chemical-Mechanical Polishing (CMP).
As shown in fig. 10, a first source conductive channel 111 is formed inside the first insulating layer 102, the dielectric layer 110 and the source conductor 1100; a second source conductive channel 112 is formed inside the source region 103 and the well region 104, between the two trenches, and over the body contact region 121; a gate conductive channel 113 is formed inside the first insulating layer 102, the dielectric layer 110 and the source conductor 1100, and over the gate contact region 122; a body contact region 121 is formed between the second source conductive channel 112 and the well region 104; a gate contact region 122 is formed inside the second gate oxide 109.
The patterning of the second source conductive channel 112 may be achieved by: the maximum width W of the second source conductive channel 112 is defined by the shortest distance between the two trenches, then the source region 103 between the two trenches is etched and metal is deposited inside the second source conductive channel 112. The method of etching the second source conductive channel 112 may be dry or wet etching. Since the shortest distance between two trenches defines the maximum width W of the conductive channel, the present invention can achieve self-aligned contact of the second source conductive channel 112, thus solving the technical problem that the conventional photolithography tool is easily misaligned to fail to satisfy the required resolution when the space between two cells is too small.
The patterning of the first source conductive channel 111 and the gate conductive channel 113 may be achieved by: a photoresist layer is formed over the trench and then etched, and metal is deposited inside the first source conductive channel 111 and the gate conductive channel 113. The method of etching the first source conductive path 111 and the gate conductive path 113 may be dry or wet etching. The fabrication process for forming the body contact region 121 and the gate contact region 122 should be familiar to those skilled in the art, and will not be described herein.
As shown in fig. 11, a source electrode 114 is formed over the first trench 105, the second trench 106, the first source conductive channel 111, and the second source conductive channel 112; a gate electrode 115 is formed over the third trench 107 and the gate conductive channel 113; and an opening 116 is formed between the source electrode 114 and the gate electrode 115. The formation of the source electrode 114 and the gate electrode 115 may be achieved by: a metal layer is formed over the MOSFET structure of fig. 10, a photoresist layer is formed over the metal layer, and then an etch is performed to etch an opening 116 between the source electrode 114 and the gate electrode 115. The method of etching the opening 116 may be dry or wet etching.
In brief, the manufacturing process steps of fig. 2 to 11 include: forming an epitaxial semiconductor layer 101 over a semiconductor substrate 100; forming a hard mask oxide layer 118 over the epitaxial semiconductor layer 101; spacers 119 are formed over the epitaxial semiconductor layer 101 and between sidewalls of the hard mask oxide layer 118; forming a source region 103 over the epitaxial semiconductor layer 101 under the coverage of the hard mask oxide layer 118 and the spacers 119; forming a well region 104 inside the epitaxial semiconductor layer 101; forming a first trench 105 and a second trench 105 inside the epitaxial semiconductor layer 101, the source region 103, and the well region 104 using the hard mask oxide layer 118 and the spacer 119 as hard masks; and inside the source region 103 and the well region 104 and between the first trench 105 and the second trench 106, a second source conductive channel 112 is formed; wherein the shortest distance W between the first trench 105 and the second trench 106 defines the maximum width of the second source conductive channel 112.
Through the fabrication processes and structure designs of fig. 2 through 11, different materials may be formed on the interface (or surface) of the MOSFET structure, for example, the first insulating layer 102 (oxide), the dielectric layer 110 (oxide), and the well region 104 (silicon) on the interface (or surface) of the MOSFET structure of fig. 9. The self-alignment of etching can be realized by arranging the etching sequence and selecting proper resists according to the chemical characteristics of different materials, so that the technical problem that the prior photoetching machine is easy to be misaligned and cannot meet the required resolution when the space between two unit cells is too small is solved.
In summary, the shielded gate trench MOSFET structure and the method for manufacturing the same according to the present invention can form different materials on the interface (or surface) of the MOSFET structure, arrange the etching sequence and select an appropriate resist according to the chemical characteristics of the different materials, and achieve self-alignment of etching, thereby solving the technical problem that the conventional photolithography tool is easily misaligned and cannot satisfy the required resolution when the space between two cells is too small. Further, because the shielded gate trench type MOSFET structure and the method for manufacturing the same provided by the present invention can realize self-alignment of etching without defining an etching pattern through a mask or defining an ion implantation range through a mask, the steps of a semiconductor manufacturing process are simplified and corresponding manufacturing time and cost are saved.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (17)
1. A method for manufacturing a shielded gate trench MOSFET structure, comprising the steps of:
forming an epitaxial semiconductor layer over a semiconductor substrate;
forming a hard mask oxide layer over the epitaxial semiconductor layer;
forming spacers between sidewalls of the hard mask oxide layer and over the epitaxial semiconductor layer, the spacers being nitride;
forming a source region over the epitaxial semiconductor layer under the coverage of the hard mask oxide layer and the spacer;
forming a well region in the epitaxial semiconductor layer;
forming a first trench and a second trench in the epitaxial semiconductor layer, the source region and the well region by using the hard mask oxide layer and the spacer as hard masks; and
forming a second source conductive channel inside the source region and the well region and between the first trench and the second trench;
wherein a shortest distance between the first trench and the second trench defines a maximum width of the second source conductive channel.
2. The method of fabricating a shielded gate trench MOSFET structure according to claim 1 wherein the step of forming said source region over said epitaxial semiconductor layer under the coverage of said hardmask oxide layer and said spacers comprises:
under the coverage of the hard mask oxide layer and the spacer, performing inclined angle comprehensive well region ion implantation on the epitaxial semiconductor layer to form the source region;
wherein a well region recess is formed between the first trench and the second trench.
3. The method of manufacturing a shielded gate trench MOSFET structure according to claim 1, wherein the step of forming said first trench and said second trench inside said epitaxial semiconductor layer, said source region and said well region using said hard mask oxide layer and said spacers as a hard mask comprises:
etching the source region and the well region by using the hard mask oxide layer and the spacer as hard masks, thereby forming a part of the first trench and the second trench;
removing the spacer;
etching the epitaxial semiconductor layer, the source region and the well region by using the hard mask oxide layer to form the first groove and the second groove completely;
wherein a trench sidewall of each of the first trench and the second trench has a stepped shape or a raised edge such that a width of each of the first trench and the second trench increases stepwise from a bottom to a top.
4. The method of manufacturing a shield-gate trench MOSFET structure according to claim 1, wherein in at least one of the first trench and the second trench, a depth from a top of the trench to a bottom of a convex edge of a trench sidewall is Da, a depth from the top of the trench to the top of the convex edge of the trench sidewall is Db, and a depth from the bottom of the convex edge of the trench sidewall to the bottom of the trench is Dc, where Da > Db, Da > Dc, and Db ≈ Dc.
5. The method of manufacturing a shielded gate trench MOSFET structure according to claim 4 wherein said depth Db from the top of said trench to the top of the raised edge of the sidewall of said trench is greater than 0.2 microns.
6. The method of manufacturing a shielded gate trench MOSFET structure according to claim 1, wherein in at least one of said first trench and said second trench, a maximum width of a top of the trench is Wa, a width of a protruding edge of a sidewall of the trench is Wb, and a maximum width of a bottom of the trench is Wc, where Wa > Wb > Wc, Wa = Wb +2 Ws, Ws is a width of said spacer.
7. The method of manufacturing a shielded gate trench MOSFET structure according to claim 6 wherein the width of said spacers is greater than 300 a and the material of said spacers is nitride.
8. A shielded gate trench MOSFET structure fabricated by the method of claim 1, comprising:
a semiconductor substrate;
an epitaxial semiconductor layer formed over the semiconductor substrate;
the well region is formed above the epitaxial semiconductor layer;
the source region is formed inside the well region;
a first trench and a second trench formed inside the epitaxial semiconductor layer, the source region and the well region; and
a second source conductive channel formed inside the source region and the well region and between the first trench and the second trench;
wherein a shortest distance between the first trench and the second trench defines a maximum width of the second source conductive channel.
9. The shielded gate trench MOSFET structure of claim 8 wherein a well recess is formed between said first trench and said second trench.
10. The shielded gate trench MOSFET structure of claim 8 wherein the trench sidewalls of each of said first trench and said second trench have a stepped shape or a raised edge such that the width of each of said first trench and said second trench increases stepwise from bottom to top.
11. The shield-gate trench MOSFET structure of claim 8 wherein in at least one of the first trench and the second trench, the depth from the top of the trench to the bottom of the raised edge of the trench sidewall is Da, the depth from the top of the trench to the top of the raised edge of the trench sidewall is Db, and the depth from the bottom of the raised edge of the trench sidewall to the bottom of the trench is Dc, where Da > Db, Da > Dc, and Db ≈ Dc.
12. The shielded gate trench MOSFET structure of claim 11 wherein said depth Db from the top of said trench to the top of the raised edge of said trench sidewall is greater than 0.2 microns.
13. The shielded gate trench MOSFET structure of claim 8 wherein in at least one of said first trench and said second trench, the maximum width of the top of the trench is Wa, the width of the raised edge of the trench sidewall is Wb, and the maximum width of the bottom of the trench is Wc, where Wa > Wb > Wc, Wa = Wb +2 Ws, Ws is the width of the spacer.
14. The shielded gate trench MOSFET structure of claim 13 wherein the spacers have a width greater than 300 a and the spacer material is nitride.
15. The shielded gate trench MOSFET structure of claim 8 wherein said shielded gate trench MOSFET structure further comprises:
a third trench formed inside the epitaxial semiconductor layer, the source region and the well region;
a first insulating layer formed inside the first trench, the second trench, and the third trench;
a source electrode formed over the first trench, the second trench, and the second source conductive channel; and
a gate electrode formed over the third trench,
wherein an opening is formed between the source electrode and the gate electrode.
16. The shielded gate trench MOSFET structure of claim 15,
inside the first trench, a source conductor, a dielectric layer and a first source conductive channel are formed inside the first insulating layer, and the first source conductive channel is electrically connected to the source electrode and the source conductor;
inside the second trench, a first gate oxide, a first shield conductor, and the dielectric layer are formed inside the first insulating layer; and
in the third trench, a second gate oxide, a second shielding conductor, a gate contact region, and a gate conductive channel are formed in the first insulating layer, the gate conductive channel is electrically connected to the gate electrode and the gate contact region, and the gate contact region is connected to the gate conductive channel and the second shielding conductor.
17. The shielded gate trench MOSFET structure of claim 16 further comprising:
and the body contact region is formed on the well region, the second source electrode conductive channel is formed on the body contact region, the second source electrode conductive channel is electrically connected with the source electrode and the body contact region, and the body contact region is electrically connected with the second source electrode conductive channel and the well region.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101626033A (en) * | 2008-07-09 | 2010-01-13 | 飞兆半导体公司 | Structure and method for forming a shielded gate trench fet with an inter-electrode dielectric having a low-k dielectric therein |
| US20110291186A1 (en) * | 2010-06-01 | 2011-12-01 | Hamza Yilmaz | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN112750897A (en) * | 2019-10-29 | 2021-05-04 | 华润微电子（重庆）有限公司 | Groove type field effect transistor structure and preparation method thereof |
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| CN102623501B (en) * | 2011-01-28 | 2015-06-03 | 万国半导体股份有限公司 | Shielded gate trench MOSFET with increased source-metal contact |
| US8541302B2 (en) * | 2011-12-15 | 2013-09-24 | Semiconductor Components Industries, Llc | Electronic device including a trench with a facet and a conductive structure therein and a process of forming the same |
| KR101832334B1 (en) * | 2013-03-05 | 2018-02-27 | 매그나칩 반도체 유한회사 | Semiconductor device and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101626033A (en) * | 2008-07-09 | 2010-01-13 | 飞兆半导体公司 | Structure and method for forming a shielded gate trench fet with an inter-electrode dielectric having a low-k dielectric therein |
| US20110291186A1 (en) * | 2010-06-01 | 2011-12-01 | Hamza Yilmaz | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN112750897A (en) * | 2019-10-29 | 2021-05-04 | 华润微电子（重庆）有限公司 | Groove type field effect transistor structure and preparation method thereof |
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