CN102623501B - Shielded gate trench MOSFET with increased source-metal contact - Google Patents
Shielded gate trench MOSFET with increased source-metal contact Download PDFInfo
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- CN102623501B CN102623501B CN201210022166.4A CN201210022166A CN102623501B CN 102623501 B CN102623501 B CN 102623501B CN 201210022166 A CN201210022166 A CN 201210022166A CN 102623501 B CN102623501 B CN 102623501B
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Abstract
Provided is a semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.
Description
Technical field
The present invention relates to a kind of shielded gate trench metal oxide semiconductor field effect tube with enhancement mode source electrode-metal joint.
Background technology
Current many design of electronic circuits, for the device parameter performance such as switch performance and on-state resistance, have strict requirement.Power MOS (Metal Oxide Semiconductor) device is just through being usually used in this circuit.Shielded gate trench mos field effect transistor (MOSFET) is a kind of power MOS (Metal Oxide Semiconductor) device, has good HF switch performance and very low on-state resistance.The existing technology of preparing of dhield grid MOSFET is very complicated and expensive, usually needs the mask of use more than six or six in processing procedure.Existing technology also has very high fraction defective.The device made has very high contact resistance usually, transient characterisitics extremely unstable.
Summary of the invention
The application is being entitled as " shielded gate trench MOSFET element and preparation thereof " in file on August 14th, 2009, and the partial continuous application case of co-pending U.S. Patent Application No. 12/583,192, quotes, hereby with for referencial use.
The invention provides a kind of shielded gate trench metal oxide semiconductor field effect tube with enhancement mode source electrode-metal joint, be applicable to larger source electrode-Metal Contact district and lower contact resistance, more reliably, there is more stable transient response.
For achieving the above object, the invention provides and be a kind ofly formed in the semiconductor device had in the Semiconductor substrate of substrate surface, be characterized in, it comprises:
One to extend to the gate trench Semiconductor substrate from substrate surface;
A gate electrode in gate trench;
A top portions of gates dielectric substance be deposited on above gate electrode;
A body zone near gate trench;
One is embedded in the source area in body zone, and source area extends to above top portions of gates dielectric substance at least partially;
A contact trench making the Contact of source area and body zone; And,
One is deposited on gate trench opening, at least partially source area at least partially and the metal level at least partially above contact trench.
Wherein metal level covers the top portions of gates dielectric substance above gate electrode, and contacts the sidewall of the source area on top portions of gates dielectric substance opposite.
It also comprises a bucking electrode be formed in gate trench, and wherein gate electrode and bucking electrode are separated by inter-electrode dielectric material.
Wherein source area has a basic vertical surface, and surface substantially vertical at least partially directly contacts with metal level.
Wherein gate trench has a trenched side-wall bent at least partly.
Wherein surface at least partially, source area meets the sweep of trenched side-wall.
Wherein metal level contacts with source area on multiple edge.
Wherein on an edge of the source area on contact trench opposite, and on an edge of the source area on top portions of gates dielectric substance opposite, metal level contacts with source area.
The wherein end face of top portions of gates dielectric substance, caves in below the top of source area.
Wherein fill contact trench at least partly with conductive plug.
For the preparation of a method for semiconductor device, be characterized in, the method comprises:
Prepare a gate trench;
A gate electrode is prepared in gate trench;
A top portions of gates dielectric substance is prepared in gate electrode over top;
Prepare a body zone and a source area;
Prepare a contact trench;
Return and carve top portions of gates dielectric substance, make source area at least partially extend to above top portions of gates dielectric substance;
At disposed thereon metal level of gate trench opening, at least partially source area at least partially and contact trench at least partially.
Before the method is also included in and prepares gate electrode, first in gate trench, prepare a bucking electrode.
The method is also included between bucking electrode and gate electrode, prepares an inter-electrode dielectric.
Wherein return and carve top portions of gates dielectric substance, and depositing metal layers, make the top portions of gates dielectric substance above metal level cover gate electrode, and contact a sidewall of the source area on top portions of gates dielectric substance opposite.
Wherein top portions of gates dielectric substance caves in below substrate surface.
Wherein source area has a basic vertical surface, and surface substantially vertical at least partially directly contacts with metal level.
Wherein gate trench has a trenched side-wall bent at least partly.
Wherein surface at least partially, source area meets the sweep of trenched side-wall.
Wherein metal level contacts with source area on multiple edge.
Wherein on an edge of the source area on contact trench opposite, and on an edge of the source area on top portions of gates dielectric substance opposite, metal level contacts with source area.
The method also comprises at least partially in contact trench, deposits a conductive plug.
Wherein metal level forms one at least partially in the conductive plug in contact trench.
The present invention with enhancement mode source electrode-metal joint shielded gate trench metal oxide semiconductor field effect tube compared to the prior art, its advantage is, the present invention is applicable to larger source electrode-Metal Contact district and lower contact resistance, more reliably, has more stable transient response.
Accompanying drawing explanation
Below describe and figure illustrate various embodiment of the present invention in detail.
Flow chart display screen shown in Fig. 1 covers the embodiment of gate MOS FET preparation technology.
Fate map shown in Fig. 2-26C represents the embodiment of device preparation technology.
Embodiment
The present invention can realize in a variety of ways, comprises technique; Device; System; Material composition.In certain embodiments, the present invention can be controlled by the computer program be embedded in readable storage medium and/or processor, such as configuration processor, to perform the order in the internal memory that is stored in and/or is coupled on processor.In the present note, these instruments, or other any forms that the present invention can adopt, be all called technology.In general, the order of affiliated processing step can change within the scope of the invention.Unless specifically stated, the above-mentioned element such as processor or internal memory for executing the task, can as a kind of universal component, provisional configuration when at a time executing the task, or as a kind of professional component, aim at and execute the task and prepare.Noun " processor " used herein refers to one or more device, circuit and/or the process kernel for the treatment of data (such as computer program instructions).
Principle of the present invention is illustrated by the following drawings, and the detailed description of one or more embodiment of the present invention.Described the present invention is relevant with these embodiments, but the present invention is not limited to any embodiment.Scope of the present invention only determined by claims, and the present invention contains various change, correction and equivalent.Various details mentioned in the following description are in order to complete understanding the present invention.These details, only for illustrating, without the need to some or all detail, just can implement the present invention according to claims.For clarity, do not describe in detail, in order to avoid produce unnecessary misunderstanding about technologic material known in technical field of the present invention.
Propose the embodiment of dhield grid MOSFET element and preparation technology.Preparation technology utilizes nitride spacer, adopts self aligned contact system.The dhield grid MOSFET element made has the gate-dielectric of depression, is applicable to larger source electrode-Metal Contact district and lower contact resistance.This device is more reliable, has more stable transient response.
Flow chart shown in Fig. 1, represents the embodiment of dhield grid MOSFET preparation technology.At 102 places, one or more gate contact opening is formed on a semiconductor substrate at least partly.At 104 places, nitride spacer is formed in gate trench open interior.Can etching grid groove, make it be self-aligned to nitride spacer.In follow-up processing procedure, pad prevents substrate to be etched, and forms self aligned contact trench.At 106 places, bucking electrode and gate electrode are formed in groove.Dielectric substance is filled with groove at least partially, and bucking electrode and gate electrode is separated.Bucking electrode protection gate electrode is not by the impact of high pressure.At 108 places, implant the alloy for the preparation of body and source area in the substrate.At 110 places, form contact trench in a self-aligned manner, without the need to any extra mask.At 112 places, conductive plug is deposited in contact trench.At 114 places, return the dielectric substance carved in gate trench, source area is at least partially extended to above dielectric substance.At 116 places, metal level is deposited on gate trench opening, at least partially source area and at least partially above contact trench at least partially.Metal level forms pattern in source electrode and gate metal.In certain embodiments, source metal can contain a metal layer at top and one or more contact trench plug, with source region contact on Multiple edge, thus reduces contact resistance, makes device more reliable.
Artwork shown in Fig. 2-26, represents the embodiment of device preparation technology.In the following discussion, what illustrate is N-type device.Also similar technique can be utilized to prepare P type device.
Fig. 2-5 represents the initial step preparing gate trench.
In fig. 2, utilize N-type substrate 602 as the drain electrode of device.In this example, N-type substrate is a kind of N+ Silicon Wafer, and N-outer layer growth on the wafer surface.In certain embodiments, the doping content of epitaxial loayer is about 3E16-1E17 alloy/cm3, and thickness is 2-4um, and resistance substrate rate is 0.5-3mohm*cm.
Silicon oxide layer 604, by deposition or thermal oxidation, is formed on substrate.Nitration case 606 is deposited on above silicon oxide layer.In certain embodiments, the thickness of silicon oxide layer is about
the thickness of nitration case is about
Then, above nitration case, use photoresist (PR) layer, and utilize the first mask (also referred to as trench mask) to form pattern.In the following discussion, for ease of illustrating, suppose to use positive PR, thus retain not exposed region, remove exposed region.Also negative PR can be used, only mask need be correspondingly revised.Mask defines active gate groove.Mask also can limit other grooves, and such as source polysilicon attracts groove and gate runner/cut-off groove, and these grooves do not indicate in detail in this figure.In certain embodiments, the width of active groove is about 0.6um.The mask fabricate devices that critical dimension can be used to be 0.35um etc. low-grade, thus reduce the cost of required mask.
In figure 3, residual PR layer 701 defines active gate trenches opening 702.In certain embodiments, the groove that source polysilicon attracts groove and gate runner/cut-off groove etc. extra can be prepared, but do not indicate in this figure.
Then, utilize hard mask (HM) to etch, etch away the exposed part of nitration case and silicon oxide layer.Etching stops on a silicon surface.Then remaining PR is removed.In the diagram, in exposed region, form groove opening, simultaneously by remaining Nitride Oxide part, form hard mask.
And then carry out etching groove, etch in groove opening in semi-conducting material 602.According to lithographic method, trenched side-wall can be straight (as shown in Figure 5A) or curved (as shown in Figure 5 B) substantially.In certain embodiments, the target depth of groove is about 0.3um ~ 0.5um.
In groove opening, deposition or heat grow a very thin oxide layer, are covered with channel bottom and trenched side-wall.In certain embodiments, the thickness of oxide layer is about
oxide layer, once be formed, just can deposit an extra nitration case 900.Below nitride, only need the oxide layer that very thin, therefore do not indicate respectively in the drawings.In certain embodiments, extra nitride thickness is about
in certain embodiments, the thickness of nitration case is about
as shown in Figure 6, nitration case 900 is covered with groove, and covers remaining exposed region.
As shown in Figure 7, after comprehensive anisotropy returns quarter, 1000 sector-meetings such as nitride pad such as grade are formed along the sidewall of groove.Initial nitration case 606 part also remains.
Then, interior lining oxide layer exposed in bottom removing groove opening, utilizes comprehensive silicon etching process, deepens the groove in Fig. 8 between nitride spacer further.According to the purposes of device, made gash depth is greatly about 1.5um ~ 2.5um, and the inclination angle of trenched side-wall is about 87 ° ~ 88 °.The alignment procedures that nitride spacer makes self aligned etching technics not need unnecessary alignment mask etc. extra, thus achieve the bevel etched of groove.The depth bounds of groove is from hundreds of dust to several microns.Utilize
circular hole (R/H) etching, make the turning of groove rounder and more smooth, to avoid the high electric field because acute angle causes.
In fig .9, deposition or the one or more oxide layer of heat growth.In certain embodiments, can growth selection one about
sacrificial oxide layer, and to remove, to improve silicon face.Exemplarily, one can be grown in the trench approximately
oxide layer, then deposit one deck about
high-temperature oxide (HTO).
As shown in Figure 10, deposit spathic silicon.In certain embodiments, the thickness of polysilicon is about
larger than the half of the width of groove (not indicating the widest groove) the widest in device.Therefore, the polysilicon layer on sidewall combines, and is filled with groove completely.This layer of polysilicon is sometimes referred to as source polysilicon, shielding polysilicon or polysilicon 1.
Then as shown in figure 11, utilize dry etching, return and carve source polysilicon.In this example, in active gate trenches, remaining polysilicon thickness is about
Then, high-density plasma (HDP) oxide 1506 also densification is deposited.In certain embodiments, densification will continue to carry out about 30 seconds at the temperature of about 1150 DEG C.As shown in figure 12, the thickness of oxide layer 1506 is greater than the half of active groove width (in certain embodiments, the thickness of oxide layer is about
), thus completely fills active groove.
Carry out oxide chemical mechanical polish (CMP).As shown in figure 13, utilize CMP polishing oxide, until the end face of oxide is equal with nitride surface, in this, as the terminal of etching.
Figure 14 represents another oxide layer of interpolation.In certain embodiments, the thickness of oxide layer is about
the thickness of this oxide layer can control the angle of wet etching erosion otch under the second mask.Nitride in this sull non-active area that also protection device is all.Shielded nitride can carry out comprehensively etching without mask of Si after a while.
In certain embodiments, spin coating one deck photoresist on the surface of structure, and utilize the second mask (also referred to as polysilicon mask film covering) to form PR pattern.By the impact of the not oxidated thing wet etching erosion in region (such as end groove, do not indicate in the drawings) that PR covers.In an illustrated embodiment, the impact of oxide wet etching erosion is not subject to by the active groove region that PR covers.
Then, wet etching erosion is carried out.The result of wet etching erosion represents in fig .15.Oxide in the region do not covered by PR has been removed, and remaining oxide is on required height.Oxide layer above polysilicon, such as oxide layer 1908, be called inter polysilicon dielectric (IPD), and its scope can from hundreds of dust to several thousand dusts.
In certain embodiments, formation be asymmetric oxide cut-off/gate runner groove, for these embodiments, the step shown in Figure 13-15 is optional.Also can select, directly return the oxide 1506 in needle drawing 12, to form the IPD 1908 shown in Figure 15.
If employ PR, it to be removed afterwards, and deposition or heat growth one deck gate oxide.In certain embodiments, additional oxidated layer thickness is about
therefore, in figure 16, gate oxide has been covered with the active groove sidewalls such as 2004 and 2006.
Carry out another polysilicon deposition and return carving.Result as shown in figure 17.Deposit spathic silicon filling groove.In certain embodiments, the polysilicon deposition of about 0.5-1um in the trench.Return the polysilicon carved and deposit, form grid polycrystalline silicon, such as 2104 and 2106.The bottom of source electrode is at least encountered at the top of grid polycrystalline silicon, in some cases, also overlapping with the bottom of source electrode, thus can form a passage.In certain embodiments, polysilicon surface is about at the bottom part down of nitride spacer
can select, metal such as deposition one deck titanium or cobalt etc., and anneal.In the place of metal and polysilicon contact, form a multi-crystal silicification layer.Titanium above oxide or nitride or cobalt can not form silicide/polycrystalline silicon, can remove.As shown in the figure, polycrystalline silicon is formed in 2112 and 2114 places above gate polycrystalline silicon electrode 2104 and 2106.
In Figure 18 A, such as, by wet etching process, nitride spacer exposed near removing active gate trenches, and the nitration case above oxide hardmask.
In certain embodiments, Technology for Heating Processing before various (such as oxide deposition, HDP oxide compacting) makes the silica in interface zone, and the degree of nitride oxide in same area is lighter.Due to the selective oxidation (LOCOS) of silicon technology, the substrate surface below nitride spacer is changed, becomes bending.This phenomenon is well known in the art, and is called " beak effect ".In addition, the etching technics before various makes nitride spacer be etched in a particular area, exposes nitride-silicon interface further and makes it be oxidized.Therefore, as shown in figure 18b, when by wet etching process removing nitride spacer and other exposed nitride materials, remaining trenched side-wall just can have curvature.
The body of implant devices and source electrode.The body of implant devices and source electrode do not need extra mask.Exactly, in Figure 19 A and 19B, carry out body implantation.With band angled Doped ions bombardment device.Can with the specific region of protecting nitride device (not indicating in figure).Not by the active area of protecting nitride, implant and form body zone, such as 2304.In certain embodiments, under 60KeV ~ 180KeV, doped level is utilized to be about the boron ion of 1.8e13, preparation N-passage device.Also the ion of other types can be used.Such as, sub-phosphonium ion is utilized to prepare P-passage device.
In Figure 20 A and 20B, carry out source electrode implantation with zero inclination angle.Again bombard device with Doped ions.In certain embodiments, under 40KeV ~ 80KeV, doped level is used to be the arsenic ion of 4e15.The source areas such as 2402 are formed in the body zone such as 2304.In Figure 20 B, the surface of source area is consistent with the curved shape of trenched side-wall.
In Figure 21 A and 21B, dielectric layer deposition (such as oxide layer), filling groove opening, and separated source and gate polysilicon region.In various embodiments, the thickness range of oxide layer exists
between.In certain embodiments, utilize chemical vapour deposition (CVD) (CVD) technique, deposit thickness is about
low temperature oxide (LTO) and containing the silex glass (BPSG) of boric acid.
In Figure 22 A and 22B, return oxide at quarter by deep dry etch process.In this example, downward etching oxide, makes the end face of oxide lower than substrate surface
left and right.The oxide hardmask formed in Fig. 2-4 also can be removed by this technique.
Also can select, (such as by chemico-mechanical polishing (CMP) technique) smooth oxide, makes the end face of oxide equal with substrate surface.What Figure 22 C represented is this possibility.
In Figure 23 A and 23B, etched substrate, forms 2702 contact trench such as grade.According to the purposes of device, etching depth is between 0.6um ~ 0.9um.Etch exposed substrate region, the region of not oxidized thing protection does not etch.Because etching technics does not need extra mask, therefore also referred to as self aligned contact process.In this case, contact trench is self-aligned to the remainder of oxide 2704.As shown in fig. 23b, after etching contact trench, the bottom at contact trench can be selected, preparation (such as implanting) heavily doped P+ body contact region.
In Figure 24 A and 24B, the barrier metal such as depositing Ti and TiN (not indicating especially) can be selected, then by RTP, near contact zone, form Ti silicide.In certain embodiments, the thickness of Ti and TiN used is respectively
with
then, the conductive plug material such as deposits tungsten (W).In certain embodiments, deposit
w.Return the W carving deposition, until substrate surface, to form independent conduction (W) plug such as 3002 grades.
In Figure 25 A and 25B, carry out oxide etching.Return and carve oxide layer.Etching technics eliminates the oxide layer of source electrode and active gate trenches overthe openings, and a part of oxide layer in gate trench, makes the recessed end face to source electrode of remaining oxide layer in gate trench.In other words, the end face of made oxide layer is lower than the end face of source electrode.In certain embodiments, the end face of oxide layer is approximately low than the end face of source area
hereafter also will discuss, in order to source electrode-Metal Contact, etching technics makes more source area out exposed.
Also can select, after the contact trench 2702 in Figure 23 A and 23B, and before preparing conductive plug 3002, carry out this oxide and return carving technology.In one alternate embodiment, the oxide that Figure 24 C and Figure 24 D representation class are similar to Figure 25 A and 25B returns carving technology, but carries out before preparing conductive plug 3002.In this alternative, after preparing the structure shown in Figure 24 C and Figure 24 D, depositing electrically conductive plug, to form the structure shown in Figure 25 A and 25B.
In Figure 26 A and 26B, deposit a metal level.In certain embodiments, AlCu is utilized to prepare the thick metal level of an about 3um ~ 6um.Then, at 450 DEG C, metal is annealed about 30 minutes.In certain embodiments, form the pattern of metal, prepare source electrode and gate metal, be connected to source electrode and gate regions by additional groove (not indicating in figure).Form the top of resulting devices.Although do not indicate, usually after backgrind technique, just can form a metal level in the bottom of substrate.
In the device made, each active gate trenches is containing a top polysilicon silicon electrode (such as polysilicon 3312), because it plays grid, therefore also referred to as grid polycrystalline silicon or gate electrode, or because it is formed at the second poiysilicon deposition process in preparation process, therefore also referred to as polysilicon 2.Each top polysilicon silicon electrode also comprises a multi-crystal silicification nitride layer 3340 be deposited on gate electrode end face, to improve the conductivity along grid.Each groove also comprises a bottom polysilicon electrode (such as polysilicon 3320), because it is connected on source electrode, therefore also referred to as source polysilicon or source electrode, or because it is formed at the first poiysilicon deposition process in preparation process, therefore also referred to as polysilicon 1, or because its dhield grid polysilicon does not affect by high-tension, therefore also referred to as shielding polysilicon or bucking electrode.The inter polysilicon dielectric region be made up of oxide, is separated source polysilicon with grid polycrystalline silicon.In active gate trenches shown in this example, surround grid polycrystalline silicon, and inside lining the oxide layer (oxide layer in such as region 3324) of trench top portion sidewall, than surrounding source electrode/shielding polysilicon, and in lining the oxide layer (such as oxide layer 3326) of channel bottom sidewall thinner.In active area, source metal 3334, by dielectric layer such as oxide 3309 grade, insulate with 3312 gate electrodes such as grade.Source metal 3334 is by the conductors such as tungsten plug 3330, and be electrically connected in source area 3332 and body zone 3348, conductor 3330 fills source body contact opening, and extends in body zone from source metal.Body contacts implantation region 3346 enhances the ohmic contact between body zone and conductor 3330.
Above-mentioned technique has prepared a kind of MOSFET element of the source electrode-Metal Contact district with strengthening.Exactly, because source area extends on gate oxide end face, therefore just there is multiple surface (such as at 3302,3304 and 3306 places, surface) contacted with top metal (such as source metal 3334 and conductive plug 3330) an independent source area.Such as, top metal is connected to source area, on the surface, source area 3302 on contact trench opposite, on the surface, source area 3306 on oxide 3309 opposite of depression, and on source area end face 3304.The oxide 3309 caved in above gate regions makes metal be connected to the source sidewall 3306 on depression oxide opposite.Source electrode-Metal Contact the district strengthened reduces contact resistance, and makes transient response more stable.And enhancement region means that the possibility of contact existing defects is minimum, and therefore device is more reliable, and output is higher.In certain embodiments, conductive plug 3330 ' is made up of the material identical with source metal 3334, as shown in Figure 26 C.In this case, can with remaining source metal 3334 preparation/filled conductive plug 3330 ' simultaneously.
Above-mentioned example majority is all be described by N-passage device.As long as by the reversal of various alloy once, above-mentioned technique just goes for P-passage device.
Although for the ease of understanding, give the detail of above-described embodiment, the present invention is not limited to these details.The present invention also has many optional implementation methods.Described embodiment, for explaining explanation, is not used in limitation.
Claims (22)
1. be formed in the semiconductor device had in the Semiconductor substrate of substrate surface, it is characterized in that, it comprises:
One to extend to the gate trench Semiconductor substrate from substrate surface;
A gate electrode in gate trench;
A top portions of gates dielectric substance be deposited on above gate electrode;
A body zone near gate trench;
One is embedded in the source area in body zone;
A contact trench making the Contact of source area and body zone; And,
One is deposited on gate trench opening, at least partially source area at least partially and the metal level at least partially above contact trench;
Described source area comprises a crooked sidewall part, and it is adjacent to gate trench, and extends to the top of top portions of gates dielectric substance.
2. semiconductor device as claimed in claim 1, it is characterized in that, wherein metal level covers the top portions of gates dielectric substance above gate electrode, and contacts the sidewall of the source area on top portions of gates dielectric substance opposite.
3. semiconductor device as claimed in claim 1, it is characterized in that, it also comprises a bucking electrode be formed in gate trench, and wherein gate electrode and bucking electrode are separated by inter-electrode dielectric material.
4. semiconductor device as claimed in claim 1, is characterized in that, wherein source area has a vertical surface, and surface vertical at least partially directly contacts with metal level.
5. semiconductor device as claimed in claim 1, is characterized in that, wherein gate trench has a trenched side-wall bent at least partly.
6. semiconductor device as claimed in claim 5, it is characterized in that, described crooked sidewall part meets the sweep of trenched side-wall at least partially.
7. semiconductor device as claimed in claim 1, it is characterized in that, wherein metal level contacts with source area on multiple edge.
8. semiconductor device as claimed in claim 1, it is characterized in that, wherein on an edge of the source area on contact trench opposite, and on an edge of the source area on top portions of gates dielectric substance opposite, metal level contacts with source area.
9. semiconductor device as claimed in claim 1, is characterized in that, wherein the end face of top portions of gates dielectric substance, caves in below the top of source area.
10. semiconductor device as claimed in claim 1, is characterized in that, wherein fill contact trench at least partly with conductive plug.
11. 1 kinds, for the preparation of the method for semiconductor device, is characterized in that, the method comprises:
Prepare a gate trench;
A gate electrode is prepared in gate trench;
A top portions of gates dielectric substance is prepared in gate electrode over top;
Prepare a body zone and a source area;
Prepare a contact trench;
Return and carve top portions of gates dielectric substance, make source area at least partially extend to above top portions of gates dielectric substance;
At disposed thereon metal level of gate trench opening, at least partially source area at least partially and contact trench at least partially.
12. methods as claimed in claim 11, is characterized in that, before the method is also included in and prepares gate electrode, first in gate trench, prepare a bucking electrode.
13. methods as claimed in claim 12, it is characterized in that, the method is also included between bucking electrode and gate electrode, prepares an inter-electrode dielectric.
14. methods as claimed in claim 11, it is characterized in that, wherein return and carve top portions of gates dielectric substance, and depositing metal layers, make the top portions of gates dielectric substance above metal level cover gate electrode, and contact a sidewall of the source area on top portions of gates dielectric substance opposite.
15. methods as claimed in claim 11, it is characterized in that, wherein top portions of gates dielectric substance caves in below substrate surface.
16. methods as claimed in claim 11, is characterized in that, wherein source area has a vertical surface, and surface vertical at least partially directly contacts with metal level.
17. methods as claimed in claim 11, is characterized in that, wherein gate trench has a trenched side-wall bent at least partly.
18. methods as claimed in claim 17, it is characterized in that, wherein surface at least partially, source area meets the sweep of trenched side-wall.
19. methods as claimed in claim 11, it is characterized in that, wherein metal level contacts with source area on multiple edge.
20. methods as claimed in claim 11, is characterized in that, wherein on an edge of the source area on contact trench opposite, and on an edge of the source area on top portions of gates dielectric substance opposite, metal level contacts with source area.
21. methods as claimed in claim 11, it is characterized in that, the method also comprises at least partially in contact trench, deposits a conductive plug.
22. methods as claimed in claim 11, it is characterized in that, wherein metal level forms one at least partially in the conductive plug in contact trench.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/016,804 | 2011-01-28 | ||
| US13/016,804 US8618601B2 (en) | 2009-08-14 | 2011-01-28 | Shielded gate trench MOSFET with increased source-metal contact |
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| CN102623501A CN102623501A (en) | 2012-08-01 |
| CN102623501B true CN102623501B (en) | 2015-06-03 |
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| US8999783B2 (en) * | 2013-02-06 | 2015-04-07 | Infineon Technologies Austria Ag | Method for producing a semiconductor device with a vertical dielectric layer |
| US9196701B2 (en) * | 2013-03-11 | 2015-11-24 | Alpha And Omega Semiconductor Incorporated | High density MOSFET array with self-aligned contacts enhancement plug and method |
| US9209305B1 (en) * | 2014-06-06 | 2015-12-08 | Stmicroelectronics, Inc. | Backside source-drain contact for integrated circuit transistor devices and method of making same |
| CN104769723B (en) * | 2014-12-04 | 2018-10-23 | 冯淑华 | Groove power semiconductor field-effect transistor |
| JP6514519B2 (en) * | 2015-02-16 | 2019-05-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| CN110896053B (en) * | 2019-12-06 | 2022-04-29 | 绍兴中芯集成电路制造股份有限公司 | Shielded gate field effect transistor and method of forming the same |
| CN113241372B (en) * | 2021-05-19 | 2022-09-06 | 深圳真茂佳半导体有限公司 | Preparation method and structure of self-aligned power field effect transistor |
| CN113241374B (en) * | 2021-05-19 | 2023-07-14 | 深圳真茂佳半导体有限公司 | Power transistor structure and manufacturing method thereof |
| CN113284953B (en) * | 2021-07-21 | 2021-11-26 | 江苏长晶科技有限公司 | Shielding gate groove type MOSFET structure and manufacturing method thereof |
| CN117393501B (en) * | 2023-12-07 | 2024-03-19 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| TWI237348B (en) * | 2004-08-26 | 2005-08-01 | Mosel Vitelic Inc | Method of manufacturing trench metal oxide semiconductor field effect transistor |
| TWI236090B (en) * | 2004-10-18 | 2005-07-11 | Episil Technologies Inc | Trench power MOSFET and method for fabricating the same |
| US7633119B2 (en) * | 2006-02-17 | 2009-12-15 | Alpha & Omega Semiconductor, Ltd | Shielded gate trench (SGT) MOSFET devices and manufacturing processes |
| US8278702B2 (en) * | 2008-09-16 | 2012-10-02 | Fairchild Semiconductor Corporation | High density trench field effect transistor |
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| CN1809928A (en) * | 2002-08-23 | 2006-07-26 | 快捷半导体有限公司 | Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses |
| CN101238581A (en) * | 2005-08-09 | 2008-08-06 | 飞兆半导体公司 | Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor |
| CN101626033A (en) * | 2008-07-09 | 2010-01-13 | 飞兆半导体公司 | Structure and method for forming a shielded gate trench fet with an inter-electrode dielectric having a low-k dielectric therein |
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