TWI528423B - Methods for fabricating semiconductor device and semiconductor device - Google Patents

Description

Method and semiconductor component for preparing a semiconductor device

The present invention relates generally to trench metal oxide semiconductor field effect transistors (MOSFETs), and more particularly to methods and semiconductor components for fabricating semiconductor devices.

A DMOS (Double Diffusion MOS) transistor is a transistor that is calibrated to the same edge using two continuous diffusion techniques to produce the channel region of the transistor. DMOS transistors are typically high current components for low voltage and high voltage, used as components of separate transistors or power integrated circuits. DMOS transistors provide very high current per unit area at very low forward voltage drops.

A typical DMOS transistor is a transistor called a trench DMOS transistor in which the channel is on the sidewall of the trench and the gate is formed in the trench, starting from the source and extending toward the drain. The trench gate is covered with a thin oxide layer and filled with polysilicon, and the ability to limit current is inferior to the planar gate DMOS transistor structure, so its specific on-resistance is lower.

However, the conventional method of fabricating such a trench DMOS field effect transistor requires five to six masking techniques, which are not only expensive but also time consuming. The first mask is a deep well mask and is also used for high voltage cutoff. Whether or not to use the mask is selected depending on whether the prepared component is a high voltage component. The second mask is a trench mask used to fabricate trenches for gate and other component structures. The third mask is a bulk mask, which is also used to prepare the cut-off region and protect the gate. The gate oxide in the runner is not destroyed by being exposed to the gate potential, and the gate/gate trace is masked away from the drain voltage. The fourth mask is the source mask, moving the source region out of the gate runner and the cutoff region, thereby shifting the breakdown current out of these regions, improving the performance of the non-embedded sensor switch (UIS). The fourth mask is also used to prepare the channel termination. The fifth mask is a contact mask for preparing the source/body and gate contacts, and the sixth mask is a metal mask for separating the metal layer into gate and source metal regions.

Figure 1 shows a cross-sectional view of trench MOSFET 100 fabricated using the conventional six mask technique described above. As shown in FIG. 1, trench MOSFET 100 includes active cell 102 and gate runner 104 in the active region. The gate runner is connected to the gate in the active cell 102. A P-inversion channel may be formed along the top surface of the N- epitaxial layer 111 toward the end of the wafer. If the P-inverting channel begins at junction stop 108 and touches wafer edge 112, then a leakage current is induced between the source/body and the drain. The heavily doped N+ channel end point 106 prevents such p-reverse channels from reaching the wafer edge 112, where it can be shorted to the drain.

It is an object of the present invention to provide a method and a semiconductor element for fabricating a semiconductor device to reduce cost and simplify fabrication techniques.

A technical solution of the present invention is to provide a method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1 having widths W1, W2, respectively , TR2, wherein W1 is narrower than W2, wherein the trench TR2 includes a first gate runner trench and a second gate slip connected to the trench TR1 a trench, wherein at least one of the first gate runner trench and the second gate runner trench abuts and surrounds the trench TR1; c) at the trenches TR1, TR2 of thickness T1, T2 A gate insulator is prepared on the bottom and sidewalls, wherein T2 is greater than T1; d) a conductive material is prepared in trench TR1 to form a gate electrode, and a conductive material is prepared in trench TR2 to form a first gate runner and a second gate runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; e) preparing a body layer on top of the semiconductor substrate; and f) preparing a top portion of the body layer a source layer; g) using an insulating layer over the semiconductor substrate; h) using a second mask over the insulating layer; i) using a second mask, forming an electrical contact by a contact opening in the insulating layer, wherein the contact opening Included in each of the gate electrodes is a source opening toward the source layer, a gate runner opening toward the gate runner, a cutoff contact opening toward the cutoff structure, and a source layer or body layer near the edge of the wafer Shorting the contact opening; and j) preparing the first metal region on the insulating layer A second metal region, and electrically insulated from each other, wherein the first metal runner and the gate region is electrically connected, wherein the second metal region and electrically connecting the source electrode, wherein a thickness T2 is thick enough, capable of carrying a blocking voltage.

In the above method, b) further comprises preparing a trench T3 having a width W3, wherein W1 is narrower than W3, wherein the trench TR3 comprises a cut-off trench surrounding the trench TR2 and the trench TR2 of the gate runner; c) further comprising preparing a gate insulator on the bottom and sidewalls of the trench TR3 having a thickness T3, wherein T3 is greater than T1; d) further comprising preparing a conductive material in the trench TR3 to form a cutoff structure, wherein the cutoff structure is electrically insulated from the gate runner and the gate electrode; i) further comprising utilizing the second mask by contact in the insulating layer Opening, the electrical connector is prepared, wherein the contact opening comprises a cut-off contact opening toward the cut-off structure, and a short-circuit contact opening toward the source layer or the body layer near the edge of the wafer; and j) further comprising preparing a third metal region on the insulating layer, Wherein the third metal region is electrically connected to the cutoff joint and the shorting joint such that the cutoff structure is shorted to the body region at the edge of the wafer, wherein the thickness T3 is sufficiently thick to carry the latching voltage.

In the method described above, step e) comprises: preparing a body layer on top of the entire semiconductor substrate.

In the above method, the step j) comprises: depositing a metal layer over the insulating layer; using a metal mask over the metal layer; and etching the metal layer to separate the first metal region and the second metal region.

In the above method, step c) comprises: preparing a gate insulating layer by using a mask on the bottom and sidewalls of the trenches TR1, TR2 having thicknesses T1, T2, wherein T2 is greater than T1.

In the above method, step c) comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TR1, TR2; using a gate insulator mask over the thin insulating layer, wherein the gate insulator The mask covers the trench TR2 but does not cover the trench TR1; the portion of the semiconductor substrate that is not covered by the second mask containing the trench TR1 is removed Removing the first gate insulator; and preparing a second gate insulator in the trench TR1, wherein the second gate insulator is thinner than the first gate insulator.

In the above method, by implanting ions at a relatively high energy, step e) is performed, at which the ions can pass through the second gate insulator and the first gate insulator, implanted into In a semiconductor substrate.

In the above method, by implanting ions of a certain energy, step f) is performed, which enables ions to pass through the second gate insulator but not through the first gate insulator and implanted into the semiconductor In the substrate.

In the above described method, the source layer is formed only in the top of the body layer near the trench TR1.

In the above method, step c) comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TR1, TR2; preparing a sacrificial material, completely filling the trench TR1, but merely lining the trench TR2 Retrieving the sacrificial material, removing the sacrificial material on TR2, but retaining the sacrificial material in TR1; preparing a gate insulating layer in trench TR2; and removing the sacrificial material in trench TR1, preparing the gate in trench TR1 A pole insulator in which the gate insulating layer thickness T2 in the trench TR2 is larger than the gate insulating layer thickness T1 in the trench TR1.

In the method described above, the source layer is formed in the top of the entire semiconductor.

In the above-described method, no more than four masks are used to complete steps a) through j).

In the above-described method, no more than three masks are used to complete steps a) through j).

In the above method: b) further comprising preparing a trench T3 having a width W3, wherein W3 is greater than W2, wherein the trench TR3 comprises a cut-off trench surrounding the trench TR1 and the gate runner trench TR2; The method also includes filling the trench TR3 with a dielectric, wherein the width W3 is sufficient to carry the latching voltage.

Only a mask is required for steps a) through j) in the method described above.

In the above method, step b) further comprises preparing a heavily doped channel termination region under trench TR2.

The present invention also provides a semiconductor device comprising: a plurality of gate electrodes over a gate insulating layer, formed in an active trench, in an active region of a semiconductor substrate; formed in a semiconductor substrate a first gate runner and electrically connected to the gate electrode, wherein the first gate runner abuts and surrounds the active region; and the second gate runner is connected to the first gate runner for Connecting the gate metal; and wherein the thickness T2 of each of the insulating layers in the gate runner trenches is greater than the thickness T1 of the gate insulating layer in the active trenches, wherein the thickness T2 is sufficient to carry the latching voltage.

The above-mentioned device further includes: a cut-off structure surrounding the first gate runner and the second gate runner and the active region, wherein the cut-off structure includes conductive in the trench covered with the insulator in the semiconductor substrate Material in which the cutoff structure is shorted to the vicinity of the edge of the wafer The source or body layer of the semiconductor substrate, thereby constituting the channel end point of the element.

The above described components further include: a dielectric filled trench that surrounds the first gate runner and the second gate runner and the active region.

The above described components also include a heavily doped channel termination region under the dielectric filled trench.

The semiconductor substrate of the above-described elements includes an active region and a body layer in the cut-off region.

The semiconductor substrate in the above described device contains a source region.

The source regions in the above described components are only located in the active region.

The first gate runner of the above described components includes a channel termination region formed below the trench.

The semiconductor substrate of the above described device further comprises a semiconductor substrate having a heavily doped underlayer and a sub-doped top layer, wherein the first gate runner trench is sufficiently deep to reach the heavily doped underlayer.

The insulator in the trench filled with insulation described in the cut-off structure is sufficiently thick to carry the latching voltage.

100, 200, 300, 700‧‧‧ trench MOSFET

102‧‧‧Active unit cell

104, 204, 206, 304, 306, 527‧‧‧ gate slides

106‧‧‧N+ channel end point

108‧‧‧End

111, 211, 311, 404, 504, 704‧‧ ‧ epitaxial layer

112, 213, 313, 413, 713‧‧‧ wafer edge

202, 302, 410, 412, 414, 416, 510, 512, 514, 516, 710, 712, 714, 716 ‧ ‧ trench

204a, 208a, 308a‧‧‧ parasitic crystal

207, 307, 707, 742, 744‧‧ joints

208, 308, 529‧‧‧ cut-off structure

210, 310, 711‧‧‧ active cell area

212, 312, 432, 528‧‧‧ body layer

214, 314, 434, 530, 736‧‧‧ source layer

248, 348, 456, 550, 754‧‧‧ gate metal layer

250, 350 ‧ ‧ gap

252, 352, 454, 552, 752‧‧‧ source metal

254, 354, 458, 548 ‧ ‧ cut-off metal

304a‧‧‧Parasitic p-channel transistor

402, 502, 702‧‧ ‧ substrate

406, 436, 522, 532‧‧ insulation

408, 508‧‧‧ first mask

418, 518‧‧‧ gate insulation

420, 520‧‧‧ sacrificial materials

422‧‧‧nitriding layer

424‧‧‧second mask

426‧‧‧ Sacrificial insulation

428, 523, 524‧‧‧ Grid insulators

430, 526‧‧‧ conductive materials

438, 534, 740 ‧ ‧ contact mask

442, 444, 445, 446, 536, 538, 540, 541, 542‧ ‧ contact holes

448‧‧‧ barrier metal

543‧‧‧ barrier material layer

450, 544, 748‧‧‧ plug

452, 546, 750‧‧‧ metal layers

506, 706, 722‧‧ ‧ oxide layer

525‧‧‧Active gate electrode

531‧‧‧Top oxide layer

595, 730 ‧ ‧ channel termination area

708‧‧‧ Trench mask

720, 728‧‧‧ polycrystalline layer

724‧‧‧Gate oxide

726‧‧‧Active Gate Oxide

732‧‧‧Oxide

734‧‧‧ body area

738‧‧‧ dielectric layer

746‧‧‧ barrier metal

Figure 1 shows a cross-sectional view of a conventional trench MOSFET device.

Fig. 2A is a plan view showing the layout of the double gate oxide trench MSOFET according to the first embodiment of the present invention.

Fig. 2B-1 shows another top view of the layout of the double gate oxide trench MOSFET 200 shown in Fig. 2A.

Figure 2B-2 shows the double-gate oxide trench MOSFET shown in Figure 2A along line A-A and Cross-sectional view of B-B.

Fig. 2C is an equivalent circuit diagram showing the double gate oxide trench MOSFET shown in Figs. 2B-1 and 2B-2.

Fig. 3A is a plan view showing the layout of a double gate oxide trench MSOFET according to a second embodiment of the present invention.

Figure 3B shows a cross-sectional view of the double gate oxide trench MOSFET shown in Figure 3A along lines A-A and B-B.

Fig. 3C is a circuit diagram showing the double gate oxide trench MOSFET shown in Fig. 3B.

4A-4R is a cross-sectional view showing a step of preparing the double gate oxide trench MOSFET shown in Fig. 2A-2B of the first embodiment of the present invention.

5A-5Q are cross-sectional views showing the steps of preparing the double gate oxide trench MOSFET shown in Fig. 3A-3B of the second embodiment of the present invention.

Figure 6 is a cross-sectional view showing the steps of preparing a dual gate oxide trench MOSFET according to an alternative embodiment of the present invention.

Figure 7A shows a top view of a dual gate oxide trench MOSFET layout in accordance with an alternate embodiment of the present invention.

Fig. 7B is a cross-sectional view showing the double gate oxide trench MOSFET shown in Fig. 7A along lines A-A and B-B.

Figures 8A-8R are cross-sectional views showing the steps of preparing the dual gate oxide trench MOSFET shown in Figures 7A-7B.

While the following detailed description contains numerous specific details Therefore, an exemplary embodiment of the present invention is proposed for a request The invention of protection does not have any general loss and is not subject to any restrictions.

<Example>

In an embodiment of the present invention, the existing junction cut-off in a conventional trench MOSFET can be replaced by a thick gate oxide in the gate runner region to terminate the active cell region, thereby eliminating junction breakdown breakdown. Improve UIS (non-embedded sensor switch) performance, and because the space required for oxide is much smaller than the space required for traditional junction cutoff, it also saves space for junction cutoff. In addition, the reverse recovery characteristic can be improved by confining the embedded body diode to the active region.

Fig. 2A is a plan view showing the layout of the double gate oxide trench MSOFET 200 of the first embodiment of the present invention. Figure 2B-2 shows a cross-sectional view of trench MOSFET 200 with double gate turn-off along lines A-A and B-B. As described in detail in Figures 4A-4R, the method for fabricating the oxide-off trench MOSFET 200 requires only four masks: a trench mask, a gate oxide mask, a contact mask, and A metal mask.

As shown in FIGS. 2A and 2B-2, trench MOSFET 200 includes a gate electrode formed in trench 202 filled with oxide, trench 202 being located in active cell region 210. The gate runners are formed in a wider set of trenches filled with oxide. The gate runner includes a first portion 204 that contacts and surrounds the active cell region 210. The gate runner contains a second portion 206 connected by a joint 207 to a gate metal layer 248 (having a contour as indicated by the dashed line in Figure 2A). The cutoff structure 208 is formed in another trench filled with oxide that surrounds the gate runners 204, 206 and the active region 210. The cutoff structure 208 can be shorted to the body or source region of the component 200 by a cutoff metal 254 and a suitable joint at a particular location. The gate metal 248 and the source metal 252 are electrically insulated from each other by the slit 250, and the slit 250 may be filled with an insulating material. Short cut The stop structure 208 serves as the end point of the channel. As an example, in the embodiment shown in FIG. 2B-2, the n-type (in the case of an n-channel MOSFT device as an example) source layer 214 may be formed only in the p-body layer 212 in the active cell region. On the top. The gate oxide of the active region gate trench 202 is much thinner than the gate oxide of the gate runner 204. The thickness of the gate runner 204 and the thick gate oxide of the turn-off trench 208 (eg, about 1000 Å to 2,000 Å) is sufficient to withstand the breakdown voltage; the required thickness depends on the component rating. Voltage. The gate oxides of the gate runners 204, 206 and the gate oxide in the turn-off trench 208 are thicker than the gate oxide in the active gate trench 202, so it can be said that the component 200 has a double gate oxide thickness. . Gate runners 206 and 204, as well as gate electrodes in active region gate trenches 202, are connected together to the element gate potential. The gate electrode in the cutoff trench 208 can be connected to the body region by the wafer edge 213, which is at the element drain potential.

Fig. 2B-1 shows another top view of the double gate oxide trench MOSFET 200 shown in Fig. 2A. However, for convenience of explanation, Fig. 2B-1 shows only the metal layer. The source metal 252 covers the active region 210 and the enclosed gate runner 204. The gate metal 248 covers the gate pick-up portion 206 of the gate runner, and the cut-off metal 254 connects the portion of the cut-off trench 208 that surrounds the component. In the layout shown in FIGS. 2A and 2B-1, the cut-off metal 254 is connected to the cut-off trench 208 at the corner of the wafer.

Fig. 2C is an equivalent circuit diagram showing the double gate oxide off-channel MOSFET shown in Fig. 2B-2. These structures are formed in a semiconductor substrate having an n- epitaxial layer 211 over the bottom n+ substrate layer 214. As shown in the circuit diagram of the figure, a parasitic p-channel (taking an n-channel element as an example) transistor 204a may be formed under the gate runner 204 from the active region 210 (located at the source potential of the component). Layer 212 begins as a parasitic drain of parasitic transistor 204a on the other side of gate runner 204 The p-body region, as the parasitic source of the parasitic transistor 204a, surrounds the portion of the n- epitaxial layer 211 of the gate runner 204 as the parasitic channel region of the parasitic transistor 204. It is noted that if component 200 is an n-channel MOSFET and the parasitic transistor is a p-channel transistor, then the component drain potential is the source potential of the parasitic transistor and vice versa. The parasitic drain of the parasitic transistor 204a is at the source potential of the element, so that the parasitic gate (the gate electrode in the gate runner 204) is shorted to the drain electrode of the element, and the parasitic transistor 204a can be turned on. When the MOSFET element 200 is turned off, all of the gate runners 204 lead to the source potential of the component, and the parasitic transistor 204a can be turned on. This causes the source potential of the element, from the active region 210, to be shorted to the drain potential at the edge 213 of the wafer, thereby generating a leakage current.

To overcome this problem, a cut-off trench 208 can be formed between the periphery of the component, between the wafer edge 213 and the gate runner 204. And below the cutoff trench 208, a p-channel parasitic transistor 208a is formed. However, the gate electrode in the cut-off trench 208 is shorted to the parasitic source terminal (the wafer edge 213 end) of the parasitic transistor 208a by the turn-off metal 254, so the parasitic transistor 208a is never turned on, so as to serve as a channel. End point, avoiding shorting from the source of the component to the edge 213 of the wafer. It is noted that since the contact trench 206 is not around the active region 210, the parasitic transistor shown is not used for the gate runner contact trench 206. If necessary, an additional channel end point can be added between the first cutoff structure 208 and the gate runner 204, which is actually between the first normally closed parasitic transistor 208a and the parasitic transistor 204a. Another normally closed parasitic transistor is added; this increases the voltage performance at the end of the channel.

Channel end points can also be prepared by other methods, such as those described in commonly assigned U.S. Patent Application Serial No. 12/731,112, the disclosure of which is hereby incorporated by reference. For example, heavy doping can be achieved by preparing a sufficiently deep gate runner trench 204 The bottom substrate 214 is formed to form a channel end point. Alternatively, a heavily doped n-region can be formed at the bottom of the gate runner trench 204 to form a channel end point. If an optional channel end point is formed, then the cutoff structure 208 can be omitted. The gate runner trench 204 surrounds the active region and has a sufficiently thick gate oxide to carry the latching voltage.

The blocking voltage is the voltage between the two main current carrying ends of the component, such as the source-to-drain voltage. Thicker gate oxides (such as gate runner trenches or oxides of the turn-off trenches) should be sufficient to carry the latch-up voltage when the component is in the off state. In other words, the oxide is thick enough that the blocking voltage is not large and an electric field beyond the oxide breakdown field cannot be generated on the oxide. Ideally, the breakdown voltage of the cut-off region is higher than the breakdown voltage of the active region, thereby improving the durability of the component.

3A is a plan view showing the layout of the double gate oxide trench MOSFET 300 according to the second embodiment of the present invention, and FIG. 3B is a cross-sectional view showing the double gate turn-off trench MOSFET 300 along lines A-A and B-B. The dual gate oxide trench MOSFET 300 is similar to the dual gate oxide trench MOSFET 200 shown in FIGS. 2A-2B. As shown in FIGS. 3A-3B, trench MOSFET 300 includes an active gate electrode formed in active gate trench 302, which is located in active cell region 310. The active gate electrode is electrically coupled to gate runners 304 and 306, which are formed in a wider trench that is filled with thicker oxide. The gate runner includes a portion 304 that reaches and surrounds the active cell region 310, and a portion 306 that is connected to the gate metal 348 by a junction 307. A cutoff structure 308 surrounds the gates 304, 306 and the active region 310. The cutoff structure 308 is electrically connected to the source layer 314 and the body layer 312 near the wafer edge 313 by a turn-off metal 354 and a suitable joint. The gate metal 348 and the source metal 352 are electrically insulated from each other, for example by the slit 350, and the slit 350 may be filled with an insulating material. Source The metal covers the active region 310 and the surrounding gate runners 304. As noted above, the shorted cutoff structure 308 serves as the end of the channel. In the present embodiment, the n-type source layer 314 may be formed on the top of the active cell region 310 and the p-body layer 312 in the cut-off region, and the source and the body are both formed in the n-type drift/epitaxial layer 311. Above. As shown in Figures 5A-5Q, a dual gate oxide trench MSOFET 300 can be fabricated using a three mask technique.

Fig. 3C is an equivalent circuit diagram showing the double gate oxide off-channel MOSFET shown in Fig. 3B. As shown in the circuit diagram, the parasitic p-channel transistor 304a is formed under the gate runner trench 304, but after the cutoff trench 308 is widened, serves as the end of the channel. The parasitic transistor 308a is located below the turn-off trench 308, with the parasitic source being shorted to the parasitic gate by the turn-off metal 354, thereby avoiding switching on as described above.

4A-4R is a cross-sectional view showing a four mask preparation method of the double gate oxide trench MOSFET of the type shown in the above 2A, 2B-1, and 2B-2. As shown in FIG. 4A, the initial material for preparing the semiconductor substrate includes, for example, a relatively lightly doped (eg, n-) epitaxial layer 404 over the heavily doped (eg, n+) substrate 402. Alternatively, the epitaxial layer is doped with p- and the substrate is doped with p+. An initial insulating layer 406 may be formed on the top surface of the epitaxial layer 404. By way of example and not limitation, insulating layer 406 may be prepared with an oxide, such as by thermal oxidation combined with deposition of a low temperature oxide or high density plasma (HDP). As shown in FIG. 4B, above the insulating layer 406, a first mask 408 (herein referred to as a trench mask) is used and a pattern with openings is formed, the openings corresponding to the trenches to be prepared. After etching, trenches 410, 412, 414, and 416 are formed through insulating layer 406, layer 404, and the top of epitaxial layer 404. The first and second gate runners can be fabricated in subsequent techniques using trenches 410 and 412. For simplicity, the trenches 410, 412 are referred to herein as first and second gate runner trenches. A portion of the active region is turned off using another trench 414. For simplicity, the trench 414 is referred to herein as a truncation Stop the groove. The active element cells are fabricated using trenches 416. For simplicity, these trenches 416 are referred to herein as active trenches. If the widths of the trenches are different, the trenches can be etched to different depths in a common etching step. For example, the gate runner trenches 410, 412 and the turn-off trench 414 can be wider than the active trench 416 to etch the gate runner trenches 410, 412 and the turn-off trench 414 using the same etch technique. The active trench 416 is deeper. All trenches can be etched using a single mask.

As shown in FIG. 4C, the first mask 408 is removed. A thick gate insulating layer 418 (e.g., an oxide) is deposited, or otherwise formed on the bottom and sidewalls of trenches 410, 412, 414, and 416, and over epitaxial layer 404. The thick gate oxide layer 418 has a thickness between about 800 Å and 1500 Å. As shown in FIG. 4D, sacrificial material 420 is deposited in trenches 410, 412, 414, and 416 and on top of epitaxial layer 404. By way of example and not limitation, the sacrificial material can be a conductive or semiconductive material such as a polysilicon. As shown in FIG. 4E, below the top surface of the gate insulating layer 418, and above the top surface of the epitaxial layer 404, the sacrificial material 420 can be etched back using the etch end. The trenches 410, 412, 414, and 416 can still be filled with the sacrificial material 420.

As shown in FIG. 4F, a thin oxygen diffusion barrier layer 422 (eg, nitride) is deposited over the sacrificial material 420 in trenches 410, 412, 414, and 416, and over gate insulating layer 418. As an example, the thin nitride layer 422 has a thickness of about 200 Å to 500 Å.

Above the thin nitride layer 422, a second mask 424 (ie, a gate oxide mask) is used. As shown in FIG. 4G, the gate oxide mask 424 covers only the trenches 410, 412, 414 located in the gate runner region and the turn-off region, but does not cover the active trench 416. The sacrificial material 420 ensures that the photoresist material does not deposit within the trenches and will be difficult to remove once deposited. The portion of the thin nitride layer 422 that is not covered by the second mask 424 is etched away. The sacrificial material 420 in the trench 416 is then etched. Above trench 416 and over epitaxial layer 404, thick gate insulating layer 418, which is not covered by second mask 424, is also etched away.

The second mask 424 is removed, and then a thin sacrificial insulator 426 is prepared (e.g., grown) as shown in FIG. 4H above the sidewalls and bottom of the active trench 416 and over the n- epitaxial layer 404. A material is not formed (e.g., grown) on the material of the thin nitride layer 422, and the sacrificial insulator is preferably made of such a material. As an example, the thin nitride layer 422 may be made of a nitride material such as tantalum nitride, and the thin sacrificial insulating layer 426 may be made of a grown oxide material such as hafnium oxide. The sacrificial insulator 426 has a thickness of about 200 Å to 500 Å.

As shown in Fig. 4I, the remaining portion of the thin nitride layer 422 is stripped. The sacrificial material 420 in the trenches 410, 412, 414 is then etched away. The thin oxygen diffusion barrier layer 422 can be made of a material that resists etching the sacrificial insulating layer 426. In addition, the thin oxygen diffusion barrier layer 422 can also be made of a material that can be etched using a technique that is resistant to the sacrificial insulating layer 426.

The sacrificial insulating layer 426 is thinner than the thick gate insulating layer 418. As shown in FIG. 4J, the sacrificial insulating layer 426 can be removed from the active trench 416 while leaving the thick gate insulating layer 418 intact. A thin gate insulator 428 is then formed in the bottom and sidewalls of the active trench 416. The thin gate insulator 428 has a thickness of about 150 Å to 500 Å.

As shown in FIG. 4K, a conductive material 430 (eg, polysilicon) is deposited in all of the trenches 410, 412, 414, and 416, and may also be over the thick gate insulator 418 and a thin gate over the epitaxial layer 404. The top of the pole insulator 428 overflows. Then, as shown in FIG. 4L, the conductive material 430 can be etched back by the end point below the top surface of the epitaxial layer 404.

As shown in FIG. 4M, a body layer 432 is formed on top of the epitaxial layer 404. For example, the body layer 432 can be prepared by a full vertical or angled implant and diffusion of dopants having a conductivity type opposite to the epitaxial layer 404 and the substrate 402. For example, if substrate 402 and epitaxial layer 404 are n-type doped, then body layer 432 can be fabricated by implanting a p-type dopant, and vice versa. Bulk implants can also be performed at very high energies (e.g., 80-120 KeV), and thick gate insulators 418 do not interfere with bulk implantation.

As shown in FIG. 4N, a source layer 434 is formed on top of the body layer 432 using a low energy implantation technique. If the source implant is performed at extremely low energy (e.g., around 20 KeV) and the thick gate insulator is relatively thick (e.g., the thickness of the oxide is about 1200 Å), then the thick gate insulator 418 hinders the implant. The thin gate oxide 428 is relatively thin so that ions can penetrate, so that the dopant is implanted only into the active cell region. Source layer 434 is prepared, for example, by vertical or angled implantation and annealing. Source layer 434 is typically prepared by implanting a dopant that is opposite in conductivity to the bulk dopant. No additional mask is required for source and body implantation.

As shown in Fig. 4O, an insulating layer 436 is formed over the structure, which is then compacted and planarized. The planarization can be accomplished by chemical mechanical planarization (CMP). The above is merely an example, but not limited thereto, the insulating layer 436 may be a low temperature oxide and a boric acid containing barium glass (BPSG).

As shown in Fig. 4P, a contact mask 438 is formed on the insulating layer 436, and an opening pattern having a defined contact hole is formed. Contact mask 438 is the third mask used in the art. The insulating layer 436, the source layer 434, and a portion of the body layer 432 in the active cell region may be etched by openings in the mask 438 to form source/body contact holes 442. The insulating layer 436 and a portion of the conductive material 430 in the trenches 412, 414 are all downward Etching to form the gate contact hole 444 and the cut-off contact hole 445. The insulating layer 436 located at the edge of the cutoff region and adjacent the trench 410 and the top of the body layer 432 may be etched down to form an off short contact hole 446.

As shown in FIG. 4Q, a barrier material (e.g., Ti/TiN) layer 448 can be deposited in contact holes 442, 444, 445, and 446. Contact holes 442, 444, 445, and 446 are then filled with a conductive (e.g., tungsten (W)) plug 450. Barrier metal 448 and tungsten plug 450 in contact hole 442 serve as source/body connections in the active region. The barrier metal 448 and the tungsten plug 450 in the contact hole 444 act as a gate contact over the gate contact trench 412. The barrier metal 448 and the tungsten plug 450 in the contact holes 445, 446 form a joint in the cut-off region, shorting the cut-off trench electrode to the body region near the edge of the wafer. A metal layer 452 (preferably Al-Si) can then be deposited over the structure.

A patterned metal mask (not shown) is deposited on the metal layer 452, and then the metal layer 452 is divided into electrically insulating portions by metal etching to form a gate, a cutoff, and a source metal, such as a gate metal. 456. The connection metal 458 and the source metal 454 are cut off to form the element 400, which is similar to the semiconductor element 300 shown in FIGS. 2A, 2B-1, and 2B-2. Metal masks are the fourth mask in this technology. The barrier metal 448 and tungsten plug 450 in the contact hole 442 serve as a source/body junction over the source region, starting from the source layer 434 and the body layer 432, up to the source metal 454. Barrier metal 448 and tungsten plug 450 in contact hole 444 act as a vertical gate runner joint above the gate runner region, starting from the gate runner to gate metal 456. The barrier metal 448 and tungsten plug 450 in the contact holes 445, 446, and the turn-off metal 458, short the gate of the turn-off trench 414 to the body region 432 between the wafer edge 413 and the turn-off trench 414.

5A-5Q are cross-sectional views showing a three mask method for preparing a double gate oxide trench MOSFET of the type shown in the above 3A-3B. The method used to fabricate the dual gate oxide trench MOSFET 300 requires only three masks: a trench mask, a contact mask, and a metal mask. In this method, the gate oxide mask shown in Fig. 4A-4R can be omitted.

As shown in FIG. 5A, the semiconductor substrate includes, for example, a relatively lightly doped (e.g., n-) epitaxial layer 504 over a heavily doped (e.g., n+) substrate 502. An oxide layer 506 is formed on the top surface of the n- epitaxial layer 504. As an example, an oxide can be prepared by thermal oxidation and deposition of a low temperature oxide or high density plasma (HDP). As shown in FIG. 5B, above the oxide layer 506, a first mask 508 (i.e., a trench mask) having an opening pattern defining a trench is used. Trench 510, 512, 514, and 516 are prepared by etching through oxide layer 506, epitaxial layer 504, and the top of n+ substrate 502. The first and second gate runners can be fabricated in subsequent techniques using trenches 510 and 512. For simplicity, trenches 510 and 512 are referred to herein as first and second gate runner trenches. A cut-off trench can be prepared using another trench 514. For simplicity, trench 514 is referred to herein as a cut-off trench. The active element cells can be fabricated using trenches 516. For simplicity, trench 516 is referred to herein as an active trench. The gate runner trenches 510, 512 and the off trench 514 may be wider than the active trench 516, so even if they are both etched in the same etch technique, the gate runner trenches 510, 512 and the cutoff trench 514 can also be etched wider than active trench 516.

As shown in FIG. 5C, the first mask 508 is removed. A gate insulating layer 518 (e.g., an oxide) is formed over the bottom and sidewalls of trenches 510, 512, 514, and 516, and over epitaxial layer 504. The gate insulating layer 518 has a thickness of about 500 Å to 1000 Å. As shown in FIG. 5D, a sacrificial material 520 (eg, polysilicon) is deposited to fill the active trenches 516. And deposited over the epitaxial layer 504. The gate runner trenches 510, 512 and the off trench 514 are relatively wide compared to the active trench 516, and the sacrificial material 520 only fills the bottom and sidewalls of the trenches 510, 512, 514 and is not filled. These grooves. The sacrificial material 520 is then anisotropically etched back by etching the active trench 516, under the top surface of the thick gate insulating layer 518, and at the end of the top surface of the epitaxial layer 504. As shown in FIG. 5E, the sacrificial material 520 can be completely removed from the gate runner trenches 510, 512 and the off trench 514. In this case, a channel end point can be formed at the bottom of the gate runner grooves 510, 512, for example by anisotropic implantation. The above is only an example, but not limited thereto. For n-channel MOSFET components, the channel end point can be n+ doped.

As shown in FIG. 5F, an insulating material is deposited over the bottom and sidewalls of trenches 510, 512, 514, and over gate insulator 518 to form a thicker insulating layer 522. In general, the type of insulating material can be the same as the type of material of the gate insulator 518. As an example, if the gate insulator 518 is an oxide, the insulating material can be formed using oxide deposition, such as high temperature oxide (HTO) deposition. Thus, a thicker gate insulating layer 522 is formed in trenches 510, 512, 514, while a thinner gate insulating layer 518 is formed in active trench 516. Then, planarization (e.g., CMP) is performed on the surface such that the top surface of the insulator 522 and the surface of the sacrificial material 520 in the trench 516 are level with each other, thereby exposing the sacrificial material 520 as shown in Fig. 5G. Then, as shown in FIG. 5H, the sacrificial material 520 is etched away from the trench 516. At this time, the thickness of the oxide layer in the sidewalls and the bottom of the trench 516 (for example, about 500 Å to 1000 Å) is smaller than the thickness of the oxide layer (for example, about 1500 Å to 2000 Å) in the sidewalls and the bottom of the trenches 510, 512, and 514.

Then, by isotropic etching, the insulators 518 and 522 are thinned so as to be in the active trench An active gate insulator 524 is formed in the trench 516, and a thicker gate insulator 523 is formed in the gate runner trenches 510, 512 and the turnoff trench 514. Preferably, a short etch is used to completely remove the insulating layer 518 from the active trench 516 while leaving the thicker insulating layer 522 of the trenches 510, 512, 514 most intact; then, in the active trench 516, A thin active gate insulating layer 524 is formed (eg, grown) while leaving a thicker gate insulator 523 in the trenches 510, 512, 514. Therefore, the component can be said to have a thickness of a double gate insulator. The active gate insulator 524 has a thickness between about 150 Å and 800 Å, while the thicker gate insulator 523 has a thickness between about 500 Å and 1200 Å.

Conductive or semiconducting material 526 (e.g., polysilicon) may be deposited or otherwise formed, as shown in Figure 5J, filling trenches 510, 512, 514, and 516 on the top surface. If necessary, the conductive material 526 can be doped to make it more conductive. Then, the conductive material 526 is etched back by the etching end point below the top surface of the epitaxial layer 504, as shown in FIG. 5K to form the active gate electrode 525, the gate runner 527, and the cutoff structure 529.

As shown in FIG. 5L, a body layer 528 can be formed on top of the epitaxial layer 504. The body layer 528 can be formed, for example, by vertical or angular full implantation and diffusion of suitable dopants, such as shown in Figure 4M above. As shown in FIG. 5M, at the top of the body layer 528, a source layer 530 is formed. The source layer 530 can be formed, for example, by implanting a suitable dopant in a vertical or angled manner and annealing, for example, as described above with reference to FIG. 4N.

As shown in Fig. 5N, an insulating layer 532 (e.g., a low temperature oxide or a boric acid containing barium glass (BPSG)) may be formed over the structure, followed by compaction and CMP planarization.

As shown in Fig. 5O, a contact mask 534 is formed on the insulating layer 532, and a pattern having openings defining the contact holes is formed. It is noted that at this point, contact mask 534 is only the second mask used in the art. The insulating layer 532, the source layer 530, and the portion of the body layer 528 in the active cell region may be etched by openings in the mask to form source contact holes 536. The insulating layer 532 and the portion of the material 526 of the trenches 512, 514 may be etched down to form the gate runner contact hole 540 and the cutoff contact hole 541. The insulating layer 532, the source layer 530, and the portion of the body layer 528 located near the edge of the cutoff region and the trench 514 are etched down to form the turn-off shorting contact hole 542.

As shown in FIG. 5P, a barrier material (e.g., Ti/TiN) layer 543 can be deposited in contact holes 536, 540, 541, and 542 and over oxide 532. Contact holes 536, 540, 541, and 542 are then filled with a conductive (e.g., tungsten (W)) plug 544. The barrier material 543 and tungsten plug 544 in the contact hole 536 act as a source/body junction in the active cell region above the source region 530. The barrier material 543 and the tungsten plug 544 in the contact hole 540 serve as gate contacts over the gate region or the turn-off region. The barrier material 543 and the tungsten plug 544 in the contact holes 541, 542 serve as a joint for short-circuiting the end of the cut-off/channel. As shown in Fig. 5P, a metal layer 546 is deposited over the resulting structure, preferably Al-Si.

A patterned metal mask (not shown) is deposited on the metal layer 546, and then the metal layer 546 is divided into electrically insulating portions by metal etching to form an electrically insulating metal region including the gate metal region 550 and the source metal. The region 552 and the cut-off metal region 548 of the semiconductor device 300 shown in FIGS. 3A-3B complete the fabrication of the device. The metal mask used in this technique is the third mask. The barrier material 543 and the tungsten plug 544 in the contact holes 536, 538 serve as a source/body joint above the source region, from the source layer 534 and body layer 532 begin up to source metal 552. The barrier material 543 and the tungsten plug 544 in the contact hole 540 serve as vertical rail joints above the gate runner region, starting from the first and second gate contacts, up to the gate metal 550. The barrier material 543 and the tungsten plug 544 in the contact holes 541, 542 serve as a joint to the cut-off metal 548 over the cut-off/channel region. In this method, the gate oxide mask is omitted.

In an alternative version of the method, after the technique illustrated in FIG. 5F, a channel termination region may be formed below the bottom of the gate runner trenches 510, 512 and below the trench 514. As shown in Fig. 6, full channel implantation is performed to form a heavily doped channel termination region 595 (having the same conductivity type as the final source region) under the trenches 510, 512, 514. As an example, the energy of the channel termination implant is sufficient to pass through the trench oxide 522 in the trenches 510, 512, 514, but not enough to pass through the thicker layer 5A-5B containing the initial trench hard mask 506. The top oxide layer 531. The top oxide layer 531 and the polysilicon 520 in the active trench 516 can serve as a hard mask such that the channel termination region 595 is formed only below the bottom of the gate runner trenches 510, 512 and below the trench 514. Optionally, the trenches 510, 512, 514 can be made deep enough to reach the substrate as the end of the channel. If the end of the channel is formed at the trenches 510, 512, the cutoff trench 514 is not necessary as long as the thickness of the oxide 522 in the gate runner trenches 510, 512 is sufficient to carry the latching voltage.

7A-7B shows an alternative structure for combining the dual gate oxide described herein with the oxide cut-off trench described in U.S. Patent Application Serial No. 12/731,112, the disclosure of which is incorporated herein by reference. The oxide cut-off trench is for reference. Fig. 7A is a plan view showing the layout of a double gate oxide trench MOSFET device 700 according to an embodiment of the present invention, and Fig. 7B is a cross-sectional view showing the oxide cutoff trench of the double gate oxide MOSFET 700 along lines A-A and B-B. Used to prepare oxide cut-off trenches The MOSFET 700 method requires only three masks: a trench mask, a contact mask, and a metal mask, which will be described in detail in Figures 8A-8R.

As shown in FIGS. 7A-7B, the trench MOSFET 700 includes a gate electrode formed in an oxide-filled trench 716 located in the active cell region 711. The gate runners are formed in a wider set of trenches filled with oxide. The gate runner includes a first portion 710 that is adjacent to and surrounds the active cell region 711. The gate runner includes a second portion 712 that is connected by a joint 707 to a gate metal layer 754 (having an outline as shown by the dashed line in Figure 7A). The oxide cutoff trench 714 is a trench filled with oxide that surrounds the gate runners 710, 712 and the active region 711. The oxide cutoff trench 714 has a heavily doped (n+) channel termination region 730 below the oxide cutoff trench 714. As an example, in the embodiment illustrated in FIG. 7B, the n-type (in the case of an n-channel MOSFET device as an example) source layer 736 may only be formed on top of the p-body layer 734 in the active cell region. A source metal layer 752 is connected to the source/body regions in the active region 711. The gate oxide of active cell gate trench 716 is much thinner than the gate oxide of gate runners 710, 712. The thick gate oxide of the gate runners 710, 712 is very thick (e.g., about 1000 Å to 2000 Å) sufficient to carry the latch-up voltage. Additionally, the oxide cut-off trench 714 is wide and filled with a dielectric material sufficient to carry a high breakdown field equivalent to the latch-up voltage. Element 700 is formed on a semiconductor substrate containing an n- epitaxial layer 704 formed over heavily doped underlying substrate 702.

Figures 8A-8R show a method in which only three masks are needed to prepare the element 700 shown in Figures 7A-7B. In Figure 8A, the initial semiconductor substrate (e.g., having an n- epitaxial layer 704 overlying the bottom substrate 702) has an oxide layer 706 formed thereon. In FIG. 8B, trench mask 708 is the first mask in the art, and trenches are etched into epitaxial layer 704 by openings in trench mask 708. The groove contains The source trench 716, the gate runner trench 710 adjacent to and surrounding the active trench 716, the gate runner trench 712, and the turnoff trench 714. Gate runner trenches 710 and 712 are wider than active trenches 716, which are wider than gate runner trenches 710, 712. In FIG. 8C, trench mask 708 is removed, and sacrificial oxide 718 is formed on the bottom and sidewalls of trenches 710, 712, 714, 716. In Fig. 8D, a temporary polysilicon layer 720 is formed over the element. The thickness of the polysilicon layer 720 is sufficient to completely fill the narrower active 716, but only to fill the sidewalls and bottom of the wider trenches 710, 712, 714. The polysilicon 720 of the trenches 710, 712, 714 is removed by an (isotropic) etch, but the polysilicon 720 in the active trench 716 is retained, as shown in FIG. 8E. In Fig. 8F, an oxide layer 722 is formed on the element. This thickens the oxide layer in trenches 710, 712, 714 and overlies polysilicon 720 in active trench 716. The top oxide 722 is planarized (e.g., by CMP) to expose the top of the polysilicon 720, but retains the oxide 722 in the trenches 710, 712, 714 as shown in Figure 8G. In the 8H picture, the temporary polysilicon 720 is removed. In FIG. 8I, the oxide in active trench 716 is etched away and an active gate oxide is formed. The sacrificial oxide can be grown and removed prior to forming the active gate oxide 726. Since the oxides in the trenches 710, 712, 714 are thicker than the oxides in the active trenches 716, they are not completely etched away during the etching of the oxide, and finally formed in the trenches 710, 712, 714. Thick gate oxide 724 is thicker than active gate oxide 726 in active trench 716. In FIG. 8J, a polysilicon layer 728 is deposited over the device. The polysilicon layer 728, while filling the trenches 710, 712, 716, is only lined in a wide oxide cut-off trench 714. In FIG. 8K, polycrystalline germanium material 728 is isotropically etched back in trenches 710, 712, 716, but is no longer present in a wide oxide cut-off trench 714. At this point, a heavily doped (n+) channel termination can be formed at the bottom of a wide oxide cut-off trench 714, for example by anisotropic implantation. Area 730. The polysilicon layer 728 in trenches 710, 712, 716 blocks implantation to the bottom of these trenches. An oxide 732 is deposited over the component to fill the remaining oxide cutoff trenches 714 and cover the polysilicon layer 728. Then, as shown in FIG. 8L, the oxide 732 is planarized to the surface of the epitaxial layer 704.

In Figure 8M, a (p-type) body region 734 is prepared over the entire wafer. In the 8N figure, above the body region 734, an (n-type) source region 736 is prepared. The body and source regions can be formed without a mask as a full implant. In FIG. 8O, a very thick dielectric layer 738 can be formed over the component, such as by LTO and BPSG deposition, and in FIG. 8P, a contact mask 740 is used. Contact mask 740 is only the second mask in the art. In the BPSG 738, the source region 736, and the body region 734, the active cell source/body connector 742 is etched. In the bare body region 734, a (P+) body contact implant (not shown) can be performed. Gate junction 744 is etched in BPSG 738 and in the polysilicon in gate runner trench 712. In the 8Q diagram, the contact mask 740 is removed and a conductive (e.g., tungsten) plug 748 is formed in the joints 742, 744. A barrier metal 746 may be prepared prior to forming the tungsten plug 748. Above the element, a metal layer 750 (e.g., aluminum) is prepared. In the 8R picture, the metal layer 750 is etched in the source metal 752 and the gate metal 754 by using a metal mask (not shown), thereby completing the double gate oxide MOSFET using only three masks. Element 700. Although not illustrated, a drain metal can be formed on the back side of the element without using a mask.

Although the invention has been described in detail with respect to certain preferred versions, other versions are possible. For example, a suitable alternative insulator may be used as an oxide. Meanwhile, according to the above description, an example of an n-channel element is used as a typical; however, embodiments of the present invention can also be applied to a p-channel element by reversing the appropriate Conductive type. Therefore, the scope of the invention should not be determined by the description of the invention. Any option (whether preferred or not) can be combined with any other option (whether preferred or not). In the context of the patent application, the indefinite article "a" or "an" The scope of the appended claims should not be construed as limiting the meaning and function unless the meaning of the function is clearly indicated by the meaning.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

200‧‧‧ trench MOSFET

202‧‧‧ trench

204‧‧‧Gate slide

206‧‧‧Gate slide

207‧‧‧Connector

208‧‧‧ cut-off structure

210‧‧‧Active area

213‧‧‧ wafer edge

248‧‧‧gate metal layer

250‧‧‧ gap

252‧‧‧ source metal

254‧‧‧cut-off metal

Claims (26)

A method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1 having widths W1, W2, and W3, respectively TR2, TR3, wherein W1 is narrower than W2, and W2 is narrower than W3, wherein the trench TR2 includes a first gate runner trench and a second gate runner trench connected to the trench TR1, wherein At least one of the first gate runner trench and the second gate runner trench abuts and surrounds the trench TR1, the trench TR3 including the trench TR1 and the trench TR2 a cut-off trench; c) preparing a gate insulator on the bottom and sidewalls of the trenches TR1, TR2, TR3 having a thickness T1, T2, T3, wherein T2 is greater than T1, T3 is greater than T1; d) A conductive material is prepared in the trench TR1 to form a gate electrode, and a conductive material is prepared in the trench TR2 to form a first gate runner and a second gate runner and a cutoff structure. The first and second gate runners are electrically connected to the gate electrode, and a conductive material is prepared in the trench TR3 to form the cutoff structure, wherein a cutoff structure electrically insulated from the gate runner and the gate electrode; e) preparing a body layer on top of the semiconductor substrate; f) preparing a source layer on top of the body layer; g) in the semiconductor An insulating layer is used over the substrate; h) a second mask is used over the insulating layer; i) using the second mask, an electrical contact is formed by a contact opening in the insulating layer, wherein the contact opening Included in the vicinity of each of the gate electrodes toward the source layer a source opening, a gate runner opening toward a gate runner, a cutoff contact opening toward the cutoff structure, and a shorting contact opening toward the source layer or the body layer near a wafer edge; a first metal region and a second metal region and a third metal region are electrically insulated from each other, wherein the first metal region is electrically connected to the gate runner, wherein the first The second metal region is electrically connected to a source terminal, wherein the third metal region is electrically connected to a cut-off joint and a short-circuit joint, so that the cut-off structure is short-circuited to a body region at the edge of the wafer; wherein the thickness T2 and T3 are thick enough to carry a blocking voltage. The method of claim 1, wherein the step e) further comprises: preparing the body layer over the top of the semiconductor substrate. The method of claim 1, wherein the step j) further comprises: depositing a metal layer over the insulating layer; using a metal mask over the metal layer; and etching the metal layer to separate the first a metal region and the second metal region. The method of claim 1, wherein the step c) further comprises: preparing a gate insulating layer by using a mask on the bottom and sidewalls of the trenches TR1 and TR2 having thicknesses T1 and T2, Where T2 is greater than T1. A method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1, TR2 having widths W1, W2, respectively, Wherein W1 is narrower than W2, wherein the trench TR2 includes a first gate runner trench and a second gate runner trench connected to the trench TR1, wherein the first gate runner trench And at least one of the second gate runner grooves abut and surround the trench TR1; c) preparing a first gate insulator on the bottom and sidewalls of the trenches TR1, TR2 having thicknesses T1, T2, wherein T2 is greater than T1; using a gate insulating over the first gate insulator a mask in which the gate insulator mask covers the trench TR2 but does not cover the trench TR1; from the portion of the semiconductor substrate that is not covered by the gate insulator mask, the first gate is removed a pole insulator, the portion not covered by the gate insulator mask includes the trench TR1; and a second gate insulator is prepared in the trench TR1, wherein the second gate insulator is The first gate insulator is thin; d) preparing a conductive material in the trench TR1 to form a gate electrode, and preparing a conductive material in the trench TR2 to form a first gate runner and a second a gate runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; e) preparing a body layer on top of the semiconductor substrate; f) in the body layer a top layer is prepared on the top; g) an insulating layer is used over the semiconductor substrate; h) is in the insulating layer a second mask is used above; i) using the second mask, an electrical contact is formed by a contact opening in the insulating layer, wherein the contact opening is included in the vicinity of each of the gate electrodes toward the source layer a source opening, a gate slide opening toward a gate runner, a cutoff contact opening toward the cutoff structure, and a shorting contact opening toward the source layer or the body layer near a wafer edge; And j) preparing a first metal region and a second metal region on the insulating layer and electrically insulated from each other, wherein the first metal region is electrically connected to the gate runner, wherein the second metal region and the second metal region The source connector is electrically connected, The thickness T2 is thick enough to carry a blocking voltage. The method of claim 5, wherein by implanting an ion at a relatively high energy, performing step e), at which energy the ion can pass through the second gate insulator and the A first gate insulator is implanted into the semiconductor substrate. The method of claim 6 wherein, by implanting the ions of a certain energy, performing step f), the energy enabling the ions to pass through the second gate insulator, but not passing through the first A gate insulator is implanted into the semiconductor substrate. The method of claim 7, wherein the source layer is formed only in the top of the body layer adjacent the trench TR1. The method of claim 5, wherein no more than four masks are used to complete steps a) through j). The method of claim 5, wherein the step b) further comprises preparing a heavily doped channel termination region under the trench TR2. The method of claim 5, wherein the step j) comprises: depositing a metal layer over the insulating layer; using a metal mask over the metal layer; and etching the metal layer to separate the first a metal region and the second metal region. A method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1, TR2 having widths W1, W2, respectively, Wherein W1 is narrower than W2, wherein the trench TR2 includes a first gate runner trench and a second gate runner trench connected to the trench TR1, wherein the first gate runner trench And abutting at least one of the second gate runner trenches and surrounding the trench TR1; c) at the bottom and sidewalls of the trenches TR1, TR2, preparing a first gate insulator; Preparing a sacrificial material to completely fill the trench TR1, but only lining the trench TR2; etching the sacrificial material to remove the sacrificial material on the trench TR2, but retaining the sacrifice in the trench TR1 a material; preparing a gate insulating layer in the trench TR2; and removing the sacrificial material in the trench TR1, the gate insulator being prepared in the trench TR1, wherein the gate in the trench TR2 The insulating layer thickness T2 is greater than the gate insulating layer thickness T1 in the trench TR1; d) preparing a conductive material in the trench TR1 to form a gate electrode, and preparing a conductive material in the trench TR2 to form a first gate runner and a second gate runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; e) at the top of the semiconductor substrate Preparing a body layer; f) preparing a source layer on top of the body layer; g) using an insulating layer over the semiconductor substrate; h) using a second mask over the insulating layer; i) utilizing the a second mask, wherein an electrical contact is formed by a contact opening in the insulating layer, wherein the connection The contact opening includes a source opening toward the source layer, a gate runner opening toward a gate runner, a cutoff contact opening toward the cutoff structure, and a wafer edge near the gate electrode. a short-circuit contact opening toward the source layer or the body layer; and j) preparing a first metal region and a second metal region on the insulating layer and electrically insulated from each other, wherein the first metal region and the The gate rail is electrically connected, wherein the second metal region is electrically connected to a source connector. The thickness T2 is thick enough to carry a blocking voltage. The method of claim 12, wherein the source layer is formed in the top of the entire semiconductor. The method of claim 12, wherein no more than three masks are used to complete steps a) through j). A method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1 having widths W1, W2, and W3, respectively TR2, TR3, wherein W1 is narrower than W2, and W2 is narrower than W3, wherein the trench TR2 includes a first gate runner trench and a second gate runner trench connected to the trench TR1, wherein At least one of the first gate runner trench and the second gate runner trench abuts and surrounds the trench TR1; the trench TR3 includes a trench TR1 and the trench TR2 a cut-off trench; the trench TR3 is filled with a dielectric, wherein a width W3 is sufficient to carry the latch voltage; c) a gate insulating is formed on the bottom and sidewalls of the trenches TR1, TR2 having thicknesses T1, T2, T3 a material in which T2 is greater than T1; d) preparing a conductive material in the trench TR1 to form a gate electrode, and preparing a conductive material in the trench TR2 to form a first gate runner and a second gate a pole runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; e) at the semiconductor Preparation of a bulk layer on top of the substrate; F) preparing a source layer on top of the bulk layer; G) using an insulating layer over the semiconductor substrate; H) using a second mask over the insulating layer; i) using the second mask, forming an electrical contact by a contact opening in the insulating layer, wherein the contact opening comprises a source opening toward the source layer adjacent to each of the gate electrodes, facing a a gate runner opening of the gate runner, a cutoff contact opening toward the cutoff structure, and a shorting contact opening toward the source layer or the body layer near a wafer edge; and j) on the insulating layer A first metal region and a second metal region are electrically insulated from each other, wherein the first metal region is electrically connected to the gate rail, wherein the second metal region is electrically connected to a source terminal, wherein The thickness T2 is thick enough to carry a blocking voltage. The method of claim 15, wherein only a mask is required for steps a) through j). The method of claim 15, wherein the step b) further comprises preparing a heavily doped channel termination region under the trench TR2. A semiconductor device comprising: a plurality of gate electrodes over a gate insulating layer formed in an active trench in an active region of a semiconductor substrate; formed in the semiconductor substrate a first gate runner electrically connected to the gate electrodes, wherein the first gate runner abuts and surrounds the active region; and a first portion connected to the first gate runner a second gate runner for connecting a gate metal; and a trench having a width W3 and filled by a dielectric, surrounding the first gate runner and the second gate runner and the active region Wherein the thickness T2 of each of the insulating layers in the trenches of the first gate runner and the second gate runner is greater than the thickness T1 of the gate insulating layer in the active trench, wherein the thickness T2 is sufficient to carry a blocking voltage; Wherein the width W3 is greater than the width W2 of the gate runner trench, and the width W3 is sufficient to carry the latching voltage. The semiconductor device of claim 18, further comprising: a cutoff structure surrounding the first gate runner and the second gate runner and the active region, wherein the cutoff structure comprises the semiconductor A conductive material in the trench of the substrate covered with an insulator, wherein the cutoff structure is shorted to a source or a body layer of the semiconductor substrate near the edge of the wafer to form a channel end point of the component. The semiconductor device of claim 18, further comprising a heavily doped channel termination region under the dielectric filled trench. The semiconductor device of claim 18, wherein the semiconductor substrate comprises a bulk layer of the active region and a cutoff region. The semiconductor device of claim 21, wherein the semiconductor substrate comprises a source region. The semiconductor device of claim 22, wherein the source region is located only in the active region. The semiconductor device of claim 18, wherein the first gate runner comprises a channel termination region formed under the trench. The semiconductor device of claim 18, wherein the semiconductor substrate further comprises the semiconductor substrate having a heavily doped underlayer and a heavily doped top layer, wherein the first gate runner trench is sufficiently deep, The heavily doped underlayer can be accessed. The semiconductor device according to claim 19, wherein the insulator in the trench filled with the insulator described in the cut-off structure is sufficiently thick to carry the blocking voltage.