TW201142929A - Dual gate oxide trench MOSFET with channel stop trench and three or four masks process - Google Patents

Abstract

A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Description

201142929 VI. Description of the Invention: [Technical Field] [0001] The present invention relates generally to trench metal oxide semiconductor field effect transistors (MOSS-FETs), and more particularly to oxide via trenches MOSFETs, And a method of preparing the element using three or four masks. [Prior Art] Qing 2] DM0S (Double Diffusion MOS) transistor is a transistor that uses two continuous diffusion techniques to calibrate to the same edge to prepare the channel region of the transistor. DMOS transistors are typically high current components for low voltage and high voltage and are used as components of separate transistors or power integrated circuits. DMOS transistors can provide very high current per unit area at very low forward voltage drops.] A typical DMOS transistor is a transistor called a trench DM0S transistor, in which the channel is located in the trench. A gate is formed in the trench on the sidewall, starting from the source and extending toward the drain. The trench gate is covered with a thin oxide layer and filled with polysilicon, the ability to limit current is inferior to the planar gate transistor structure, so its specific on-resistance is lower. [〇〇〇4] However, the conventional method of preparing such a trench DM0S field effect transistor requires five to six masking techniques, which are not only expensive but also time consuming. The first mask is a deep well mask and is also used for high voltage cutoff. Whether or not to use the mask is selected depending on whether the prepared component is a pressure component. The second mask is a trench mask used to fabricate trenches for gate and other component structures. The third mask is a bulk mask and is also used to prepare the cut-off region. The gate oxide in the protection gate runner is not destroyed by being exposed in the gate potential, and the gate pad/gate is masked. The track is far from the drain voltage. The fourth mask is the source 100117201 Form No. A0101 Page 4 / Total 55 Page 1003238382-0 201142929 Mask, the source region is removed from the gate runner and the cut-off region, thereby shifting the breakdown current out of these regions, improving non- Clamp-inductive switch (UIS) performance. The fourth mask is also used to prepare the channel termination. The fifth mask is a contact mask for the source/body and gate contacts, and the sixth mask is a metal mask for separating the metal layer into gate and source metal regions. [0005] FIG. 1 shows a cross-sectional view of a trench MOSFET 100 which is fabricated using the conventional six mask technique described above. As shown in FIG. j, the trench m〇sfet 100 includes an active cell 1 〇 2 and a gate runner 1 〇 4 in the active region. The gate runner is connected to the gate in the active cell 1〇2. The p-reverse channel may be formed along the top surface of the N- epitaxial layer ill toward the end of the wafer. If the P-inverting channel begins at junction stop 108 and touches wafer edge 112, then the N+ channel end point 106 that causes the leakage current β heavily doped between the source/body and the drain can prevent this ρ-reverse. The transfer channel contacts the wafer edge 112' at the wafer edge 112, which can be shorted to the drain. SUMMARY OF THE INVENTION It is an object of the present invention to provide a dual gate oxide trench MOSFET with a channel stop trench and its three or four masking techniques to reduce cost and simplify fabrication techniques. A technical solution of the present invention is to provide a method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1 having a width W1 'W2, respectively , TR2, wherein W1 is narrower than W2, wherein the trench TR2 includes a first gate runner 100117201 connected to the trench TR1. Form No. A0101 Page 5 / Total 55 Page 1003238382-0 201142929 Trench and second gate slip a trench, wherein at least one of the first gate runner trench and the second gate runner trench abuts and surrounds the trench TR1; [0011] c) trench TR1 having a thickness of ΤΙ, T2 Preparing a gate insulator on the bottom and sidewalls of TR2, wherein T2 is greater than T1; d) preparing a conductive material in trench TR1 to form a gate electrode, and preparing a conductive material in trench TR2 to form a first gate runner and a second gate runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; [0013] e) preparing a body layer on top of the semiconductor substrate [0014] f) preparing a source layer on top of the bulk layer; [0015] g) in semiconducting An insulating layer is used over the bulk substrate; [0016] h) using a second mask over the insulating layer; [0017] i) using a second mask, forming an electrical contact by a contact opening in the insulating layer, wherein the contact opening comprises a source opening toward the source layer near each gate electrode, a gate runner opening toward the gate runner, a cut-off contact opening toward the cutoff structure, and a short circuit toward the source layer or the body layer near the edge of the wafer a contact opening; and [0018] j) preparing a first metal region and a second metal region on the insulating layer and electrically insulated from each other, wherein the first metal region is electrically connected to the gate runner, wherein the second metal region and the source The pole connector is electrically connected, wherein the thickness T2 is sufficiently thick to carry the blocking voltage. [0020] In the above described method: 100117201 Form No. A0101 Page 6 / Total 55 Page 1003238382-0 201142929 _1] b) Also includes a trench T3 having a width W3 prepared therein, wherein wutw3 is narrow, wherein trench TR3 is surrounded by The trench TR1 and the off-channel of the trench TR2 of the gate runner; [0022] c) further comprising preparing a gate insulator on the bottom and sidewalls of the trench TR3 having a thickness, wherein the T3 is greater than T1 [0〇23] d) further comprising preparing a conductive material in the trench TR3 to form a cut-off structure, wherein the cut-off structure is electrically insulated from the gate runner and the gate electrode; _] i) S comprising using the second mask An electrical contact 'where the contact opening includes an off-contact opening toward the cut-off structure' and a short-circuit contact opening toward the source or body layer near the edge of the wafer is prepared by a contact opening in the insulating layer; and [0025] [0028] [0033] [0033] [0033] 10017201 J) further comprising preparing a third metal region on the insulating layer, wherein the third metal region [, the cutoff joint and the shorting joint are electrically Connecting so that the cutoff structure is shorted to the body region at the edge of the wafer Above, wherein the thickness T3 is thick enough to be able to bear the blocking voltage. In the method described above, step e) comprises: preparing a body layer throughout the semiconductor portion. In the above method, step j) comprises: depositing a metal layer over the insulating layer; using a metal mask over the metal layer; and t-domain and the method described above, the step 〇 includes the form number A0101 ^ 1003238382-0 page 7 / total 55 pages 201142929 [0034] [0036] [0040] [0040] [0044] [0044] [0045] [0045] For the bottom and sidewalls of the trenches TR1, TR2 of ΤΙ, T2, a gate insulating layer is prepared using a mask, where T2 is greater than T1. In the above method, step c) comprises: forming a first thumb insulator on the bottom and sidewalls of the trenches TR1, TR2; using a gate insulator mask over the thin insulating layer, wherein the gate The insulator mask covers the trench TR2 but does not cover the trench TRi; the first gate insulator is removed from the portion of the semiconductor substrate not covered by the second mask containing the trench TR1; and in the trench TR1 A second gate insulator is prepared wherein the second gate insulator is thinner than the first gate insulator. In the above method, by implanting ions at a relatively high energy, step e) is performed, at which the ions can pass through the second gate insulator and the first gate insulator, implanted into In a semiconductor substrate. In the above method, by implanting ions of a certain energy, a step 〇 is performed, which enables the ions to pass through the second gate insulator, but does not pass through the first gate insulator, and is implanted into the semiconductor lining In the bottom. In the above method, the source layer is formed only in the top of the body layer in the vicinity of the trench TRi. In the above method, step c) comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TRI, TR2; preparing a sacrificial material 'completely filling the trench TR1, but merely lining the trench 100117201 Form No. A0101, page 8 of 55, 1003238382-201142929 TR2; [0046] etch back the sacrificial material, remove the sacrificial material on TR2, but retain the sacrificial material in TR1; [0047] Prepare a gate in trench TR2 a very insulating layer; and [0048] removing the sacrificial material in the trench TR1, preparing a gate insulator in the trench TR1, wherein the gate insulating layer thickness T2 in the trench TR2 is larger than the gate in the trench TR1 The thickness of the pole insulating layer is T1. [0050] In the above method, the source layer is formed in the top of the entire semiconductor. [0051] In the above method, no more than four masks are used to complete steps a) through j). [0052] In the above method, no more than three masks are used to complete steps a) through j). [0053] In the above method: [0054] b) further comprising preparing a trench T3 having a width W3, wherein W3 is greater than W2, wherein the trench TR3 comprises a trench TR1 and a gate runner trench TR2 The cut-off trench; [0055] wherein the method further comprises: [0056] filling the trench TR3 with a dielectric, wherein the width W3 is sufficient to carry the latch-up voltage. 100117201 Form No. A0101 Page 9 of 55 1003238382-0 201142929 [0058] Only a mask is required for steps a) through j) in the above described method. [0059] In the above method, step b) further comprises preparing a heavily doped channel termination region under trench TR2. [0060] The present invention also provides a semiconductor device comprising: [0061] a plurality of gate electrodes over a gate insulating layer formed in an active trench in an active region of a semiconductor substrate, [ Forming a first gate runner in the semiconductor substrate and electrically connecting to the gate electrode, wherein the first gate runner abuts and surrounds the active region; [0063] connecting to the first gate a second gate runner on the slide for connecting the gate metal; and [0064] wherein the thickness T2 of each of the insulating layers in the gate runner trench is greater than the thickness T1 of the gate insulating layer in the active trench Where the thickness T2 is sufficient to carry the blocking voltage. [0065] The above-mentioned device further includes: a cut-off structure surrounding the first gate runner and the second gate runner and the active region, wherein the cut-off structure includes a trench filled with an insulator in the semiconductor substrate A conductive material in which the carrier structure is shorted to the source or body layer of the semiconductor substrate near the edge of the wafer to form the channel end of the element. [0066] The above described components further include: a dielectric filled trench surrounding the first gate runner and the second gate runner and the active region. [0067] The above described components further include a heavily doped channel termination region under the dielectric filled trench. 100117201 Form No. A0101 Page 10 of 55 1003238382-0 201142929 [0068] The semiconductor substrate of the above-described elements includes an active region and a body layer in the cut-off region. [0069] The semiconductor substrate in the above described device contains a source region. [0070] The source regions in the above described components are only located in the active region. [0071] The first gate runner of the above described component has a channel termination region formed below the trench. [0072] The semiconductor substrate of the above described device further comprises a semiconductor substrate having a heavily doped underlayer and a second heavily doped top layer, wherein the first gate runner trench is sufficiently deep to reach the heavily doped underlayer. [0073] The insulator in the trench filled with the insulator described in the cut-off structure is sufficiently thick to carry the latching voltage. The present invention is to be understood as being limited to the details of the invention. Accordingly, the exemplary embodiment of the present invention does not impose any general loss on the claimed invention without any limitation. <Embodiment> In an embodiment of the present invention, a conventional junction cutoff in a conventional trench MOSFET can be replaced with a thick gate oxide in a gate runner region to terminate the active crystal. Cell area, thus eliminating the wear and tear of the junction, improving the performance of the UIS (non-embedded sensor switch), and the space required for the oxide is much smaller than the space required for the conventional junction cutoff, and also saves the junction cutoff Space. This 100117201 Form No. A0101 Page 11 of 55 1003238382-0 201142929 External 'Reverse recovery characteristics can be improved by confining the embedded body diode to the active area. 2A is a plan view showing the layout of the double gate oxide trench MSOFET 200 according to the first embodiment of the present invention. [0078] FIG. Figure 2B-2 shows a cross-sectional view of trench gate MOSFET 200 along the lines A-A and B-B. As described in detail in Figures 4A-4R, the method for fabricating the oxide cut-off trench M〇SFET 200 requires only four masks: a trench mask, a gate oxide mask, and a contact. Mask and a metal mask. As shown in Figs. 2A and 2B-2, the trench M 〇 SFET 2 〇〇 includes a gate electrode formed in the trench 202 filled with oxide, and the trench 202 is located in the active cell region 210. The gate runners are formed in a wide set of trenches filled with oxide. The gate runner includes a first portion 2〇4 contact and surrounds the active cell region 21 (the gate trace includes a second portion 2〇6, connected to the gate metal layer 248 by a junction 2〇7 The outline is as shown by the dashed line in the second figure. The cutoff structure 208 is formed in another trench filled with oxide, which surrounds the gate runners 204, 206 and the active region 210. 208 may be shorted to the body or source region of component 200 by a turn-off metal 254 and a suitable joint at a particular location. Gate metal - and source metal 252 are electrically insulated from each other by slot 250, slot 25 〇 can be filled with an insulating material. The short-circuited cutoff structure 2嶋 is the end point of the channel. As an example, in the embodiment shown in Fig. 2B-2, the n_ type (using the n-channel _FT element as an example) source Layer 214 may be formed only on top of P-body layer 212 in the active cell region. The gate oxide of active region gate trench 2〇2 is thinner than the gate oxide of gate runner 2G4 The thickness of the gate runner 2〇4 and the thick gate oxide of the off trench 2G8 (eg, approximately 100117201 Form No. A0101) Page 2 of pp. 1003238382-0 201142929 1 000 angstroms (4) to face (A), sufficient to withstand the breakdown voltage; the required thickness depends on the rating of the component. The trenches of the gate runners 204, 206 And the gate oxide in the trench lion 8 is thicker than the gate oxide in the active gate trench, so it can be said that the component 200 has a double thumb oxide thickness. The gate runners 206 and 204, And the gate electrode 'in the active region gate trench 2〇2 is connected together to the element gate potential. The gate electrode in the off trench 2〇8 can be connected to the body region by the wafer edge 213' Wafer edge 213 is at the element drain potential.

2B-1 shows another top view of the double gate oxide trench M〇SFET 200 shown in FIG. 2A, but for convenience of explanation, the first to top view shows only the metal layer. The source metal 252 covers the active region 21A, and the enclosed gate runner 204 » the gate metal 248 covers the gate trace portion of the gate trace 206. The wear stop metal 254 connects the cutoff trench 208 to surround the component. That part. In the layout shown in Figs. 2A and 2B-1, the cut-off metal 254 is connected to the cut-off trench 208 at the corner of the wafer. 2C is an equivalent circuit diagram of a double-storage gate oxide trench MOSFET of the second B-2 diagram. These structures are formed in a semiconductor substrate having an n- epitaxial layer 211 over the bottom n+ substrate layer 214. As shown in the circuit diagram of the figure, the parasitic ρ-channel (taking the η_channel element as an example) transistor 204a can be formed under the gate runner 204 from the active region 210 (located at the source potential of the component). Layer 212 begins as the parasitic drain of parasitic transistor 204a, in the P-body region on the other side of gate runner 204, as the parasitic source of parasitic transistor 204a, the portion of gate gate 204 that surrounds gate runner 204. The epitaxial layer 211 serves as a parasitic channel region of the parasitic transistor 204. It should be noted that if the component 200 is an η-channel 100117201 Form No. Α0101 Page 13/55 page 1003238382-0 201142929 MOSFET, the parasitic transistor is a p-channel transistor, then the element drain potential is the source of the parasitic transistor. Extreme potential and vice versa. The parasitic drain of the parasitic transistor 204a is at the source potential of the element, so that the parasitic gate (the gate electrode in the gate runner 204) is shorted to the drain electrode of the element, and the parasitic transistor 204a can be opened. When the MOSFET element 200 is turned off, all of the gate runners 204 lead to the source potential of the component, and the parasitic transistor 204a can be turned on. This causes the source potential of the element to be shorted from the active region 21{) to the drain potential at the wafer edge 213, thereby generating a leakage current. [0082] To overcome this problem, a cut-off trench 2〇8 may be formed between the periphery of the component, between the wafer edge 213 and the gate runner 204. And below the carrier trench 208, a p-channel parasitic transistor 2〇8a is formed. However, the gate electrode in the via trench 208 is shorted to the parasitic source terminal (the wafer edge 213 end) of the parasitic transistor 208a by the carrier metal 254, so the parasitic transistor 208a is never turned on, so as to One channel end point, avoiding shorting from the source of the component to the edge 213 of the wafer. It is to be noted that since the contact trench 206 is not around the active region 210, the parasitic transistor shown is not used for the gate runner contact trench 2〇6. If necessary, an additional channel end point can be added between the first cutoff structure 208 and the gate runner 2〇4, which is actually the first-normally closed parasitic transistor 2〇8a and the parasitic transistor. Between 204a, another normally closed parasitic transistor is added; thereby increasing the voltage performance at the end of the channel. Channel end points can also be prepared by other methods, such as those described in commonly assigned U.S. Patent Application Serial No. 12/731,112, the disclosure of which is incorporated herein by reference. For example, the heavily doped bottom substrate 214 can be accessed by preparing a sufficiently deep gate runner trench 204 to form the channel 100117201 Form No. A0101 Page 14 of 55 page 1003238382-0 201142929 End point. Alternatively, II is prepared by forming a heavily doped n-region at the bottom of the gate runner trench 2〇4 to form the end of the channel. If an optional channel end point is formed, then the cutoff structure 2〇8 can be omitted. The gate runner trench 204 surrounds the active region and has a sufficiently thick gate oxide to carry the latch voltage. [0083] 闭 The blocking voltage is the voltage between the two main current carrying terminals of the element (eg, the source-to-drain voltage). When the component is in the off state, the thicker gate oxide (such as the gate runner trench or the oxide of the turn-off trench) should be sufficient to carry the latch-up voltage. In other words, the oxide is thick enough and the latch-up voltage is not large. An electrical % over oxide breakdown field is produced on the oxide. Ideally, the breakdown voltage of the cut-off region is higher than the breakdown voltage of the active region, thereby improving the durability of the component. 3A is a plan view showing a layout of a double gate oxide trench MOSFET 300 according to a second embodiment of the present invention, and FIG. 3B is a cross-sectional view showing a double gate turn-off trench MOSFET 300 along lines AA and BB. . The dual gate oxide trench MOSFET 300 is similar to the dual gate oxide trench MOSFET 200 shown in Figures 2A-2B. As shown in Figures 3A-3B, trench MOSFET 300 includes an active gate electrode formed in active gate trench 3〇2, with active gate trench 302 being located in active cell region 310. The active gate electrode is electrically coupled to gate runners 304 and 306, which are formed in a wider trench that is filled with thicker oxide. The gate runner includes a portion 304 that reaches and surrounds the active cell region 310, and a portion 306 that is coupled to the gate metal 348 by a junction 307. A cutoff structure 308 surrounds the gates 304, 306 and the active region 310. The cut-off metal 354 and the appropriate joint &apos; cut-off structure 308 are electrically connected to the source 100117201 Form No. A0101, page 15 / page 55, 1003238382-0, 201142929, pole layer 314 and body layer 312. The gate metal 348 and the source metal 352 are electrically insulated from each other. For example, by the gap 350, the gap 350 ° source metal can be filled with the insulating region 310 and the surrounding gate runner 304. As noted above, the shorted cutoff structure 308 serves as the end of the channel. In the present embodiment, the 'n-type source layer 314 may be formed on the top of the active cell region 31 and the P-body layer 312 in the cut-off region, and the source and the body are both formed in the n-type drift/epitaxial layer. Above 311. As shown in Figures 5A-5Q, a dual gate oxide trench MS 〇 FET 3 可以 can be fabricated using a two mask technique. [0086] FIG. 3C is an equivalent circuit diagram showing the double gate oxide cutoff trench m〇sfet h shown in FIG. 3B. As shown in the circuit diagram, the parasitic p-channel transistor 304a is formed under the gate runner trench 304, but after the cutoff trench 308 is reduced, as the end of the channel. The parasitic transistor 308a is located below the cut-off trench 3'. By means of the turn-off metal 354, its parasitic source is shorted to the parasitic gate, thereby avoiding switching on as described above. 4A 4R is a cross-sectional view showing a four mask preparation method of the double gate oxide trench MOSFET of the type shown in Figs. 2A, 2B-1 and 2B-2. As shown in FIG. 4A, the initial material for preparing the semiconductor substrate comprises 1"', for example, a relatively lightly doped (eg, η-) epitaxial layer 4〇4 is over the heavily doped (eg, η+) substrate 4〇2 . Alternatively, the epitaxial layer is doped with ρ_ and the substrate is doped with Ρ+. An initial insulating layer 406 may be formed on the top surface of the epitaxial layer 4A4. By way of example, but not by way of limitation, insulating layer 406 may be prepared with an oxide, such as by thermal oxidation combined with deposition of a low temperature oxide or high density plasma (HDP). As shown in Fig. 4, above the insulating layer Mg, a first mask 408 (herein referred to as a trench mask) is used, and a pattern having an opening corresponding to the trench to be prepared is formed. After the moment, 100117201 Form No. Α0101 Page 16 of 55 1003238382-0 201142929 Grooves 41G, 412, 414 and 416 are formed through the insulating layer _, the sound 4 〇 4 and the top of the epitaxial layer. The first and second gate runners can be prepared in a subsequent technique using trenches and 412 turns. For simplicity, the trenches 410, 412 are referred to herein as first and second gate runner trenches. Lee Yi

[0087] G

[0088] A trench 414 is formed to partially cut off the active region. For simplicity, the trenches 414 are referred to herein as damascene trenches. The active element cells are fabricated using trenches 416. For simplicity, these trenches 416 are referred to herein as active trenches. If the width of the groove is different, then it can be in the common engraving step. For example, the gate runner trenches 41, ^ and the off trench 4U may be wider than the active trenches 416 to etch the gate runner trenches 4iq, 412 and the turn-off trenches 414 using the same reticle technique. It is deeper than the active trench 416 and has a trench. In order to utilize the single-mask, the remainder is removed as shown in Fig. 4C. A thick gate insulating layer 118 ((iv)-properate) is deposited, the fabric filaments being formed on the bottom and sidewalls of the trenches 412, 414 and 416, and over the epitaxial layer 404. Thick gate oxide layer 418 has a thickness between about 800 and 1,500 Å. As shown on the first side, sacrificial material 420 is deposited in trenches 41(), 412, 414, and 416 and on top of epitaxial layer 404. As an example, but not by way of limitation, the sacrificial material may be a conductive m (four) material, such as polycrystalline as shown on the front side 'below the top surface of the gate insulating layer 418, and above the top surface of the epitaxial layer 404, which may be used to sharpen the end point. The sacrifice material 420 is etched back. The trenches 410, 412, 414, and 416 can still be filled with the sacrificial material 420. As shown in FIG. 4F, the thin oxygen diffusion barrier layer 422 (eg, nitride) sinks 100117201 Form No. A0101 Page 17 of 55 Page 1003238382-0 [0091] 100117201 is deposited over the sacrificial material 420 in the trenches 41G 412' 414 and 416, and over the gate, germanium edge layer 418. As an example, a thin nitride layer-like thickness of about 200A to 5〇〇1 is used above the thin nitride layer 422' using a second mask 424 (i.e., a gate oxide mask). As shown in Fig. 4G, the gate oxide mask appears to cover only the trenches 410, 412, 414 located in the sugar pole runner region and the cutoff region, but does not cover the active trench 416. The sacrificial material 420 ensures that the photo-resistance material does not deposit in the trenches - deposition will be difficult to remove. The last name is the portion of the thin nitride layer 422 that is not covered by the second mask 424, and then the sacrificial material 42Q in the side trenches 416. In the trench 416 and above the epitaxial layer 4A4, the thick gate insulating layer 418 which is not covered by the second mask 424 is also etched away. The first mask 424' is removed and then over the sidewalls and bottom of the active trench 416 and over the η- epitaxial layer 404, as shown in FIG. 4H, a sacrificial insulator 426 is prepared (e.g., grown). A material is not formed (e.g., grown) on the material of the thin nitride layer 422, and the sacrificial insulator is preferably made of such a material. As an example, the thin nitride layer 422 may be made of a nitride material (e.g., nitride nitride). The thin sacrificial insulating layer 426 may be made of a grown oxide material such as hafnium oxide. The sacrificial insulator 426 has a thickness of about 2 〇〇A to 500 Å. As shown in Fig. 41, the remaining portion of the thin nitride layer 422 is stripped. The sacrificial material 42 in the trenches 410, 412, 414 is then etched away. The thin oxygen diffusion barrier layer 422 can be made of a material that resists the sacrificial insulating layer 426. Further, the 'thin oxygen diffusion barrier layer 422 can also be made of a material that can be etched using a technique that the sacrificial insulating layer 4 26 can resist. Form No. A0101 Page 18 of 55 1003238382-0 201142929 [0092] 009 [0095] 100117201 The sacrificial insulating layer 426 is thinner than the thick gate insulating layer 418, as shown in FIG. 4J. The sacrificial insulating layer 426 is removed from the active trenches 416 while leaving the thick gate insulating layer 418 intact. A thin gate insulator 428 is then formed in the bottom and sidewalls of the active trench 416. The thin gate insulator 428 has a thickness of about 150 A to 500 Å. As shown in FIG. 4K, in all of the trenches 41A, 412, 414, and 416, a conductive material 430 (eg, polysilicon) is deposited, which may also be above the thick gate insulator 418 and thin above the epitaxial layer 404. The top of the gate insulator 428 overflows. Then, as shown in Fig. 4L, the conductive material 43〇 can be etched back by the end point below the top surface of the epitaxial layer 404. As shown in FIG. 4M, a body layer 432 is formed on top of the epitaxial layer 404. For example, the body layer 432 can be prepared by a full vertical or angled implant and diffusion of dopants having a conductivity type opposite to the epitaxial layer 404 and the substrate 402. For example, if substrate 402 and epitaxial layer 404 are n-type doped, then body layer 432 can be fabricated by implanting a p-type dopant, and vice versa. The bulk implant can also be performed at very high energies (eg, 80-1 20 keV), and the thick gate insulator 418 does not interfere with bulk implantation as shown in FIG. 4N, using low energy implant technology, at body layer 432. A source layer 434 is formed on the top. If the source implant is performed at extremely low energy (e.g., around 2 OKeV) and the thick gate insulator is relatively thick (e.g., the thickness of the oxide is about 1200 A), then the thick gate insulator 418 hinders Implanted, and the thin gate oxide 428 is relatively thin, allowing the ions to penetrate into the 'so that the dopant is implanted only into the active cell region. Source layer 434 is prepared, for example, by vertical or angled implantation and annealing. Typically, the form nickname A0101, page 19, page 55, 1003238382-0, 201142929 The source layer 434 is fabricated by implanting dopants of opposite conductivity types to the bulk dopant. No additional masking is required when source and ontology are implanted. [0098] 100117201 As shown on the side, an insulating layer is formed over the structure, which is compact and flat. The planarization can be accomplished by chemical mechanical planarization (CMP). The above is merely an example, but not limited thereto, the insulating layer can be a low temperature oxide and contain __glass (BpsG). As shown in the fourth (fourth), the contact mask poplar is wounded on the upper floor of the insulating layer, and an open σ pattern of the strip-shaped contact hole is formed. The contact mask appears to be the third mask used in the art. The insulating layer, the source layer 434, and a portion of the body layer 432 in the active cell region may be etched by openings in the mask 438 to form the source/body contact holes 442. The insulating layer and a portion of the conductive material in the trenches 412, 414 are all left downward to form a gate contact hole 444 and an insulating layer 436 that cuts off the contact hole 445 at the edge of the cutoff region and near the trench 410, and the body layer 432. The top portion can be etched down to form a cut-off shorting contact hole 446. A barrier material (e.g., Ti/TiN) layer 448 may be deposited in contact holes 442, 444, 445, and 446 as shown in the . Contact holes 442, 444, 445, and 446 are then filled with a conductive (e.g., tungsten (W)) plug 450. The barrier metal 448 and the tungsten plug 45A in the contact hole 442 serve as a source/body joint in the active region. Barrier metal 448 and tungsten plug 450 in contact hole 444 act as a gate contact over gate contact trench 412. The barrier metal 448 and the tungsten plug 45() in the contact holes 445, 446 form a joint in the cut-off region, shorting the via-groove electrode to the body region near the edge of the wafer. A metal layer 452 can then be deposited over the structure (form number A0101 page 20/55 pages 1003238382-0 201142929 preferably Ab Si). [00&quot;] depositing a patterned metal mask (not shown) on the metal layer 452, and then dividing the metal layer 452 into electrically insulating portions by metal stamping to form a gate 'cutoff and source metal For example, the gate metal 456, the cut-off connection metal 458, and the source metal 454, thereby forming the device 4, the device 400 and the semiconductor device shown in FIG. 2A, 2B-1, and 2B-2 300 is similar. The metal mask is the fourth mask in the technique. The barrier metal 448 and the tungsten plug 450 in the contact hole 442 serve as source/" body contacts above the source region, starting from the source layer 434 and the body layer 432. Until the source metal 454. Barrier metal 448 and tungsten plug 450 in contact hole 444 act as a vertical gate runner joint above the gate runner region, starting from the gate runner, up to gate metal 456. The potential metal 448 and the tungsten plug 450 in the contact holes 445, 446, and the cut-off metal 458' short the gate of the cut-off trench 414 to the body region 432 between the wafer edge 413 and the turn-off trench 414. The _] 帛 5A-5Q diagram shows a cross-sectional view of a three mask method for preparing a dual thumb oxide trench MOSFET of the type shown in the above wA_3B. The method used to fabricate the dual gate oxide trench M〇SFET 3 turns requires only three masks: a trench mask, a contact mask, and a metal mask. In this method, the gate oxide mask shown in the 4th HR diagram can be omitted. [0101] As shown in FIG. 5, the semiconductor substrate includes, for example, a relatively lightly doped (e.g., η) epitaxial layer 504 over a substrate 502 heavily doped (3). An oxide layer 5G6 is formed on the top surface of the n- epitaxial layer (10). As an example, the oxide can be prepared by thermal oxidation and deposition of a low temperature oxide or a high density plasma. As shown in Figure 5, wide 100117201 Form Compilation 0101 Page 21 of 55 '1003238382-0 201142929 Above layer 506, using a first mask 508 with an opening pattern defining the trench (ie trench mask) ). The trenches 510, 512, 514, and 516 are formed by etching through the oxide layer 5〇6, the epitaxial layer (10), and the top of the n+ substrate 502. The first and second gate runners can be prepared in subsequent techniques using trenches 51A and 512. For simplicity, trenches 510 and 512 are referred to herein as first and second gate runner trenches. A further trench 514 can be used to prepare the cut-off trench. For simplicity, trench 514 is referred to herein as a cut-off trench. The active element cells can be fabricated using trenches 516. For simplicity, trench 516 is referred to herein as an active trench. The gate runner trenches 51A, 512 and the via trenches 514 can be wider than the active trenches 516, so even if they are all etched in the same etch technique, the gate runner trenches 510, 51 2 and The cutoff trench 514 can also be etched wider than the active trench 516. [0102] As shown in FIG. 5C, the first mask 5〇8 is removed. A gate insulating layer 518 (e.g., an oxide) is formed on the bottom and sidewalls of the trenches 51, 512, 514, and 516, and over the epitaxial layer 5?. The gate insulating layer 518 has a thickness of about 500A to 1 000A. As shown in Figure 5D, a deposition sacrificial material 520 (e.g., polysilicon) fills the active trenches 516 and is deposited over the epitaxial layer 504. The gate runner trenches 510, 512 and the cutoff trenches 5丨4 are substantially wider than the active trenches 516, and the sacrificial material 52〇 only fills the bottom and sidewalls of the trenches 510, 512, 514. They did not fill these grooves. Then, the sacrificial material 52A is anisotropically etched back by etching the active trench 516, under the top surface of the thick gate insulating layer 518, and at the end point above the top surface of the epitaxial layer 5?4. As shown in Fig. 5E, the sacrificial material 520 can be completely removed from the gate runner trenches 510, 51 2 and the off trench 514. In this case, an end point of the channel can be formed at the bottom of the gate chute groove 51〇, 100117201 Form No. A0101, page 22/55 pages 1003238382-0 201142929 512, such as by anisotropic implantation . The above is only an example, but not limited thereto, m For the η-channel rib element, the channel end point may be η + doped. [0103] As shown in FIG. 5F, on the bottom and sidewalls of the trenches 510, 512, u 14 and above the gate insulator 518, the sinking material is formed around the edge material to form A thicker insulating layer 522. In general, the type of insulating material can be the same as the type of material of the gate insulator 518. Rabbit _, edge 518 is an oxide, then the insulation is thick * The fruit can be formed by oxide deposition (such as high temperature oxide (ΗΤΟ), +). Therefore, a thicker gate insulating layer 522 is formed in the trenches 51A, _512, 514, and a thinner gate insulating layer 518 is formed in the active trenches 516. Then, planarization (e.g., CMP) is performed on the surface such that the surfaces of the insulator 522 = face and the sacrificial material 52 in the groove 516 are level with each other to expose the sacrificial material 520 ' as shown in Fig. 2, and then As shown in Fig. 5, the sacrificial material is removed from the trench 516. At this time, the thickness of the oxide layer in the sidewalls and the bottom of the trench 516 (for example, about 500 Å to 1 〇 Α) is smaller than the thickness of the oxide layer in the sidewalls and the bottom of the trenches 510, 512, 514 (for example, about 1500 Å to 10,000 Å). 2〇〇〇Α). The insulators 518 and 522 are then thinned by isotropic etching to form active gate insulators 524 in the active trenches 516, as well as in the gate runner trenches 510, 512 and the via trenches. A thicker gate insulator 514 is formed in 514. A short etch is preferably used to completely remove the insulating layer 518 from the active trench 516 while leaving the thickest insulation of the trenches 510 ' 512, 514 * most completely intact. Layer 522; then, in the active trench 516, a thin active gate insulating layer 524 is formed (eg, grown) while being in the trenches 51〇, 100117201 Form No. A0101 Page 23/55 pages 1003238382-0 201142929 512 Thicker gate insulator 523 is retained in 514. Therefore, the component can be said to have a thickness of a double gate insulator. The thickness of the active gate insulator 5 2 4 is between about 150 A and 800 A, while the thickness of the thicker gate insulator 523 is between about 5 Å and 1200 Å. [0107] A conductive or semiconductive material 526 (eg, polysilicon) may be deposited or otherwise formed, as shown in FIG. 5J, filling the trenches 510, 512, 514 on the top surface. And 51 6. If necessary, the conductive material 526 can be doped to make it more conductive. Then, the conductive material 526 is etched back by the etching end point below the top surface of the epitaxial layer 504, as shown in FIG. 5K, to form the active gate electrode 525, the gate runner 527, and the wearing structure 529. As shown in the 5L diagram, a body layer 528 may be formed on top of the epitaxial layer 5〇4. The body layer 528 can be formed, for example, by full implantation in a vertical or angled manner and diffusion of a suitable dopant. For example, as shown in Figure 4M above. As shown in Fig. 5M, at the top of the body layer 528, a source layer 530 is formed. The source layer 530 can be formed, for example, by implanting a suitable dopant in a vertical or angled manner and annealing, for example, as shown in Figure 4N above. As shown in Fig. 5N, an insulating layer 532 (e.g., low temperature telluride or boric acid containing barium glass (BPSG)) may be formed over the structure, then compacted and CMP planarized. As shown in Fig. 50, a contact mask 534 is formed on the insulating layer 532, and a pattern having openings defining the contact holes is formed. It is to be noted that at this point, the contact mask 534 is only the second mask used in the art. By 100117201 Form No. A0101 Page 24 / Total 55 Page 1003238382-0 [0108] 201142929 The opening σ in the mask can be _ insulating layer 532, source layer 530 and the portion of the body layer 528 in the active cell region To form the source contact hole 536. The insulating layer 532 and the trench 512, the portion of the material 526 in the middle can be etched down to contact the hole 541. The insulating layer 532 'source layer 53 〇 and the portion of the body layer 528 located near the edge of the cut-off region and the trench 514 are etched down to form the cut-off short-circuit contact hole 542. [0109] θ Ο As shown in FIG. 5P, a barrier material (for example, Ti/TiN) layer 543 may be deposited in the contact holes 536, 54A, 541, and 542 and over the oxide 532. The contact holes 536, 540, 541 and 542 are then filled with an electrically conductive (e.g., tungsten (1)) plug 544. Barrier material 543 and tungsten plug 544 in contact hole 536 act as a source/body junction in the active cell region above source region 530. The barrier material 543 and the tungsten plug 544 in the contact hole 540 serve as gate contacts over the gate region or the turn-off region. The barrier material 543 and the tungsten plug 544 in the contact holes 541, 542 serve as a joint for short-circuiting at the end of the cut-off/channel. As shown in Fig. 5P, above the resulting structure, a metal layer 546 is deposited, preferably Al-Si. A patterned metal mask (not shown) is deposited on the metal layer 546, and then the metal layer 546 is divided into electrically insulating portions by metal etching to form an electrically insulating metal region including the gate metal region 55 〇 and the source. The metal region 552 and the cut-off metal region 548 of the semiconductor device 300 shown in FIGS. 3A-3B complete the fabrication of the device. The metal mask used in this technique is the third mask. The barrier material 543 and the tungsten plug 544 in the contact holes 536, 538 act as source/body contacts over the source region, starting from the source layer 534 and the body layer 532, up to the source metal 552. 100117201 in contact hole 540 Form No. A0101 Page 25 / Total 55 Page 1003238382-0 201142929 Barrier material 543 and tungsten plug 544, as vertical slide joints above the gate runner region, from the first and second gates The joint begins until the gate metal 550. The barrier material 543 and the tungsten plug 544 in the contact holes 541, 542 serve as a joint to the cut-off metal 548 over the cut-off/channel region. In this method, the gate oxide mask is omitted. [0112] In an alternative version of the method, after the technique shown in FIG. 5F, it may be formed below the bottom of the gate runner grooves 51A, 512 and below the cutoff trench 514. Channel termination area. As shown in Fig. 6, a full channel implant is performed to form a heavily doped channel termination region 595 (having the same conductivity type as the final source region) under the trenches 510, 512, 514. As an example, the energy of the channel termination implant is sufficient to pass through the trench oxide 522 in the trenches 510, 512, 514, but not enough to pass through the initial trench hard mask 5〇6 in the 5A-5B diagram. The thicker top oxide layer 531 ° top oxide layer 531 and the polycrystalline spine 520 in the active trench 516 can serve as a hard mask such that the channel termination region 595 is formed only at the bottom of the gate runner trenches 510, 512. Below and below the cut-off trench 514, the trenches 510, 512, 514 may also be chosen to be deep enough to touch the bottom of the channel as the end of the channel. If the end of the channel is formed at trenches 510, 512, then as long as the thickness of oxide 522 in gate runner trenches 510, 512 is sufficient to carry the latching voltage, turn-off trench 514 is not necessary. 7A-7B shows an alternative structure for combining the dual gate oxide described herein with the oxide cut-off trench described in U.S. Patent Application Serial No. 12/731,112, the entire disclosure of which is incorporated herein by reference. The oxide trimming trenches described in 12/731,112 are incorporated by reference. 7A is a plan view showing the layout of a double-stacked gate trench MOSFET device 700 according to an embodiment of the present invention, No. 100117201, Form No. A0101, Page 26 of 55, 1003238382-0, 201142929 7 Β Figure shows a double gate oxide MOSFET A cross-sectional view of the oxide cutoff trench of 700 along lines AA and BB. The method used to fabricate the oxide cut-off trench M〇SFET 7 turns requires only three masks: a trench mask, a contact mask, and a metal mask, which will be detailed in Figure 8A-8R. Introduction. [0113] As shown in FIGS. 7A-7B, the trench M〇SFET 7A includes a gate electrode formed in the oxide-filled trench 716 located in the active cell region 711. The gate runners are formed in a wide set of oxide-filled trenches. The thumbpole slide includes a first portion 71A adjacent to and surrounding the active cell region 711. The gate runner includes a second portion 712 that is connected to the gate metal layer 754 (shown as a dashed line in Figure 7A) by a joint 7?7. The oxide stop trench 714 is a trench filled with oxide that surrounds the thumb slides 710, 712 and the active region m. The oxide cutoff trench 714 has a heavily doped (n+) channel termination region 730 located below the oxide cutoff trench 714. As an example, in the embodiment shown in the "FIG." figure, the source-type (in the case of an η-channel MOSFET element) may be formed only in the source layer 36.

G The top of the Ρ-body layer 734 in the active cell region. A source metal layer pin is connected to the source/body region in the active region 711. The gate oxide of active cell gate trench 716 is much thinner than the gate oxide of gate runners m, 712. The gate runners 710, 1000A to 2000A) have a wide stop trench 714, and the thick gate oxide of 712 is very thick (eg, about 'sufficient to carry the latch-up voltage. In addition, the oxide is trapped, filled with dielectric material, sufficient to carry A high breakdown field equivalent to the blocking voltage. On the semiconductor substrate of 704, over the substrate 702. The spacer 700 is formed to include an epitaxial layer 704 formed on the heavily doped bottom [0114] 8A-8R The figure shows a method in which only three masks are required to prepare the 100117201 Form No. A0101 27th Stomach/55 pages 1003238382-0 201142929 element 700 shown in Figures 7A-7B. In the figure, 'Initial Semiconductor Substrate (e.g. There is an n- epitaxial layer 7〇4) located above the underlying substrate 7〇2) having an oxide layer 7〇6 formed thereon. In the 8th β-graph, the trench mask 7〇8 is the first in the technique- The masks are engraved into the epitaxial layer 7〇4 by openings in the trench mask 708. The trenches include active trenches 716, gates adjacent to and surrounding the active trenches 716. Channel trench 71(), gate runner trench 712, and turnoff trench 714〇 gate runner trench 71〇 The sum 712 is wider than the active trench 716, and the off trench 714 is wider than the gate runner trenches 71, 712. In Fig. 8C, the trench mask 708 is removed, in the trenches 71, 712,

Sacrificial oxides 718 are formed on the bottom and sidewalls of 714, 716. In Fig. 8D, a temporary polysilicon layer 72 is formed over the element. The polysilicon layer 720 is thick enough to completely fill the narrower active 716, but only fills the sidewalls and bottom of the wider trenches 710, 712, 714. The polysilicon 72 of the trenches 710, 712, 714 is removed by an (isotropic) etch, but the polysilicon 720 in the active trench 716 is retained, as shown in Figure 8E. In Fig. 8F, an oxide layer 722 is formed on the element. This causes the oxide layer in the trenches 710, 712, 714 to thicken and cover the polysilicon 720 in the active trench 716. The top oxide 722 is planarized (e.g., by CMp) to expose the top of the polysilicon 720, but retains the oxide 722 in the trenches 71, 712, 714, as shown in Figure 8G. In the 8JJ diagram, the temporary polysilicon 720 is removed. At 81, the oxide in active trench 716 is etched away and an active gate oxide is formed. The sacrificial oxide can be grown and removed prior to forming the active gate oxide 726. Since the oxides in the trenches 710, 712, 714 are thicker than the oxides in the active trenches 716, they are not completely etched away during the etching of the oxide, and finally formed in the trenches 710, 712, 714. Thick Gate Telluride γ24 Form Number Fine 01 Page 28 / Total 55 Page 1003238382-0 201142929

'greater than the active gate oxide 726 in the active trench 716. In the figure, a polysilicon layer 728 is deposited over the device, and the 矽t 曰 矽 layer 728, although filled with trenches 710, 712, 716, is only partially inside the oxide-off trench 714. In Fig. 8K, the polycrystalline material 728 is etched back to the keel, so that it remains in the trenches 710, 712, 716 and is present in the wide oxide stop trench 714. At this time, a heavily doped (n+) channel termination region 73A may be formed at the bottom of the wide oxide cutoff trench 714, e.g., by the inversion of the opposite. The polycrystalline layer 728 in the dragon trenches 710, 712, 716 blocks the implantation of these trenches at the bottom. An oxide 732 is deposited over the element to fill the remaining oxide cut-off trench 714&apos; and to cover the polysilicon layer 728&lt;&apos;&gt;&gt; and then flatten the oxide 732 to the surface of the epitaxial layer 704 as shown by the flute. [0115] In Fig. 8M, a (p_type) yoke body region 734 is prepared over the entire wafer. In Fig. 8N, an (n~ type) source region 736 is formed over body region 734. The body and source regions can be formed without a mask as a full implant. In Fig. 80, a very thick dielectric layer 738 can be formed over the element, e.g., by O LTO and BPSG deposition. In the figure, a contact mask 740 is used. Contact mask 740 is only the second mask in the art. In the BPSG 738, the source region 736, and the body region 734, the active cell source/body connector 742 is etched. In the bare body region 734, a (p+) body contact implant (not shown) can be performed. In the BPSG 738 and in the polysilicon in the gate runner trench 712, the gate junction 744 is left. In Fig. 8Q, the contact mask 74 is removed, and a conductive (e.g., tungsten) plug 748 is formed in the contacts 742, 744. A barrier metal 746 can be prepared prior to forming the tungsten plug 748. On the component 100117201 Form No. A0101 Page 29 of 55 1003238382-0 201142929, prepare a metal layer 750 (eg aluminum). In the 8R picture, the metal layer 750 is etched in the source metal 752 and the gate metal 754 using a metal mask (not shown), thereby completing the double gate oxide MOSFET using only three masks. Element 700. Although not illustrated, a drain metal can be formed on the back side of the element without using a mask. [0116] Although the invention has been described in detail with respect to certain preferred versions, other versions are possible. For example, a suitable alternative insulator may be used as an oxide. Meanwhile, according to the above description, an example of an n-channel element is typically used; however, embodiments of the present invention can also be applied to a p-channel element by inverting an appropriate conductivity type. Therefore, the scope of the invention should be determined not by the description of the invention, and the scope of the invention should Any optional item (whether preferred or not) can be combined with any other option (whether preferred or not). In the scope of the patent application, the indefinite article "a" or "an" The scope of the appended patent application should not be construed as a limitation of the meaning and function unless the meaning of the function is clearly indicated by the meaning. While the present invention has been described in detail by the foregoing preferred embodiments, it should be understood that Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0118] Fig. 1 is a cross-sectional view showing a conventional trench MOSFET device. 100117201 Form No. A0101 Page 30 of 55 1003238382-0 201142929 The 2A chart is a top view of the dual gate oxide trench MSOFET layout of the first embodiment of the present invention. The second B-1 chart is not another top view of the dual gate oxide trench M〇SFET 200 layout shown in FIG. 2A. The 2B-2 chart is not a cross-sectional view of the double gate oxide trench M 〇 SFET shown in Fig. 2A along lines A-A and B-B. The equivalent circuit diagram of the double-gate oxide trench MOSFET shown in the 2C-1f and 2B_2 of the 2C chart tf.

Figure 3A is a top plan view of a dual gate oxide trench MSOFET layout in accordance with a second embodiment of the present invention. A cross-sectional view of the double gate oxide trench (4) shown in Fig. 3A along line A-A and B-B. A circuit diagram of the double gate oxide trench mqsfet shown in Fig. 3C, tf, Fig. 3B. 4A 4R Chart 7F is a cross-sectional view showing the step of the double gate oxide trench MOSFET shown in the (9)th embodiment of the present invention. Fig. 5A-5Q is a cross-sectional view showing the steps of preparing the double gate oxide trench MOSFET shown in the third Α_3β diagram of the second embodiment of the present invention. Figure 6 is a cross-sectional view showing the steps of preparing a dual gate oxide trench MOSFET according to an alternative embodiment of the present invention. Figure 7A shows a top view of a dual gate oxide trench MOSFET layout in accordance with an alternate embodiment of the present invention. Fig. 7B is a cross-sectional view showing the double gate oxide trench MOSFET shown in Fig. 7A along lines A-A and B-B. Fig. 8A-8R is a cross-sectional view showing the steps of preparing the double gate oxide trench MOSFET shown in Figs. 7A-7B. 100117201 Form No. A0101 Page 31 of 55 1003238382-0 201142929 [Main component symbol description]

100, 200, 300, 700: Trench MOSFET 102: Active Cell 104, 204, 206, 304, 306, 527: Gate Slide 106: N+ Channel End 108: Junction Cutoff 111, 211, 311 , 404, 504, 704: epitaxial layers 112, 213, 313, 413, 713: wafer edges 202, 302, 410, 412, 414, 416, 510, 512, 514, 516, 710, 712, 714, 716: trench Slots 204a, 208a, 308a: parasitic transistors 207, 307, 707 '742, 744: joints 208' 308, 529: cut-off structures 210, 310, 711: active cell regions 212, 312, 432, 528: body layer 214, 314, 434, 530, 736: source layer 248, 348, 456, 550, 754: gate metal layer 250, 350: slit 252 ' 352, 454, 552, 752: source metal 254, 354, 458 548: cut-off metal 304a: parasitic p-channel transistor 402, 502, 702: substrate 406, 436, 522, 532: insulating layer 4 0 8 ' 5 0 8 : first mask 418, 518: gate insulation Layers 420, 520: sacrificial material 100117201 Form No. A0101 Page 32 / Total 55 pages 1003238382-0 201142929 422: Nitride layer 424: Second mask 426: Sacrificial insulator 428 ' 523, 524: Gate insulator 430, 526: conductive material 438, 534, 740: contact mask 442, 444, 445, 446, 536, 538, 540, 541, 542: contact hole 448: barrier metal 5 4 3 : barrier material layer 450, 544, 748: plugs 452, 546, 750: metal layers 506, 706, 722: oxide layer 5 2 5: active gate electrode 531: top oxide layer 595, 730: channel termination region 708: trench masks 720, 728: Polycrystalline germanium layer 724: gate oxide 726: active gate oxide 732: oxide 734: body region 738: dielectric layer 746: barrier metal 100117201 Form No. A0101 Page 33 of 55 page 1003238382-0

Claims (1)

201142929 VII. Patent application scope: 1. A method for preparing a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming a width separately The trenches TR1 and TR2 of W1 and W2 are narrower than W2, wherein the trench TR2 includes a first gate runner trench and a second gate runner trench connected to the trench TR1, wherein At least one of the first gate runner trench and the second gate runner trench abuts and surrounds the trench TR1; c) at the trenches TR1, TR2 having a thickness of ΤΙ, T2 A gate insulator is prepared on the bottom and sidewalls, wherein T2 is greater than T1; d) a conductive material is prepared in the trench TR1 to form a gate electrode, and a conductive material is prepared in the trench TR2 to form a first a gate runner and a second gate runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; e) preparing a body on top of the semiconductor substrate a layer; f) preparing a source layer at the top of the body layer; g) at the semiconductor An insulating layer is used over the bulk substrate; h) a second mask is used over the insulating layer; and the second mask is used to form an electrical contact by a contact opening in the insulating layer, wherein the contact opening Included in a vicinity of each of the gate electrodes, a source opening toward the source layer, a thumb slide opening toward a thumb slide, a cut-off contact opening toward the wearing structure, and a vicinity of a wafer edge a short-circuit contact opening toward the source layer or the body layer; and j) preparing a first metal region and a second metal region on the insulating layer, and 100117201 Form No. A0101 Page 34 / Total 55 Page 1003238382- 0 201142929 and electrically insulated from each other, wherein the first metal region is electrically connected to the gate runner, wherein the second metal region is electrically connected to a source connector, wherein the thickness T2 is thick enough to carry a latching voltage. 2. The method of claim 1, wherein: b) further comprising preparing a trench TR3 having a width W3, wherein W1 is narrower than W3, the trench TR3 comprising surrounding the trench TR1 and the gate a cut-off trench of the trench TR2; c) further comprising preparing the gate insulator on a bottom and a sidewall of the trench TR3 having a thickness T3, wherein T3 is greater than T1; d) further included in the trench A conductive material is prepared in the trench TR3 to form the cutoff structure, wherein the cutoff structure is electrically insulated from the gate runner and the gate electrode; i) further comprising using the second mask by the insulating layer The contact opening, the electrical contact is prepared, wherein the contact opening includes the cut-off contact opening toward the cut-off structure, and the short-circuit contact opening toward the source layer or the body layer near the edge of the wafer; and j) further comprising Forming a third metal region on the insulating layer, wherein the third metal region is electrically connected to a cut-off joint and a short-circuit joint, so that the cut-off structure is short-circuited to a body region at the edge of the wafer, wherein the thickness T3 is thick enough to The carrier blocking voltage. 3. The method of claim 1, wherein the step e) further comprises: preparing the body layer over the top of the semiconductor substrate. 4. The method of claim 1, wherein the step j) further comprises: depositing a metal layer over the insulating layer; using a metal mask over the metal layer; and etching the metal layer to separate The first metal region and the second metal region. The method of claim 1, wherein the step c) further comprises: the trenches TR1, TR2 having a thickness of ΤΙ, T2, in the form of the method of claim 1, the method of claim 1 On the bottom and sidewalls, a gate insulating layer is prepared using a mask, wherein T2 is greater than T1. 6. The method of claim 1, wherein the step further comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TR1, TR2; using a gate over the thin insulating layer a pole insulator mask, wherein the gate insulator mask covers the trench TR2 but does not cover the trench; from the semiconductor substrate, the second mask t is not covered by the trench TR1 a portion of the first gate insulator; and a second gate insulator in the &quot;Hail trench TR1, wherein the second gate insulator is thinner than the first gate insulator. 7. The method of claim 6, wherein the step e) is performed by implanting a _ sub-amount at a relatively high monthly b, at which the ion can pass through the second gate insulation The material and the first gate insulator are implanted into the semiconductor substrate. 8. The method of claim 7, wherein the implanting of the ions of a certain energy proceeds to step f), the energy enabling the ions to pass through the second gate insulator 'but not through The first pole insulator is implanted into the semiconductor substrate. 9. The method of claim 8 wherein the source layer is formed only in the top of the body layer adjacent the trench TR1. The method of claim 1, wherein the step c) further comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TR1, TR2; preparing a sacrificial material, completely filling the Trench TR1, but only lining in the trenches TR2 of the 100117201 Form No. A0101, page 36 / pp. 1003238382-0 201142929; the sacrificial material is etched back, the sacrificial material on the trench TR2 is removed, but the The sacrificial material in the trench TR1; preparing a gate insulating layer in the trench TR2; and removing the sacrificial material in the trench TR1, the gate insulator being prepared in the trench TR1, 11 . 12 . 13 . 14 . 15 16 . 17 . wherein the gate insulating layer thickness T2 in the trench TR2 is greater than the gate insulating layer thickness T1 in the trench TR1. The method of claim 10, wherein the source layer is formed in the top of the entire semiconductor. The method of claim 6, wherein no more than four masks are used to complete steps a) through j). The method of claim 10, wherein no more than three masks are used to complete steps a) through j). The method of claim 1, wherein: b) further comprising preparing the trench T3 having a width W3, wherein W3 is greater than W2, wherein the trench TR3 surrounds the trench TR1 and the gate is slippery The cutoff trench of the trench TR2; wherein the method further comprises: filling the trench TR3 with a dielectric, wherein the width W3 is sufficient to carry the latching voltage. The method of claim 14, wherein only one of the masks is required from step a) to step j). The method of claim 1, wherein the step b) further comprises preparing a heavily doped channel termination region under the trench TR2. A semiconductor device comprising: 100117201 Form No. A0101 Page 37/55 Page 1003238382-0 201142929 A plurality of gate electrodes over a gate insulating layer are formed in an active trench on a semiconductor substrate a first gate runner formed in the semiconductor substrate and electrically connected to the gate electrodes, wherein the first gate runner abuts and surrounds the a source region, connected to a second gate runner on the first gate runner for connecting a gate metal; and a trench in the first gate runner and the second gate runner The respective thickness T2 of the insulating layer is greater than the thickness T1 of the gate insulating layer in the active trench, wherein the thickness T2 is sufficient to carry a latching voltage. 18. The semiconductor device of claim 17, further comprising: a cutoff structure surrounding the first gate runner and the second gate runner and the active region, wherein the cutoff structure comprises The semiconductor substrate is filled with a conductive material in the trench of the insulator, wherein the cutoff structure is shorted to a source or a body layer of the semiconductor substrate near the edge of the wafer to form a channel end point of the component. 19. The semiconductor device of claim 17, further comprising: a dielectric filled trench surrounding the first gate runner and the second gate runner and the active region. 20. The semiconductor device of claim 19, further comprising a heavily doped channel termination region under the dielectric filled trench. The semiconductor device of claim 17, wherein the semiconductor substrate comprises a body layer of the active region and a cutoff region. 22. The semiconductor device of claim 21, wherein the semiconductor substrate comprises a source region. The semiconductor element of claim 22, wherein the source region is located only in the active region. The semiconductor device of claim 22, wherein the source region is located only in the active region. The semiconductor device of claim 17, wherein the first gate runner comprises a channel termination region formed under the trench. The semiconductor device of claim 17, wherein the semiconductor substrate further comprises the semiconductor substrate having a heavily doped underlayer and a heavily heavily doped top layer, wherein the first gate runner trench is sufficient Deep, able to reach the heavily doped underlayer. The semiconductor device according to claim 18, wherein the insulator in the trench filled with the insulator described in the cutoff structure is sufficiently thick to carry the latch voltage. ❹ 100117201 Form No. A0101 Page 39 of 55 1003238382-0