CN114284149B - Preparation method of shielded gate trench field effect transistor - Google Patents
Preparation method of shielded gate trench field effect transistor Download PDFInfo
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- CN114284149B CN114284149B CN202111582066.2A CN202111582066A CN114284149B CN 114284149 B CN114284149 B CN 114284149B CN 202111582066 A CN202111582066 A CN 202111582066A CN 114284149 B CN114284149 B CN 114284149B
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Abstract
The invention provides a preparation method of a shielded gate trench field effect transistor, which comprises the steps of forming an intermediate oxide layer and a gate oxide layer in steps, so that the intermediate oxide layer with better appearance and quality can be formed, and the thickness of the intermediate oxide layer can be controlled according to the requirement, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, the gate-source capacitance and the gate-drain capacitance of an SGT-MOSFET device can be modulated, and the SGT-MOSFET device can be adapted to different application scenes; in addition, the intermediate oxide layer with better appearance and quality and controllable thickness can also improve the electric performance of the gate-source leakage of the SGT-MOSFET device; therefore, the invention can optimize the morphology of the intermediate oxide layer, greatly improve the quality of the intermediate oxide layer, and the thickness of the intermediate oxide layer is controllable so as to improve the electrical performance of the SGT-MOSFET device.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and relates to a preparation method of a shielded gate trench field effect transistor.
Background
The shielded gate trench field effect transistor (Shielding Gate Trench MOSFET, SGT-MOSFET) is an advanced power MOSFET device, and by introducing a shielded gate electrode, the overlapping area of the gate and the drain of the device is reduced, so that the gate-drain capacitance is reduced, the switching speed of the device is improved, the dynamic loss of the device is reduced, and the use efficiency of the system is improved.
In prior art SGT-MOSFET devices, the gate includes an upper polysilicon gate electrode and a lower polysilicon shield gate electrode, and the lower polysilicon shield gate electrode is shorted to the source. In order to avoid the short circuit between the polysilicon shielding gate electrode and the upper polysilicon gate electrode, an intermediate oxide layer is arranged between the polysilicon shielding gate electrode and the upper polysilicon gate electrode, so that the insulation between the upper polysilicon gate electrode and the lower polysilicon shielding gate electrode is ensured, and the quality of the intermediate oxide layer can influence the performance of the SGT-MOSFET device to a certain extent.
At present, regarding the preparation of an intermediate oxide layer in an SGT-MOSFET device, the problems that the process is difficult to control, the quality of the intermediate oxide layer is unstable, and the thickness of the intermediate oxide layer is limited by the thickness of a gate oxide layer still exist, so that the gate-source leakage current (I GSS ) Is a function of the electrical properties of the battery.
Therefore, it is necessary to provide a method for manufacturing a shielded gate trench field effect transistor.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a shielded gate trench field effect transistor, which is used for solving the problem that it is difficult to manufacture a gate intermediate oxide layer with high quality and controllable thickness for SGT-MOSFET devices in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a shielded gate trench field effect transistor, comprising the steps of:
providing a substrate with an epitaxial layer on the surface;
forming a hard mask structure on the epitaxial layer, wherein the hard mask structure comprises a silicon dioxide bottom layer, a silicon nitride layer and a silicon dioxide top layer which are sequentially overlapped from bottom to top;
patterning the hard mask structure and etching the epitaxial layer to form a trench;
forming a field oxide layer on the side wall of the groove;
forming a polysilicon layer filling the trench;
carrying out planarization treatment to expose the surface of the silicon nitride layer;
removing part of the field oxide layer on the side wall of the groove from top to bottom in the cell area, so that the top surface of the field oxide layer is lower than the surface of the polysilicon layer, and forming a gap between the polysilicon layer and the side wall of the groove;
forming a silicon dioxide protective layer, wherein the silicon dioxide protective layer covers the exposed side wall of the groove and the exposed polysilicon layer;
forming a silicon nitride cover layer, wherein the silicon nitride cover layer fills the gap;
etching the silicon nitride covering layer to expose the polysilicon layer;
removing part of the polysilicon layer in the cell area to form a polysilicon shielding gate electrode at the bottom of the groove;
forming an intermediate oxide layer, wherein the intermediate oxide layer covers the polysilicon shielding gate electrode, and the interface between the polysilicon shielding gate electrode and the intermediate oxide layer is lower than the interface between the field oxide layer and the silicon nitride cover layer;
removing the silicon nitride cover layer;
forming a gate oxide layer, wherein the gate oxide layer covers the exposed side wall of the groove;
and forming a polysilicon gate electrode in the groove.
Optionally, when removing a portion of the polysilicon layer located in the cell region, a top surface of the polysilicon shielding gate electrode is formed lower than an interface between the silicon nitride cover layer and the field oxide layer.
Optionally, when removing a part of the polysilicon layer located in the cell area, the polysilicon shielding gate electrode, the silicon nitride cover layer and the surface of the field oxide layer are formed on the same horizontal plane; or when removing part of the polysilicon layer in the cell area, forming the top surface of the polysilicon shielding gate electrode higher than the interface between the silicon nitride covering layer and the field oxide layer.
Optionally, the method for forming the intermediate oxide layer includes a thermal oxidation method, and the process parameters of the thermal oxidation method are controlled so that the interface between the polysilicon shielding gate electrode and the intermediate oxide layer is lower than the interface between the field oxide layer and the silicon nitride cover layer.
Optionally, the thickness of the intermediate oxide layer is formed to be greater than the thickness of the gate oxide layer.
Optionally, the intermediate oxide layer is formed to a thickness of
Optionally, the top surface of the field oxide layer is below the surface of the polysilicon layer by a depth ranging from 0.5 μm to 2.0 μm.
Optionally, the bottom surface of the polysilicon gate electrode is formed to be a horizontal plane.
Optionally, the method further comprises the following steps:
performing ion implantation to form a body region and a source region in the epitaxial layer respectively;
forming a silicon dioxide insulating layer, wherein the silicon dioxide insulating layer covers the polysilicon gate electrode;
forming an interlayer dielectric layer;
etching the contact hole to form a metal layer which is respectively contacted with the polycrystalline silicon layers of the source region and the terminal region in the cellular region;
forming a passivation layer covering the metal layer, and patterning the passivation layer to form a pad window;
thinning the substrate;
and forming a drain electrode on the surface of the thinned substrate.
Optionally, the shielded gate trench field effect transistor comprises a P-type shielded gate trench field effect transistor or an N-type shielded gate trench field effect transistor.
As described above, the preparation method of the shielded gate trench field effect transistor of the present invention forms the intermediate oxide layer and the gate oxide layer step by step, so that the intermediate oxide layer with good morphology and quality can be formed, and the thickness of the intermediate oxide layer can be controlled as required, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, and thus the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) of the SGT-MOSFET device can be modulated, so that the SGT-MOSFET device can adapt to different application scenarios; in addition, the intermediate oxide layer with better appearance and quality and controllable thickness can also improve the gate-source leakage (I) of the SGT-MOSFET device GSS ) Is a metal alloy, is an electrical property of (a) a metal alloy; therefore, the invention can optimize the morphology of the intermediate oxide layer, greatly improve the quality of the intermediate oxide layer, and the thickness of the intermediate oxide layer is controllable so as to improve the electrical performance of the SGT-MOSFET device.
Drawings
Fig. 1 is a schematic diagram of a manufacturing process flow of a shielded gate trench field effect transistor in an embodiment.
Fig. 2 shows a schematic structure of a substrate having an epitaxial layer in an embodiment.
Fig. 3 is a schematic structural diagram of the embodiment after forming the trench.
Fig. 4 is a schematic structural diagram of a field oxide layer formed on a sidewall of a trench in an embodiment.
Fig. 5 is a schematic diagram of a structure after forming a polysilicon layer filling the trench in the embodiment.
Fig. 6 is a schematic structural diagram of the embodiment after planarization treatment.
Fig. 7 is a schematic structural diagram of an embodiment after removing a portion of the field oxide layer to form a void in the cellular region.
Fig. 8 is a schematic structural diagram of the silicon dioxide protective layer formed in the embodiment.
Fig. 9 is a schematic diagram of a structure after forming a silicon nitride cap layer in an embodiment.
Fig. 10 is a schematic diagram of a structure after etching the silicon nitride cap layer to expose the polysilicon layer in an embodiment.
Fig. 11a to 11c are schematic views showing three different structures after removing a portion of the polysilicon layer in the cell region to form a polysilicon shield gate electrode in the embodiment.
Fig. 12 is a schematic structural diagram of an embodiment after forming an intermediate oxide layer.
Fig. 13 is a schematic diagram of a structure after removing the silicon nitride cap layer in an embodiment.
Fig. 14 is a schematic diagram showing a structure after forming a gate oxide layer in the embodiment.
Fig. 15 is a schematic diagram of a structure after forming a polysilicon gate electrode in an embodiment.
Fig. 16 is a schematic structural view of an embodiment after ion implantation to form a body region.
Fig. 17 is a schematic diagram of a structure after ion implantation to form a source region in the embodiment.
Fig. 18 is a schematic structural diagram of a silicon dioxide insulating layer and an interlayer dielectric layer formed in the embodiment.
Fig. 19 is a schematic view showing a structure after forming a contact hole in the embodiment.
Fig. 20 is a schematic structural diagram of the embodiment after forming a metal layer.
Fig. 21 is a schematic structural view of a passivation layer having a pad window in an embodiment.
Description of element reference numerals
100. Substrate and method for manufacturing the same
200. Epitaxial layer
301. Bottom layer of silicon dioxide
302. Silicon nitride layer
303. Top layer of silicon dioxide
400. Groove(s)
500. Field oxide layer
600. Polysilicon layer
601. Polysilicon shielded gate electrode
602. Polysilicon gate electrode
700. Silicon dioxide protective layer
800. Silicon nitride cap layer
900. Intermediate oxide layer
110. Gate oxide layer
120. Body region
130. Source region
140. Silicon dioxide insulating layer
150. Interlayer dielectric layer
160. Contact hole
171. Barrier layer
172. A first metal layer
173. Second metal layer
180. Passivation layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in FIG. 1, the embodiment provides a method for manufacturing a shielded gate trench field effect transistor, which forms an intermediate oxide layer with better morphology and quality by forming the intermediate oxide layer and the gate oxide layer step by step, andthe thickness of the intermediate oxide layer can be controlled according to the requirement, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, and the size of the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) of the SGT-MOSFET device can be modulated, so that the SGT-MOSFET device can be adapted to different application scenes; in addition, the intermediate oxide layer with better appearance and quality and controllable thickness can also improve the gate-source leakage (I) of the SGT-MOSFET device GSS ) Is a metal alloy, is an electrical property of (a) a metal alloy; therefore, the invention can optimize the morphology of the intermediate oxide layer, greatly improve the quality of the intermediate oxide layer, and the thickness of the intermediate oxide layer is controllable so as to improve the electrical performance of the SGT-MOSFET device.
As an example, the shielded gate trench fet may include a P-type shielded gate trench fet or an N-type shielded gate trench fet, and in this embodiment, the shielded gate trench fet is an N-type shielded gate trench fet, but is not limited thereto, and those skilled in the art may set the shielded gate trench fet as a P-type shielded gate trench fet according to actual needs, which is not limited herein.
Referring to fig. 2 to 21, the technical solution of the present embodiment is further described below with reference to the accompanying drawings.
First, as shown in fig. 2, step S1 is performed to provide a substrate 100 having an epitaxial layer 200 on a surface thereof.
Specifically, the substrate 100 may employ N + A silicon substrate, the epitaxial layer 200 can be N - The thickness, preparation and material of the epitaxial layers 200 and the substrate 100 are not limited herein.
Next, as shown in fig. 2, step S2 is performed to form a hard mask structure on the epitaxial layer 200, where the hard mask structure includes a silicon dioxide bottom layer 301, a silicon nitride layer 302 and a silicon dioxide top layer 303 stacked in sequence from bottom to top.
Specifically, a thin silicon dioxide film with a certain thickness may be grown on the surface of the epitaxial layer 200 as the silicon dioxide bottom layer 301, then silicon nitride with a certain thickness is deposited on the silicon dioxide bottom layer 301 as the silicon nitride layer 302, and finally silicon dioxide is deposited on the silicon nitride layer 302 as the silicon dioxide top layer 303, so as to form a silicon dioxide-silicon nitride-silicon dioxide hard mask structure stacked sequentially from bottom to top, so as to facilitate the subsequent process preparation. The specific fabrication processes and thicknesses of the silicon dioxide bottom layer 301, the silicon nitride layer 302, and the silicon dioxide top layer 303 are not excessively limited herein.
Next, as shown in fig. 3, step S3 is performed to pattern the hard mask structure and etch the epitaxial layer 200 to form a trench 400.
Specifically, by using the silicon dioxide-silicon nitride-silicon dioxide as a hard mask layer, the morphology of the trench region to be prepared can be defined by photolithography, so that the trench 400 can be etched as desired. The distribution, size and morphology of the trenches 400 are not overly limited herein.
Next, as shown in fig. 4, step S4 is performed to form a field oxide layer 500 on the sidewall of the trench 400.
Specifically, after the trench 400 is etched, a layer of silicon dioxide having a certain thickness may be formed by chemical vapor deposition or other methods to prepare the field oxide 500. Regarding the thickness of the field oxide layer 500, it may be set as needed, and is not excessively limited here.
Next, as shown in fig. 5, step S5 is performed to form a polysilicon layer 600 filling the trench 400. Regarding the method for forming the polysilicon layer 600, the thickness may be set as desired, and is not excessively limited herein.
Next, as shown in fig. 6, step S6 is performed to perform a planarization process, so as to expose the surface of the silicon nitride layer 302.
Specifically, the polysilicon layer 600 may be planarized to expose the silicon oxide top layer 303, and then the polysilicon layer 600 in the trench 400 is etched back, and then planarized until the surface of the silicon nitride layer 302 is exposed. Wherein the planarization process may include mechanical polishing or CMP, without undue limitation.
Next, as shown in fig. 7, step S7 is performed, in the cellular region, a portion of the field oxide layer 500 located on the sidewall of the trench 400 is removed from top to bottom, such that the top surface of the field oxide layer 500 is lower than the surface of the polysilicon layer 600, and a gap is formed between the polysilicon layer 600 and the sidewall of the trench 400.
As an example, the top surface of the field oxide layer 500 may have a depth ranging from 0.5 μm to 2.0 μm, such as any of 0.5 μm1 μm, 1.2 μm, 1.5 μm, 2.0 μm, etc., below the surface of the polysilicon layer 600 to provide room for subsequent processes.
Next, as shown in fig. 8, step S8 is performed to form a silicon dioxide protection layer 700, where the silicon dioxide protection layer 700 covers the exposed sidewalls of the trench 400 and the exposed polysilicon layer 600. To protect the polysilicon layer 600 and the trench 400 from the subsequent process by the silicon oxide protection layer 700, the thickness of the silicon oxide protection layer 700 is not excessively limited here.
Next, as shown in fig. 9, step S9 is performed to form a silicon nitride cap layer 800, and the silicon nitride cap layer 800 fills the void. The method of preparing the silicon nitride cap layer 800 and the thickness thereof are not excessively limited herein.
Next, as shown in fig. 10, step S10 is performed to etch the silicon nitride cap layer 800, exposing the polysilicon layer 600.
Specifically, since the surface of the polysilicon layer 600 has the silicon oxide protective layer 700, the silicon oxide protective layer 700 may be used as an etching stop layer to protect the polysilicon layer 600 when the silicon nitride cap layer 800 is removed. The method of etching the silicon nitride cap layer 800 is not limited herein.
Next, step S11 is performed to remove a portion of the polysilicon layer 600 located in the cellular region, so as to form a polysilicon shielding gate electrode 601 located at the bottom of the trench 400.
As an example, as shown in fig. 11a, the top surface of the polysilicon shielding gate electrode 601 formed when the polysilicon layer 600 located in the cell region is removed may be lower than the interface between the silicon nitride capping layer 800 and the field oxide layer 500, but is not limited thereto, and as shown in fig. 11b, the surfaces of the polysilicon shielding gate electrode 601, the silicon nitride capping layer 800 and the field oxide layer 500 formed when the polysilicon layer 600 located in the cell region is removed may be at the same level; or as shown in fig. 11c, when the polysilicon layer 600 in the cell region is removed, the top surface of the polysilicon shielding gate electrode 601 may be formed higher than the interface between the silicon nitride cap layer 800 and the field oxide layer 500.
Specifically, when the top surface of the polysilicon shielding gate electrode 601 is lower than the interface between the silicon nitride capping layer 800 and the field oxide layer 500 during etching the polysilicon layer 600 located in the cell region, the interface between the subsequently formed intermediate oxide layer 900 and the polysilicon shielding gate electrode 601 is ensured to be lower than the interface between the field oxide layer 500 and the silicon nitride capping layer 800; when the top surface of the polysilicon shield gate electrode 601 is equal to the interface between the silicon nitride capping layer 800 and the field oxide layer 500, the intermediate oxide layer 900 may be formed by a thermal oxidation method, so that the interface between the intermediate oxide layer 900 and the polysilicon shield gate electrode 601 may be ensured to be lower than the interface between the field oxide layer 500 and the silicon nitride capping layer 800; when the top surface of the polysilicon shielding gate electrode 601 is higher than the interface between the silicon nitride cover layer 800 and the field oxide layer 500, the process parameters of the thermal oxidation method can be controlled so that the interface between the intermediate oxide layer 900 and the polysilicon shielding gate electrode 601 is lower than the interface between the field oxide layer 500 and the silicon nitride cover layer 800. Thus, a thicker intermediate oxide layer 900 can be formed between the polysilicon gate electrode 602 and the polysilicon shielding gate electrode 601, so as to optimize the morphology of the intermediate oxide layer 900, greatly improve the quality of the intermediate oxide layer 900, and the thickness of the intermediate oxide layer 900 is controllable, so as to improve the electrical performance of the SGT-MOSFET device.
Next, as shown in fig. 12, step S12 is performed, where the intermediate oxide layer 900 is formed, the intermediate oxide layer 900 covers the polysilicon shielding gate electrode 601, and the interface between the polysilicon shielding gate electrode 601 and the intermediate oxide layer 900 is lower than the interface between the field oxide layer 500 and the silicon nitride cover layer 800.
As an example, the thickness of the intermediate oxide layer 900 may be formed as follows
Specifically, the thickness of the intermediate oxide layer 900 may be controlled by controlling the process parameters of thermal oxidation, and preferably the thickness of the intermediate oxide layer 900 is
For example->
Is->
And the like, without undue limitation herein.
Next, as shown in fig. 13, step S13 is performed to remove the silicon nitride cap layer 800.
Next, as shown in fig. 14, step S14 is performed, and a gate oxide layer 110 is formed, where the gate oxide layer 110 covers the exposed sidewalls of the trench 400.
Specifically, a layer of silicon dioxide may be continuously grown on the exposed upper portion of the trench 400 to form the gate oxide layer 110 with a certain thickness, where the thickness of the intermediate oxide layer 900 formed is greater than the thickness of the gate oxide layer 110, and the gate oxide layer 110 may be prepared by a thermal oxidation method, and the thickness may include, for example
Such as
Is->
And the like, without undue limitation herein.
In this embodiment, the gate oxide layer 110 and the intermediate oxide layer 900 are formed step by step, if they are prepared by one-time thermal oxidation, the process parameters of the furnace tube are required to be higher, if the process parameters of the furnace tube are not controllable enough, a small drift of the process parameters will affect the quality of the prepared intermediate oxide layer, thereby affecting the gate-source leakage current (I GSS ) And the thickness of the intermediate oxide layer is limited by the thickness of the gate oxide. The preparation method of the embodiment can optimize the morphology of the intermediate oxide layer 900, greatly improve the quality of the intermediate oxide layer 900, and the thickness of the intermediate oxide layer 900 is controllable so as to improve the electrical performance of the SGT-MOSFET device.
Next, as shown in fig. 15, step S15 is performed to form a polysilicon gate electrode 602 in the trench 400.
Specifically, the polysilicon gate electrode 602 located on the intermediate oxide layer 900 may be formed by depositing and etching polysilicon, so that the polysilicon shield gate electrode 601, the intermediate oxide layer 900 and the polysilicon gate electrode 602 are formed in the trench 400 from bottom to top.
As an example, the bottom surface of the polysilicon gate electrode 602 is formed as a horizontal surface.
Specifically, by controlling the thickness of the intermediate oxide layer 900 so that the bottom surface of the polysilicon gate electrode 602 is horizontal, a small "sharp angle" shape formed at the edge of the bottom surface of the polysilicon gate electrode 602 can be avoided, so as to reduce the gate-drain overlap area and the gate-drain capacitance (C gd ) To increase the turn-on speed of the shielded gate trench field effect transistor.
Further, referring to fig. 16 to 21, regarding the method for manufacturing the shielded gate trench field effect transistor, the method may further include the following steps:
as shown in fig. 16 and 17, ion implantation is performed to form a body region 120 and a source region 130 in the epi 200, respectively, such as P-type ion implantation is performed to form a P-type body region 120, and then N is performed + To form N typeThe source region 130.
As in fig. 18, a silicon dioxide insulating layer 140 is formed, the silicon dioxide insulating layer 140 covering the polysilicon gate electrode 602, and as in fig. 18, an interlayer dielectric layer 150 is formed, wherein the interlayer dielectric layer 150 may comprise borophosphosilicate glass, but is not limited thereto.
As shown in fig. 19 and 20, etching the contact hole 160 is performed to form metal layers respectively contacting the source region 130 and the polysilicon layer 600 in the cell region, wherein the metal layers may include a barrier layer 171, such as a Ti/TiN barrier layer, a first metal layer 172, such as a W metal layer, on the Ti/TiN barrier layer, and a second metal layer 173, such as an AlCu metal layer, on the first metal layer 172.
As shown in fig. 21, a passivation layer 180 is formed to cover the metal layer, and the passivation layer 180 is patterned to form a pad window for subsequent electrical contact, wherein the passivation layer 180 may be a silicon nitride passivation layer, but is not limited thereto.
Further, the method may further include a step of thinning the substrate 100, and a step of forming a drain on the thinned surface of the substrate 100, and the preparation method, thickness and material of the drain are not limited herein.
In summary, according to the preparation method of the shielded gate trench field effect transistor, the intermediate oxide layer and the gate oxide layer are formed step by step, so that the intermediate oxide layer with better morphology and quality can be formed, and the thickness of the intermediate oxide layer can be controlled as required, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, and the sizes of the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) of the SGT-MOSFET device can be modulated, so that the SGT-MOSFET device can adapt to different application scenes; in addition, the intermediate oxide layer with better appearance and quality and controllable thickness can also improve the gate-source leakage (I) of the SGT-MOSFET device GSS ) Is a metal alloy, is an electrical property of (a) a metal alloy; therefore, the invention can optimize the morphology of the intermediate oxide layer, greatly improve the quality of the intermediate oxide layer, and the thickness of the intermediate oxide layer is controllable so as to improve the electrical performance of the SGT-MOSFET device.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the shielded gate trench field effect transistor is characterized by comprising the following steps of:
providing a substrate with an epitaxial layer on the surface;
forming a hard mask structure on the epitaxial layer, wherein the hard mask structure comprises a silicon dioxide bottom layer, a silicon nitride layer and a silicon dioxide top layer which are sequentially overlapped from bottom to top;
patterning the hard mask structure and etching the epitaxial layer to form a trench;
forming a field oxide layer on the side wall of the groove;
forming a polysilicon layer filling the trench;
carrying out planarization treatment to expose the surface of the silicon nitride layer;
removing part of the field oxide layer on the side wall of the groove from top to bottom in the cell area, so that the top surface of the field oxide layer is lower than the surface of the polysilicon layer, and forming a gap between the polysilicon layer and the side wall of the groove;
forming a silicon dioxide protective layer, wherein the silicon dioxide protective layer covers the exposed side wall of the groove and the exposed polysilicon layer;
forming a silicon nitride cover layer, wherein the silicon nitride cover layer fills the gap;
etching the silicon nitride covering layer to expose the polysilicon layer;
removing part of the polysilicon layer in the cell area to form a polysilicon shielding gate electrode at the bottom of the groove;
forming an intermediate oxide layer, wherein the intermediate oxide layer covers the polysilicon shielding gate electrode, and the interface between the polysilicon shielding gate electrode and the intermediate oxide layer is lower than the interface between the field oxide layer and the silicon nitride cover layer;
removing the silicon nitride cover layer;
forming a gate oxide layer, wherein the gate oxide layer covers the exposed side wall of the groove;
forming a polysilicon gate electrode in the groove;
the intermediate oxide layer and the gate oxide layer are formed step by step, so that the thickness of the intermediate oxide layer is not limited by the thickness of the gate oxide layer.
2. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: and when part of the polysilicon layer in the cell area is removed, the top surface of the formed polysilicon shielding gate electrode is lower than the interface between the silicon nitride covering layer and the field oxide layer.
3. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: when part of the polysilicon layer in the cell area is removed, the formed polysilicon shielding gate electrode, the silicon nitride covering layer and the surface of the field oxide layer are positioned on the same horizontal plane; or when removing part of the polysilicon layer in the cell area, forming the top surface of the polysilicon shielding gate electrode higher than the interface between the silicon nitride covering layer and the field oxide layer.
4. The method for manufacturing the shielded gate trench field effect transistor according to claim 3, wherein: the method for forming the intermediate oxide layer comprises a thermal oxidation method, and the process parameters of the thermal oxidation method are controlled so that the interface between the polycrystalline silicon shielding gate electrode and the intermediate oxide layer is lower than the interface between the field oxide layer and the silicon nitride covering layer.
5. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: the thickness of the intermediate oxide layer is formed to be greater than the thickness of the gate oxide layer.
6. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: the thickness of the intermediate oxide layer is formed to be
7. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: the depth of the top surface of the field oxide layer below the surface of the polysilicon layer is in the range of 0.5 μm to 2.0 μm.
8. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: and the bottom surface of the formed polysilicon gate electrode is a horizontal surface.
9. The method of manufacturing a shielded gate trench field effect transistor of claim 1, further comprising the steps of:
performing ion implantation to form a body region and a source region in the epitaxial layer respectively;
forming a silicon dioxide insulating layer, wherein the silicon dioxide insulating layer covers the polysilicon gate electrode;
forming an interlayer dielectric layer;
etching the contact hole to form a metal layer which is respectively contacted with the polycrystalline silicon layers of the source region and the terminal region in the cellular region;
forming a passivation layer covering the metal layer, and patterning the passivation layer to form a pad window;
thinning the substrate;
and forming a drain electrode on the surface of the thinned substrate.
10. The method for manufacturing the shielded gate trench field effect transistor according to claim 1, wherein: the shielded gate trench field effect transistor comprises a P-type shielded gate trench field effect transistor or an N-type shielded gate trench field effect transistor.
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| CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
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| CN110164967A (en) * | 2018-02-11 | 2019-08-23 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method |
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