CN110164967A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN110164967A CN110164967A CN201810139717.2A CN201810139717A CN110164967A CN 110164967 A CN110164967 A CN 110164967A CN 201810139717 A CN201810139717 A CN 201810139717A CN 110164967 A CN110164967 A CN 110164967A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 208
- 229920005591 polysilicon Polymers 0.000 claims abstract description 191
- 238000000034 method Methods 0.000 claims abstract description 97
- 238000002955 isolation Methods 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 172
- 230000000994 depressogenic effect Effects 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 239000011800 void material Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910001029 Hf alloy Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- PAULRCPWJCOFGG-UHFFFAOYSA-N [Hf+4].[Si+4].[O-2].[O-2].[Ti+4] Chemical compound [Hf+4].[Si+4].[O-2].[O-2].[Ti+4] PAULRCPWJCOFGG-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- MJGARAGQACZIPN-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O--].[O--].[Al+3].[Hf+4] MJGARAGQACZIPN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of manufacturing method of semiconductor device, comprising: provides a substrate；Multiple grooves are formed in substrate；A layer of isolation oxide is formed in groove and above substrate；It deposits in layer of isolation oxide of the mask polysilicon in groove and on substrate；One first etching technics is carried out to remove a first part of mask polysilicon, and exposes a part of surface of the isolating oxide layer in groove；One first removal technique is carried out to remove a first part of layer of isolation oxide；One second etching technics is carried out to remove a second part of mask polysilicon, and exposes another part surface of the isolating oxide layer in groove；One second removal technique is carried out to remove a second part of layer of isolation oxide；And a polysilicon interlevel oxide layer (inter poly oxide layer) is formed on remaining mask polysilicon and remaining layer of isolation oxide, wherein polysilicon interlevel oxide layer has a concave upper surface.The present invention also provides a kind of semiconductor device.
Description
Technical field
The present invention can reduce gate-to-drain electricity about a kind of semiconductor device and its manufacturing method, especially in regard to one kind
Hold the semiconductor device and its manufacturing method of (Cgd) and suppressor grid leakage current.
Background technique
Semiconductor integrated circuit (IC) industry is after the fast-developing stage.Integrated circuit material and design are technically
Progress produced the integrated circuit in many generations.The integrated circuit of every generation has smaller and more multiple than the integrated circuit of former generation
Miscellaneous circuit.
Split type gate trench Metal Oxide Semiconductor Field Effect Transistor (Metal-Oxide-Semiconductor
Field-Effect Transistor；It MOSFET, can be by applying sss mask gate trench (shield gate) in element
trench；SGT structure) reduces gate drain capacitor (Cgd), with the switch speed of lift elements.In mask gate trench
Mask polysilicon is electrically connected with source electrode, and trench-gate polysilicon is made to be electrically insulated with drain electrode.Grid polycrystalline silicon and mask polysilicon
(shield polysilicon) then passes through oxide (inter-poly oxide between therebetween polysilicon layer；IPO) and
Mutually it is electrically insulated.
However, it is continuous miniature with component size, it is brilliant in Split type gate trench metal oxide semiconductor field-effect
In the technique of body tube elements, using backfill oxide as oxide between polysilicon layer (IPO) with insulated gate electrode polysilicon and screening
The technology of cover polysilicon, the depth-to-width ratio (aspect ratio) of groove when due to being limited to backfill oxide, so that controlling polycrystalline
The ability of the thickness of oxide and quality is limited between silicon layer, and element is caused to generate gate-source leakage current (gate to source
Leakage current) higher problem.In addition, mask gate trench (SGT) structure reduces gate drain capacitor (Cgd's)
Ability is also restrained.
Therefore, in this technical field, a kind of Split type gate trench metal oxide semiconductcor field effect of improvement is needed
Answer transistor unit and its manufacturing method.
Summary of the invention
One embodiment of the invention provides a kind of manufacturing method of semiconductor device.The above method includes: to provide a substrate；
Multiple grooves are formed in substrate；A layer of isolation oxide is formed in groove and above substrate；Deposit a mask polysilicon
In the layer of isolation oxide of (shield polysilicon) in groove and on substrate；One first etching technics is carried out to remove
One first part of mask polysilicon, and expose a part of surface of the isolating oxide layer in groove；Carry out one first removal
Technique is to remove a first part of layer of isolation oxide；One second etching technics is carried out to remove the one second of mask polysilicon
Part, and expose another part surface of the isolating oxide layer in groove；One second removal technique is carried out to remove isolation from oxygen
One second part of compound layer；And a polysilicon interlevel oxide layer (inter-poly oxide layer) is formed in remaining
On mask polysilicon and remaining layer of isolation oxide.Wherein, polysilicon interlevel oxide layer has a concave upper surface.
Another embodiment of the present invention provides a kind of semiconductor device.Above-mentioned semiconductor device includes: a substrate, including more
A groove；One isolating oxide layer is located in groove；One mask polysilicon in groove and is isolated oxide layer and surrounds；And
One polysilicon interlevel oxide layer is located on isolating oxide layer and mask polysilicon.Wherein, polysilicon interlevel oxide layer is recessed with one
Shape top surface.
The beneficial effects of the present invention are manufacturing method for semiconductor device of the invention is by carrying out two to mask oxide
The etching technics in stage simultaneously carries out two stage removal technique to layer of isolation oxide, to slow down in technique in the past in trenched side-wall
The sinking degree of generated isolation oxide between mask oxide side walls, so that the interlayer polycrystalline that subsequent technique is inserted
Si oxide can be deposited on mask polysilicon and isolating oxide layer well without generating hole (void).Also, isolation from oxygen
Change layer generated sinking degree between trenched side-wall and mask polysilicon sidewall to be slowed down, and inserted in subsequent technique
Polysilicon interlevel oxide layer (IPO) does not have hole (void).It is provided between grid polycrystalline silicon and mask polysilicon good
Be electrically insulated effect.Also, due to not having hole, polysilicon interlevel oxide layer (IPO) can provide good suppressor grid extremely
The isolation effect of source leakage currents, and then improve the performance of semiconductor device.In addition, polysilicon interlevel oxide layer (IPO) is recessed
The radian being bent upwards is being presented close to the part of trenched side-wall for shape top surface, equivalent to increase oxide layer in grid polycrystalline silicon
Thickness between drain electrode, therefore the gate drain capacitor (Cgd) of semiconductor device can be reduced.
For above and other purpose, feature and advantage of the invention can be clearer and more comprehensible, preferably implementation is cited below particularly out
Example, and cooperate institute's accompanying drawings, it is described in detail below:
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only
Some embodiments of the present invention, for those of ordinary skill in the art, without any creative labor, also
Other drawings may be obtained according to these drawings without any creative labor.
Fig. 1~Figure 10 is to be shown according to the section that some embodiments of the invention are shown in each stage in the technique of semiconductor device
It is intended to.
Drawing reference numeral:
10~device；
100~substrate；
102~groove；
104,104 '~isolating oxide layer
104 "~remaining isolating oxide layer；
104a, 104b~surface portion；
The top surface portion of 104S-1~first
The top surface portion of 104S-2~second；
106,106 '~mask polysilicon；
106 "~remaining mask polysilicon；
106 ' S, 106 " S~side wall；
Oxide between 108~polysilicon layer；
108 '~polysilicon interlevel oxide layer；
106S, 108S~top surface；
110~grid oxic horizon；
112~grid polycrystalline silicon；
D1, D2~depth；
H~difference in height；
P1, P2~profile；
T1, T2, T3~thickness；
W1, W2~depressed section.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
Embodiment in invention, relevant technical staff in the field's every other reality obtained without making creative work
Example is applied, the range of protection of the invention is belonged to.
Description of the invention provides different embodiments to illustrate the technical characteristic of different embodiments of the present invention.The present invention
In specific element and configuration be to put it more simply, but the present invention be not limited with these embodiments.For example, in second element
The upper description for forming first element may include the embodiment that first element is directly contacted with second element, also include with additional
Element is formed between first element and second element, makes first element and second element embodiment not in direct contact.
In addition, for simplicity, the present invention is indicated in different examples with duplicate component symbol and/or letter, but do not represent described
There is specific relationship between each embodiment and/or structure.It is emphasized that each element is not according to industrial standard operation
It must be drawn according to ratio.In fact, may arbitrarily zoom in or out the size of each element for clear discussion.
Unless interior text clearly indicates, singular " one " as used herein and "the" also include most forms.It can be into
One step is appreciated that, when using the terms such as " comprising " in specification, be in order to point out the feature, step, operation, element and/
Or the presence of component, but it is not excluded for one or more additional other features, step, operation, element, component and/or said combination
In the presence of.
Signified " a kind of embodiment " or " embodiment " means the spy being described in embodiment in entire disclosure
Determine feature, structure or characteristic to include at least in one embodiment.Phrase that therefore, entire disclosure different places occur "
In a kind of embodiment " or " in one embodiment " signified embodiment being not necessarily to the same.In addition, specific feature, structure or
Characteristic can be combined in one or more of embodiment by any suitable method.
Some embodiments of the present invention are described below.Fig. 1~Figure 10 is to be shown in partly to lead according to some embodiments of the invention
The diagrammatic cross-section in each stage in the technique of body device 10.It can be before the stage described in Fig. 1~Figure 10, period and/or later
Additional operation is provided.In various embodiments, move, delete or replace some operations above-mentioned.It can be added additional
Feature is to semiconductor device.In various embodiments, move, delete or replace some features as described below.
The embodiment of the present invention provides a kind of semiconductor device and its manufacturing method.In some embodiment of the invention, above-mentioned
Semiconductor device is Split type gate trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) element.Needle of the present invention
Technique is improved, two stage etching technics is carried out to mask polysilicon (shield polysilicon) and to isolation from oxygen
Compound layer carries out two stage removal technique, is produced between trenched side-wall and mask polysilicon sidewall with slowing down in technique in the past
The sinking degree of raw isolation oxide, so that oxide (inter-poly between the polysilicon layer that subsequent technique is inserted
Oxide (or not generating generally) hole (void)) is not generated, and then promotes the thickness and quality to polysilicon interlevel oxide layer
Control ability, achieve the purpose that suppressor grid leakage current.
One embodiment of the invention provides a kind of manufacturing method of semiconductor device.As shown in Figure 1, according to some implementations
Example, provides a substrate 100.In some embodiments, substrate 100 can be bulk semiconductor substrate, seem semiconductor wafer.Example
Such as, substrate 100 is a Silicon Wafer.Substrate 100 may include silicon or other elements semiconductor material, seem germanium.In some embodiments
In, substrate 100 may include a sapphire substrate, a silicon substrate or a silicon carbide substrate.In some embodiments, substrate 100 can
Including one or more layers structure composed by semiconductor material, insulating material, conductor material or aforementioned combinatorial.For example, substrate
100 can be as being selected from least one of group composed by Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP
Semiconductor material is formed.In another embodiment, substrate 100 may also comprise silicon (silicon on an insulating layer
insulator；SOI).It is implanted into using oxygen and (SIMOX) technique, wafer joint technology, other applicable modes or preceding is isolated
The combination stated forms SOI substrate.In another embodiment, substrate 100 can also be made of multilayer material, such as: Si/SiGe, Si/
SiC.In another embodiment, substrate 100 may include insulating material, such as: organic insulator, inorganic insulator or aforementioned
Combine one or more layers structure formed.In another embodiment, substrate 100 may also comprise conductor material, such as: polysilicon,
One or more layers structure that metal, alloy or aforementioned combinatorial are formed.
As shown in Figure 1, forming multiple grooves (or groove) 102 in substrate 100 according to some embodiments.In some realities
It applies in example, groove 102 can be formed using for example one or more lithography and etching techniques.It should be understood that ditch shown in FIG. 1
102 size of slot, shape and position are only illustration, rather than to limit the present invention.
Then, as shown in Fig. 2, according to some embodiments, a layer of isolation oxide 104 is formed in groove 102 and substrate
On 100.In some embodiments, using such as thermal oxidation method or other suitable depositing operations, it is conformally formed isolation
Oxide skin(coating) 104 is on the side wall of groove 102 and bottom and on the top surface of substrate 100.It can be according to the member of semiconductor device
Part size and design need and adjust the thickness T1 of layer of isolation oxide 104.In some embodiments, layer of isolation oxide 104
In the thickness T1 on the side wall of groove 102 and bottom and on the top surface of substrate 100 may be, for example, 70nm to 150nm.
As shown in Fig. 2, depositing a mask polysilicon 106 in groove 102 and on substrate 100 according to some embodiments
In layer of isolation oxide 104.In some embodiments, using such as chemical vapor deposition (chemical vapor
deposition；CVD) or other suitable polysilicon deposition techniques, mask polysilicon 106 is filled in groove 102 and is sunk
Product is in the layer of isolation oxide 104 on substrate 100.In some embodiments, mask polysilicon 106 can be by undoped polycrystalline
Silicon or polysilicon through adulterating in situ are formed.
As shown in figure 3, carrying out one first etching technics according to some embodiments to remove the first of mask polysilicon 106
Part, and expose a part of surface 104a of the isolating oxide layer 104 in groove 102.In some embodiments, the first etching
Technique may include for example being etched back to technique.In some embodiments, by removing the first part of mask polysilicon 106, can make
Mask polysilicon 106 is recessed in groove 102, until reaching required depth.For example, as shown in figure 3, in an embodiment
In, the top surface of mask polysilicon 106 ' can be lower than the top surface of substrate 100.Surface 104a is formed at the side wall of groove 102
On isolating oxide layer 104 a part of surface, via remove mask polysilicon 106 first part and be exposed.?
In some embodiments, the mask polysilicon 106 ' after removed first part has a depth D1 in groove 102, such as Fig. 3 institute
Show.It should be noted that in some embodiments, the depth D1 and the mask in non-final semiconductor device of mask polysilicon 106 '
Depth required for polysilicon.In some embodiments, the depth D1 of mask polysilicon 106 ' is greater than in final semiconductor device
Mask polysilicon required for depth.
In some embodiments, above-mentioned first etching technics can carried out to remove the first part of mask polysilicon 106
Before, first carrying out a chemical planarization picture to mask polysilicon 106 is chemical-mechanical planarization grinding (CMP) technique, directly
To exposing layer of isolation oxide 104.Alternatively, in some embodiments, above-mentioned chemical-mechanical planarization grinding (CMP) can be omitted
The step of technique, directly carries out above-mentioned first etching technics, so that mask polysilicon 106 is recessed in groove 102, until reaching
Required depth.
As shown in figure 4, according to some embodiments, one first removal technique is carried out to remove the of layer of isolation oxide 104
A part.In some embodiments, the first removal technique may include such as wet etching process, oxide etch technique or other conjunctions
Suitable technique.In some embodiments, after first removes technique, the layer of isolation oxide 104 ' of removed first part
The part (part corresponding to Fig. 3 with surface 104a) for being exposed to groove 102 has relatively thin thickness T2, as shown in Figure 4.?
In some embodiments, after first removes technique, the layer of isolation oxide 104 ' on substrate 100 also has relatively thin thickness
Spend T2.In some embodiments, thickness T2 is less than thickness T1.In some embodiments, removed after first removes technique
The layer of isolation oxide 104 ' of first part is forming a depressed section W1 adjacent to the part of mask polysilicon 106 ', and exposes to the open air
106 ' the S of a part of side wall of mask polysilicon 106 ' out.As shown in figure 4, in some embodiments, the depressed section W1 is hiding
Extend between the side wall of cover polysilicon 106 ' and the layer of isolation oxide 104 ' with thickness T2.
Although the depressed section W1 drawn in Fig. 4 has a flat upper surface, it will be appreciated, however, that institute in Fig. 4
The schema of drafting is merely illustrative, and in some embodiments, the upper surface of the depressed section W1 of layer of isolation oxide 104 ' can have
One spill radian.
As shown in figure 5, carrying out one second etching technics according to some embodiments to remove the second of mask polysilicon 106
Part, and expose another part surface 104b of the isolating oxide layer 104 in groove 102.In some embodiments, the first quarter
Etching technique may include for example being etched back to technique.It in some embodiments, can by removing the second part of mask polysilicon 106
It is recessed to mask polysilicon 106 further in groove 102, until reaching required depth.For example, as shown in figure 5, one
In embodiment, the top surface of mask polysilicon 106 " can be lower than the upper surface of the depressed section W1 of layer of isolation oxide 104 '.Table
Face 104b is formed at another part surface of the isolating oxide layer 104 on the side wall of groove 102, via removal mask polysilicon
106 second part and be exposed.In some embodiments, the mask polysilicon 106 " after removed second part is in ditch
There is a depth D2, as shown in Figure 5 in slot 102.It should be noted that in some embodiments, the depth of mask polysilicon 106 "
D2 is depth required for the mask polysilicon in final semiconductor device.In some embodiments, depth D2 is less than depth
D1。
As shown in figure 5, since the part that isolating oxide layer 104 is exposed in groove 102 through the second etching technics (has
Have the part of surface 104b) it is not removed during the first removal technique by the protection of mask polysilicon 106 ', therefore,
After second etching technics, isolating oxide layer 104 " still has thickness identical with thickness T1 with the part of surface 104b.
That is, since the embodiment of the present invention carries out two stage etching technics (the first etching technics and to mask oxide 106
Two etching technics), during carrying out first to isolation oxide 104 and removing technique, a part of isolating oxide layer 104 can be by
The protection of mask oxide 106 ' after to the first etching technics with depth D1, so remaining the thickness T1 of script.Therefore,
After the second etching technics, the isolating oxide layer 104 ' in groove 102 is exposed to different thickness (T1 and T2), and with
Such state (as shown in Figure 5) then carries out subsequent second and removes technique.
As shown in fig. 6, according to some embodiments, one second removal technique is carried out to remove the of layer of isolation oxide 104
Two parts.In some embodiments, the second removal technique may include such as wet etching process, oxide etch technique or other conjunctions
Suitable technique.In some embodiments, it is identical can to remove technique with first for the second removal technique.In some embodiments, second
Removing technique can be different from the first removal technique.It can be hidden according in the component size of semiconductor device, two stage etching technics
The difference of the process conditions such as the depth of cover polysilicon, first removes technique and second removes technique and adjust the used in selection
One removes the process conditions of technique and the second removal technique.It should be noted that technique and the second shifting can be removed by control first
Except technique condition and determine the final top surface profile of layer of isolation oxide, and then influence polycrystalline in final semiconductor device 10
The top surface profile of silicon interlevel oxide layer 108 '.
As shown in fig. 6, in some embodiments, after second removes technique, the isolation oxidation of removed second part
The part for being exposed to groove 102 of nitride layer 104 " (being otherwise referred to as remaining layer of isolation oxide 104 " herein) is (substantially
Part corresponding to Fig. 3 with surface 104a) there is thinner thickness T3.In some embodiments, second remove technique it
Afterwards, the remaining layer of isolation oxide 104 " on substrate 100 also has thinner thickness T3.In some embodiments, thick
It spends T3 and is less than thickness T2.In further embodiments, after second removes technique, layer of isolation oxide 104 ' is being generally corresponding to
It can also be fully removed in Fig. 3 with the part of surface 104a, and the layer of isolation oxide 104 ' being located on substrate 100 can also
Fully it is removed.
As shown in fig. 6, in some embodiments, after second removes technique, the isolation oxidation of removed second part
Nitride layer 104 " is further formed another depressed section W2 in the region of neighbouring mask polysilicon 106 ", and exposes mask polysilicon
106 " 106 " S of a part of side wall.As shown in fig. 6, in some embodiments, the depressed section W2 is in mask polysilicon 106 "
Side wall and with thickness T3 layer of isolation oxide 104 " between extend.
It should be noted that during second removes technique, the isolating oxide layer 104 " that is protected as described in Fig. 5
(part with surface 104b) still has thickness identical with thickness T1, and therefore, second removes technique for this part
Sinking degree caused by isolating oxide layer 104 " can more slow down.As shown in fig. 6, in some embodiments, carrying out second
After removing second part of the technique to remove layer of isolation oxide 104, the top surface of remaining isolating oxide layer 104 " is on the whole
On gently up extend from the side wall of mask polysilicon 106 to the sidewall direction of groove 102.In some embodiments,
The top surface that depressed section W2 has unsmooth (or discontinuous) is formed by after two removal techniques.
As shown in fig. 6, in some embodiments, the top surface of depressed section W2 is formed by after the second removal technique
104S can be made of the first top surface portion 104S-1 and the second top surface portion 104S-2.Although that is drawn in Fig. 6 is recessed
Concave portion divides the first top surface portion 104S-1 and the second top surface portion 104S-2 of W2 to be flat surface, however, it is to be appreciated that
, the schema drawn in Fig. 6 is merely illustrative, in some embodiments, the depressed section W2's of layer of isolation oxide 104 "
First top surface portion 104S-1 and the second top surface portion 104S-2 can be respectively provided with a spill radian.
More particularly, as shown in fig. 6, in some embodiments, removing technique in carry out second to remove isolation oxidation
After the second part of nitride layer 104, remaining isolating oxide layer 104 " first top adjacent with the side wall of mask polysilicon 106 "
Surface portion 104S-1 have a first curvature, and remaining isolating oxide layer 104 " it is adjacent with the side wall of groove 102 second
Top surface portion 104S-2 has a torsion.In some embodiments, first curvature is different from torsion.In some realities
It applies in example, first curvature is greater than torsion.In some embodiments, first curvature may be, for example, 0.06 to 0.1nm-1.One
In a little embodiments, torsion may be, for example, 0.02 to 0.025nm-1。
As shown in fig. 6, in some embodiments, technique is removed in carry out second to remove the of layer of isolation oxide 104
After two parts, remaining isolating oxide layer 104 " is adjacent to the first top surface portion 104S-1 of mask polysilicon 106 " most
The height difference H of the top surface 106S of low spot and remaining mask polysilicon 106 " be smaller than isolating oxide layer 104 as shown in Figure 2 in
The thickness T1 of 100 top of substrate.
It is noted that difference in height lesser in this way comes from the result that the present invention is improved for technique.It crosses
Go in order to remove be located at trenched side-wall on and substrate on isolating oxide layer, previous technique would generally to layer of isolation oxide into
Row over etching, thus isolating oxide layer is caused to form apparent recess between the side wall of mask polysilicon and the side wall of groove,
Make to generate apparent difference in height between isolating oxide layer and the top surface of mask polysilicon.However, due to the embodiment of the present invention pair
Mask polysilicon carries out two stage etching technics and carries out two stage removal technique, isolation oxide to layer of isolation oxide
Generated sinking degree is slowed down between the side wall of mask polysilicon and the side wall of groove, while also reducing isolation oxidation
Difference in height between layer and the top surface of mask polysilicon.Such result to fill in subsequent technique into groove 102
Oxide does not generate (or not generating generally) hole (void) between polysilicon layer.Since oxide can be good between polysilicon layer
Ground deposition, therefore the formation of oxide skin(coating) between polysilicon layer can be preferably controlled, improve the performance of final semiconductor device.
As shown in fig. 6, in some embodiments, removing technique carrying out one second to remove layer of isolation oxide 104
After second part, the first top surface portion 104S-1 and the second top surface portion 104S-2 of remaining isolating oxide layer 104 "
And the top surface 106S of mask polysilicon 106 " constitutes profile P1.In some embodiments, profile P1 generally can be considered that one is recessed
Shape curve.
As shown in fig. 7, according to some embodiments, oxide 108 is deposited between a polysilicon layer in groove 102 and substrate
100 tops.In some embodiments, using such as high density plasma enhanced chemical vapor deposition (high density plasma
chemical vapor deposition；HDPCVD oxide) or between other suitable depositing operation deposit polycrystalline silicon layers
108.As described above, in some embodiments, oxide 108 can fully cover isolating oxide layer 104 and hide between polysilicon layer
Cover polysilicon 106, without generation (or not generating generally) hole (void).Such result is conducive to be promoted for polysilicon
The thickness of interlevel oxidation nitride layer and the control of quality, improve the performance of final semiconductor device, for example, reducing gate-to-drain electricity
Hold (Cgd) and suppressor grid to source leakage currents (gate to source leakage current).
As shown in figure 8, carrying out a third etching technics according to some embodiments to remove oxide 108 between polysilicon layer
A part, and expose a part of the side wall of groove 102.In some embodiments, third etching technics may include for example
Deep dry etch process, wet etching process are etched back to technique, other suitable etching technics or combination above-mentioned.As shown in figure 8,
In some embodiments, oxide 108 between polysilicon layer is etched to target depth using technique is for example etched back to, forms more than one
Crystal silicon interlevel oxide layer 108 ' is on remaining mask polysilicon 106 " and remaining layer of isolation oxide 104 ".For example, such as Fig. 8
Shown, in one embodiment, the top surface 108S of polysilicon interlevel oxide layer 108 ' can be lower than the top surface of substrate 100.One
In a little embodiments, after third etching technics, it can will be located on 102 side wall of groove together and remaining isolation on substrate 100
Oxide skin(coating) 104 " completely removes.In some embodiments, polysilicon interlevel oxide layer 108 ' can be used for making mask polysilicon
106 " are electrically insulated with the grid polycrystalline silicon for being subsequently formed in top.In some embodiments, polysilicon interlevel oxide layer 108 '
Average thickness may be, for example, 90nm to 170nm.
According to some embodiments, Fig. 8 is shown in after the second removal technique described in Fig. 6, layer of isolation oxide 104 '
The part (corresponding roughly to the part that Fig. 3 has surface 104a) for being exposed to groove 102 and the isolation oxidation on substrate 100
The fully removed semiconductor device diagrammatic cross-section of nitride layer 104 '.In other embodiments, as Fig. 8 is also shown in Fig. 6 institute
After second stated removes technique, the part for being exposed to groove 102 of remaining layer of isolation oxide 104 " (corresponds roughly to figure
3 parts with surface 104a) the semiconductor device diagrammatic cross-section (shown in dotted line) with thinner thickness T3.However,
For up to succinct purpose, in hereafter and as described in Fig. 9, Figure 10 omitting dotted portion in description.
It should be noted that as shown in figure 8, the top surface of polysilicon interlevel oxide layer 108 ' is one according to some embodiments
Concave upper surface 108S.Concave upper surface 108S has a profile P2.In some embodiments, profile P2 can be considered as having one
Concave curve, and the radian being bent upwards is being presented close to the part of 102 side wall of groove.As shown in figure 8, in some embodiments
In, the profile P2 of the concave upper surface 108S of polysilicon interlevel oxide layer 108 ' and the first top of remaining isolating oxide layer 104 "
The top surface 106S of surface portion 104S-1, the second top surface portion 104S-2 and remaining mask polysilicon 106 " are constituted
Profile P1 it is roughly the same.That is, in some embodiments, profile P2 and profile P1 are roughly the same, and can be considered have
Roughly the same concave curve.
In some embodiments, the side wall of the concave upper surface 108S of polysilicon interlevel oxide layer 108 ' and groove 102 it
Between angle may be, for example, 110 ° to 120 °.In some embodiments, the concave upper surface of polysilicon interlevel oxide layer 108 '
The curvature of 108S may be, for example, 0.045 to 0.055nm-1.In some embodiments, the curvature of the concave upper surface 108S is
The curvature of profile P2.In some embodiments, the curvature of profile P2 is substantially equal to the curvature of profile P1.In some embodiments,
Angle between the concave upper surface 108S of polysilicon interlevel oxide layer 108 ' and the side wall of groove 102 is bigger or polysilicon layer
Between oxide layer 108 ' concave upper surface 108S curvature it is bigger, the decline of the gate drain capacitor (Cgd) of final semiconductor device
Degree is bigger.
According to an embodiment, the polysilicon interlevel oxide layer 108 ' of semiconductor device 10 provided by the embodiment of the present invention
Angle between concave upper surface 108S and the side wall of groove 102 is the spill top table of 120 °, polysilicon interlevel oxide layer 108 '
In the case that the curvature (i.e. the curvature of profile P2) of face 108S is 120 °, the gate drain capacitor (Cgd) of semiconductor device 10 is
2.5E-9 to 3E-9 coulombs.
It is noted that since the concave upper surface 108S of polysilicon interlevel oxide layer 108 ' is close to 102 side of groove
The radian being bent upwards is presented in the part of wall, equivalent to increase oxide layer (for example, polysilicon interlevel oxide layer 108 ' and residue
Isolating oxide layer 104 ") therefore the thickness between the grid polycrystalline silicon and drain electrode being subsequently formed can reduce final semiconductor
The gate drain capacitor (Cgd) of device.
In some embodiments, remaining isolating oxide layer 104 " is from the second top surface portion for being adjacent to groove 102
The difference in height of minimum point of the highest point of 104S-2 to the first top surface portion 104S-1 for being adjacent to mask polysilicon 106 " can
For example, 30nm to 40nm.In some embodiments, the highest point of the concave upper surface 108S of polysilicon interlevel oxide layer 108 '
Difference in height to the minimum point of concave upper surface 108S may be, for example, 32nm to 38nm.
As shown in figure 9, forming a grid oxic horizon 110 on polysilicon interlevel oxide layer 108 ' according to some embodiments.
In some embodiments, available for example to utilize chemical vapor deposition (CVD) technique, atomic layer deposition (ALD) technique, thermal oxide
Technique, physical vapour deposition (PVD) (PVD) technique, lithographic patterning technique, etching technics, other applicable techniques or above-mentioned
Combination forms grid oxic horizon 110.In some embodiments, grid oxic horizon 110 can be by silica, hafnium oxide, zirconium oxide, oxygen
Change aluminium, aluminium dioxide hafnium alloy, titanium dioxide silicon-hafnium, hafnium silicon oxynitride, tantalum hafnium oxide, titanium oxide hafnium, hafnium zirconium oxide, other suitable
High dielectric constant (high-k) dielectric material or it is above-mentioned combination formed.
As shown in Figure 10, according to some embodiments, a grid polycrystalline silicon 112 is formed on grid oxic horizon 110.Some
In embodiment, grid polycrystalline silicon is formed using such as chemical vapor deposition (CVD) or other suitable polysilicon deposition techniques
112.So far, semiconductor device 10 provided by the embodiment of the present invention is completed.
Then, subsequent step can be carried out according to technology known to the art related technical personnel, for example, available
It seem that chemical vapor deposition (CVD) or other suitable depositing operations form boron phosphorus silicate glass (BPSG), phosphosilicate glass
The insulating layers such as glass (PSG) or borosilicate glass (BSG) are above semiconductor device 10, and form the techniques such as metal layer step
Suddenly.For up to succinct purpose, therefore, not repeat them here.
Another embodiment of the present invention, which provides, a kind of is formed by semiconductor device by above-mentioned semiconductor making method.Such as
Shown in Figure 10, semiconductor device 10 includes that there is a substrate 100 of multiple grooves 102 and isolating oxide layer 104 " to be located at ditch
In slot 102.The material of substrate 100 can refer to aforementioned relevant paragraph, not in this repeated description.In some embodiments, isolation from oxygen
Changing layer 104 " can be conformally formed on the side wall of groove 102 and bottom and on the top surface of substrate 100.
In some embodiments, semiconductor device 10 further includes mask polysilicon 106 ".In some embodiments, mask is more
Crystal silicon 106 " can be by undoped polysilicon or the polysilicon through adulterating in situ is formed.In some embodiments, mask is more
Crystal silicon 106 ", which is located in groove 102 and is partly isolated oxide layer 104 ", to be surrounded.
In some embodiments, a top surface of isolating oxide layer 104 " from the 106 " S of side wall of mask polysilicon 106 " to
The sidewall direction of groove 102 up extends.In some embodiments, there are two different for the top surface tool of isolating oxide layer 104 "
Curvature.In some embodiments, the first top table adjacent with the 106 " S of side wall of mask polysilicon 106 " of isolating oxide layer 104 "
Face part 104S-1 has first curvature, second top surface portion adjacent with the side wall of groove 102 of isolating oxide layer 104 "
104S-2 has torsion.In some embodiments, first curvature is greater than torsion.In some embodiments, isolation from oxygen
Change the top surface that layer 104 " has unsmooth (or discontinuous).
In some embodiments, isolating oxide layer 104 " is adjacent to the first top surface portion of mask polysilicon 106 "
The difference in height of one top surface 106S of 104S-1 and mask polysilicon 106 " is less than 50nm.Such result makes in subsequent technique
Oxide does not generate (or not generating generally) hole (void) between filling the polysilicon layer into groove 102.Due to polysilicon
Interlevel oxidation object can be deposited well, therefore can preferably control the formation of oxide skin(coating) between polysilicon layer, improvement final half
The performance of conductor device, for example, reducing gate drain capacitor (Cgd) and suppressor grid to source leakage currents.
In some embodiments, isolating oxide layer 104 " is from the second top surface portion 104S-2's for being adjacent to groove 102
The difference in height of minimum point of highest point to the first top surface portion 104S-1 for being adjacent to mask polysilicon 106 " may be, for example,
30nm to 40nm.
In some embodiments, semiconductor device 10 further includes polysilicon interlevel oxide layer 108 '.In some embodiments,
Polysilicon interlevel oxide layer 108 ' may be, for example, high density plasma enhanced chemical vapor deposition (HDPCVD) oxide.Oxygen between polysilicon layer
Change layer 108 ' to be located on isolating oxide layer 104 " and mask polysilicon 106 ".In some embodiments, polysilicon interlevel oxide layer
108 ' fully cover isolating oxide layer 104 " and mask polysilicon 106 ", without (or not having generally) hole
(void).Polysilicon interlevel oxide layer 108 ' has a concave upper surface 108S.
In some embodiments, the profile and isolating oxide layer of the concave upper surface 108S of polysilicon interlevel oxide layer 108 '
The one of 104 " top surface (the first top surface portion 104S-1 and the second top surface portion 104S-2) and mask polysilicon 106 "
The profile P1 that top surface 106S is constituted is roughly the same.
It should be noted that since the concave upper surface 108S of polysilicon interlevel oxide layer 108 ' is close to 102 side wall of groove
Part the radian that is bent upwards is presented, equivalent to increase oxide layer (for example, polysilicon interlevel oxide layer 108 ' and remaining
Isolating oxide layer 104 ") therefore thickness between the grid polycrystalline silicon and drain electrode being subsequently formed can reduce final semiconductor dress
The gate drain capacitor (Cgd) set.In some embodiments, the average thickness of polysilicon interlevel oxide layer 108 ' may be, for example,
90nm to 170nm.
In some embodiments, the side wall of the concave upper surface 108S of polysilicon interlevel oxide layer 108 ' and groove 102 it
Between angle may be, for example, 110 ° to 120 °.In some embodiments, the concave upper surface of polysilicon interlevel oxide layer 108 '
The curvature of 108S may be, for example, 0.045 to 0.055nm-1.In some embodiments, the spill top of polysilicon interlevel oxide layer 108 '
Angle between surface 108S and the side wall of groove 102 is bigger or the concave upper surface 108S of polysilicon interlevel oxide layer 108 '
Curvature it is bigger, the gate drain capacitor (Cgd) of final semiconductor device decline degree is bigger.
In some embodiments, semiconductor device 10 further includes a grid oxic horizon 110 and is located at polysilicon interlevel oxide layer
On 108 ' and a grid polycrystalline silicon 112 is located on grid oxic horizon 110.Grid oxic horizon 110 and grid polycrystalline silicon 112
Material can refer to aforementioned relevant paragraph, therefore not in this repeated description.It will be appreciated that semiconductor device 10 may also include other not
The element being shown in schema, for example, being located at boron phosphorus silicate glass (BPSG), the phosphosilicate glass of 10 top of semiconductor device
The structures such as insulating layers and metal layer such as glass (PSG) or borosilicate glass (BSG).Since above structure is the art
Known to related technical personnel, for up to succinct purpose, therefore, not repeat them here.
Manufacturing method for semiconductor device provided by the embodiment of the present invention is by carrying out two stage quarter to mask oxide
Etching technique simultaneously carries out two stage removal technique to layer of isolation oxide, to slow down in technique in the past in trenched side-wall and mask oxygen
The sinking degree of generated isolation oxide between compound side wall, so that the interlayer polysilicon oxide that subsequent technique is inserted
It can be deposited on well on mask polysilicon and isolating oxide layer without generating hole (void).
The obtained semiconductor device of manufacturing method for semiconductor device provided by according to embodiments of the present invention has following
Advantage.Semiconductor device provided by the embodiment of the present invention is compared to semiconductor device provided by past technique, isolation oxidation
Layer generated sinking degree between trenched side-wall and mask polysilicon sidewall is slowed down, and is inserted in subsequent technique more
Crystal silicon interlevel oxide layer (IPO) does not have hole (void).Therefore, between the polysilicon layer of the semiconductor device of the embodiment of the present invention
Oxide layer (IPO) can provide the good effect that is electrically insulated between grid polycrystalline silicon and mask polysilicon.Also, due to not having
There is hole, polysilicon interlevel oxide layer (IPO) can provide the isolation effect of good suppressor grid to source leakage currents, Jin Erti
The performance of high semiconductor device.
Further, since carrying out two stage etching technics to mask oxide and being carried out to layer of isolation oxide two stage
Remove technique, the isolating oxide layer of the provided semiconductor device of the embodiment of the present invention trenched side-wall and mask polysilicon sidewall it
Between depressed area have improvement profile.Also, by oxygen between the polysilicon layer of the provided semiconductor device of the embodiment of the present invention
Change layer (IPO) is roughly the same with the profile of above-mentioned isolating oxide layer depressed area, therefore, the provided semiconductor of the embodiment of the present invention
The polysilicon interlevel oxide layer (IPO) of device has a concave upper surface.The spill top table of polysilicon interlevel oxide layer (IPO)
The radian being bent upwards is being presented close to the part of trenched side-wall for face, equivalent to increase oxide layer in grid polycrystalline silicon and drain electrode
Between thickness, therefore the gate drain capacitor (Cgd) of semiconductor device can be reduced.
Although this present invention is exposed in embodiment, however, it is not to limit the invention, any art technology
Personnel, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection scope of the present invention
Subject to view as defined in claim.
Claims (20)
1. a kind of manufacturing method of semiconductor device characterized by comprising
One substrate is provided；
Multiple grooves are formed in the substrate；
A layer of isolation oxide is formed in those grooves and on the substrate；
It deposits in the layer of isolation oxide of a mask polysilicon in those grooves and on the substrate；
One first etching technics is carried out to remove a first part of the mask polysilicon, and expose in those grooves should be every
A part of surface from oxide layer；
One first removal technique is carried out to remove a first part of the layer of isolation oxide；
One second etching technics is carried out to remove a second part of the mask polysilicon, and expose in those grooves should be every
Another part surface from oxide layer；
One second removal technique is carried out to remove a second part of the layer of isolation oxide；And
A polysilicon interlevel oxide layer is formed on the remaining mask polysilicon and the remaining layer of isolation oxide；
Wherein the polysilicon interlevel oxide layer has a concave upper surface.
2. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that further include:
A grid oxic horizon is formed on the polysilicon interlevel oxide layer；And
A grid polycrystalline silicon is formed on the grid oxic horizon.
3. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that form the polysilicon interlevel oxide layer
In including: on the remaining mask polysilicon and the remaining layer of isolation oxide
Oxide is in those grooves and above the substrate between depositing a polysilicon layer；
A third etching technics is carried out to remove a part of oxide between the polysilicon layer, and exposes the side wall of those grooves
A part.
4. the manufacturing method of semiconductor device as claimed in claim 3, which is characterized in that oxide is complete between the polysilicon layer
Ground covers the isolating oxide layer and the mask polysilicon.
5. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that further include:
Before carrying out the first part of first etching technics to remove the mask polysilicon, which is carried out
One chemical-mechanical planarization grinding technics is until exposing the layer of isolation oxide.
6. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that carry out this second remove technique with
After the second part for removing the layer of isolation oxide, a top surface of the remaining isolating oxide layer is from the mask polysilicon
Side wall up extend to the sidewall direction of the groove.
7. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that carry out this second remove technique with
After the second part for removing the layer of isolation oxide, the remaining isolating oxide layer is adjacent with the side wall of the mask polysilicon
The first top surface portion have a first curvature, the remaining isolating oxide layer it is adjacent with the side wall of the groove second push up table
Face part has a torsion, and wherein the first curvature is greater than the torsion.
8. such as the manufacturing method of semiconductor device according to any one of claims 1 to 7, which is characterized in that the polysilicon layer
Between oxide layer the profile of the concave upper surface and the top surface of the remaining isolating oxide layer and the remaining mask polysilicon
The profile that is constituted of top surface it is roughly the same.
9. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that the remaining isolating oxide layer is adjacent
In the height of a top surface of the minimum point and remaining mask polysilicon of one first top surface portion of the mask polysilicon
Difference is less than the isolating oxide layer in the thickness on the substrate.
10. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that the polysilicon interlevel oxide layer
Angle between the concave upper surface and the side wall of the groove be 110 ° to 120 ° and/or the polysilicon interlevel oxide layer this is recessed
The curvature of shape top surface is 0.045 to 0.055nm-1。
11. a kind of semiconductor device characterized by comprising
One substrate, including multiple grooves；
One isolating oxide layer is located in those grooves；
One mask polysilicon, surrounds in those grooves and partly by the isolating oxide layer；And
One polysilicon interlevel oxide layer is located on the isolating oxide layer and the mask polysilicon；
Wherein the polysilicon interlevel oxide layer has a concave upper surface.
12. semiconductor device as claimed in claim 11, which is characterized in that further include:
One grid oxic horizon is located on the polysilicon interlevel oxide layer；And
One grid polycrystalline silicon is located on the grid oxic horizon.
13. semiconductor device as claimed in claim 11, which is characterized in that the polysilicon interlevel oxide layer fully covers should
Isolating oxide layer and the mask polysilicon.
14. semiconductor device as claimed in claim 11, which is characterized in that a top surface of the isolating oxide layer is from the mask
The side wall of polysilicon up extends to the sidewall direction of the groove.
15. semiconductor device as claimed in claim 11, which is characterized in that there are two the top surface tools of the isolating oxide layer
Different curvature.
16. semiconductor device as claimed in claim 11, which is characterized in that the side of the isolating oxide layer and the mask polysilicon
One first adjacent top surface portion of wall have a first curvature, the isolating oxide layer it is adjacent with the side wall of the groove one second
Top surface portion has a torsion, and wherein the first curvature is greater than the torsion.
17. the semiconductor device as described in any one of claim 11~16, which is characterized in that the polysilicon interlevel oxide layer
The profile of the concave upper surface and the top surface of the isolating oxide layer and the mask polysilicon the profile that is constituted of top surface
It is roughly the same.
18. semiconductor device as claimed in claim 11, which is characterized in that the isolating oxide layer is adjacent to the mask polysilicon
One first top surface portion and the mask polysilicon a top surface difference in height be less than 50nm.
19. semiconductor device as claimed in claim 11, which is characterized in that the isolating oxide layer is from being adjacent to the one of the groove
The difference in height of minimum point of the highest point of second top surface portion to the first top surface portion for being adjacent to the mask polysilicon is
The average thickness of 30nm to 40nm and/or the polysilicon interlevel oxide layer is 90nm to 170nm.
20. semiconductor device as claimed in claim 11, which is characterized in that the spill top table of the polysilicon interlevel oxide layer
Angle between face and the side wall of the groove is 110 ° to 120 ° and/or the concave upper surface of the polysilicon interlevel oxide layer
Curvature is 0.045 to 0.055nm-1。
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| CN110600371A (en) * | 2019-08-23 | 2019-12-20 | 中芯集成电路制造(绍兴)有限公司 | Polycrystalline silicon filling method, semiconductor device manufacturing method and semiconductor device |
| CN112133637A (en) * | 2020-11-30 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
| CN113013027A (en) * | 2021-03-24 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
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