CN114284149A - Preparation method of shielded gate trench field effect transistor - Google Patents
Preparation method of shielded gate trench field effect transistor Download PDFInfo
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- CN114284149A CN114284149A CN202111582066.2A CN202111582066A CN114284149A CN 114284149 A CN114284149 A CN 114284149A CN 202111582066 A CN202111582066 A CN 202111582066A CN 114284149 A CN114284149 A CN 114284149A
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Abstract
The invention provides a preparation method of a shielded gate trench field effect transistor, which comprises the steps of forming an intermediate oxide layer and a gate oxide layer step by step, so that the intermediate oxide layer with better appearance and quality can be formed, and the thickness of the intermediate oxide layer can be controlled according to requirements, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, the sizes of a gate source capacitor and a gate drain capacitor of an SGT-MOSFET device can be modulated, and the SGT-MOSFET device can be adapted to different application scenes; in addition, the intermediate oxide layer with good appearance and quality and controllable thickness can also improve the electrical property of grid-source leakage of the SGT-MOSFET device; therefore, the shape of the middle oxide layer can be optimized, the quality of the middle oxide layer is greatly improved, and the thickness of the middle oxide layer is controllable, so that the electrical property of the SGT-MOSFET device is improved.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and relates to a preparation method of a shielded gate trench field effect transistor.
Background
A shielded Gate Trench field effect transistor (SGT-MOSFET for short) is an advanced power MOSFET device, and reduces the overlapping area of Gate and drain of the device by introducing a shielded Gate electrode, thereby reducing the Gate-drain capacitance, achieving the purposes of increasing the switching speed of the device and reducing the dynamic loss of the device, and improving the use efficiency of the system.
In the prior art SGT-MOSFET device, the gate includes a polysilicon gate electrode located at an upper layer and a polysilicon shield gate electrode located at a lower layer, and the polysilicon shield gate electrode located at the lower layer is shorted to the source. In order to avoid short circuit between the polysilicon shield gate electrode and the polysilicon gate electrode on the upper portion of the polysilicon shield gate electrode, an intermediate oxide layer is arranged between the polysilicon shield gate electrode and the polysilicon gate electrode to ensure insulation between the polysilicon gate electrode on the upper portion and the polysilicon shield gate electrode on the lower portion, and therefore the quality of the intermediate oxide layer can affect the performance of the SGT-MOSFET device to a certain extent.
At present, the preparation of the intermediate oxide layer in the SGT-MOSFET device still has the problems of difficult process control, unstable quality of the intermediate oxide layer and limitation of the thickness of the intermediate oxide layer by the thickness of the gate oxide layer, so that the gate source-drain current (I) in the SGT-MOSFET device is influencedGSS) Electrical properties of the film.
Therefore, it is necessary to provide a method for manufacturing a shielded gate trench field effect transistor.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a shielded gate trench field effect transistor, which is used to solve the problem in the prior art that it is difficult to manufacture a high-quality and thickness-controllable intermediate oxide layer applied to a gate of an SGT-MOSFET device.
To achieve the above and other related objects, the present invention provides a method for manufacturing a shielded gate trench field effect transistor, comprising the steps of:
providing a substrate with an epitaxial layer on the surface;
forming a hard mask structure on the epitaxial layer, wherein the hard mask structure comprises a silicon dioxide bottom layer, a silicon nitride layer and a silicon dioxide top layer which are sequentially overlapped from bottom to top;
patterning the hard mask structure, and etching the epitaxial layer to form a groove;
forming a field oxide layer on the side wall of the groove;
forming a polysilicon layer filling the trench;
carrying out planarization treatment to expose the surface of the silicon nitride layer;
in the cellular region, removing part of the field oxide layer on the side wall of the groove from top to bottom, so that the top surface of the field oxide layer is lower than the surface of the polycrystalline silicon layer, and a gap is formed between the polycrystalline silicon layer and the side wall of the groove;
forming a silicon dioxide protective layer, wherein the silicon dioxide protective layer covers the exposed side wall of the groove and the exposed polycrystalline silicon layer;
forming a silicon nitride covering layer, wherein the silicon nitride covering layer fills the gap;
etching the silicon nitride covering layer to expose the polycrystalline silicon layer;
removing part of the polycrystalline silicon layer in the cellular region to form a polycrystalline silicon shielding gate electrode at the bottom of the groove;
forming an intermediate oxide layer, wherein the intermediate oxide layer covers the polysilicon shielding gate electrode, and the interface between the polysilicon shielding gate electrode and the intermediate oxide layer is lower than the interface between the field oxide layer and the silicon nitride covering layer;
removing the silicon nitride covering layer;
forming a gate oxide layer, wherein the gate oxide layer covers the exposed side wall of the groove;
and forming a polysilicon gate electrode in the groove.
Optionally, when removing a portion of the polysilicon layer located in the cell region, a top surface of the polysilicon shield gate electrode is formed to be lower than an interface between the silicon nitride capping layer and the field oxide layer.
Optionally, when removing a portion of the polysilicon layer located in the cell region, the formed polysilicon shield gate electrode, the silicon nitride capping layer and the surface of the field oxide layer are located at the same horizontal plane; or when removing part of the polysilicon layer in the cellular region, the top surface of the formed polysilicon shield gate electrode is higher than the interface of the silicon nitride covering layer and the field oxide layer.
Optionally, the method for forming the intermediate oxide layer includes a thermal oxidation method, and an interface between the polysilicon shield gate electrode and the intermediate oxide layer is lower than an interface between the field oxide layer and the silicon nitride capping layer by controlling process parameters of the thermal oxidation method.
Optionally, the thickness of the intermediate oxide layer is formed to be greater than the thickness of the gate oxide layer.
Optionally, the intermediate oxide layer is formed to a thickness of
Optionally, a depth of a top surface of the field oxide layer below a surface of the polysilicon layer ranges from 0.5 μm to 2.0 μm.
Optionally, the bottom surface of the formed polysilicon gate electrode is a horizontal surface.
Optionally, the method further comprises the following steps:
performing ion implantation to form a body region and a source region in the epitaxial layer respectively;
forming a silicon dioxide insulating layer, wherein the silicon dioxide insulating layer covers the polysilicon gate electrode;
forming an interlayer dielectric layer;
etching the contact hole to form metal layers respectively contacted with the polycrystalline silicon layers of the source region and the terminal region in the cellular region;
forming a passivation layer covering the metal layer, and patterning the passivation layer to form a pad window;
thinning the substrate;
and forming a drain electrode on the surface of the thinned substrate.
Optionally, the shielded gate trench field effect transistor comprises a P-type shielded gate trench field effect transistor or an N-type shielded gate trench field effect transistor.
As described above, the method for preparing the shielded gate trench field effect transistor of the invention forms the intermediate oxide layer and the gate oxide layer step by step, thereby forming the intermediate oxide layer with better appearance and quality, and can control the thickness of the intermediate oxide layer according to the requirement, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, thereby modulating the gate source capacitance of the SGT-MOSFET device(Cgs) and gate-drain capacitance (Cgd) such that the SGT-MOSFET device can be adapted to different application scenarios; in addition, the intermediate oxide layer with good appearance and quality and controllable thickness can also improve the grid source leakage (I) of the SGT-MOSFET deviceGSS) Electrical properties of; therefore, the shape of the middle oxide layer can be optimized, the quality of the middle oxide layer is greatly improved, and the thickness of the middle oxide layer is controllable, so that the electrical property of the SGT-MOSFET device is improved.
Drawings
Fig. 1 is a schematic flow chart of a process for manufacturing a shielded gate trench field effect transistor according to an embodiment.
Fig. 2 is a schematic structural view of a substrate having an epitaxial layer in the embodiment.
FIG. 3 is a schematic diagram illustrating a structure after forming a trench in an embodiment.
Fig. 4 is a schematic structural diagram illustrating a structure after a field oxide layer is formed on the sidewall of the trench in the embodiment.
Fig. 5 is a schematic structural diagram illustrating a structure of the embodiment after a polysilicon layer filling the trench is formed.
FIG. 6 is a schematic structural diagram of an embodiment after planarization.
Fig. 7 is a schematic structural diagram of an embodiment after a void is formed in a cell region by removing a portion of a field oxide layer.
FIG. 8 is a schematic structural diagram of an embodiment after a silicon dioxide passivation layer is formed.
FIG. 9 is a schematic diagram illustrating a structure of an embodiment after forming a silicon nitride capping layer.
FIG. 10 is a schematic diagram illustrating the structure of the embodiment after the polysilicon layer is exposed by etching the silicon nitride capping layer.
FIGS. 11a to 11c are schematic diagrams showing three different structures of the embodiment after removing a portion of the polysilicon layer in the cell region to form a polysilicon shield gate electrode.
FIG. 12 is a schematic structural diagram of an embodiment after an intermediate oxide layer is formed.
FIG. 13 is a schematic view of the structure after the removal of the silicon nitride cap layer in the embodiment.
Fig. 14 is a schematic structural diagram after a gate oxide layer is formed in the embodiment.
Fig. 15 is a schematic structural view after a polysilicon gate electrode is formed in the embodiment.
Fig. 16 is a schematic structural view after ion implantation is performed to form a body region in the embodiment.
Fig. 17 is a schematic structural diagram illustrating a source region formed by ion implantation in the embodiment.
FIG. 18 is a schematic diagram illustrating a structure of an embodiment after forming a silicon dioxide insulating layer and an interlayer dielectric layer.
FIG. 19 is a schematic diagram illustrating a structure after forming a contact hole according to an embodiment.
FIG. 20 is a schematic structural diagram of an embodiment after a metal layer is formed.
Fig. 21 is a schematic structural diagram of the passivation layer with a pad window formed in the embodiment.
Description of the element reference numerals
100 substrate
200 epitaxial layer
301 bottom layer of silicon dioxide
302 silicon nitride layer
303 silicon dioxide top layer
400 groove
500 field oxide layer
600 polysilicon layer
601 polysilicon shield gate electrode
602 polysilicon gate electrode
700 silicon dioxide protective layer
800 silicon nitride capping layer
900 middle oxide layer
110 gate oxide layer
120 body region
130 source region
140 silicon dioxide insulating layer
150 interlayer dielectric layer
160 contact hole
171 barrier layer
172 first metal layer
173 second metal layer
180 passivation layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, in the present embodiment, a method for manufacturing a shielded gate trench field effect transistor is provided, in which an intermediate oxide layer and a gate oxide layer are formed step by step, so that the intermediate oxide layer with good morphology and quality can be formed, and the thickness of the intermediate oxide layer can be controlled as required, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, and thus the size of a gate source capacitance (Cgs) and a gate drain capacitance (Cgd) of an SGT-MOSFET device can be modulated, so that the SGT-MOSFET device can adapt to different application scenarios; in addition, the intermediate oxide layer with good appearance and quality and controllable thickness can also improve the grid source leakage (I) of the SGT-MOSFET deviceGSS) Electrical properties of; therefore, the shape of the middle oxide layer can be optimized, the quality of the middle oxide layer is greatly improved, and the thickness of the middle oxide layer is controllable, so that the electrical property of the SGT-MOSFET device is improved.
By way of example, the shielded gate trench field effect transistor may include a P-type shielded gate trench field effect transistor or an N-type shielded gate trench field effect transistor, and in this embodiment, the shielded gate trench field effect transistor is an N-type shielded gate trench field effect transistor, but the present invention is not limited thereto.
Referring to fig. 2 to 21, the technical solution of the present embodiment will be further described below with reference to the accompanying drawings.
First, as shown in fig. 2, step S1 is performed to provide the substrate 100 with the epitaxial layer 200 on the surface.
Specifically, the substrate 100 may employ N+A silicon substrate, wherein said epitaxial layer 200 may correspondingly adopt N-The epitaxial layer is not limited herein with respect to the thickness, preparation and material of the substrate 100 and the epitaxial layer 200.
Next, as shown in fig. 2, step S2 is performed to form a hard mask structure on the epitaxial layer 200, wherein the hard mask structure includes a silicon dioxide bottom layer 301, a silicon nitride layer 302, and a silicon dioxide top layer 303 stacked in sequence from bottom to top.
Specifically, a thin silicon dioxide film with a certain thickness is grown on the surface of the epitaxial layer 200 to serve as the silicon dioxide bottom layer 301, then silicon nitride with a certain thickness is deposited on the silicon dioxide bottom layer 301 to serve as the silicon nitride layer 302, and finally a layer of silicon dioxide is deposited on the silicon nitride layer 302 to serve as the silicon dioxide top layer 303, so that a silicon dioxide-silicon nitride-silicon dioxide hard mask structure which is sequentially stacked from bottom to top is formed, and the subsequent process preparation is facilitated. The specific fabrication process and thickness of the silicon dioxide bottom layer 301, the silicon nitride layer 302 and the silicon dioxide top layer 303 are not overly limited herein.
Next, as shown in fig. 3, step S3 is performed to pattern the hard mask structure and etch the epitaxial layer 200 to form a trench 400.
Specifically, the silicon dioxide-silicon nitride-silicon dioxide is used as a hard mask layer, and the topography of the trench region to be prepared can be defined through photolithography, so that the required trench 400 can be etched. The distribution, size and topography of the trenches 400 is not overly limited herein.
Next, as shown in fig. 4, step S4 is performed to form a field oxide layer 500 on the sidewall of the trench 400.
Specifically, after the trench 400 is etched, a layer of silicon dioxide with a certain thickness may be formed by using chemical vapor deposition or other methods to prepare and form the field oxide layer 500. Regarding the thickness of the field oxide layer 500, it can be set according to the requirement, and is not limited too much here.
Next, as shown in fig. 5, step S5 is performed to form a polysilicon layer 600 filling the trench 400. The method and thickness of the polysilicon layer 600 may be set according to the requirement, and are not limited herein.
Next, as shown in fig. 6, step S6 is performed to perform a planarization process, so as to expose the surface of the silicon nitride layer 302.
Specifically, the polysilicon layer 600 may be planarized to expose the silicon dioxide top layer 303, and then the polysilicon layer 600 in the trench 400 is etched back and planarized until the surface of the silicon nitride layer 302 is exposed. Wherein the planarization process may include mechanical polishing or CMP, which is not limited herein.
Next, as shown in fig. 7, step S7 is performed, in the cell region, a portion of the field oxide layer 500 on the sidewall of the trench 400 is removed from top to bottom, such that the top surface of the field oxide layer 500 is lower than the surface of the polysilicon layer 600, and a gap is formed between the polysilicon layer 600 and the sidewall of the trench 400.
As an example, the depth of the top surface of the field oxide layer 500 below the surface of the polysilicon layer 600 may be in a range of 0.5 μm to 2.0 μm, such as a value in any range of 0.5 μm1 μm, 1.2 μm, 1.5 μm, 2.0 μm, etc., to provide space for the subsequent process.
Next, as shown in fig. 8, step S8 is performed to form a silicon dioxide protection layer 700, where the silicon dioxide protection layer 700 covers the exposed sidewalls of the trench 400 and the exposed polysilicon layer 600. So as to protect the polysilicon layer 600 and the trench 400 from the influence of the subsequent process by the silicon dioxide protection layer 700, the thickness of the silicon dioxide protection layer 700 is not limited herein.
Next, as shown in fig. 9, step S9 is performed to form a silicon nitride capping layer 800, where the silicon nitride capping layer 800 fills the gap. The method for forming the silicon nitride cap layer 800 and the thickness thereof are not limited herein.
Next, as shown in fig. 10, step S10 is performed to etch the silicon nitride capping layer 800, exposing the polysilicon layer 600.
Specifically, since the surface of the polysilicon layer 600 has the silicon dioxide protection layer 700, when the silicon nitride capping layer 800 is removed, the silicon dioxide protection layer 700 may be used as an etching stop layer to protect the polysilicon layer 600. The method for etching the silicon nitride cap layer 800 is not limited herein.
Next, step S11 is performed to remove a portion of the polysilicon layer 600 in the cell region, and form a polysilicon shield gate electrode 601 at the bottom of the trench 400.
As an example, in fig. 11a, when removing the polysilicon layer 600 in the cell region, the top surface of the polysilicon shield gate electrode 601 may be formed lower than the interface between the silicon nitride cap layer 800 and the field oxide layer 500, but not limited thereto, in fig. 11b, when removing the polysilicon layer 600 in the cell region, the surfaces of the polysilicon shield gate electrode 601, the silicon nitride cap layer 800 and the field oxide layer 500 may be formed at the same level; or as shown in fig. 11c, when the polysilicon layer 600 in the cell region is removed, the top surface of the polysilicon shield gate electrode 601 is formed to be higher than the interface between the silicon nitride cap layer 800 and the field oxide layer 500.
Specifically, when the polysilicon layer 600 in the cell region is etched, when the top surface of the polysilicon shield gate electrode 601 is lower than the interface between the silicon nitride cap layer 800 and the field oxide layer 500, it can be ensured that the interface between the subsequently formed middle oxide layer 900 and the polysilicon shield gate electrode 601 is lower than the interface between the field oxide layer 500 and the silicon nitride cap layer 800; when the top surface of the polysilicon shield gate electrode 601 is equal to the interface between the silicon nitride cap layer 800 and the field oxide layer 500, the intermediate oxide layer 900 may be formed by a thermal oxidation method, so as to ensure that the interface between the formed intermediate oxide layer 900 and the polysilicon shield gate electrode 601 is lower than the interface between the field oxide layer 500 and the silicon nitride cap layer 800; when the top surface of the polysilicon shield gate electrode 601 is higher than the interface between the silicon nitride cap layer 800 and the field oxide layer 500, the interface between the formed middle oxide layer 900 and the polysilicon shield gate electrode 601 is lower than the interface between the field oxide layer 500 and the silicon nitride cap layer 800 by controlling the process parameters of the thermal oxidation method. Therefore, a thicker middle oxide layer 900 can be formed between the subsequently prepared polysilicon gate electrode 602 and the polysilicon shield gate electrode 601, so as to optimize the appearance of the middle oxide layer 900, greatly improve the quality of the middle oxide layer 900, and control the thickness of the middle oxide layer 900, so as to improve the electrical performance of the SGT-MOSFET device.
Next, as shown in fig. 12, step S12 is executed to form the intermediate oxide layer 900, the intermediate oxide layer 900 covers the polysilicon shield gate electrode 601, and an interface between the polysilicon shield gate electrode 601 and the intermediate oxide layer 900 is lower than an interface between the field oxide layer 500 and the silicon nitride capping layer 800.
As an example, the intermediate oxide layer 900 may be formed to a thickness of
Specifically, the thickness of the intermediate oxide layer 900 may be controlled by controlling the process parameters of thermal oxidation, and preferably, the thickness of the intermediate oxide layer 900 is
Such as
And
and the like, in any range, and are not unduly limited herein.
Next, as shown in fig. 13, step S13 is performed to remove the silicon nitride capping layer 800.
Next, as shown in fig. 14, step S14 is performed to form a gate oxide layer 110, where the gate oxide layer 110 covers the exposed sidewalls of the trench 400.
Specifically, a layer of silicon dioxide may be grown on the exposed upper portion of the trench 400 to form the gate oxide layer 110 with a certain thickness, wherein the thickness of the formed intermediate oxide layer 900 is greater than the thickness of the gate oxide layer 110, and the gate oxide layer 110 may be prepared by a thermal oxidation method, and the thickness may include, for example
Such as
And
and the like, in any range, and are not unduly limited herein.
In this embodiment, the gate oxide layer 110 and the intermediate oxide layer 900 are formed in steps, and if the two layers are prepared by one-time thermal oxidation, although the steps are simple and have cost advantages, the requirements on the process parameters of the furnace tube are high, and if the process parameter control capability of the furnace tube is insufficient, slight fluctuation of the process parameters can affect the quality of the prepared intermediate oxide layer, thereby affecting the gate-source leakage current (I) of the SGT-MOSFET deviceGSS) The thickness of the intermediate oxide layer is limited by the thickness of the gate oxide. By adopting the preparation method of the embodiment, the morphology of the middle oxide layer 900 can be optimized, the quality of the middle oxide layer 900 is greatly improved, and the thickness of the middle oxide layer 900 is controllable, so that the electrical property of the SGT-MOSFET device is improved.
Next, as shown in fig. 15, step S15 is performed to form a polysilicon gate electrode 602 in the trench 400.
Specifically, the polysilicon gate electrode 602 located on the middle oxide layer 900 may be formed by depositing and etching polysilicon, so as to form the polysilicon shield gate electrode 601, the middle oxide layer 900 and the polysilicon gate electrode 602 in the trench 400 from bottom to top.
As an example, the bottom surface of the polysilicon gate electrode 602 is formed as a horizontal surface.
Specifically, by controlling the thickness of the intermediate oxide layer 900, the bottom surface of the formed polysilicon gate electrode 602 is a horizontal surface, so that a small "sharp corner" shape can be prevented from being formed at the edge of the bottom surface of the polysilicon gate electrode 602, the overlapping area of gate and drain can be reduced, and the gate and drain capacitance (C) can be reducedgd) So as to improve the turn-on speed of the shielded gate trench field effect transistor.
Further, referring to fig. 16 to fig. 21, the method for manufacturing the shielded gate trench field effect transistor may further include the following steps:
referring to fig. 16 and 17, ion implantation is performed to form a body region 120 and a source region 130 in the epitaxy 200, for example, P-type ion implantation is performed to form the P-type body region 120, and then N is performed+Forming the N-type source region 130.
Forming a silicon dioxide insulating layer 140 as shown in fig. 18, wherein the silicon dioxide insulating layer 140 covers the polysilicon gate electrode 602, and forming an interlayer dielectric layer 150 as shown in fig. 18, wherein the interlayer dielectric layer 150 may include, but is not limited to, borophosphosilicate glass.
Referring to fig. 19 and 20, a contact hole 160 is etched to form a metal layer in contact with the polysilicon layer 600 in the source region 130 and the termination region in the cell region, wherein the metal layer may include a barrier layer 171 such as a Ti/TiN barrier layer, a first metal layer 172 such as a W metal layer on the Ti/TiN barrier layer, and a second metal layer 173 such as an AlCu metal layer on the first metal layer 172.
As shown in fig. 21, a passivation layer 180 is formed overlying the metal layer, and the passivation layer 180 is patterned to form a pad window for subsequent electrical contact, wherein the passivation layer 180 may be, but is not limited to, a silicon nitride passivation layer.
Further, the method may further include a step of thinning the substrate 100, and a step of forming a drain on the thinned surface of the substrate 100, and the method, the thickness, and the material of the drain are not limited herein.
In summary, according to the preparation method of the shielded gate trench field effect transistor, the intermediate oxide layer and the gate oxide layer are formed step by step, so that the intermediate oxide layer with good appearance and quality can be formed, and the thickness of the intermediate oxide layer can be controlled according to needs, so that the thickness of the prepared intermediate oxide layer is not limited by the thickness of the gate oxide layer, and the sizes of the gate source capacitance (Cgs) and the gate drain capacitance (Cgd) of the SGT-MOSFET device can be modulated, so that the SGT-MOSFET device can be adapted to different application scenes; in addition, the intermediate oxide layer with good appearance and quality and controllable thickness can also improve the grid source leakage (I) of the SGT-MOSFET deviceGSS) Electrical properties of; therefore, the shape of the middle oxide layer can be optimized, the quality of the middle oxide layer is greatly improved, and the thickness of the middle oxide layer is controllable, so that the electrical property of the SGT-MOSFET device is improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for manufacturing a shielded gate trench Field Effect Transistor (FET) comprises the following steps:
providing a substrate with an epitaxial layer on the surface;
forming a hard mask structure on the epitaxial layer, wherein the hard mask structure comprises a silicon dioxide bottom layer, a silicon nitride layer and a silicon dioxide top layer which are sequentially overlapped from bottom to top;
patterning the hard mask structure, and etching the epitaxial layer to form a groove;
forming a field oxide layer on the side wall of the groove;
forming a polysilicon layer filling the trench;
carrying out planarization treatment to expose the surface of the silicon nitride layer;
in the cellular region, removing part of the field oxide layer on the side wall of the groove from top to bottom, so that the top surface of the field oxide layer is lower than the surface of the polycrystalline silicon layer, and a gap is formed between the polycrystalline silicon layer and the side wall of the groove;
forming a silicon dioxide protective layer, wherein the silicon dioxide protective layer covers the exposed side wall of the groove and the exposed polycrystalline silicon layer;
forming a silicon nitride covering layer, wherein the silicon nitride covering layer fills the gap;
etching the silicon nitride covering layer to expose the polycrystalline silicon layer;
removing part of the polycrystalline silicon layer in the cellular region to form a polycrystalline silicon shielding gate electrode at the bottom of the groove;
forming an intermediate oxide layer, wherein the intermediate oxide layer covers the polysilicon shielding gate electrode, and the interface between the polysilicon shielding gate electrode and the intermediate oxide layer is lower than the interface between the field oxide layer and the silicon nitride covering layer;
removing the silicon nitride covering layer;
forming a gate oxide layer, wherein the gate oxide layer covers the exposed side wall of the groove;
and forming a polysilicon gate electrode in the groove.
2. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: when removing part of the polysilicon layer in the cellular region, the top surface of the formed polysilicon shield gate electrode is lower than the interface of the silicon nitride covering layer and the field oxide layer.
3. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: when removing part of the polysilicon layer in the cellular region, the formed polysilicon shield gate electrode, the silicon nitride covering layer and the surface of the field oxide layer are positioned on the same horizontal plane; or when removing part of the polysilicon layer in the cellular region, the top surface of the formed polysilicon shield gate electrode is higher than the interface of the silicon nitride covering layer and the field oxide layer.
4. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 3, wherein: the method for forming the intermediate oxide layer comprises a thermal oxidation method, and the interface of the polysilicon shielding gate electrode and the intermediate oxide layer is lower than the interface of the field oxide layer and the silicon nitride covering layer by controlling the technological parameters of the thermal oxidation method.
5. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: the thickness of the formed intermediate oxide layer is larger than that of the gate oxide layer.
6. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: the thickness of the intermediate oxide layer is formed
7. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: the depth range of the top surface of the field oxide layer lower than the surface of the polycrystalline silicon layer is 0.5-2.0 μm.
8. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: the bottom surface of the formed polysilicon gate electrode is a horizontal plane.
9. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1 further comprising the steps of:
performing ion implantation to form a body region and a source region in the epitaxial layer respectively;
forming a silicon dioxide insulating layer, wherein the silicon dioxide insulating layer covers the polysilicon gate electrode;
forming an interlayer dielectric layer;
etching the contact hole to form metal layers respectively contacted with the polycrystalline silicon layers of the source region and the terminal region in the cellular region;
forming a passivation layer covering the metal layer, and patterning the passivation layer to form a pad window;
thinning the substrate;
and forming a drain electrode on the surface of the thinned substrate.
10. The method of manufacturing a shielded gate trench field effect transistor as claimed in claim 1, wherein: the shielded gate trench field effect transistor comprises a P-type shielded gate trench field effect transistor or an N-type shielded gate trench field effect transistor.
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