CN105914234A - Separating gate power MOS transistor structure and manufacturing method therefor - Google Patents
Separating gate power MOS transistor structure and manufacturing method therefor Download PDFInfo
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- CN105914234A CN105914234A CN201610482674.9A CN201610482674A CN105914234A CN 105914234 A CN105914234 A CN 105914234A CN 201610482674 A CN201610482674 A CN 201610482674A CN 105914234 A CN105914234 A CN 105914234A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 82
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 166
- 125000006850 spacer group Chemical group 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 13
- 239000010937 tungsten Substances 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 210000001951 dura mater Anatomy 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses a separating gate power MOS transistor structure and a manufacturing method therefor. A high-density plasma dielectric layer is deposited in a flat region on the top of a separating gate polysilicon through a chemical vapor deposition method while only a relatively thin dielectric layer is arranged on the side wall of a trench; then the dielectric layer on the side wall of the trench is removed through an etching process; the isolating dielectric layer with enough thickness is kept on the top of the separating gate polysilicon; finally, a thermal oxidization layer is grown on the side wall of the trench, and a gate oxidization layer which is the same as that of the conventional low-voltage MOS device is kept; and the isolating dielectric layer on the top of the separating polysilicon is better than the thermal oxidation layer formed on the polysilicon through a thermal oxidization process. From the aspect of the device structure, the device dimensional limitation of the isolating dielectric layer used as the thermal oxidization layer is broken through; a thin-gate-oxygen low-voltage power consumption separating gate MOS device can be manufactured; and the thickness of the separating gate isolating dielectric layer can be far higher than that of the gate oxidization layer, so that the electric leakage performance of the device can be ensured consequently.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process field, particularly to a kind of separate gate power MOS pipe, and
And further relate to the manufacture method of a kind of separate gate power MOS pipe.
Background technology
As it is shown in figure 1, be the structural representation of existing separate gate power MOS pipe, wherein grid is groove-shaped；Existing
Separate gate power MOS pipe is had to be formed by multiple single cell structure parallel connections, including:
Substrate 1 and be formed at the epitaxial layer 2 of described substrate 1 top surface；
Body knot implanted layer 8, is formed at the top area of described epitaxial layer 2；
Source electrode implanted layer 9, is formed at the top area of described body knot implanted layer 8；
Multiple separate gate groove structures, described groove is gone forward side by side through described source electrode implanted layer 9 and described body knot implanted layer 8
Enter in the epitaxial layer 2 bottom described body knot implanted layer 8；Groove has separate gate polysilicon 4 and grid polycrystalline silicon 7,
The sidewall surfaces isolation of grid polycrystalline silicon 7 and groove has gate oxide 6, grid polycrystalline silicon 7 and separate gate polysilicon 4
Between isolation have spacer medium layer 5, separate gate polysilicon 4 and the sidewall surfaces of groove and bottom directly to isolate to have ditch
Groove field oxide 3；
Interlayer dielectric layer 10 covers at described source electrode implanted layer 9 and the top surface of grid polycrystalline silicon 7, described source electrode
Implanted layer 9 and body knot implanted layer 8 are drawn by tungsten plug 11, the top of described tungsten plug 11 and interlayer dielectric layer 10
Top surface contacts with surface metal 12.
Above-mentioned device is when additional backward voltage, and first the electric field that separate gate polysilicon 4 is formed makes epitaxial layer 2 exhaust,
Be equivalent to reduce extension doping concentration. thus improve extension body junction breakdown voltage.
In prior art, commonly used thermal oxidation technology grows thermal oxidation silicon on separate gate polysilicon 4 and is situated between as isolation
Matter layer 5, but the thermal oxidation silicon quality of grown on polysilicon is the most poor, and therefore device is when additional forward voltage,
Separate gate polysilicon 4 connects with source electrode, and the electric leakage between grid source can be very big, and then can affect the VTH (threshold of device
Threshold voltage) and UIS (non-clamp perception switching tests) performance.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of separate gate power MOS pipe structure, can solve existing device
The shortcoming of thermal oxide sealing coat between separate gate polysilicon and grid polycrystalline silicon in structure, optimizes the low pressure of thin gate oxide
Separated bar part characteristic.To this end, the present invention also provides for the manufacture method of a kind of separate gate power MOS pipe.
For solving above-mentioned technical problem, the manufacture method of the separate gate power MOS pipe that the present invention provides, including walking as follows
Rapid:
Step one, forms epitaxial layer on substrate, and etching forms groove in the epitaxial layer；
Step 2, forms groove field oxide in the side of groove and lower surface；
Step 3, groove is filled up by deposit ground floor polysilicon, carries out back ground floor polysilicon carving, is formed and be positioned at ditch
Separate gate polysilicon in groove；
Step 4, removes the groove field oxide of the groove side surface above separate gate polysilicon, only retains separate gate many
Groove field oxide between crystal silicon and groove side surface and lower surface；
Step 5, deposits high-density plasma dielectric layer at separate gate polysilicon surface and groove side surface；
Step 6, etching is removed the high-density plasma dielectric layer of groove side surface deposit, is retained on separate gate polysilicon
The high-density plasma dielectric layer of portion's deposit；
Step 7, grows thermal silicon oxide layer, and wherein the thermal silicon oxide layer composition gate oxide of groove side surface growth, separates
The spacer medium layer on gate polysilicon grid top is made up of the thermal silicon oxide layer of the high-density plasma layer deposited and growth；
Step 8, groove is filled up by deposit second layer polysilicon, carries out back second layer polysilicon carving formation gate polycrystalline
Silicon；
Step 9, sequentially forms body knot implanted layer, source electrode implanted layer, interlayer dielectric layer, tungsten plug and surface metal.
Wherein, the thickness of described spacer medium layer is more than the thickness of gate oxide.
Further, step 9 comprises the steps:
The first step, carries out body knot and injects；
Second step, carries out pushing away trap, forms body knot implanted layer, and described body knot implanted layer is positioned at the top area of epitaxial layer；
3rd step, defines active area regions, carries out ion implanting, and described active area regions is positioned at the top of body knot implanted layer
Region；
4th step, carries out annealing and advances, form source electrode implanted layer described source region；
5th step, deposits interlayer dielectric layer；
6th step, forms tungsten plug；
7th step, forms surface metal.
For solving above-mentioned technical problem, the separate gate power MOS pipe structure that the present invention provides, including:
Substrate and be formed at the epitaxial layer of described its top surface；
Body knot implanted layer, is formed at the top area of described epitaxial layer；
Source electrode implanted layer, is formed at the top area of described body knot implanted layer；
Multiple separate gate groove structures, described groove is tied implanted layer through described source electrode implanted layer and described body and enters into
In epitaxial layer bottom described body knot implanted layer；Groove has separate gate polysilicon and grid polycrystalline silicon, grid polycrystalline silicon
Isolating with the sidewall surfaces of groove and have gate oxide, between grid polycrystalline silicon and separate gate polysilicon, isolation has spacer medium
Layer, separate gate polysilicon and the sidewall surfaces of groove and bottom are directly isolated groove field oxide, described gate oxidation
Layer is made up of thermal silicon oxide layer, and described spacer medium layer is made up of high-density plasma dielectric layer and thermal silicon oxide layer；
Interlayer dielectric layer covers at described source electrode implanted layer and the top surface of grid polycrystalline silicon, described source electrode implanted layer and
Body knot implanted layer is drawn by tungsten plug, and the described top of tungsten plug and the top surface of interlayer dielectric layer connect with surface metal
Touch.
The present invention utilizes the film forming characteristics of chemical gaseous phase depositing process medium high density plasma, i.e. at separate gate polysilicon
Top flat region forms thicker spacer medium layer trenched side-wall simultaneously and only has relatively thin dielectric layer, then by etching
The dielectric layer of trenched side-wall is removed by technique, and separate gate polysilicon top can leave sufficiently thick spacer medium layer,
After trenched side-wall growth thermal oxide layer and retain the gate oxide identical with conventional low MOS device, separate gate polycrystalline
The separate gate spacer medium layer that silicon top is formed is better than the thermal oxide layer formed on the polysilicon by thermal oxidation technology.From
From the point of view of device architecture angle, the present invention breaches the thermal oxide layer device size restriction as separate gate spacer medium layer,
Can make the low-voltage and low-power dissipation separate gate power MOS (Metal Oxide Semiconductor) device of thin grid oxygen, wherein the thickness of separate gate spacer medium layer can
To realize being far longer than the thickness of gate oxide, thus ensure the electric leakage performance of device.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing separate gate power MOS pipe；
Fig. 2 A to Fig. 2 M is the device architecture in each step of manufacture method of embodiment of the present invention separate gate power MOS pipe
Figure；
Fig. 3 A is the partial enlarged drawing of existing separate gate power MOS pipe；
Fig. 3 B is the partial enlarged drawing of separate gate power MOS pipe of the present invention；
Fig. 4 A is the electromicroscopic photograph of existing separate gate power MOS pipe；
Fig. 4 B is the electromicroscopic photograph of separate gate power MOS pipe of the present invention.
Detailed description of the invention
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings.
As shown in figure 2m, it is the structural representation of separate gate power MOS pipe of the present invention, in parallel by multiple single cell structures
Formed, including:
Substrate 1 and be formed at the epitaxial layer 2 of described substrate 1 top surface；
Body knot implanted layer 8, is formed at the top area of described epitaxial layer 2；
Source electrode implanted layer 9, is formed at the top area of described body knot implanted layer 8；
Multiple separate gate groove structures, described groove is gone forward side by side through described source electrode implanted layer 9 and described body knot implanted layer 8
Enter in the epitaxial layer 2 bottom described body knot implanted layer 8；Lower trench has separate gate polysilicon 4, groove top to have
Grid polycrystalline silicon 7, the sidewall surfaces isolation of grid polycrystalline silicon 7 and groove has gate oxide 6, grid polycrystalline silicon 7 He
Between separate gate polysilicon 4, isolation has spacer medium layer 5, separate gate polysilicon 4 and the sidewall surfaces of groove and the end
Portion directly isolates groove field oxide 3, and the thermal silicon oxide layer that wherein gate oxide 6 is formed by thermal oxidation technology forms,
The thermal silicon oxide layer that described spacer medium layer 5 is formed by high-density plasma dielectric layer 15 and thermal oxidation technology forms；
Interlayer dielectric layer 10 covers at described source electrode implanted layer 9 and the top surface of grid polycrystalline silicon 7, described source electrode
Implanted layer 9 and body knot implanted layer 8 are drawn by tungsten plug 11, the top of described tungsten plug 11 and interlayer dielectric layer 10
Top surface contacts with surface metal 12.
The manufacture method of above-mentioned separate gate power MOS pipe, comprises the steps:
Step one, as shown in Figure 2 A, forms epitaxial layer 2 on substrate 1；
Step 2, as shown in Figure 2 B, at epitaxial layer 2 superficial growth etching groove dura mater plate 13, and is coated with photoresistance 14,
Exposure imaging defines trench region；
Step 3, as shown in Figure 2 C, use dry etch process dig out groove, then take out photoresistance 14, groove carve
Erosion dura mater plate 13；
Step 4, as shown in Figure 2 D, forms groove field oxide 3 in the side of described groove and lower surface, described
Groove field oxide 3 also extends into epitaxial layer 2 surface outside described groove；
Step 5, as shown in Figure 2 E, at described groove field oxide 3 surface deposition ground floor polysilicon, described
Groove is filled up completely with full by one layer of polysilicon；
Step 6, as shown in Figure 2 F, carries out back described ground floor polysilicon carving so that the ground floor outside groove
Polysilicon is removed completely, and in groove, the ground floor polysilicon at top is removed, many by the ground floor remaining in channel bottom
Crystal silicon composition separate gate polysilicon 4；
Step 7, as shown in Figure 2 G, removes the groove field oxide of the groove side surface above separate gate polysilicon 4,
Only retain the groove field oxide 3 between separate gate polysilicon 4 and groove side surface and lower surface, extend to outside groove
The groove field oxide in portion is also removed；
Step 8, as illustrated in figure 2h, uses chemical gaseous phase depositing process in separate gate polysilicon 4 surface and channel side
Face deposit high-density plasma dielectric layer 15, described high-density plasma dielectric layer 15 extends to outside groove
Epitaxial layer 2 surface；
Step 9, as shown in figure 2i, etching removes the high-density plasma dielectric layer 15 of groove side surface deposit, protects
Stay the high-density plasma dielectric layer 15 that separate gate polysilicon 4 top deposits, high density outside this outer channel etc. from
Daughter dielectric layer 15 also can retain；
Step 10, as shown in fig. 2j, uses thermal oxidation technology growth thermal silicon oxide layer, and wherein groove side surface grows
Thermal silicon oxide layer composition gate oxide 6, the spacer medium layer 5 on separate gate polysilicon 4 top is by high-density plasma
Dielectric layer 15 and epontic thermal silicon oxide layer composition thereof, thicker medium is formed on such separate gate polysilicon 4 top
While Ceng, the gate oxide of trenched side-wall is still identical with the gate oxide thickness of traditional low pressure MOS device；
Step 11, as shown in figure 2k, deposits second layer polysilicon, and described second layer polysilicon will be formed with grid oxygen
The groove changing layer 6 and spacer medium layer 5 is filled up completely with, and carries out back described second layer polysilicon carving, outside groove
Second layer polysilicon all remove, the second layer polysilicon being filled in groove top form grid polycrystalline silicon 7；
Step 12, as shown in figure 2l, carries out body knot and injects, form body knot implanted layer 8；
Step 13, pushes away trap, and source region photoetching/injection/activation forms source electrode implanted layer 9, and interlayer dielectric layer 10 deposits,
Contact hole etching, contact hole injects, and barrier metal deposits, and tungsten plug 11 deposits/return quarter, and surface metal 12 deposits/light
Carving/etching, alloying annealing etc., consistent with common MOSFET way, the separate gate power MOS pipe ultimately formed is tied
Structure is as shown in figure 2m.
The present invention utilizes the film forming characteristics of chemical gaseous phase depositing process medium high density plasma, i.e. at separate gate polysilicon
Top flat region forms thicker spacer medium layer trenched side-wall simultaneously and only has relatively thin dielectric layer, then by etching
The dielectric layer of trenched side-wall is removed by technique, and separate gate polysilicon top can leave sufficiently thick spacer medium layer,
After trenched side-wall growth thermal oxide layer and retain the gate oxide identical with conventional low MOS device, separate gate polycrystalline
The separate gate spacer medium layer that silicon top is formed is better than the thermal oxide layer formed on the polysilicon by thermal oxidation technology.From
From the point of view of device architecture angle, the present invention breaches the thermal oxide layer device size restriction as separate gate spacer medium layer,
The low-voltage and low-power dissipation separate gate power MOS (Metal Oxide Semiconductor) device of thin grid oxygen, the wherein thickness A of separate gate spacer medium layer can be made
Can realize being far longer than the thickness of gate oxide, B is as shown in Fig. 3 A, 3B, thus ensures the electric leakage performance of device.
Separate gate power MOS pipe the most on the market mostly is the application of more than 30V, can make at low pressure after using the present invention
Separate gate power MOS pipe.
Carrying out feasibility analysis can obtain, in low pressure 30V separates gate power MOS, employing this patent can be by source and drain end
Electric leakage stability contorting is at below 10nA, and on market, same specification product electric leakage specification is 75nA, as shown in Fig. 4 A, 4B.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can make many deformation and improve, these
Also should be regarded as protection scope of the present invention.
Claims (5)
1. the manufacture method of a separate gate power MOS pipe, it is characterised in that comprise the steps:
Step one, forms epitaxial layer on substrate, and etching forms groove in the epitaxial layer；
Step 2, forms groove field oxide in the side of groove and lower surface；
Step 3, groove is filled up by deposit ground floor polysilicon, carries out back ground floor polysilicon carving, is formed and be positioned at ditch
Separate gate polysilicon in groove；
Step 4, removes the groove field oxide of the groove side surface above separate gate polysilicon, only retains separate gate many
Groove field oxide between crystal silicon and groove side surface and lower surface；
Step 5, deposits high-density plasma dielectric layer at separate gate polysilicon surface and groove side surface；
Step 6, etching is removed the high-density plasma dielectric layer of groove side surface deposit, is retained on separate gate polysilicon
The high-density plasma dielectric layer of portion's deposit；
Step 7, grows thermal silicon oxide layer, and wherein the thermal silicon oxide layer composition gate oxide of groove side surface growth, separates
The spacer medium layer on gate polysilicon grid top is made up of the thermal silicon oxide layer of the high-density plasma layer deposited and growth；
Step 8, groove is filled up by deposit second layer polysilicon, carries out back second layer polysilicon carving formation gate polycrystalline
Silicon；
Step 9, sequentially forms body knot implanted layer, source electrode implanted layer, interlayer dielectric layer, tungsten plug and surface metal.
The manufacture method of separate gate power MOS pipe the most according to claim 1, it is characterised in that described every
Thickness from dielectric layer is more than the thickness of gate oxide.
The manufacture method of separate gate power MOS pipe the most according to claim 1, it is characterised in that step 9
Comprise the steps:
The first step, carries out body knot and injects；
Second step, carries out pushing away trap, forms body knot implanted layer, and described body knot implanted layer is positioned at the top area of epitaxial layer；
3rd step, defines active area regions, carries out ion implanting, and described active area regions is positioned at the top of body knot implanted layer
Region；
4th step, carries out annealing and advances, form source electrode implanted layer described source region；
5th step, deposits interlayer dielectric layer；
6th step, forms tungsten plug；
7th step, forms surface metal.
4. a separate gate power MOS pipe structure, it is characterised in that including:
Substrate and be formed at the epitaxial layer of described its top surface；
Body knot implanted layer, is formed at the top area of described epitaxial layer；
Source electrode implanted layer, is formed at the top area of described body knot implanted layer；
Multiple separate gate groove structures, described groove is tied implanted layer through described source electrode implanted layer and described body and enters into
In epitaxial layer bottom described body knot implanted layer；Groove has separate gate polysilicon and grid polycrystalline silicon, grid polycrystalline silicon
Isolating with the sidewall surfaces of groove and have gate oxide, between grid polycrystalline silicon and separate gate polysilicon, isolation has spacer medium
Layer, separate gate polysilicon and the sidewall surfaces of groove and bottom are directly isolated groove field oxide, described gate oxidation
Layer is made up of thermal silicon oxide layer, and described spacer medium layer is made up of high-density plasma dielectric layer and thermal silicon oxide layer；
Interlayer dielectric layer covers at described source electrode implanted layer and the top surface of grid polycrystalline silicon, described source electrode implanted layer and
Body knot implanted layer is drawn by tungsten plug, and the described top of tungsten plug and the top surface of interlayer dielectric layer connect with surface metal
Touch.
Separate gate power MOS pipe structure the most according to claim 4, it is characterised in that described spacer medium
The thickness of layer is more than the thickness of gate oxide.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108364870A (en) * | 2018-01-23 | 2018-08-03 | 西安龙腾新能源科技发展有限公司 | Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality |
| CN109216172A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the division grid structure of semiconductor devices |
| CN109216175A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The gate structure and its manufacturing method of semiconductor devices |
| CN111261717A (en) * | 2020-01-19 | 2020-06-09 | 上海华虹宏力半导体制造有限公司 | Shielding gate power MOSFET structure and manufacturing method |
| CN111293038A (en) * | 2020-02-25 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN111415868A (en) * | 2020-03-30 | 2020-07-14 | 捷捷微电(上海)科技有限公司 | Manufacturing method of split gate MOSFET |
| CN111834462A (en) * | 2018-06-28 | 2020-10-27 | 华为技术有限公司 | Semiconductor device and manufacturing method |
| CN111883592A (en) * | 2020-08-06 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench power device and method of making same |
| CN112397390A (en) * | 2019-08-19 | 2021-02-23 | 南京紫竹微电子有限公司 | Method for forming shielding polysilicon side wall of protective shielding gate trench type field effect transistor |
| CN113078067A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Manufacturing method of trench separation gate device |
| CN114284149A (en) * | 2021-12-22 | 2022-04-05 | 瑶芯微电子科技(上海)有限公司 | Preparation method of shielded gate trench field effect transistor |
| WO2022083076A1 (en) * | 2020-10-22 | 2022-04-28 | 无锡华润上华科技有限公司 | Manufacturing method for split-gate trench mosfet |
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