CN208819886U - A kind of superjunction IGBT device structure - Google Patents
A kind of superjunction IGBT device structure Download PDFInfo
- Publication number
- CN208819886U CN208819886U CN201821740353.5U CN201821740353U CN208819886U CN 208819886 U CN208819886 U CN 208819886U CN 201821740353 U CN201821740353 U CN 201821740353U CN 208819886 U CN208819886 U CN 208819886U
- Authority
- CN
- China
- Prior art keywords
- conduction type
- igbt device
- epitaxial layer
- device structure
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
The utility model discloses a kind of superjunction IGBT device structures, comprising: the first conductivity type substrate；The second conductive type epitaxial layer on the first conductive type substrate is set；The first conduction type cylindricality diffusion region in second conductive type epitaxial layer is set；First conduction type well region, the first conduction type well region and the first conduction type cylindricality diffusion region pass through a floating mined-out area isolation；The first conduction type heavily doped region in the first conduction type well region is set；Second conduction type heavily doped region；And grid.
Description
Technical field
The utility model relates to technical field of semiconductor device more particularly to a kind of superjunction IGBT device structures.
Background technique
Insulated gate bipolar transistor (IGBT) is a kind of common power device, in fields such as industry, electrical, new energy
With extensive use.Its structure is added in traditional vertical double-diffused MOS transistor (VD MOS) bottom device
Enter p type island region, forms the composite construction of a kind of MOS device and bipolar device.IGBT has voltage control, capacitor input, input
The features such as impedance is big, driving current is small, control circuit is simple, operating temperature is high, thermal stability is good.
For the power device of conventional single conduction type, to obtain higher breakdown voltage, necessarily just be formed compared with
Thick epitaxial layer drift region and lower doping concentration, thus conducting resistance can increased dramatically with the increase of breakdown voltage.
However, conducting resistance is generally higher and can not further decrease.
Super-junction structure is as a kind of advanced drift region structure increasingly by the attention of industry.The drift of super-junction structure
Area uses alternate PN junction structure, and the advantages of this structure is, in identical resistance to pressure, the doping concentration of super-junction structure drift region
An order of magnitude can be improved, therefore conducting resistance can reduce 5-10 times.
Super-junction structure is mainly realized by two kinds of processes at present: 1) multiple extension and multiple ion implantation technology；2) deep
The first conduction type epitaxy technique of deposition embedment in slot.In semiconductor field, cost is reduced usually to increase device integration density,
Volume production effect is realized to realize.In order to overcome the high cost problem of existing IGBT device, the utility model proposes a kind of novel
Superjunction IGBT device structure and its manufacturing method have been reduced significantly the size of device, to reduce the device of the entire classification of IGBT
Cost.
Utility model content
For the high cost problem of IGBT device existing in the prior art, one embodiment according to the present utility model,
A kind of superjunction IGBT device is provided, comprising:
First conductivity type substrate；
The second conductive type epitaxial layer on the first conductive type substrate is set；
The first conduction type cylindricality diffusion region in second conductive type epitaxial layer is set；
First conduction type well region, the first conduction type well region pass through with the first conduction type cylindricality diffusion region
One floating mined-out area isolation；
The first conduction type heavily doped region in the first conduction type well region is set；
Second conduction type heavily doped region；And
Grid.
In one embodiment of the utility model, in the first conductivity type substrate boron ion implantation dosage be 1E12 extremely
1E16。
In one embodiment of the utility model, the first conductivity type substrate with a thickness of 1 micron to 20 microns.
In one embodiment of the utility model, the second conductive type epitaxial layer with a thickness of 30 microns to 80 microns.
In one embodiment of the utility model, the distance in floating area is less than 5 microns.
In one embodiment of the utility model, the ion doping concentration of the first conduction type heavily doped region is greater than described
Ion doping concentration in first conduction type well region.
In one embodiment of the utility model, the first conduction type cylindricality diffusion region passes through multiple epitaxial deposition knot
Graphical ion implanting is closed to be formed.
In one embodiment of the utility model, the first conduction type cylindricality diffusion region passes through deep plough groove etched combination
The epitaxial deposition of one conduction type is embedded to be formed.
In one embodiment of the utility model, the second conduction type heavily doped region is located at the first conduction type weight
At the surface-boundary of doped region.
In one embodiment of the utility model, grid is the plane above second conductive type epitaxial layer
Grid.
In one embodiment of the utility model, grid is the groove embedment for being embedded to second conductive type epitaxial layer
Grid.
In one embodiment of the utility model, superjunction IGBT device further include:
Metal interconnection and dielectric layer above second conductive type epitaxial layer and the grid；And
Metal area below first conductivity type substrate.
Another embodiment according to the present utility model provides a kind of manufacturing method of superjunction IGBT device, comprising:
The substrate of first conduction type is provided；
Super-junction structure is formed on the substrate of first conduction type, the super-junction structure includes the second conduction type
The column type diffusion region of epitaxial layer and the first conduction type；
The epitaxial thin layer of the second conduction type is formed on the super-junction structure；
Grid is formed on the epitaxial thin layer of second conduction type；
Ion implanting is carried out to the corresponding region of the epitaxial thin layer of second conduction type and forms doped region；
It carries out high temperature and pushes away trap；
Form positive metal interconnecting layer and surface passivation layer；
The substrate of first conduction type is thinned；
The ion implanting of the first conduction type is carried out to the substrate of the first conduction type after being thinned；
It is made annealing treatment；And
Metal is formed in the substrate back of first conduction type of the ion implanting for completing the first conduction type
Area.
In another embodiment of the utility model, the resistivity of the substrate of the first conduction type is arrived in 4 Ohmcm
Between 25Ohmcm.
In another embodiment of the utility model, on the substrate of first conduction type formed super-junction structure into
One step includes:
The epitaxial layer of the second conduction type of single layer is formed on the substrate of first conduction type；
Photoetching defines the first conduction type cylindricality diffusion region on the epitaxial layer of second conduction type of single layer；
The cylindricality diffusion first conduction type Doped ions being injected into the epitaxial layer of second conduction type of single layer
Area；
Remove mask layer and surface oxide layer；
Judge whether the overall thickness of super-junction structure reaches predetermined value, if being less than predetermined value, returns and start step continuation shape
At the second conduction type of single layer epitaxial layer and make cylindricality diffusion region, if reaching predetermined value, enter in next step；And
It carries out high temperature and pushes away trap, so that the cylindricality diffusion region of the epitaxial layer of the second conduction type of each single layer and the first conduction type
Form connection in vertical direction respectively, the cylindricality of the epitaxial layer and the first conduction type that obtain alternate second conduction type expands
Dissipate area.
In another embodiment of the utility model, the epitaxial layer of the second conduction type of single layer with a thickness of 5 microns extremely
10 microns.
In another embodiment of the utility model, it is conductive that the first conduction type Doped ions are injected into single layer second
The method of the epitaxial layer of type is: injection ion accelerated using kiloelectron-volt superfine to million electro-volt superfine energy, from
And cylindricality diffusion region is enabled to reach predetermined dopant concentration and predetermined doped depth.
In another embodiment of the utility model, on the substrate of first conduction type formed super-junction structure into
One step includes:
The epitaxial layer and silica of the second conduction type are sequentially formed in the first conductivity type substrate；
Lithographic definition goes out the first conduction type cylindricality diffusion region and removes the silica in the region；
Remove photoresist；
Using silica as exposure mask, the Yanzhong outside the second conduction type etches the first conduction type cylindricality diffusion region deep trouth；
The first conduction type epitaxial material is deposited in deep trouth；And
Remove the first conduction type epitaxial material of silicon chip surface.
In another embodiment of the utility model, the epitaxial layer of the second conduction type it is micro- with a thickness of 30 microns to 80
Rice.
In another embodiment of the utility model, before the first conduction type epitaxial material is deposited in deep trouth, also wrap
It includes:
In deep trouth Surface Creation silica and silicon nitride；And
Wet process removal generates silica and silicon nitride.
In another embodiment of the utility model, the corresponding region of the epitaxial layer of second conduction type is carried out
The method that ion implanting forms doped region further comprises:
Form the well region of the first conduction type；
The first conduction type heavily doped region is formed in the well region of first conduction type；And
The second conduction type heavily doped region is formed between the first conduction type heavily doped region boundary and grid.
In another embodiment of the utility model, progress high temperature, which pushes away trap, makes well region and the institute of first conduction type
It states and forms the floating area for being no more than 5 microns between the column type diffusion region of the first conduction type.
It is micro- with a thickness of 1 after the substrate of first conduction type is thinned in another embodiment of the utility model
Rice is to 15 microns.
In another embodiment of the utility model, it is conductive that first is carried out to the substrate of the first conduction type after being thinned
The ion implanting of type is to carry out the boron ion injection of 1E12 to 1E16 dosage.
In another embodiment of the utility model, make annealing treatment as laser annealing or furnace anneal, wherein laser
For the energy of annealing in the range of 1~4 millijoule, the time is 0.5~4 microsecond, and the temperature of furnace anneal is at 300~350 degrees Celsius
In the range of.
The utility model provides a kind of superjunction IGBT device structure and its manufacturing method, by making superjunction in silicon chip surface
Structure, the back side uses P- substrate, while carrying out back side boron injection, and a kind of completely new knot is then formed by the way of the thermal annealing of the back side
The IGBT device of structure.This kind of superjunction IGBT device based on the utility model is in its performance and existing IGBT device performance phase
Under the premise of matching, chip size can reduce 30% or more, and the cost for realizing IGBT device product reduces, and improve the competing of product
Strive power.
Detailed description of the invention
In order to further elucidate the utility model each embodiment the above and other advantages and features, will with reference to attached drawing come
The more specific description of each embodiment of the utility model is presented.It is appreciated that these attached drawings only describe the allusion quotation of the utility model
Type embodiment, therefore be not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding portion
Part will be indicated with same or similar label.
Fig. 1 shows a kind of section signal of superjunction IGBT device structure 100 of one embodiment according to the present utility model
Figure.
Fig. 2 shows a kind of signals of the section of superjunction IGBT device structure 200 of another embodiment according to the present utility model
Figure.
Fig. 3 shows a kind of section signal of superjunction IGBT device structure 300 of another embodiment according to the present utility model
Figure.
Fig. 4 A to Fig. 4 J shows one embodiment according to the present utility model and forms a kind of superjunction IGBT device structure 300
Process schematic cross-section.
Fig. 5 shows that one embodiment according to the present utility model forms a kind of stream of superjunction IGBT device structure 300
Cheng Tu.
Fig. 6 shows the super-junction structure that a kind of superjunction IGBT device structure 300 is formed according to the utility model one embodiment
Flow chart.
Fig. 7 shows the super-junction structure that a kind of superjunction IGBT device structure 300 is formed according to another embodiment of the utility model
Flow chart.
Specific embodiment
In the following description, the utility model is described with reference to each embodiment.However, those skilled in the art
Will be recognized can in the case where none or multiple specific details or with other replacements and/or addition method, material or
Component implements each embodiment together.In other situations, be not shown or be not described in detail well known structure, material or operation in order to avoid
Keep the aspects of each embodiment of the utility model obscure.Similarly, for purposes of explanation, specific quantity, material are elaborated
And configuration, in order to provide the comprehensive understanding to the embodiments of the present invention.However, the utility model can be in no specific detail
In the case where implement.Further, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the utility model.Occur in everywhere in this specification
The phrase " in one embodiment " be not necessarily all referring to the same embodiment.
It should be noted that the embodiments of the present invention are described processing step with particular order, however this
It is to distinguish each step for convenience, and be not the sequencing for limiting each step, in the different embodiments of the utility model,
The sequencing of each step can be adjusted according to the adjusting of technique.
The utility model provides a kind of superjunction IGBT device structure and its manufacturing method, by making superjunction in silicon chip surface
Structure, the back side uses P- substrate, while carrying out back side boron injection, and a kind of completely new knot is then formed by the way of the thermal annealing of the back side
The IGBT device of structure.This kind of superjunction IGBT device based on the utility model is in its performance and existing IGBT device performance phase
Under the premise of matching, chip size can reduce 30% or more, and the cost for realizing IGBT device product reduces, and improve the competing of product
Strive power.
A kind of superjunction IGBT device knot of one embodiment according to the present utility model is discussed in detail below with reference to Fig. 1
Structure.Fig. 1 shows a kind of schematic cross-section of superjunction IGBT device structure 100 of one embodiment according to the present utility model.Such as
Shown in Fig. 1, which includes the first conductivity type substrate 101, the second conductive type epitaxial layer 102, and the
One conduction type cylindricality diffusion region 103-1,103-2, first conduction type well region 104-1,104-2, the first conduction type are heavily doped
Miscellaneous area 105, the second conduction type heavily doped region 106, planar gate 107 and floating area 108.
In one embodiment of the utility model, the first conductivity type substrate 101 is P-type substrate, micro- with a thickness of 1
Rice has specific initial dopant concentration, resistivity is between 4Ohmcm to 25Ohmcm to 20 microns.It is practical at this
In a novel specific embodiment, which is injected by the thinning back side and backside particulate of substrate
It is formed, ion implanting is the injection of 1E12 to 1E16 dosage boron.
Second conductive type epitaxial layer 102 be arranged on the first conductivity type substrate 101, wherein the second conduction type with
First conduction type is different.In one embodiment of the utility model, the thickness of the second conductive type epitaxial layer 102 is about 30
Micron is to 80 microns.
First conduction type cylindricality diffusion region 103-1,103-2 is located inside the second conductive type epitaxial layer 102.In this reality
With in novel one embodiment, first conduction type cylindricality diffusion region 103-1,103-2 is by multiple epitaxial deposition knot
The boron ion for closing predetermined concentration injects the cylindricality diffusion region to be formed.In another embodiment of the utility model, it can also pass through
Deep plough groove etched combination fills to form first conduction type cylindricality diffusion region 103-1,103-2.
First conduction type well region 104-1,104-2 is located on first conduction type cylindricality diffusion region 103-1,103-2
Side, but the two separates, and has the floating area 108 less than 5 microns.
First conduction type heavily doped region 105 is located in the first conduction type well region 104, and the two conduction type is identical.The
The doping concentration of one conduction type heavily doped region 105 is greater than the doping concentration of the first conduction type well region 104.
Second conduction type heavily doped region 106 is located at the surface-boundary of the first conduction type heavily doped region 105.Second leads
The doping concentration of electric type heavily doped region 106 is greater than the doping concentration of the second conductive type epitaxial layer 102.
Planar gate 107 is arranged above the second conductive type epitaxial layer 102.
A kind of superjunction IGBT device structure of another embodiment according to the present utility model is introduced below with reference to Fig. 2.Fig. 2 shows
The schematic cross-section of the superjunction IGBT device structure 200 of another embodiment according to the present utility model out.As shown in Fig. 2, this is super
Tying IGBT device structure 200 includes the first conductivity type substrate 201, the second conductive type epitaxial layer 202, the first conduction type
Column type diffusion region 203-1,203-2, first conduction type well region 204-1,204-2, the first conduction type heavily doped region 205, the
Two conduction type heavily doped regions 206 are embedded to grid 207, floating area 208.The superjunction IGBT device structure 200 and aforementioned superjunction
IGBT device structure 100 is similar, and difference is only that its grid 207 is buried gate.Concrete condition is no longer described in detail.
A kind of superjunction IGBT device architecture of another embodiment according to the present utility model is discussed in detail below with reference to Fig. 3.
Fig. 3 shows a kind of schematic cross-section of superjunction IGBT device structure 300 of another embodiment according to the present utility model.Such as Fig. 3
It is shown, the superjunction IGBT device structure 300 include the first conductivity type substrate 301, the second conductive type epitaxial layer 302, first
Conduction type column type diffusion region 303-1,303-2, first conduction type well region 304-1,304-2, the first conduction type heavy doping
Area 305, the second conduction type heavily doped region 306, planar gate 307, floating area 308, front metal layer 309, insulating medium layer
310 and back metal area 311.
The superjunction IGBT device structure 300 carries out chip front side on the basis of aforementioned superjunction IGBT device structure 100
Metal interconnection and passivation layer protection, while that made of metal has also been carried out to the back side is standby.Other structures are identical.
The method and mistake to form superjunction IGBT device structure 300 are described in detail below with reference to Fig. 4 A to Fig. 4 J and Fig. 5
Journey.Fig. 4 A to Fig. 4 J shows the process that one embodiment according to the present utility model forms a kind of superjunction IGBT device structure 300
Schematic cross-section；Fig. 5 shows that one embodiment according to the present utility model forms a kind of superjunction IGBT device structure 300
Flow chart.
Firstly, as shown in Figure 4 A, providing the substrate 410 of the first conduction type in step 501.The one of the utility model
In a embodiment, the substrate 410 of the first conduction type is P-type substrate, has specific initial dopant concentration, and resistivity exists
Between 4Ohmcm to 25Ohmcm.
Next, as shown in Figure 4 B, forming super-junction structure 420 on the substrate 410 of the first conduction type in step 502.
Super-junction structure 420 further comprise the second conduction type epitaxial layer 421 and the first conduction type column type diffusion region 422-1,
422-2.Wherein the second conduction type is different from the first conduction type.Super-junction structure 420 can be formed by two methods: a kind of
It is that multilayer epitaxial coupled ion injects to form super-junction structure；Another kind is deep plough groove etched combination embedment extension super-junction structure.Tool
The forming method of body is described in detail again in subsequent specification.
Then, in step 503, as shown in Figure 4 C, the epitaxial layer 430 of the second conduction type is formed on super-junction structure 420.
In one embodiment of the utility model, the epitaxial layer 430 of second conduction type with a thickness of 3 microns to 6 microns.Its
In the second conduction type epitaxial layer 430 doping concentration be scheduled concentration, with mixing for the epitaxial layer 421 of the second conduction type
Miscellaneous concentration is essentially identical.
Next, as shown in Figure 4 D, forming grid 440 on the epitaxial layer 430 of the second conduction type in step 504.Grid
Pole 440 is located at the surface of the epitaxial layer between column type diffusion region 422-1,422-2 of the first conduction type.In the utility model
One embodiment in, grid 440 is the planar gate positioned at 430 surface of epitaxial layer of the second conduction type, this is practical
In novel another embodiment, grid 440 is the embedment grid inside the epitaxial layer 430 of the second conduction type.It is specific to be formed
Technique can be formed by photoetching, deposition, doping etc..
Then, in step 505, as shown in Figure 4 E, ion is carried out to the corresponding region of the epitaxial layer 430 of the second conduction type
Injection forms doped region 450.It more specifically include sequentially forming the first conduction type by techniques such as photoetching, ion implantings
Well region 451, the first conduction type heavily doped region 452 and the second conduction type heavily doped region 453.Wherein the first conduction type weight
Doped region 452 is located in the first conduction type well region 451, and the two conduction type is identical.First conduction type heavily doped region 452
Doping concentration is greater than the doping concentration of the first conduction type well region 451；Second conduction type heavily doped region 453, which is located at first, leads
At the surface-boundary of electric type heavily doped region 452.The doping concentration of second conduction type heavily doped region 453 is greater than the second conduction
The doping concentration of type epitaxial layer 430.In a specific embodiment of the utility model, it is conductive that first is formed by doping boron
Type well region 451；The first conduction type heavily doped region 452 is formed by doping boron；Second is formed by arsenic doped and/or phosphorus to lead
Electric type heavily doped region 453.
Next, as illustrated in figure 4f, carrying out high temperature in step 506 and pushing away trap.High temperature pushes away the second conductive type epitaxial layer after trap
421 and 430 integrations, while needing to control the well region 451 of the first conduction type and the column type diffusion region 422 of the first conduction type
Push away well depth, both make to be not connected to, between form the floating area 460 less than 5 microns.
Then, in step 507, as shown in Figure 4 G, the metal interconnecting layer 470 and surface passivation layer 480 of chip front side are made.
Wherein metal interconnecting layer 470 further comprises via layer and interconnection line layer.Specific formation process can be heavy by metal layer
The techniques such as product, metallic layer graphic etching, passivation layer deposition are formed；Also can be formed by Damascus technics etc..
Next, as shown at figure 4h, carrying out being thinned for the substrate 410 of the first conduction type in step 508.The after being thinned
The residual thickness of the substrate 410 of one conduction type is about 1 micron to 15 microns.
Then, in step 509, as shown in fig. 41, first is carried out to the substrate 410 of the first conduction type after being thinned and is led
The ion implanting of electric type.The boron ion injection of 1E12 to 1E16 dosage is carried out in one embodiment of the utility model.
Next, being made annealing treatment in step 510.Specific annealing process can be laser annealing or boiler tube moves back
Fire processing.For the energy of laser annealing in the range of 1~4 millijoule, the time is 0.5~4 microsecond；The temperature of furnace anneal is 300
In the range of~350 degrees Celsius.
Finally, preparation forms back metal area 490 in step 511.
303 method of super-junction structure and mistake to form superjunction IGBT device structure 300 is described in detail in conjunction with Fig. 6 below
Journey.Fig. 6 shows the process that the super-junction structure 303 of superjunction IGBT device structure 300 is formed according to the utility model one embodiment
Figure.
Firstly, forming the epitaxial layer of the second conduction type of single layer on the substrate of the first conduction type in step 601.?
In one example embodiment of the utility model, substrate can be P-type silicon substrate, and the epitaxial layer of the second conduction type of single layer
It is the silicon epitaxy layer of the second conduction type of the predetermined thickness by epitaxial growth on P-type silicon substrate.For example, practical at this
In novel embodiment, the thickness range of the epitaxial layer of the second conduction type of single layer is between 6 microns to 8 microns.It is practical at this
In another novel embodiment, the thickness of the epitaxial layer of the second conduction type of single layer can be more than 8 microns, it is micro- to reach or surpass 10
Rice.
Next, photoetching defines the first conduction type on the epitaxial layer of the second conduction type of single layer in step 602
Cylindricality diffusion region.
Then, in step 603, the first conduction type Doped ions are injected into the epitaxial layer of the second conduction type of single layer
Cylindricality diffusion region, with formed the first conduction type adulterate cylindricality diffusion region.In the embodiments of the present invention, thousand electricity are used
Sub- volt grade to million electro-volt superfine energy accelerates injection ion, so that cylindricality diffusion region can reach predetermined concentration
And predetermined depth.
Next, removing mask layer and surface oxide layer in step 604.And surface inspection is carried out, to ensure mask layer quilt
Removal is clean.In the embodiment that mask layer is photoresist layer, photoresist can be removed using chemical reagent wet process, or can also
With using plasma dry technique stripping photoresist.This dry technique can not only remove a large amount of photoresists, and can also
Remove some remaining organic matters.Surface oxide layer is removed, to guarantee that surface is suitble to the normal growth of next layer of extension.
Then, in step 605, judge whether the overall thickness of super-junction structure reaches predetermined value, make a reservation for if overall thickness is less than
It is worth, then return step 601；If the overall thickness of epitaxial layer reaches predetermined value, 606 are entered step.
Finally, carrying out high temperature in step 606 and pushing away trap, so that the epitaxial layer of the second conduction type of each single layer and the first conduction
The cylindricality diffusion region of type forms connection in vertical direction respectively, obtains the epitaxial layer and first of alternate second conduction type
The cylindricality diffusion region of conduction type.
In above process, since ion implantation concentration precision can control within 2%, only 10% or so essence is compared
The stability of concentration and consistency of the first conductivity type regions can be improved in the epi dopant concentration precision of degree, and final improve surpasses
The electricity consistency of junction device.
Be described in detail below with reference to Fig. 7 another 303 method of super-junction structure for forming superjunction IGBT device structure 300 and
Process.Fig. 7 shows the process that the super-junction structure of superjunction IGBT device structure 300 is formed according to another embodiment of the utility model
Figure.
Firstly, sequentially forming the epitaxial layer and dioxy of the second conduction type in the first conductivity type substrate in step 701
SiClx.It is micro- by growing 30 microns to 80 in the first conductivity type substrate in an example embodiment of the utility model
Meter Hou Du, predetermined concentration the second conduction type epitaxial layer, then the epi-layer surface growth predetermined thickness titanium dioxide
Silicon, etch mask of the silica for subsequent technique act on.
Next, lithographic definition goes out the first conduction type cylindricality diffusion region and removes the titanium dioxide in the region in step 702
Silicon.Specific technique includes that gluing/rubberizing, photoetching, development, silica etching (can be etched with dry method RIE or wet process carved
Erosion) etc..
Then, in step 703, photoresist is removed.Thus expose the first conduction type cylindricality diffusion region figure.
Next, using silica as exposure mask, the Yanzhong outside the second conduction type etches the first conductive-type in step 704
Type cylindricality diffusion region deep trouth.Specific lithographic method can be RIE dry etching or wet etching.
Then, in step 705, the deep trouth Surface Creation silica and silicon nitride to be formed optionally are etched in above-mentioned steps
Then wet process removes.The purpose of the processing step is to remove the etching residue in deep trouth, improve the structure size of deep trouth simultaneously
Increase the binding force of subsequent epitaxial deposition material.
Next, depositing the first conduction type epitaxial material in deep trouth in step 706.
Finally, the first conduction type epitaxial material and remaining silica for removing silicon chip surface are covered in step 707
Film.Because inevitably will continue to cover after having filled deep trouth when the process deposits such as CVD the first conduction type epitaxial material
Silicon chip surface can obtain desired super-junction structure by techniques such as chemically mechanical polishings.
Based on this kind of superjunction IGBT device structure provided by the utility model and its manufacturing method, by silicon chip surface system
Make super-junction structure, the back side uses P- substrate, while carrying out back side boron injection, then forms one kind by the way of the thermal annealing of the back side
The IGBT device of brand new.This kind of superjunction IGBT device based on the utility model is in its performance and existing IGBT device
Under the premise of performance matches, chip size can reduce 30% or more, and the cost for realizing IGBT device product reduces, and improve
The competitiveness of product.
Although described above is each embodiments of the utility model, however, it is to be understood that they are intended only as example to be in
Existing, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, change can be made to it
Type and the spirit and scope changed without departing from the utility model.Therefore, the width and model of the utility model disclosed herein
Enclosing should not be limited by above-mentioned disclosed exemplary embodiment, and should be according only to the appended claims and its equivalent replacement
To define.
Claims (10)
1. a kind of superjunction IGBT device structure characterized by comprising
First conductivity type substrate；
The second conductive type epitaxial layer on the first conductive type substrate is set；
The first conduction type cylindricality diffusion region in second conductive type epitaxial layer is set；
First conduction type well region, the first conduction type well region and the first conduction type cylindricality diffusion region are floating by one
Mined-out area isolation；
The first conduction type heavily doped region in the first conduction type well region is set；
Second conduction type heavily doped region；And
Grid.
2. superjunction IGBT device structure as described in claim 1, which is characterized in that first conductivity type substrate with a thickness of
1 micron to 20 microns.
3. superjunction IGBT device structure as described in claim 1, which is characterized in that the thickness of second conductive type epitaxial layer
Degree is 30 microns to 80 microns.
4. superjunction IGBT device structure as described in claim 1, which is characterized in that the distance in the floating area is less than 5 microns.
5. superjunction IGBT device structure as described in claim 1, which is characterized in that the first conduction type cylindricality diffusion region
Graphical ion implanting is combined to be formed by multiple epitaxial deposition.
6. superjunction IGBT device structure as described in claim 1, which is characterized in that the first conduction type cylindricality diffusion region
Embedment is deposited by deep plough groove etched the first conductive type epitaxial layer of combination to be formed.
7. superjunction IGBT device structure as described in claim 1, which is characterized in that the second conduction type heavy doping position
At the surface-boundary of the first conduction type heavily doped region.
8. superjunction IGBT device structure as described in claim 1, which is characterized in that the grid is conductive positioned at described second
Planar gate above type epitaxial layer.
9. superjunction IGBT device structure as described in claim 1, which is characterized in that the grid is to be embedded to second conduction
The groove of type epitaxial layer is embedded to grid.
10. superjunction IGBT device structure as described in claim 1, which is characterized in that further include:
Metal interconnection and dielectric layer above second conductive type epitaxial layer and the grid；And
Metal area below first conductivity type substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821740353.5U CN208819886U (en) | 2018-10-25 | 2018-10-25 | A kind of superjunction IGBT device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821740353.5U CN208819886U (en) | 2018-10-25 | 2018-10-25 | A kind of superjunction IGBT device structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208819886U true CN208819886U (en) | 2019-05-03 |
Family
ID=66280215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821740353.5U Expired - Fee Related CN208819886U (en) | 2018-10-25 | 2018-10-25 | A kind of superjunction IGBT device structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208819886U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109300978A (en) * | 2018-10-25 | 2019-02-01 | 上海超致半导体科技有限公司 | A kind of superjunction IGBT device structure and its manufacturing method |
| CN113871455A (en) * | 2021-09-28 | 2021-12-31 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113921595A (en) * | 2021-10-11 | 2022-01-11 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113937156A (en) * | 2021-10-11 | 2022-01-14 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
-
2018
- 2018-10-25 CN CN201821740353.5U patent/CN208819886U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109300978A (en) * | 2018-10-25 | 2019-02-01 | 上海超致半导体科技有限公司 | A kind of superjunction IGBT device structure and its manufacturing method |
| CN113871455A (en) * | 2021-09-28 | 2021-12-31 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113871455B (en) * | 2021-09-28 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113921595A (en) * | 2021-10-11 | 2022-01-11 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113937156A (en) * | 2021-10-11 | 2022-01-14 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113937156B (en) * | 2021-10-11 | 2023-07-04 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113921595B (en) * | 2021-10-11 | 2023-11-17 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208819886U (en) | A kind of superjunction IGBT device structure | |
| CN103456791B (en) | Groove power mosfet | |
| CN104517856B (en) | Semiconductor devices and its manufacture method with horizontal FET units and field plate | |
| CN101707210B (en) | Anti-radiation field effect transistor, CMOS integrated circuit and preparation thereof | |
| CN103187442B (en) | Integrated heterojunction semiconductor device and the method being used for producing this semiconductor device | |
| CN104733531A (en) | Dual oxide trench gate power mosfet using oxide filled trench | |
| CN104078462A (en) | Semiconductor device and manufacturing method thereof | |
| CN105914234A (en) | Separating gate power MOS transistor structure and manufacturing method therefor | |
| CN104347422A (en) | Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit | |
| CN103151310B (en) | Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof | |
| CN103681318A (en) | Method for manufacturing junction barrier schottky diode through selective oxidation of silicon | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN103094359A (en) | High voltage Schottky diode and manufacturing method thereof | |
| TW541630B (en) | Manufacture of trench-gate semiconductor devices | |
| US20130164915A1 (en) | Method for fabricating power semiconductor device with super junction structure | |
| CN102522335A (en) | Power device terminal ring production method and structure of terminal ring | |
| CN104253050B (en) | A kind of manufacture method of grooved lateral MOSFET device | |
| CN102737970B (en) | Semiconductor device and manufacturing method for gate dielectric layer thereof | |
| CN105977285A (en) | Semiconductor device and method of manufacturing the same | |
| CN108807502A (en) | A kind of manufacturing method of NLDMOS device and LDMOS power devices | |
| CN106298966A (en) | Semiconductor device and preparation method thereof and electronic installation | |
| CN102110687A (en) | Trench MOS (metal-oxide semiconductor) device | |
| CN102479816B (en) | Metal-oxide semiconductor type field-effect transistor and manufacturing method thereof | |
| CN109300978A (en) | A kind of superjunction IGBT device structure and its manufacturing method | |
| CN103779416B (en) | The power MOSFET device of a kind of low VF and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190503 Termination date: 20211025 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |