CN113937156B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113937156B
CN113937156B CN202111181712.4A CN202111181712A CN113937156B CN 113937156 B CN113937156 B CN 113937156B CN 202111181712 A CN202111181712 A CN 202111181712A CN 113937156 B CN113937156 B CN 113937156B
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region
substrate
doped
deep trench
ions
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CN113937156A (en
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潘嘉
杨继业
邢军军
陈冲
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises: a substrate doped with first ions; the deep trench structures are positioned in the substrate and are mutually independent, each deep trench structure comprises a first region, a second region and a blocking doped region between the first region and the second region, second ions are doped in the first region and the second region, the conductivity types of the second ions are opposite to those of the first ions, third ions are doped in the blocking doped region, and the conductivity types of the third ions are the same as those of the first ions; a body region within the substrate between adjacent deep trench structures; a gate structure located within the body region and the substrate; a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the blocking doped region; and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed from the bottom surface of the substrate, and the collector region is separated from the bottom of the deep trench structure by the substrate. To provide an insulated gate bipolar transistor that combines better voltage withstand, lower on-state voltage drop, and less turn-off loss.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In a medium-high power switching power supply device, an insulated gate bipolar transistor (Insulated Gate Bipolar transistor, abbreviated as IGBT) has the advantages of high input impedance, simple driving and high speed, and simultaneously has the advantages of low-on-state voltage drop and large capacity, so that the insulated gate bipolar transistor is widely applied to modern power electronic technology.
Fig. 1 is a schematic diagram of a prior art insulated gate bipolar transistor. As shown in fig. 1, the insulated gate bipolar transistor of the related art includes: a silicon substrate 10, wherein N-ions are doped in the silicon substrate 10, and the silicon substrate 10 is a drift region; the P+ doped region 11 is positioned at the bottom of the silicon substrate 10, and the P+ doped region 11 is a collector region; a P-well region 12 located within the silicon substrate 10; an n+ source region 13 located at the upper portion of the P-well region 12, the drift region and the n+ source region 13 being separated by the P-well region 12; the grid electrodes 14 are positioned at two sides of the P well region 12, the grid electrodes 14 are in contact with the side wall surfaces of the P well region 12 and the N+ source region 13, and a channel connecting the drift region and the emission region is formed in the region, close to the grid electrode 12, of the P well region 12 by inputting an opening signal to the grid electrode 12; a p+ connection layer 15 penetrating the n+ source region 13 and extending into the P well region 12, wherein the p+ connection layer 15 is used for leading out the P well region 12; an emitter conductive layer 16 located on the surface of the n+ source region 13 and the surface of the p+ connection layer 15.
However, with the development of integrated circuits, there is a higher demand for the performance of existing insulated gate bipolar transistors. Accordingly, there is a need for an insulated gate bipolar transistor that combines better voltage withstand, lower on-state voltage drop, and less turn-off loss (EOFF) to improve the performance of the insulated gate bipolar transistor of the prior art.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof to improve the performance of an insulated gate bipolar transistor.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate doped with first ions, the substrate having opposite top and bottom surfaces; the deep trench structures are arranged in the substrate and are mutually independent, the deep trench structures comprise a first region, a second region and a blocking doped region, the first region and the second region are arranged along the direction perpendicular to the top surface of the substrate, the top surface of the substrate exposes out of the surface of the first region, second ions are doped in the first region and the second region, the conductivity types of the second ions and the first ions are opposite, third ions are doped in the blocking doped region, and the conductivity types of the third ions and the first ions are the same; a body region in the substrate between adjacent deep trench structures, the body region being higher than the contact surface of the barrier doped region and the second region; a gate structure located within the body region and a substrate, a top surface of the substrate exposing a top surface of the gate structure; a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the blocking doped region; and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed out of the bottom surface of the substrate, and the collector region is separated from the bottom of the deep trench structure by the substrate.
Optionally, a minimum spacing between the barrier doped region and the surface of the first region exposed by the top surface of the substrate is above 1 micron.
Optionally, the height of the blocking doped region in a direction perpendicular to the top surface of the substrate ranges from 1 micron to 10 microns.
Optionally, a minimum distance between the contact surfaces of the blocking doped region and the second region and the body region in a direction perpendicular to the top surface of the substrate is greater than 0 microns and less than or equal to 3 microns.
Optionally, the doping concentration of the third ion is higher than the doping concentration of the first ion.
Optionally, the doping concentration of the third ion doped in the blocking doped region is in a range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
Optionally, the first ion and the third ion are N-type ions, and the second ion is P-type ion.
Optionally, a fourth ion is doped in the collector region, the fourth ion is a P-type ion, and the doping concentration of the fourth ion is greater than the doping concentration of the second ion.
Optionally, P-type ions are doped in the body region, and N-type ions are doped in the source region.
Optionally, the gate structure includes: the gate dielectric layer is positioned between the gate electrode and the substrate and between the gate electrode and the body region and the source region.
Optionally, the top surface of the substrate exposes surfaces of the body region and the source region, and the semiconductor structure further includes: the interlayer dielectric layer is positioned on the top surface of the substrate, the top surface of the grid structure, the exposed surfaces of the body region and the source region and the exposed surface of the first region on the top surface of the substrate; the first conductive structure is positioned in the interlayer dielectric layer and is connected with the grid structure; and the second conductive structure is positioned in the interlayer dielectric layer and is connected with the body region and the source region.
Optionally, the method further comprises: and a third conductive structure connected with the collector region.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate doped with first ions, the substrate having opposite top and bottom surfaces; forming a plurality of mutually independent deep trench structures in the substrate, wherein the deep trench structures comprise a first region, a second region and a blocking doped region arranged along the direction vertical to the top surface of the substrate, the first region surface is exposed out of the top surface of the substrate, second ions are doped in the first region and the second region, the conductivity types of the second ions and the first ions are opposite, third ions are doped in the blocking doped region, and the conductivity types of the third ions and the first ions are the same; after the deep trench structures are formed, a body region, a source region and a gate structure are formed in a substrate between the adjacent deep trench structures, the body region is higher than the contact surface of the blocking doped region and the second region, the gate structure is positioned in the body region and the substrate, the top surface of the substrate exposes the top surface of the gate structure, the source region is positioned in the body region between the gate structure and the deep trench structure, and the source region is higher than the blocking doped region; after the body region, the source region and the gate structure are formed, a collector region is formed at the bottom of the substrate, the bottom surface of the substrate exposes the collector region surface, and the collector region is spaced from the bottom of the deep trench structure by the substrate.
Optionally, the method for forming the plurality of independent deep trench structures in the substrate comprises the following steps: forming a plurality of initial deep trench structures which are mutually independent and doped with second ions in the substrate, wherein the initial deep trench structures comprise a first region, a second region and an initial blocking doped region between the first region and the second region, wherein the first region, the second region and the initial blocking doped region are arranged along the direction perpendicular to the top surface of the substrate; and performing ion implantation on the initial blocking doped region from the surface of the first region by adopting a high-energy ion implantation process to form the deep trench structure and the blocking doped region, wherein the implantation energy of the high-energy ion implantation process is higher than a preset first implantation energy.
Optionally, the method for forming the plurality of initial deep trench structures includes: forming a deep trench mask layer on the top surface of the substrate, wherein the deep trench mask layer exposes part of the top surface of the substrate; etching the substrate by taking the deep trench mask layer as a mask, and forming a plurality of mutually independent deep trenches in the substrate; forming the initial deep trench structure within the deep trench.
Optionally, the method for performing ion implantation on the initial blocking doped region from the surface of the first region by adopting a high-energy ion implantation process further comprises: and after the initial deep trench structure is formed, ion implantation is carried out on the initial blocking doped region from the surface of the first region by taking the deep trench mask layer as a mask.
Optionally, the preset first implantation energy is 2000KeV.
Optionally, the implantation energy of the high-energy ion implantation process is below 4000 KeV.
Optionally, the process parameters of the high-energy ion implantation process further include: the implantation dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
Optionally, the top surface of the substrate exposes surfaces of the body region and the source region, and the method for forming the semiconductor structure further includes: after forming the body region, the source region and the gate structure, and before forming the collector region, forming an interlayer dielectric layer on the top surface of the substrate, the top surface of the gate structure, the exposed surfaces of the body region and the source region, and the exposed surface of the first region on the top surface of the substrate; forming a first conductive structure in the interlayer dielectric layer, wherein the first conductive structure is connected with the grid structure; and forming a second conductive structure in the interlayer dielectric layer, wherein the second conductive structure is connected with the body region and the source region.
Optionally, the method further comprises: after the collector region is formed, a third conductive structure is formed on the collector region surface.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the semiconductor structure provided by the technical scheme of the invention, the deep trench structure is positioned in the substrate, and the second ions doped in the first region and the second region are opposite to the first ions doped in the substrate in conductivity type, so that the first region and the second region of the deep trench structure and the substrate part adjacent to the first region and the second region of the deep trench structure form the super junction structure. The superjunction structure can not only improve the device withstand voltage capability, but also increase the minority carrier concentration in the drift region (substrate) under the condition that the withstand voltage capability is maintained. On this basis, since the blocking doped region is doped with a third ion having the same conductivity type as the first ion (i.e., opposite to the second ion), and the body region is higher than the contact surface of the blocking doped region and the second region, the blocking doped region achieves physical isolation between the body region and the second region, and minority carriers injected from the collector region into the body region through the deep trench structure are blocked at a distance from the body region by the blocking doped region, thereby reducing minority carriers entering the body region. Thus, minority carriers injected from the collector region are better accumulated in the drift region (substrate) portion under the body region and the gate structure, and the minority carrier concentration of the entire drift region is increased. Therefore, the on-resistance of the drift region can be reduced, so that the on-state voltage drop of the insulated gate bipolar transistor is reduced, and meanwhile, the turn-off loss of the insulated gate bipolar transistor can be improved. In conclusion, the performance of the insulated gate bipolar transistor is improved.
Drawings
Fig. 1 is a schematic diagram of a prior art insulated gate bipolar transistor;
fig. 2 to 7 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, with the development of integrated circuits, there is a higher requirement on the performance of the existing insulated gate bipolar transistor. Therefore, there is a need for an insulated gate bipolar transistor that combines better voltage withstand, lower on-state voltage drop, and less turn-off loss.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a forming method thereof, wherein the formed semiconductor structure includes: a substrate doped with first ions, the substrate having opposite top and bottom surfaces; the deep trench structures are arranged in the substrate and are mutually independent, the deep trench structures comprise a first region, a second region and a blocking doped region, the first region and the second region are arranged along the direction perpendicular to the top surface of the substrate, the top surface of the substrate exposes out of the surface of the first region, second ions are doped in the first region and the second region, the conductivity types of the second ions and the first ions are opposite, third ions are doped in the blocking doped region, and the conductivity types of the third ions and the first ions are the same; a body region in the substrate between adjacent deep trench structures, the body region being higher than the contact surface of the barrier doped region and the second region; a gate structure located within the body region and a substrate, a top surface of the substrate exposing a top surface of the gate structure; a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the blocking doped region; and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed out of the bottom surface of the substrate, and the collector region is separated from the bottom of the deep trench structure by the substrate. Thus, an insulated gate bipolar transistor is provided that combines better voltage withstand, lower on-state voltage drop, and less turn-off loss.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2, a substrate 100 doped with first ions is provided, the substrate 100 having opposite top and bottom surfaces 101 and 102.
In this embodiment, the material of the substrate 100 includes a semiconductor material. Specifically, the material of the substrate 100 includes silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Among them, the iii-v group element-made multi-element semiconductor material includes InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the first ion is an N-type ion. Namely: the substrate 100 is an N-type substrate.
Specifically, the N-type ions include phosphorus ions or arsenic ions.
In another embodiment, the first ions may also be P-type ions to form a device structure having a conductivity type that is diametrically opposite to that of the present embodiment.
Next, a plurality of independent deep trench structures are formed in the substrate 100, wherein the deep trench structures comprise a first region, a second region and a blocking doped region between the first region and the second region, the first region is exposed from the top surface 101 of the substrate 100, the second region and the second region are doped with second ions, the conductivity types of the second ions and the first ions are opposite, and the blocking doped region is doped with third ions, and the conductivity types of the third ions and the first ions are the same. The step of forming the deep trench structure is shown in fig. 3 to 4.
Referring to fig. 3, a plurality of initial deep trench structures 110 are formed in the substrate 100 independently of each other.
The material of the initial deep trench structure 110 comprises a semiconductor material.
In this embodiment, the material of the initial deep trench structure 110 comprises silicon.
The initial deep trench structure 110 is doped with a second ion having a conductivity type opposite to that of the first ion.
In this embodiment, the second ion is a P-type ion.
Specifically, the P-type ions include boron ions or indium ions.
The initial deep trench structure 110 includes: a first region I, a second region II, and an initial blocking doped region a between the first region I and the second region II, arranged in a direction perpendicular to the top surface 101 of the substrate 100.
The initial blocking doped region A is used for forming a blocking doped region later.
In this embodiment, the method for forming the plurality of initial deep trench structures 110 includes: forming a deep trench mask layer 120 on the top surface 101 of the substrate 100, wherein the deep trench mask layer 120 exposes a portion of the top surface 101 of the substrate 100; etching the substrate 100 with the deep trench mask layer 120 as a mask, and forming a plurality of deep trenches (not shown) in the substrate 100, wherein the deep trenches are independent of each other; the initial deep trench structure 120 is formed within the deep trench.
In this embodiment, the material of the deep trench mask layer 120 includes photoresist.
In this embodiment, the process of etching the substrate 100 using the deep trench mask layer 120 as a mask includes at least one of a dry etching process and a wet etching process.
In this embodiment, the process of forming the initial deep trench structure 120 within the deep trench includes an epitaxial growth process.
Referring to fig. 4, an ion implantation is performed from the surface of the first region I to the initial blocking doped region a to form a deep trench structure 130 and a blocking doped region B.
Specifically, the deep trench structure 130 includes: the first region I, the second region II, and the blocking doped region B between the first region I and the second region II, which are arranged in a direction perpendicular to the top surface 101 of the substrate 100, the top surface 101 of the substrate 100 exposing the surface of the first region I.
And doping second ions in the first region I and the second region II, and doping third ions in the barrier doped region B, wherein the third ions have the same conductivity type as the first ions.
Since the deep trench structure 130 is located in the substrate 100 and the second ions doped in the first region I and the second region II are of opposite conductivity type to the first ions doped in the substrate 100, the first region I and the second region II of the deep trench structure 130 and the portion of the substrate 100 adjacent to the first region I and the second region II of the deep trench structure 130 constitute a Super Junction structure (Super Junction). The superjunction structure can not only improve the withstand voltage capability of an insulated gate bipolar transistor (hereinafter referred to as IGBT device), but also increase the minority carrier concentration in the drift region (substrate 100) under the condition that the withstand voltage capability is maintained.
Specifically, for the N-type substrate 100, the hole concentration of the drift region during turn-on is increased.
On this basis, the blocking doped region B achieves physical isolation between the body region and the second region II, since the blocking doped region B is doped with a third ion of the same conductivity type as the first ion (i.e., opposite to the second ion conductivity type), and the subsequently formed body region is higher than the contact surface 131 (shown in fig. 4) of the blocking doped region B and the second region I. Minority carriers (holes) injected from the collector region through the deep trench structure 130 into the body region are blocked by the blocking doped region B at a distance from the body region, thereby reducing minority carriers (holes) entering the body region. Further, minority carriers (holes) injected from the collector region are better accumulated in the body region and a drift region (substrate 100) portion under a gate structure formed later, and the minority carrier (hole) concentration of the entire drift region is increased. Therefore, the on-resistance of the drift region can be reduced, so that the on-state voltage drop of the IGBT device is reduced, and meanwhile, the turn-off loss of the IGBT device can be improved. In conclusion, the performance of the IGBT device is improved.
In this embodiment, the third ion is an N-type ion.
In this embodiment, the method for performing ion implantation on the initial blocking doped region a from the surface of the first region I includes: after the initial deep trench structure 130 is formed, the deep trench mask layer 120 is used as a mask, and a high-energy ion implantation process is used to perform ion implantation from the surface of the first region I to the initial blocking doped region a.
Compared with the formation of the blocking doped region and the region above the blocking doped region (the first region I) by an epitaxial growth process, the process difficulty of the high-energy ion implantation process is lower, so that the blocking doped region B having a certain minimum distance from the top surface (the surface of the first region I) of the initial deep trench structure 110 can be simply and efficiently formed in the initial deep trench structure 110 by adopting the high-energy ion implantation process. To effect formation of deep trench structure 130.
In this embodiment, the implantation energy of the high-energy ion implantation process is above a preset first implantation energy, so as to implement ion implantation of the initially blocking doped region a.
Specifically, the preset first injection energy is 2000KeV. That is, the implantation energy of the high-energy ion implantation process is 2000KeV or more.
The implantation energy of the high-energy ion implantation is too low to form a blocking doped region B at a preset initial blocking region a, namely: the minimum spacing between the formed blocking doped region B and the top surface of the deep trench structure 130 is too small. On the one hand, therefore, it is easy to cause the subsequently formed body region to be lower than the contact surface of the blocking doped region B and the second region II, so that the blocking doped region B cannot realize a better blocking of minority carriers (holes). On the other hand, the subsequently formed source region is easily contacted with the blocking doped region B, resulting in a short circuit between the source region and the substrate 100, which cannot be controlled by switching through the subsequently formed gate structure, thereby deteriorating the reliability of the IGBT device. Therefore, by making the implantation energy of the high-energy ion implantation process be more than 2000KeV, the blocking doped region B can realize better blocking of minority carriers (holes) and meanwhile, the reliability of the IGBT device is considered.
In this embodiment, the minimum distance H1 between the barrier doped region B and the surface of the first region I exposed by the top surface 101 of the substrate 100 is 1 μm or more. And, in a direction perpendicular to the top surface 101 of the substrate 100, the height range H2 (shown in fig. 4) of the barrier-doped region B is 1 to 10 micrometers.
Accordingly, the minimum spacing H3 (as shown in fig. 5) between the contact surfaces 131 of the barrier doped region B and the second region II and the body region in a direction perpendicular to the top surface 101 of the substrate 100 is greater than 0 microns and less than or equal to 3 microns.
In this embodiment, the implantation energy of the high-energy ion implantation process is 4000KeV or less.
The high energy ion implantation has too high energy, which increases the difficulty of the high energy ion implantation process. Therefore, by setting the implantation energy range of the high-energy ion implantation process to 4000KeV or less, the process difficulty of the high-energy ion implantation can be reduced.
In summary, when the implantation energy of the high-energy ion implantation process is between 2000KeV and 4000KeV, on one hand, the blocking doped region B can achieve better blocking of minority carriers (holes) and give consideration to the reliability of the IGBT device, and on the other hand, the difficulty of the high-energy ion implantation process is reduced.
In this embodiment, the doping concentration of the third ion is higher than the doping concentration of the first ion.
Since the doping concentration of the third ion is higher than that of the first ion, the blocking capability of the blocking doped region B for holes injected from the collector region to enter the body region is further improved.
Preferably, the doping concentration of the third ion doped in the blocking doped region B ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
In this embodiment, the process parameters of the high-energy ion implantation process further include: the implantation dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
The blocking doped region B in the above-described doping concentration range can be formed by making the implantation dose of the high-energy ion implantation process 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
In this embodiment, after the deep trench structure 130 is formed, the deep trench mask layer 120 is removed. The process of removing the deep trench mask layer 120 includes an ashing process and the like.
Referring to fig. 5, after the deep trench structures 130 are formed, body regions 140, source regions 150, and gate structures 160 are formed in the substrate 100 between adjacent deep trench structures 130.
In this embodiment, the body region 140 is higher than the contact surface 131 of the blocking doped region B and the second region II. The gate structure 160 is located within the body region 140 and the substrate 100, and the top surface 101 of the substrate 100 exposes the top surface of the gate structure 160. The source region 150 is located in the body region 140 between the gate structure 160 and the deep trench structure 130, and the source region 150 is higher than the blocking doped region B.
In this embodiment, the body region 140 is doped with P-type ions.
In this embodiment, the source region 150 is heavily doped with N-type ions.
In this embodiment, the gate structure 160 includes: a gate electrode and a gate dielectric layer between the gate electrode and the substrate 100 and between the gate electrode and the body 140 and source 150.
Specifically, the top surface 101 of the substrate 100 exposes the surfaces of the body region 140 and the source region 150.
In this embodiment, the method of forming the gate structure 160 includes: forming a first mask layer (not shown) on the surface of the substrate 100, wherein the first mask layer exposes a part of the surface of the substrate 100 between the adjacent deep trench structures 130; etching the substrate 100 by using the first mask layer as a mask, and forming a gate opening (not shown) in the substrate 100; forming a gate dielectric layer (not shown) on the inner wall surface of the gate opening; after forming the gate dielectric layer, a gate electrode is formed in the gate opening to form the gate structure 160.
In this embodiment, the method of forming the body region 140 and the source region 150 includes: performing ion implantation on the substrate 100 between the gate structure 160 and the deep trench structure 130 to form the body region 140, wherein the depth of the body region 140 is smaller than the height of the gate structure 160 in the direction perpendicular to the top surface 101 of the substrate 100; ion implantation is performed on a portion of the body region 140 between the gate structure 160 and the deep trench structure 130, and the source region 150 is formed in the body region 140.
In other embodiments, the body and source regions may also be formed prior to the gate structure.
Referring to fig. 6, an interlayer dielectric layer 170 is formed on the top surface 101 of the substrate 100, the top surface of the gate structure 160, the exposed surfaces of the body region 140 and the source region 150, and the exposed surface of the first region I on the top surface 101 of the substrate 100.
The material of the interlayer dielectric layer 170 includes a dielectric material.
In this embodiment, the process of forming the interlayer dielectric layer 170 includes a chemical vapor deposition process and the like.
With continued reference to fig. 6, a first conductive structure (not shown) is formed within the interlayer dielectric layer 170, and the first conductive structure is connected to the gate structure 160; a second conductive structure 180 is formed within the interlayer dielectric layer 170, and the second conductive structure 180 connects the body region 140 and the source region 150.
The first conductive structure is used to extract the gate structure 160 (the gate of the IGBT device).
The second conductive structure is used to lead out the body region 140 and the source region 150 (the emitter of the IGBT device).
In this embodiment, the method for forming the first conductive structure and the second conductive structure 180 in the interlayer dielectric layer 170 includes: forming a second mask layer (not shown) on the surface of the interlayer dielectric layer 170, wherein the second mask layer exposes a part of the surface of the interlayer dielectric layer 170; etching the interlayer dielectric layer 170 with the second mask layer as a mask until forming a first opening (not shown) exposing a portion of the top surface of the gate structure 160 and a second opening (not shown) exposing a portion of the top surfaces of the source region 150 and the body region 140; conductive material is filled in the first and second openings to form the first and second conductive structures 180.
In other embodiments, the first epitaxial layer may be patterned according to different mask layers, so as to form the first opening and the second opening respectively.
Next, referring to fig. 7, a collector region 190 is formed at the bottom of the substrate 100, the bottom surface 102 of the substrate 100 exposes the surface of the collector region 190, and the collector region 190 is spaced from the bottom of the deep trench structure 130 by the substrate 100.
In this embodiment, the collector region is doped with fourth ions.
Specifically, the fourth ion is a P-type ion, and the doping concentration of the fourth ion is greater than the doping concentration of the second ion.
In this embodiment, a wafer back thinning process is used to thin the substrate 100 from the bottom surface 102 of the substrate 100 prior to forming the collector region 190.
In this embodiment, the method of forming the collector region 190 includes: after the substrate 100 is thinned, an ion implantation process is performed on the bottom surface 102 of the substrate 100 to form a collector region 190 at the bottom of the substrate 100.
In this embodiment, after forming the collector region 190, a bottom interlayer dielectric layer (not shown) is formed on the bottom surface 102 of the substrate 100 and the exposed collector region 190 surface; a third conductive structure (not shown) is formed in the bottom interlayer dielectric layer, and is connected to the collector region 190 to lead out the collector region 190 (collector of the IGBT device).
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to fig. 7, which includes: a substrate 100 doped with first ions, the substrate 100 having opposite top and bottom surfaces 101, 102; a plurality of deep trench structures 130 located in the substrate 100 and independent of each other, wherein the deep trench structures 130 include a first region I, a second region II, and a blocking doped region B between the first region I and the second region II arranged along a direction perpendicular to a top surface 101 of the substrate 100, the top surface 101 of the substrate 100 exposes the surface of the first region I, the first region I and the second region II are doped with second ions, conductivity types of the second ions and the first ions are opposite, and the blocking doped region B is doped with third ions, and the third ions are the same as the first ions in conductivity type; a body region 140 located in the substrate 100 between adjacent deep trench structures 130, and the body region 140 is higher than the contact surface 131 of the barrier doped region B and the second region II; a gate structure 160 located within the body region 140 and the substrate 100, the top surface 101 of the substrate 100 exposing a top surface of the gate structure 160; a source region 150 located in the body region 140 between the gate structure 160 and the deep trench structure 130, the source region 150 being higher than the blocking doped region B; the collector region 190 is located at the bottom of the substrate 100, the bottom surface 102 of the substrate 100 exposes the collector region 190 surface, and the collector region 190 is spaced from the bottom of the deep trench structure 130 by the substrate 100.
Since the deep trench structure 130 is located within the substrate 100 and the second ions doped in the first region I and the second region II are of opposite conductivity type to the first ions doped in the substrate 100, the first region I and the second region II of the deep trench structure 130, and the portion of the substrate 100 adjacent to the first region I and the second region II of the deep trench structure 130, constitute a superjunction structure. The superjunction structure can not only improve the withstand voltage capability of the IGBT device, but also increase the minority carrier concentration in the drift region (substrate 100) while maintaining the withstand voltage capability.
On this basis, the blocking doped region B achieves physical isolation between the body region 140 and the second region II, since the blocking doped region B is doped with a third ion of the same conductivity type as the first ion (i.e., opposite to the second ion conductivity type) and the body region 140 is higher than the contact surface 131 of the blocking doped region B and the second region I. By blocking the doped region B, minority carriers injected from the collector region 190 through the deep trench structure 130 into the body region 140 are blocked at a distance from the body region 140, thereby reducing minority carriers entering the body region 140. Further, minority carriers injected from the collector region 190 are better accumulated in the body region 140 and the drift region (substrate 100) portion under the gate structure 160, and the minority carrier concentration of the entire drift region is increased. Therefore, the on-resistance of the drift region can be reduced, so that the on-state voltage drop of the IGBT device is reduced, and meanwhile, the turn-off loss of the IGBT device can be improved. In conclusion, the performance of the IGBT device is improved.
In some practical applications, the on-voltage drop (VCE) of an IGBT device formed of the semiconductor structure in this embodiment can be as low as 1.452 v.
In this embodiment, the material of the substrate 100 includes a semiconductor material. Specifically, the material of the substrate 100 includes silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Among them, the iii-v group element-made multi-element semiconductor material includes InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the first ion is an N-type ion. Namely: the substrate 100 is an N-type substrate. Thus, the minority carriers are holes. Specifically, the N-type ions include phosphorus ions or arsenic ions.
In another embodiment, the first ions may also be P-type ions to form a device structure having a conductivity type that is diametrically opposite to that of the present embodiment.
In this embodiment, the second ion is a P-type ion. Specifically, the P-type ions include boron ions or indium ions.
In this embodiment, the third ion is an N-type ion.
In this embodiment, P-type ions are doped in the body region 140, and N-type ions are heavily doped in the source region 150.
In this embodiment, the collector region 190 is doped with a fourth ion, the fourth ion is a P-type ion, and the doping concentration of the fourth ion is greater than the doping concentration of the second ion.
In this embodiment, the minimum distance H1 between the barrier doped region B and the surface of the first region I exposed by the top surface 101 of the substrate 100 is 1 μm or more.
If the minimum distance between the blocking doped region B and the top surface of the deep trench structure 130 is too small, the source region 150 is easily contacted with the blocking doped region B, so that the source region 150 and the substrate 100 are shorted and cannot be controlled by the gate structure 160, thereby deteriorating the reliability of the IGBT device. In addition, the minimum distance between the blocking doped region B and the top surface of the deep trench structure 130 is too small, which is disadvantageous in that the body region 140 is higher than the contact surface 131 of the blocking doped region B and the second region II, thereby resulting in a deterioration of the blocking ability of the blocking doped region B to minority carriers (holes). Therefore, by making the minimum distance H1 between the blocking doped region B and the surface of the first region I exposed by the top surface 101 of the substrate 100 be 1 μm or more, the reliability of the IGBT device can be better ensured while the blocking capability of the blocking doped region B against minority carriers (holes) is improved.
In this embodiment, the height range H2 of the barrier doped region B is 1 to 10 micrometers in a direction perpendicular to the top surface 101 of the substrate 100.
The height range H2 of the blocking doped region B is too small, which is disadvantageous in that the body region 140 is higher than the contact surface 131 of the blocking doped region B and the second region II, thereby resulting in a deterioration of the blocking ability of the blocking doped region B to minority carriers (holes). The height range H2 of the blocking doped region B is too large, so that the process difficulty of forming the blocking doped region B is increased, and the performance waste of the IGBT device is caused. Therefore, by adopting the proper height range H2, the blocking capability of the blocking doped region B to minority carriers (holes) can be improved, and the waste of the IGBT device in performance can be reduced.
Accordingly, the minimum spacing H3 between the contact surfaces 131 of the barrier doped region B and the second region II and the body region in a direction perpendicular to the top surface 101 of the substrate 100 is greater than 0 microns and less than or equal to 3 microns.
In this embodiment, the doping concentration of the third ion is higher than the doping concentration of the first ion.
Since the doping concentration of the third ion is higher than that of the first ion, the blocking ability of the blocking doped region B to holes injected from the collector region 190 into the body region 140 is further improved.
Preferably, the doping concentration of the third ion doped in the blocking doped region B ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
In this embodiment, the gate structure 160 includes: a gate electrode and a gate dielectric layer between the gate electrode and the substrate 100 and between the gate electrode and the body 140 and source 150.
Specifically, the top surface 101 of the substrate 100 exposes the surfaces of the body region 140 and the source region 150
In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 170 on the top surface 101 of the substrate 100, the top surface of the gate structure 160, the exposed surfaces of the body region 140 and the source region 150, and the exposed surface of the first region I on the top surface 101 of the substrate 100; a first conductive structure (not shown) within the interlayer dielectric layer 170, and the first conductive structure is connected to the gate structure 160; a second conductive structure 180 is located within the interlayer dielectric layer 170, and the second conductive structure 180 connects the body region 140 and the source region 150.
The material of the interlayer dielectric layer 170 includes a dielectric material.
The first conductive structure is used to extract the gate structure 160 (the gate of the IGBT device).
The second conductive structure is used to lead out the body region 140 and the source region 150 (the emitter of the IGBT device).
In this embodiment, the semiconductor structure further includes: a bottom interlayer dielectric layer (not shown) located on the bottom surface 102 of the substrate 100 and the surface of the exposed collector region 190; a third conductive structure (not shown) located in the bottom interlayer dielectric layer, and connected to the collector region 190 to lead out the collector region 190 (collector of the IGBT device).
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (21)

1. A semiconductor structure, comprising:
a substrate doped with first ions, the substrate having opposite top and bottom surfaces;
the deep trench structures are arranged in the substrate and are mutually independent, the deep trench structures comprise a first region, a second region and a blocking doped region, the first region and the second region are arranged along the direction perpendicular to the top surface of the substrate, the top surface of the substrate exposes out of the surface of the first region, second ions are doped in the first region and the second region, the conductivity types of the second ions and the first ions are opposite, third ions are doped in the blocking doped region, and the conductivity types of the third ions and the first ions are the same;
A body region in the substrate between adjacent deep trench structures, the body region being higher than the contact surface of the barrier doped region and the second region;
a gate structure located within the body region and a substrate, a top surface of the substrate exposing a top surface of the gate structure;
a source region located in the body region between the gate structure and the deep trench structure, the source region being higher than the blocking doped region;
and the collector region is positioned at the bottom of the substrate, the surface of the collector region is exposed out of the bottom surface of the substrate, and the collector region is separated from the bottom of the deep trench structure by the substrate.
2. The semiconductor structure of claim 1, wherein a minimum spacing between the barrier doped region and a surface of the first region exposed by a top surface of the substrate is greater than 1 micron.
3. The semiconductor structure of claim 2, wherein the barrier doped region has a height in a range of 1 micron to 10 microns in a direction perpendicular to the top surface of the substrate.
4. The semiconductor structure of claim 1, wherein a minimum spacing between a contact surface of the barrier doped region and the second region and the body region in a direction perpendicular to a top surface of the substrate is greater than 0 microns and less than or equal to 3 microns.
5. The semiconductor structure of claim 1, wherein a doping concentration of the third ion is higher than a doping concentration of the first ion.
6. The semiconductor structure of claim 5, wherein a doping concentration of the third ions doped within the blocking doped region ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
7. The semiconductor structure of claim 1, wherein the first and third ions are N-type ions and the second ion is a P-type ion.
8. The semiconductor structure of claim 7, wherein a fourth ion is doped in the collector region, the fourth ion is a P-type ion, and a doping concentration of the fourth ion is greater than a doping concentration of the second ion.
9. The semiconductor structure of claim 1, wherein P-type ions are doped in the body region and N-type ions are doped in the source region.
10. The semiconductor structure of claim 1, wherein the gate structure comprises: the gate dielectric layer is positioned between the gate electrode and the substrate and between the gate electrode and the body region and the source region.
11. The semiconductor structure of claim 1, wherein a top surface of the substrate exposes surfaces of the body and source regions, the semiconductor structure further comprising: the interlayer dielectric layer is positioned on the top surface of the substrate, the top surface of the grid structure, the exposed surfaces of the body region and the source region and the exposed surface of the first region on the top surface of the substrate; the first conductive structure is positioned in the interlayer dielectric layer and is connected with the grid structure; and the second conductive structure is positioned in the interlayer dielectric layer and is connected with the body region and the source region.
12. The semiconductor structure of claim 1, further comprising: and a third conductive structure connected with the collector region.
13. A method of forming a semiconductor structure, comprising:
providing a substrate doped with first ions, the substrate having opposite top and bottom surfaces;
forming a plurality of mutually independent deep trench structures in the substrate, wherein the deep trench structures comprise a first region, a second region and a blocking doped region arranged along the direction vertical to the top surface of the substrate, the first region surface is exposed out of the top surface of the substrate, second ions are doped in the first region and the second region, the conductivity types of the second ions and the first ions are opposite, third ions are doped in the blocking doped region, and the conductivity types of the third ions and the first ions are the same;
After the deep trench structures are formed, a body region, a source region and a gate structure are formed in a substrate between the adjacent deep trench structures, the body region is higher than the contact surface of the blocking doped region and the second region, the gate structure is positioned in the body region and the substrate, the top surface of the substrate exposes the top surface of the gate structure, the source region is positioned in the body region between the gate structure and the deep trench structure, and the source region is higher than the blocking doped region;
after the body region, the source region and the gate structure are formed, a collector region is formed at the bottom of the substrate, the bottom surface of the substrate exposes the collector region surface, and the collector region is spaced from the bottom of the deep trench structure by the substrate.
14. The method of forming a semiconductor structure of claim 13, wherein forming a plurality of independent deep trench structures in the substrate comprises: forming a plurality of initial deep trench structures which are mutually independent and doped with second ions in the substrate, wherein the initial deep trench structures comprise a first region, a second region and an initial blocking doped region between the first region and the second region, wherein the first region, the second region and the initial blocking doped region are arranged along the direction perpendicular to the top surface of the substrate; and performing ion implantation on the initial blocking doped region from the surface of the first region by adopting a high-energy ion implantation process to form the deep trench structure and the blocking doped region, wherein the implantation energy of the high-energy ion implantation process is higher than a preset first implantation energy.
15. The method of forming a semiconductor structure of claim 14, wherein the method of forming a plurality of initial deep trench structures comprises: forming a deep trench mask layer on the top surface of the substrate, wherein the deep trench mask layer exposes part of the top surface of the substrate; etching the substrate by taking the deep trench mask layer as a mask, and forming a plurality of mutually independent deep trenches in the substrate; forming the initial deep trench structure within the deep trench.
16. The method of forming a semiconductor structure of claim 15, wherein the method of ion implanting the initial blocking doped region from the first region surface using a high energy ion implantation process further comprises: and after the initial deep trench structure is formed, ion implantation is carried out on the initial blocking doped region from the surface of the first region by taking the deep trench mask layer as a mask.
17. The method of claim 14, wherein the predetermined first implant energy is 2000KeV.
18. The method of claim 17, wherein the high energy ion implantation process has an implantation energy of 4000KeV or less.
19. The method of forming a semiconductor structure of claim 18, wherein the process parameters of the high energy ion implantation process further comprise: the implantation dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter.
20. The method of forming a semiconductor structure of claim 13, wherein a top surface of the substrate exposes surfaces of the body and source regions, the method of forming a semiconductor structure further comprising: after forming the body region, the source region and the gate structure, and before forming the collector region, forming an interlayer dielectric layer on the top surface of the substrate, the top surface of the gate structure, the exposed surfaces of the body region and the source region, and the exposed surface of the first region on the top surface of the substrate; forming a first conductive structure in the interlayer dielectric layer, wherein the first conductive structure is connected with the grid structure; and forming a second conductive structure in the interlayer dielectric layer, wherein the second conductive structure is connected with the body region and the source region.
21. The method of forming a semiconductor structure of claim 13, further comprising: after the collector region is formed, a third conductive structure is formed on the collector region surface.
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