CN113838919B - Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof - Google Patents

Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof Download PDF

Info

Publication number
CN113838919B
CN113838919B CN202111116282.8A CN202111116282A CN113838919B CN 113838919 B CN113838919 B CN 113838919B CN 202111116282 A CN202111116282 A CN 202111116282A CN 113838919 B CN113838919 B CN 113838919B
Authority
CN
China
Prior art keywords
type
region
layer
gate electrode
charge storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111116282.8A
Other languages
Chinese (zh)
Other versions
CN113838919A (en
Inventor
张金平
朱镕镕
陈子珣
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN202111116282.8A priority Critical patent/CN113838919B/en
Publication of CN113838919A publication Critical patent/CN113838919A/en
Application granted granted Critical
Publication of CN113838919B publication Critical patent/CN113838919B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)

Abstract

The invention relates to a three-dimensional trench gate charge storage IGBT and a manufacturing method thereof. The reduction of the channel density and the advanced saturation of the NMOS channel reduce the saturation current density of the device and improve the short-circuit safe operating area (SCSOA) of the device. Meanwhile, the clamping of the PMOS can effectively reduce the gate capacitance and the gate charge, so that the switching speed of the device is improved, and the switching loss of the device and the requirement on the capability of a gate driving circuit are reduced. The distance between the PMOS channel and the NMOS channel is shortened, so that the clamping effect of the PMOS channel and the current uniformity in the chip are improved, and a wider Reverse Bias Safe Operating Area (RBSOA) is obtained.

Description

Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, relates to an Insulated Gate Bipolar Transistor (IGBT), and particularly relates to a three-dimensional trench gate charge storage type IGBT and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is used as a new generation of power electronic device, combines the advantages of a field effect transistor (MOSFET) and a bipolar crystallization transistor (BJT), has the advantages of easiness in driving, low input impedance and high switching speed of the MOSFET, and has the advantages of high on-state current density, low on-state voltage, low loss and good stability of the BJT. Therefore, the method is widely applied to various fields of traffic, communication, household appliances and aerospace, and becomes one of core electronic components in modern power electronic circuits. The use of IGBTs greatly improves the performance of power electronics systems.
Since the early IGBT of the last 80 years of the 70 th century of the 20 th century was invented, how to reduce the switching loss of the IGBT and improve the trade-off relationship between the on-voltage drop and the off-loss of the device has been the focus of research. Through the development of more than three decades, several generations of IGBT device structures including trench gate charge storage type IGBTs are sequentially proposed to continuously improve the performance of the device. The trench gate charge storage type IGBT introduces a hole potential barrier under the P type base region by introducing an N type charge storage layer with higher doping concentration and certain thickness under the P type base region, so that the surface carrier concentration is enhanced, the carrier distribution of a drift region of the device is improved, the conduction voltage drop of the device is reduced, and the trade-off relation between the conduction voltage drop and the switching loss of the device is optimized. However, the charge storage layer may degrade the breakdown voltage of the device. For the trench type IGBT, as the feature size of the semiconductor device is smaller and smaller, in order to improve the chip integration level and the current processing capability, the pitch between trenches is continuously reduced, however, as the channel density is increased, the gate capacitance, especially the miller capacitance, is obviously increased, the switching speed of the device is reduced, and the switching loss of the device is increased. Further, a large channel density also causes an increase in saturation current so that the short-circuit safe operation capability of the IGBT is deteriorated.
Disclosure of Invention
To improve the influence of degradation of breakdown characteristics of a charge storage type IGBT caused by the introduction of a charge storage layer, while reducing the adverse influence of saturation current and excessive gate capacitance due to a large channel density. The invention provides a three-dimensional trench gate charge storage type IGBT structure, and a schematic structure diagram of the three-dimensional trench gate charge storage type IGBT structure is shown in fig. 2. According to the invention, the P-type buried layer and the separation gate electrode which are equipotential with the emitter are introduced on the basis of the traditional trench gate charge storage type IGBT structure, and the influence of the doping concentration of the N-type charge storage layer on the breakdown characteristic of the device is eliminated through charge compensation by the P-type buried layer and the separation gate electrode, so that the breakdown voltage and the reliability of the device are improved. Therefore, the concentration of the N-type charge storage layer can be further improved, the carrier distribution of the device in forward conduction is improved, the conduction voltage drop is reduced, and the on-state loss is reduced. In addition, the separation gate electrode, the P-type base region/P+ emitter region, the N-type charge storage layer and the P-type buried layer form a parasitic PMOS structure, and because the gate electrode and the separation gate electrode are positioned in the same groove and are arranged at intervals along the Z-axis direction, the parasitic POMS structure exists in each cell, and the parasitic PMOS and NMOS channels of the IGBT are arranged at intervals along the Z-axis direction and are connected through the P-type base region and the N-type charge storage layer; meanwhile, the gate electrodes are distributed at intervals along the Z-axis direction, so that the channel density inside the chip can be reduced. The potential of the P-type buried layer and the N-type charge storage layer increases with the increase of the collector voltage, and the PMOS is turned on when the potential of the P-type buried layer increases to a certain value. So when the device is shorted, the collector voltage is the bus voltage so that the PMOS is turned on, at which time the potential of the N-type charge storage layer is clamped so that the NMOS channel enters the saturation region in advance, the reduction of channel density and the NMOS channel saturation in advance cause the device to have a small saturation current density and a wide short-circuit safe operating region (SCSOA). And the N-type charge storage layer is correspondingly in short circuit with the emitter when the PMOS is started along with the increase of the collector voltage, so that the grid-collector capacitance is converted into the grid-emitter capacitance, the grid-collector capacitance (Miller capacitance) is effectively reduced, the switching speed of the device is improved, and the switching loss is reduced. The gate capacitance is reduced, the gate charge of the device can be reduced, the driving is easy, the requirement on driving capability is reduced, and the driving loss is reduced. In addition, the introduced PMOS structure can accelerate the extraction of holes when the device is turned off, and further improves the trade-off relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff. According to the invention, the gate electrode and the separation gate electrode are arranged in the same groove in parallel along the Z axis, so that the channel distance between the parasitic PMOS and the NMOS is reduced, the clamping effect of the PMOS is improved, the current uniformity in the chip is improved, and the reliability of the device and the Reverse Bias Safe Operating Area (RBSOA) are improved.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a three-dimensional trench gate charge storage type IGBT device defines a 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device from the n+ emission region 3 to the gate electrode 71 as the X-axis direction, the direction from the P-type collector region 10 to the collector metal 11 as the Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as the Z-axis direction;
the device comprises collector metal 11, a P-type collector region 10, an N-type field stop layer 9 and an N-drift region 8 which are sequentially stacked from bottom to top along the Y-axis direction; the P-type buried layer 12 is positioned above the N-drift region 8, the P-type buried layer 12 is discontinuous along the Z-axis direction, the N-drift region 8 is arranged between the adjacent P-type buried layers 12 along the Z-axis direction, and the upper surface of the P-type buried layer 12 is flush with the upper surface of the N-drift region 8; an N-type charge storage layer 6 located over the N-drift region 8 and the P-type buried layer 12; a P-type base region 5 located above the N-type charge storage layer 6; the N+ emitter regions 3 and the P+ emitter regions 4 are alternately arranged above the P-type base region 5 along the Z-axis direction; an emitter metal 1 located above the n+ emitter region 3 and the p+ emitter region 4;
a groove structure is arranged above the N-drift region 8, the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74, the groove structure sequentially penetrates through the N+ emitter region 3, the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards from the surface of the device and then extends into the N-drift region 8, and the whole groove structure penetrates through the device along the Z-axis direction; the gate electrodes 71 and the separation gate electrodes 73 are alternately arranged in the Z-axis direction, and the length of the gate electrode 71 in the Z-axis direction is less than or equal to the length of the separation gate electrode 73; the gate electrode 71 and the separation gate electrode 73 are isolated by a gate dielectric layer 72; the gate electrode 71 passes through the N+ emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 downwards and enters the N-drift region 8, and the depth of the lower surface of the gate electrode 71 is larger than the junction depth of the P-type buried layer 12; the gate electrode 71 is connected with the N+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 and the N-drift region 8 through the gate dielectric layer 72; the separation gate electrode 73 passes through the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards and enters the N-drift region 8, and the depth of the lower surface of the separation gate electrode 73 is larger than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72; the separation gate electrode 73 is equipotential with the emitter metal 1.
The invention also provides a second three-dimensional trench gate charge storage IGBT device, which defines the 3-dimensional direction of the device by a 3-dimensional rectangular coordinate system: defining the direction of the device from the n+ emission region 3 to the gate electrode 71 as the X-axis direction, the direction from the P-type collector region 10 to the collector metal 11 as the Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as the Z-axis direction;
comprises a back collector metal 11, a P-type collector region 10, an N-type field stop layer 9 and an N-drift region 8 which are sequentially stacked from bottom to top along the Y-axis direction; the semiconductor device comprises a P-type buried layer 12 positioned above an N-drift region 8, wherein the P-type buried layer 12 is discontinuous along the X axis direction, the N-drift region 8 is arranged between adjacent P-type buried layers 12 along the X axis direction, and the upper surface of the P-type buried layer 12 is flush with the upper surface of the N-drift region 8; an N-type charge storage layer 6 located over the N-drift region 8 and the P-type buried layer 12; a P-type base region 5 located above the N-type charge storage layer 6; the N+ emitter regions 3 and the P+ emitter regions 4 are alternately arranged above the P-type base region 5 along the Z-axis direction; an emitter metal 1 located above the n+ emitter region 3 and the p+ emitter region 4;
a groove structure is arranged above the P-type buried layer 12, and the P-type buried layer 12 wraps the bottom of the groove in an L-shaped manner on an XY plane and isolates the groove structure from the N-drift region 8; the trench structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74, penetrates through an N+ emitter 3, a P+ emitter 4, a P-type base region 5 and an N-type charge storage layer 6 from the surface of the device downwards in sequence, extends into a P-type buried layer 12, and penetrates through the device along the Z-axis direction; the gate electrodes 71 and the separation gate electrodes 73 are alternately arranged in the Z-axis direction, and the length of the gate electrode 71 in the Z-axis direction is less than or equal to the length of the separation gate electrode 73; the gate electrode 71 and the separation gate electrode 73 are isolated by a gate dielectric layer 72; the gate electrode 71 passes through the N+ emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 downwards and enters the P-type buried layer 12, and the depth of the lower surface of the gate electrode 71 is larger than the junction depth of the N-type charge storage layer 6 and smaller than the junction depth of the P-type buried layer 12; the gate electrode 71 is connected with the N+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 through the gate dielectric layer 72; the separation gate electrode 73 passes through the P+ emitter region 4, the P-type base region 5 and the N-type charge storage layer 6 downwards and enters the P-type buried layer 12, and the depth of the lower surface of the separation gate electrode 73 is greater than the junction depth of the N-type charge storage layer 6 and less than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72; the separation gate electrode 73 is equipotential with the emitter metal 1.
The invention also provides a third three-dimensional trench gate charge storage IGBT device, which defines the 3-dimensional direction of the device by a 3-dimensional rectangular coordinate system: defining the direction of the device from the n+ emission region 3 to the gate electrode 71 as the X-axis direction, the direction from the P-type collector region 10 to the collector metal 11 as the Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as the Z-axis direction;
comprises a back collector metal 11, a P-type collector region 10, an N-type field stop layer 9 and an N-drift region 8 which are sequentially stacked from bottom to top along the Y-axis direction; a P-type buried layer 12 located above the N-drift region 8, wherein the P-type buried layer 12 is discontinuous along the Z-axis direction, an N-drift region 8 is arranged between adjacent P-type buried layers 12, and the upper surface of the P-type buried layer 12 is flush with the upper surface of the N-drift region 8; an N-type charge storage layer 6 located over the N-drift region 8 and the P-type buried layer 12; a P-type base region 5 located above the N-type charge storage layer 6; n+ emitter regions 3 which are arranged above the P-type base region 5 and distributed at intervals along the Z-axis direction, wherein the upper surface of the P-type base region 5,N + emitter region 3 is flush with the upper surface of the P-type base region 5 between two adjacent N+ emitter regions 3 along the Z-axis direction; an emitter metal 1 located above the n+ emitter region 3;
the Schottky contact metal 2 is located above the P-type base region 5; a groove structure is arranged above the N-drift region 8, the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74, the groove structure sequentially penetrates through the N+ emitter region 3, the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards from the surface of the device and then extends into the N-drift region 8, and the whole groove structure penetrates through the device along the Z-axis direction; the gate electrodes 71 and the separation gate electrodes 73 are alternately arranged in the Z-axis direction, and the relative positions of the gate electrodes 71 in the Z-axis direction are the same as those of the n+ emission region 3, and the length of the gate electrodes 71 in the Z-axis direction is less than or equal to the length of the separation gate electrodes 73; the gate electrode 71 and the separation gate electrode 73 are isolated by a gate dielectric layer 72; the gate electrode 71 passes down through the n+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 into the N-drift region 8; the gate electrode 71 is connected with the N+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 and the N-drift region 8 through the gate dielectric layer 72; the separation gate electrode 73 passes through the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards and enters the N-drift region 8, and the depth of the lower surface of the separation gate electrode 73 is larger than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72; the separation gate electrode 73 and the schottky contact metal 2 are equipotential with the emitter metal 1.
As a preferable mode, the device further comprises a P-type floating hollow area 13, wherein the P-type floating area 13 and the whole groove structure are arranged in parallel along the X axis, and the floating P-type floating area 13 is positioned outside the device along the X axis direction; the P-type floating region 13 is connected to the gate electrode 71 through the gate dielectric layer 72, and the P-type floating region 13 is connected to the separation gate electrode 73 through the separation gate dielectric layer 74.
Preferably, in the X-axis direction, the width of the gate electrode 71 plus the gate dielectric layer 72 is smaller than the entire trench width, the gate electrode 71 and the gate dielectric layer 72 are not connected to the floating P-type floating region 13, and a separation gate electrode 73 is provided in the middle, and the separation gate electrode 73 is connected to the P-type floating region 13 through the separation gate dielectric layer 74.
Preferably, the semiconductor device comprises a P-type floating hollow region 13, wherein the P-type floating hollow region 13 and the whole groove structure are arranged in parallel along the X direction, and the P-type floating hollow region 13 is positioned outside the device along the X axis direction; the P-type floating void 13 is connected with the gate electrode 71 through the gate dielectric layer 72 and is connected with the separation gate electrode 73 through the separation gate dielectric layer 74; the P-type buried layer 12 wraps the bottom of the trench in an L-shape on the XY plane, and the junction depth of the P-type floating region 13 is larger than the depth of the trench so that the P-type buried layer 12 and the P-type floating region 13 are connected.
Preferably, the doping concentration of the N-type charge storage layer 6 is graded from the region in contact with the trench structure, where the region in contact with the trench structure has the lowest doping concentration, to the intermediate region away from the trench, where the intermediate region away from the trench has the highest doping concentration.
Preferably, there are super junction P pillars 14 and super junction N pillars 15 arranged in parallel in the N-drift region 8; the super junction N column 15 is positioned below the N-type charge storage layer 6; the superjunction P-pillars 14 and superjunction N-pillars 15 meet the charge balance requirement.
The invention also provides a manufacturing method of the three-dimensional trench gate charge storage type IGBT device, which comprises the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer with the thickness of 200-300 mu m is selected to form an N-drift region 8 of the device, and the doping concentration of the N-drift region is 10 13 ～10 14 Individual/cm 3 ；
Step 2: manufacturing a terminal structure of a device on the front surface of a silicon wafer through preoxidation, photoetching, etching, ion implantation and annealing processes on the surface of the silicon wafer;
step 3: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, regrowing a pre-oxide layer, photoetching, and implanting P-type impurities to obtain a P-type buried layer 12, wherein the doping concentration of the P-type buried layer 12 is 10 15 ～10 16 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the An N-type charge storage layer 6 is prepared on the upper surface of the P-type buried layer 12 by ion implantation of N-type impurities, and the doping concentration of the N-type charge storage layer 6 is 10 15 ～10 17 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the P-type base region 5 is prepared on the upper surface of N-type charge storage layer 6 by ion implantation of P-type impurity and annealing treatment, and the doping concentration of P-type base region 5 is 10 16 ～10 17 /cm 3 ；
Step 4: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and further etching on the N-drift region 8 to form a separation gate groove, wherein the depth of the separation gate groove is larger than the junction depth of the P-type buried layer 12;
step 5: o at 1050-1150 DEG C 2 Forming a separation gate dielectric layer 74 on the inner wall of the groove under the atmosphere, wherein the thickness of the separation gate dielectric layer 74 is 0.1-0.5 mu m; then depositing polysilicon on the dielectric layer at 750-950 ℃, and then reversely etching off superfluous polysilicon on the surface to obtain a separated gate electrode 73;
step 6: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the polysilicon and the dielectric layer, and further etching the isolation gate grooves to form gate grooves, wherein the gate grooves are distributed at intervals along the Z-axis direction, isolation gate electrodes 73 are arranged between the gate grooves, and the depth of the gate grooves is larger than the junction depth of the P-type buried layer 12;
step 7: forming a gate dielectric layer 72 on the inner wall of the gate trench, wherein the thickness of the dielectric layer is 0.1-0.3 mu m; then, polysilicon is deposited in the gate groove and redundant polysilicon on the surface is reversely etched to prepare a gate electrode 71, the gate electrode 71 is isolated from a separation gate electrode 73 through a gate dielectric layer 72, and the thickness of the gate dielectric layer 72 is smaller than or equal to that of the separation gate dielectric layer 74;
Step 8: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region 5 through photoetching and ion injection processes, and preparing N+ emitter regions 3 and P+ emitter regions 4 which are alternately arranged along the Z-axis direction and mutually contacted; the junction depth of the N+ emission region 3 and the P+ emission region 4 is 0.2-0.5 mu m; one side of the N+ emission region 3 is connected with the gate electrode 71 along the X-axis direction through the gate dielectric layer 72; the p+ emission region 4 is connected with the separation gate electrode 73 along the X-axis direction of the device through the separation gate dielectric layer 74;
step 9: depositing metal with the thickness of 1-6 mu m on the surface of the device, and forming emitter metal 1 on the upper surfaces of the N+ emitter region 3 and the P+ emitter region 4 by adopting photoetching and etching processes;
step 10: turning over the silicon wafer, thinning the thickness of the silicon wafer, injecting N-type impurities into the back surface of the silicon wafer, manufacturing an N-type field stop layer 9 of the device through multiple laser annealing, wherein the thickness of the formed N-type field stop layer is 1-6 mu m, the ion injection energy is 40-500 KeV, and the injection dosage is 10 13 ～10 14 Individual/cm 2 ；
Step 11: p-type impurities are injected into the back surface of the N-type field stop layer 9 to form a P-type collector region 10, the thickness of the formed P-type collector region is 0.5-2 microns, the ion implantation energy is 30-100 keV, and the implantation dosage is 10 13 ～10 14 Individual/cm 2 Ion activation is carried out through multiple times of laser annealing, and metal with the thickness of 1-6 mu m is deposited on the back surface to form collector metal 11; thus, the preparation of the three-dimensional trench gate charge storage type IGBT is completed.
The working principle of the invention is detailed as follows:
to improve the influence of degradation of breakdown characteristics of a trench gate charge storage type IGBT device caused by the introduction of a charge storage layer, while reducing the adverse influence of saturation current and gate capacitance due to large channel density. The invention introduces the separation gate electrode 73 equipotential with the emitter metal on the basis of the traditional trench charge storage type IGBT, and enables the gate electrode 71 and the separation gate electrode 73 to be arranged at intervals along the Z-axis direction, meanwhile, the P-type buried layer 12 is introduced below the N-type charge storage layer, the P-type buried layer 12 is discontinuous along the Z-axis direction, and an N-drift region exists between the adjacent P-type buried layers. The P-type buried layer 12, the N-type charge storage layer 6, the P-type base region 5/p+ emitter region 4 and the split gate electrode 73 constitute a parasitic PMOS structure. When the device works in a blocking state, the PN junction between the P-type buried layer 12 and the drift region is reversely biased, so that the drift region 8 is depleted before the N-type charge storage layer 6 is depleted, and the electric field of the charge storage layer is shielded, and the equipotential of the separation gate electrode 73 and the emitter metal 1 is connected with a low potential, which is equivalent to providing negatively charged charges, so that the electric field of the charge storage layer 6 is effectively shielded by charge compensation, and the limitation of the doping concentration of the charge storage layer on the breakdown characteristic of the device is further improved. When the device works in the on state, the carrier distribution during forward conduction of the device can be improved by increasing the doping concentration of the charge storage layer 6, so that the conductivity modulation capability of the drift region 8 is improved, the forward conduction voltage drop of the device is reduced, the on-state loss of the device is reduced, and the trade-off relation between the forward conduction voltage drop Vceon and the off-state loss Eoff of the device is improved. The split gate electrode 73 is introduced in the middle of the gate electrode 71 in the Z-axis direction so that the gate electrodes 71 are arranged at intervals in the Z-axis direction, reducing the channel density of the entire chip. Meanwhile, the separated gate electrode and the gate electrode are positioned in the same groove, so that a parasitic POMS structure exists in each cell, and NMOS channels of the PMOS and the device are arranged at intervals along the Z-axis direction and are connected through the P-type base region 5 and the N-type charge storage layer 6. Wherein the potential of the P-type buried layer 12 and the N-type charge storage layer 6 increases with an increase in collector voltage, and the PMOS is turned on when the potential of the P-type buried layer 12 increases to a certain value. So when the device is shorted, the collector voltage is the bus voltage so that the PMOS is turned on, at which time the potential of the N-type charge storage layer is clamped so that the NMOS channel enters the saturation region in advance, the reduction of channel density and the NMOS channel saturation in advance cause the device to have a small saturation current density and a wide short-circuit safe operating region (SCSOA). And the N-type charge storage layer is correspondingly in short circuit with the emitter when the PMOS is turned on along with the increase of the collector voltage, so that partial grid-collector capacitance is converted into grid-emitter capacitance, the grid-collector capacitance (Miller capacitance) is greatly reduced, the switching speed of the device is improved, and the turn-off loss is reduced. The gate capacitance is reduced, the gate charge of the device can be reduced, the driving is easy, the requirement on driving capability is reduced, and the driving loss is reduced. In addition, the introduced PMOS structure can accelerate the extraction of holes when the device is turned off, and further improves the trade-off relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff. According to the invention, the gate electrode and the separation gate electrode are arranged in the same groove in parallel along the Z axis, so that the channel distance between the parasitic PMOS and the NMOS is reduced, the clamping effect of the PMOS is improved, the current uniformity in the chip is improved, and the reliability of the device and the Reverse Bias Safe Operating Area (RBSOA) are improved.
The beneficial effects of the invention are as follows:
according to the invention, the separation gate electrode and the P-type buried layer are introduced on the basis of the traditional trench charge storage type IGBT, so that adverse effects of the N-type charge storage layer on the breakdown characteristic of the device can be effectively eliminated. The breakdown voltage and the reliability of the device are improved, the carrier distribution of the drift region during forward conduction of the device can be improved, and the conduction voltage drop is reduced, so that the trade-off relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff is improved. According to the invention, the grid electrode and the separation grid electrode are arranged in the same groove at intervals along the Z-axis direction, so that the channel density in the chip is reduced, and meanwhile, the parasitic PMOS is started to saturate the NMOS channel in advance, so that the saturation current density is reduced, and the short-circuit safe operating area (SCSOA) of the device is improved. In addition, the opening of the PMOS can effectively reduce the gate capacitance and the gate charge, and the opening of the PMOS in the turn-off process can accelerate the extraction of holes, so that the switching speed of the device is improved, and the switching loss of the device and the requirement on the capability of a gate driving circuit are reduced. Since the distance between the parasitic PMOS and NMOS channels is shortened, this is advantageous for improving the clamping effect of PMOS and current uniformity inside the chip, resulting in high reliability and wide Reverse Bias Safe Operating Area (RBSOA).
Drawings
Fig. 1 is a schematic diagram of a half cell structure of a conventional trench gate charge storage type IGBT device;
fig. 2 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 1 of the invention;
fig. 3 is a schematic cross-sectional view of a half cell structure of the three-dimensional trench gate charge storage IGBT according to embodiment 1 of the present invention along line AB;
fig. 4 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 1 of the present invention along a CD line;
fig. 5 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 1 of the present invention along an EF line;
fig. 6 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 1 of the present invention along a GH line;
fig. 7 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 2 of the invention;
fig. 8 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 2 of the present invention along line AB;
fig. 9 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 2 of the present invention along a CD line;
fig. 10 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 2 of the present invention along an EF line;
Fig. 11 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 2 of the present invention along a GH line;
fig. 12 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 2 of the present invention along the IJ line;
fig. 13 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 3 of the invention;
fig. 14 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 3 of the invention along line AB;
fig. 15 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 3 of the present invention along a CD line;
fig. 16 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 3 of the present invention along an EF line;
fig. 17 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 3 of the present invention along a GH line;
fig. 18 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 4 of the invention;
fig. 19 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 4 of the invention along line AB;
Fig. 20 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 4 of the present invention along a CD line;
fig. 21 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 4 of the present invention along an EF line;
fig. 22 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 4 of the invention along a GH line;
fig. 23 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 5 of the invention;
fig. 24 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 5 of the invention along line AB;
fig. 25 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 5 of the present invention along a CD line;
fig. 26 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 5 of the present invention along an EF line;
fig. 27 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 5 of the invention along a GH line;
fig. 28 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 6 of the invention;
Fig. 29 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 6 of the invention along line AB;
fig. 30 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 6 of the invention along a CD line;
fig. 31 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 6 of the invention along an EF line;
fig. 32 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 6 of the invention along a GH line;
fig. 33 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 6 of the invention along the IJ line;
fig. 34 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 8 of the invention;
fig. 35 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 8 of the invention along line AB;
fig. 36 is a schematic cross-sectional view of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 8 of the invention along a CD line;
fig. 37 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 9 of the present invention after forming a P-type buried layer, an N-type charge storage layer, a P-type base region, and a split gate trench;
Fig. 38 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 9 of the present invention after a separation gate dielectric layer 74 is formed;
fig. 39 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 9 of the invention after polysilicon deposition to form a split gate electrode 73;
fig. 40 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 9 of the present invention after polysilicon and dielectric layer etching in a split gate electrode to form a gate trench;
fig. 41 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 9 of the present invention after forming a gate dielectric layer 72;
fig. 42 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 9 of the invention after forming split gate electrode 71;
fig. 43 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 9 of the present invention after forming the n+ emitter 3 and the p+ emitter 4;
fig. 44 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage IGBT according to embodiment 9 of the present invention after emitter metal 1 is formed on the upper surfaces of the n+ emitter region 3 and the p+ emitter region;
Fig. 45 is a schematic diagram of a half cell structure of a three-dimensional trench gate charge storage type IGBT according to embodiment 9 of the invention after all the steps are completed;
fig. 1 to 45,1 are emitter metals, 2 are schottky contact metals, 3 are n+ emitter regions, 4 are p+ emitter regions, 5 are P-type base regions, 6 are N-type charge storage layers, 71 are gate electrodes, 72 are gate dielectric layers, 73 are separation gate electrodes, 74 are separation gate dielectric layers, 8 are N-drift regions, 9 are N-type field stop layers, 10 are P-type collector regions, 11 are collector metals, 12 are P-type buried layers, 13 are P-type floating regions, 14 are superjunction P columns, and 15 are superjunction N columns.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1:
the three-dimensional trench gate charge storage type IGBT provided by the invention defines the 3-dimensional direction of a device by using a 3-dimensional rectangular coordinate system: defining the direction of the device from the n+ emission region 3 to the gate electrode 71 as the X-axis direction, the direction from the P-type collector region 10 to the collector metal 11 as the Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as the Z-axis direction;
The half cell structure and the cross section along the AB line, the CD line, the EF line and the GH line are shown in figures 2, 3, 4, 5 and 6,
the device comprises collector metal 11, a P-type collector region 10, an N-type field stop layer 9 and an N-drift region 8 which are sequentially stacked from bottom to top along the Y-axis direction; the P-type buried layer 12 is positioned above the N-drift region 8, the P-type buried layer 12 is discontinuous along the Z-axis direction, the N-drift region 8 is arranged between the adjacent P-type buried layers 12 along the Z-axis direction, and the upper surface of the P-type buried layer 12 is flush with the upper surface of the N-drift region 8; an N-type charge storage layer 6 located over the N-drift region 8 and the P-type buried layer 12; a P-type base region 5 located above the N-type charge storage layer 6; the N+ emitter regions 3 and the P+ emitter regions 4 are alternately arranged above the P-type base region 5 along the Z-axis direction; an emitter metal 1 located above the n+ emitter region 3 and the p+ emitter region 4;
a groove structure is arranged above the N-drift region 8, the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74, the groove structure sequentially penetrates through the N+ emitter region 3, the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards from the surface of the device and then extends into the N-drift region 8, and the whole groove structure penetrates through the device along the Z-axis direction; the gate electrodes 71 and the separation gate electrodes 73 are alternately arranged in the Z-axis direction, and the length of the gate electrode 71 in the Z-axis direction is less than or equal to the length of the separation gate electrode 73; the gate electrode 71 and the separation gate electrode 73 are isolated by a gate dielectric layer 72; the gate electrode 71 passes through the N+ emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 downwards and enters the N-drift region 8, and the depth of the lower surface of the gate electrode 71 is larger than the junction depth of the P-type buried layer 12; the gate electrode 71 is connected with the N+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 and the N-drift region 8 through the gate dielectric layer 72; the separation gate electrode 73 passes through the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards and enters the N-drift region 8, and the depth of the lower surface of the separation gate electrode 73 is larger than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72; the separation gate electrode 73 is equipotential with the emitter metal 1.
The semiconductor material used in this embodiment is silicon, and any suitable semiconductor material such as silicon, gallium nitride, etc. may be used in other embodiments. The thickness of the metallized electrode (emitter metal and collector metal) in the embodiment is 1-6 μm; the doping concentration of the N+ emitter region 3 is 5×10 18 cm -3 ～1×10 20 cm -3 The depth is 0.2-0.5 mu m; the doping concentration of the P+ emitter region 4 is 1×10 18 cm -3 ～1×10 19 cm -3 The depth is 0.2-0.5 mu m; the doping concentration of the P-type base region 5 is 1×10 16 cm -3 ～1×10 17 cm -3 The depth is 1-2.5 mu m; the doping concentration of the N-type charge storage layer 6 is 1×10 15 cm -3 ～1×10 17 cm -3 The depth is 1-2.5 mu m; the doping concentration of the P-type buried layer 12 is 1×10 16 cm -3 ～1×10 18 cm -3 The depth is 1-2.5 μm; the doping concentration of the N-type drift region 8 is 1×10 13 cm -3 ～1×10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the separation gate dielectric layer 74 is 0.1 to 0.5 μm; the thickness of the gate dielectric layer 72 is 0.1-0.3 mu m; the depth of the gate electrode is 5-7 mu m; the depth of the separation gate electrode 73 is 5 to 7 μm; the length of the gate electrode 71 in the Z-axis direction is 0.5 to 2 μm; the length of the separation gate electrode 73 in the Z-axis direction is 0.5 to 5 μm.
In addition, in the present embodiment, the length of the gate electrode 71 is less than or equal to the length of the split gate electrode 73, so that the channel density can be reduced, and the clamping effect of the PMOS can be made better; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72, which can improve the device reliability in the blocking state.
Example 2:
the three-dimensional trench gate charge storage type IGBT provided by the embodiment defines the 3-dimensional direction of the device by a 3-dimensional rectangular coordinate system: defining the direction of the device from the n+ emission region 3 to the gate electrode 71 as the X-axis direction, the direction from the P-type collector region 10 to the collector metal 11 as the Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as the Z-axis direction;
the half cell structure and the cross section along the line AB, CD, EF, GH and IJ are shown in figures 7, 8, 9, 10, 11 and 12,
comprises a back collector metal 11, a P-type collector region 10, an N-type field stop layer 9 and an N-drift region 8 which are sequentially stacked from bottom to top along the Y-axis direction; the semiconductor device comprises a P-type buried layer 12 positioned above an N-drift region 8, wherein the P-type buried layer 12 is discontinuous along the X axis direction, the N-drift region 8 is arranged between adjacent P-type buried layers 12 along the X axis direction, and the upper surface of the P-type buried layer 12 is flush with the upper surface of the N-drift region 8; an N-type charge storage layer 6 located over the N-drift region 8 and the P-type buried layer 12; a P-type base region 5 located above the N-type charge storage layer 6; the N+ emitter regions 3 and the P+ emitter regions 4 are alternately arranged above the P-type base region 5 along the Z-axis direction; an emitter metal 1 located above the n+ emitter region 3 and the p+ emitter region 4;
A groove structure is arranged above the P-type buried layer 12, and the P-type buried layer 12 wraps the bottom of the groove in an L-shaped manner on an XY plane and isolates the groove structure from the N-drift region 8; the trench structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74, penetrates through an N+ emitter 3, a P+ emitter 4, a P-type base region 5 and an N-type charge storage layer 6 from the surface of the device downwards in sequence, extends into a P-type buried layer 12, and penetrates through the device along the Z-axis direction; the gate electrodes 71 and the separation gate electrodes 73 are alternately arranged in the Z-axis direction, and the length of the gate electrode 71 in the Z-axis direction is less than or equal to the length of the separation gate electrode 73; the gate electrode 71 and the separation gate electrode 73 are isolated by a gate dielectric layer 72; the gate electrode 71 passes through the N+ emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 downwards and enters the P-type buried layer 12, and the depth of the lower surface of the gate electrode 71 is larger than the junction depth of the N-type charge storage layer 6 and smaller than the junction depth of the P-type buried layer 12; the gate electrode 71 is connected with the N+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 through the gate dielectric layer 72; the separation gate electrode 73 passes through the P+ emitter region 4, the P-type base region 5 and the N-type charge storage layer 6 downwards and enters the P-type buried layer 12, and the depth of the lower surface of the separation gate electrode 73 is greater than the junction depth of the N-type charge storage layer 6 and less than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72; the separation gate electrode 73 is equipotential with the emitter metal 1.
The semiconductor material used in this embodiment is silicon, and any suitable semiconductor material such as silicon, gallium nitride, etc. may be used in other embodiments. The thickness of the metallized electrode (emitter metal and collector metal) in the embodiment is 1-6 μm; the doping concentration of the N+ emitter region 3 is 5×10 18 cm -3 ～1×10 20 cm -3 The depth is 0.2-0.5 mu m; the doping concentration of the P+ emitter region 4 is 1×10 18 cm -3 ～1×10 19 cm -3 The depth is 0.2-0.5 mu m; the doping concentration of the P-type base region 5 is 1×10 16 cm -3 ～1×10 17 cm -3 The depth is 1-2.5 mu m; the doping concentration of the N-type charge storage layer 6 is 1×10 15 cm -3 ～1×10 17 cm -3 The depth is 1-2.5 mu m; the doping concentration of the P-type buried layer 12 is 1×10 16 cm -3 ～5×10 18 cm -3 The depth is 2-4 mu m; the doping concentration of the N-type drift region 8 is 1×10 13 cm -3 ～1×10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the separation gate dielectric layer 74 is 0.2 to 0.5 μm; the thickness of the gate dielectric layer 72 is 0.1-0.3 mu m; the depth of the gate electrode is 5-7 mu m; the depth of the separation gate electrode 73 is 5 to 7 μm; the length of the gate electrode 71 in the Z-axis direction is 0.5 to 2 μm; the length of the separation gate electrode 73 in the Z-axis direction is 0.5 to 5 μm.
In this embodiment, the P-type buried layer wraps the bottom of the trench in an "L" shape, so that the gate electrode is isolated from the N-drift region, which can shield the coupling effect between the gate electrode and the drift region, effectively reduce the gate capacitance, especially the gate-collector capacitance (miller capacitance), improve the switching speed, and reduce the switching loss. Meanwhile, the electric field concentration at the corner of the bottom of the groove can be relieved, and the breakdown voltage and the reliability are improved.
Example 3
The three-dimensional trench gate charge storage type IGBT provided by the invention defines the 3-dimensional direction of a device by using a 3-dimensional rectangular coordinate system: defining the direction of the device from the n+ emission region 3 to the gate electrode 71 as the X-axis direction, the direction from the P-type collector region 10 to the collector metal 11 as the Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as the Z-axis direction;
the half cell structure and the cross section along the AB line, the CD line, the EF line and the GH line are shown in figures 13, 14, 15, 16 and 17,
comprises a back collector metal 11, a P-type collector region 10, an N-type field stop layer 9 and an N-drift region 8 which are sequentially stacked from bottom to top along the Y-axis direction; a P-type buried layer 12 located above the N-drift region 8, wherein the P-type buried layer 12 is discontinuous along the Z-axis direction, an N-drift region 8 is arranged between adjacent P-type buried layers 12, and the upper surface of the P-type buried layer 12 is flush with the upper surface of the N-drift region 8; an N-type charge storage layer 6 located over the N-drift region 8 and the P-type buried layer 12; a P-type base region 5 located above the N-type charge storage layer 6; n+ emitter regions 3 which are arranged above the P-type base region 5 and distributed at intervals along the Z-axis direction, wherein the upper surface of the P-type base region 5,N + emitter region 3 is flush with the upper surface of the P-type base region 5 between two adjacent N+ emitter regions 3 along the Z-axis direction; an emitter metal 1 located above the n+ emitter region 3;
The Schottky contact metal 2 is located above the P-type base region 5; a groove structure is arranged above the N-drift region 8, the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74, the groove structure sequentially penetrates through the N+ emitter region 3, the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards from the surface of the device and then extends into the N-drift region 8, and the whole groove structure penetrates through the device along the Z-axis direction; the gate electrodes 71 and the separation gate electrodes 73 are alternately arranged in the Z-axis direction, and the relative positions of the gate electrodes 71 in the Z-axis direction are the same as those of the n+ emission region 3, and the length of the gate electrodes 71 in the Z-axis direction is less than or equal to the length of the separation gate electrodes 73; the gate electrode 71 and the separation gate electrode 73 are isolated by a gate dielectric layer 72; the gate electrode 71 passes down through the n+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 into the N-drift region 8; the gate electrode 71 is connected with the N+ emitter region 3, the P-type base region 5, the N-type charge storage layer 6 and the N-drift region 8 through the gate dielectric layer 72; the separation gate electrode 73 passes through the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards and enters the N-drift region 8, and the depth of the lower surface of the separation gate electrode 73 is larger than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P+ emitter region 4, the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72; the separation gate electrode 73 and the schottky contact metal 2 are equipotential with the emitter metal 1.
The semiconductor material used in this embodiment is silicon, and any suitable semiconductor material such as silicon, gallium nitride, etc. may be used in other embodiments. The thickness of the metallized electrode (emitter metal, collector metal, schottky contact metal) in this embodiment is 1-6 μm; the doping concentration of the N+ emitter region 3 is 5×10 18 cm -3 ～1×10 20 cm -3 The depth is 0.2-0.5 mu m; the doping concentration of the P-type base region 5 is 1×10 16 cm -3 ～1×10 17 cm -3 The depth is 1-3 mu m; the doping concentration of the N-type charge storage layer 6 is 1×10 15 cm -3 ～1×10 17 cm -3 The depth is 1-2.5 mu m; the doping concentration of the P-type buried layer 12 is 1×10 16 cm -3 ～5×10 18 cm -3 The depth is 1-2.5 μm; the doping concentration of the N-type drift region 8 is 2×10 14 cm -3 ～1×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the separation gate dielectric layer 74 is 0.1 to 0.5 μm; the thickness of the gate dielectric layer 72 is 0.1-0.3 mu m; the depth of the gate electrode is 5-7 mu m; the depth of the separation gate electrode 73 is 5 to 7 μm; the length of the gate electrode 71 in the Z-axis direction is 0.5 to 2 μm; the length of the separation gate electrode 73 in the Z-axis direction is 0.5 to 5 μm.
In the embodiment, the schottky contact metal 2 equipotential with the emitter metal 1 is introduced on the upper surface of the P-type base region 5, and the schottky contact metal 2 and the upper surface of the P-type base region 5 form schottky contact, so that the conduction voltage drop of the PMOS can be reduced, and the PMOS can be started more quickly. The clamping effect is better when the device is conducted in the forward direction, and the short circuit working safety area of the device is better improved; the switching speed of the device can be further improved when the device is turned off, and the switching loss of the device is reduced.
Example 4
The three-dimensional trench gate charge storage type IGBT has a half cell structure and cross sections along the AB line, the CD line, the EF line, and the GH line as shown in fig. 18, 19, 20, 21, and 22, respectively, and the P-type floating region 13 can be introduced by ion implantation based on embodiment 1 or 3, and the other structures are the same as those of embodiment 1 or 3.
The device also comprises a P-type floating hollow zone 13, wherein the P-type floating hollow zone 13 and the whole groove structure are arranged in parallel along the X axis, and the floating P-type floating hollow zone 13 is positioned outside the device along the X axis direction; the P-type floating region 13 is connected to the gate electrode 71 through the gate dielectric layer 72, and the P-type floating region 13 is connected to the separation gate electrode 73 through the separation gate dielectric layer 74.
Preferably, the lower surface of the P-type floating void 13 is equal to or greater than the depth of the groove, holes are accumulated on the surface when the device is conducted due to the introduction of the P-type floating void 13, and due to the charge balance principle, the accumulated holes can induce corresponding number of electrons, so that the conductivity modulation capability of the drift region is greatly enhanced, and the conduction voltage drop and conduction loss of the device are reduced.
Example 5
The three-dimensional trench gate charge storage type IGBT has a half cell structure and cross sections along AB line, CD line, EF line and GH line as shown in fig. 23, 24, 25, 26 and 27, respectively, in this embodiment, the gate trench etching is performed on the basis of embodiment 4, the opening size of the mask is adjusted during etching, the width of the gate electrode 71 in the X-axis direction is changed, and the width of the gate electrode 71 plus the gate dielectric layer 72 in the X-axis direction is smaller than the entire trench width, and the other structures are the same as embodiment 4.
The difference from example 4 is that: in the X-axis direction, the width of the gate electrode 71 plus the gate dielectric layer 72 is smaller than the whole trench width, the gate electrode 71 and the gate dielectric layer 72 are not connected with the floating P-type floating region 13, and a separation gate electrode 73 is arranged in the middle, and the separation gate electrode 73 is connected with the P-type floating region 13 through the separation gate dielectric layer 74.
By shielding the coupling effect between the gate electrode 71 and the floating P-type doped region 13 by the split gate electrode 73, the negative capacitance effect due to the displacement current of the floating P-type doped region is reduced. Thus, the grid-collector capacitance can be reduced to improve the switching speed of the device; and reducing the displacement current can improve the grid control capability and reduce the EMI noise.
Example 6
The three-dimensional trench gate charge storage type IGBT provided by the invention has a half cell structure and cross sections along an AB line, a CD line, an EF line, a GH line, and an IJ line as shown in fig. 28, 29, 30, 31, 32, and 33, and the P-type floating region 13 introduced by ion implantation can be formed on the basis of embodiment 2, and the junction depth of the P-type floating region 13 is greater than the depth of the trench structure, so that the P-type floating region 13 and the P-type buried layer 12 are in contact, and the other structures are the same as those of embodiment 2.
The difference from example 2 is that: the device comprises a P-type floating hollow area 13, wherein the P-type floating area 13 and the whole groove structure are arranged in parallel along the X direction, and the P-type floating area 13 is positioned outside the device along the X axis direction; the P-type floating void 13 is connected with the gate electrode 71 through the gate dielectric layer 72 and is connected with the separation gate electrode 73 through the separation gate dielectric layer 74; the P-type buried layer 12 wraps the bottom of the trench in an L-shape on the XY plane, and the junction depth of the P-type floating region 13 is larger than the depth of the trench so that the P-type buried layer 12 and the P-type floating region 13 are connected.
The introduction of the P-type floating empty area 13 causes the accumulation of holes on the surface when the device is conducted, and due to the charge balance principle, the accumulated holes can induce corresponding quantity of electrons, so that the conductivity modulation capability of the drift region is greatly enhanced, and the conduction voltage drop and conduction loss of the device are reduced.
In comparison with embodiment 4, this embodiment connects the P-type buried layer 12 and the P-type relief region 13. When the PMOS is turned on, the P-type floating region 13 is connected to the emitter through the PMOS, and the potential of the P-type floating region 13 can also be clamped, reducing the displacement current formed in the P-type floating region 13. The reduction of displacement current can weaken the coupling effect of the gate electrode and the P-type float 13, reduce the capacitance of the gate-collector electrode and improve the switching speed of the device; and the grid control capability can be improved, and the EMI noise can be reduced.
Example 7
A three-dimensional trench gate charge storage type IGBT in which the doping concentration of the N-type charge storage layer 6 is graded from the region in contact with the trench structure to the intermediate region away from the trench by the technique of varying doping or zonal doping, wherein the region in contact with the trench structure has the lowest doping concentration and the intermediate region away from the trench has the highest doping concentration.
According to the embodiment, the doping concentration of the N-type charge storage layer 6 close to the groove area is reduced, the threshold voltage of the PMOS can be reduced, so that the PMOS is started faster, the clamping effect is better when the PMOS is conducted in the forward direction, and the short-circuit working safety area of the device is better improved; the switching speed of the device can be further improved when the device is turned off, and the switching loss of the device is reduced. In the forward conduction, the grid electrode is connected with high potential, and an electron accumulation layer is formed at the position of the N-type charge storage layer close to the grid electrode, so that the forward conduction characteristic of the device is not affected.
EXAMPLE 8
The half cell structure and the cross sections along the AB line and the CD line of the trench gate charge storage type IGBT are shown in fig. 34, 35, and 36, respectively, and a superjunction P column 14 and a superjunction N column 15 arranged in parallel may be introduced into the N-drift region 8 on the basis of any one of embodiments 1 to 7, where the superjunction P column 14 and the superjunction N column 15 satisfy the charge balance requirement, and the doping concentration of the superjunction N column 15 is greater than or equal to the doping concentration of the N-drift region 8, and the other structures may be the same as those of embodiments 1 to 7.
In the embodiment, the super-junction P column 14 and the super-junction N column 15 are introduced into the drift region 8 to change the one-dimensional voltage resistance in the drift region into the two-dimensional voltage resistance, so that the compromise relation between the conduction voltage drop and the breakdown voltage of the device is improved, and the performance of the device is improved.
Example 9
In this embodiment, a 1200V voltage class IGBT with three-dimensional trench gate charge storage is taken as an example for illustration, and devices with different performance parameters can be prepared according to actual requirements according to common knowledge in the art.
Step 1: selecting an N-type lightly doped monocrystalline silicon wafer with the thickness of 200-300 mu m to form an N-drift region of a deviceThe doping concentration of the 8, N-drift region is 10 13 ～10 14 Individual/cm 3 ；
Step 2: manufacturing a terminal structure of a device on the front surface of a silicon wafer through preoxidation, photoetching, etching, ion implantation and high-temperature annealing processes on the surface of the silicon wafer;
Step 3: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, regrowing a pre-oxide layer, photoetching and implanting P-type impurities to obtain a P-type buried layer 12, wherein the P-type buried layer 12 is discontinuous along the Z-axis direction, an N-drift region 8 is arranged between the connected P-type buried layers 12, and the doping concentration of the P-type buried layer 12 is 10 15 ～10 16 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the An N-type charge storage layer 6 is prepared above the P-type buried layer by photoetching and ion implantation of N-type impurities, and the doping concentration of the N-type charge storage layer 6 is 10 15 ～10 17 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the P-type base region 5 is prepared above N-type charge storage layer 6 by ion implantation of P-type impurity and annealing treatment, and the doping concentration of P-type base region 5 is 10 16 ～10 17 /cm 3 ；
Step 4: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and further etching on the N-drift region 8 to form a separation gate groove, wherein the depth of the separation gate groove is larger than the junction depth of the P-type buried layer 12, as shown in figure 37;
step 5: forming a dielectric layer as a separation gate dielectric layer 74 on the inner wall of the groove in an O2 atmosphere at 1050-1150 ℃, wherein the thickness of the dielectric layer 74 is 0.1-0.5 mu m as shown in figure 38; then depositing polysilicon on the dielectric layer at 750-950 ℃, and then back-etching off superfluous polysilicon on the surface to obtain a separated gate electrode 73, as shown in fig. 39;
Step 6: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the polysilicon and the dielectric layer, and further etching in the separation gate groove to form a gate groove, wherein the gate groove is discontinuous along the Z-axis direction, and a separation gate electrode 73 is arranged between adjacent gate grooves, as shown in an attached figure 40;
step 7: forming a gate dielectric layer 72 on the inner wall of the gate trench, wherein the thickness of the dielectric layer 72 is 0.1-0.3 μm as shown in fig. 41; then polysilicon is deposited in the gate trench, and then the surface redundant polysilicon is reversely etched to prepare a gate electrode 71, the gate electrode is arranged side by side with a separation gate electrode 73 along the Z-axis direction and is mutually independent, the gate electrode 71 and the separation gate electrode 73 are separated by a gate dielectric layer 72, and the thickness of the dielectric layer 72 is smaller than or equal to that of a dielectric layer 74, as shown in figure 42;
step 8: n-type impurities and P-type impurities are respectively injected into the top layer of the P-type base region 5 through photoetching and ion injection processes to form N+ emitter regions 3 and P+ emitter regions 4 which are alternately arranged along the Z-axis direction and mutually contacted, as shown in figure 43, the N+ emitter regions 3 are connected with a gate electrode 71 through a gate dielectric layer 72, the junction depth of the N+ emitter regions 3 is 0.2-0.5 mu m, and the doping concentration of the N+ emitter regions 3 is 10 18 ～10 19 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The P+ emission region 4 and the separation gate electrode 73 are connected by a separation gate dielectric layer 74, the junction depth of the P+ emission region 4 is 0.2-0.5 μm, and the doping concentration of the P+ emission region 4 is 10 18 ～10 19 /cm 3 ；
Step 9: depositing metal with the thickness of 1-6 mu m on the surface of the device, and forming emitter metal 1 on the upper surfaces of the N+ emitter region 3, the P+ emitter region 4 and the upper surface by adopting photoetching and etching processes, as shown in figure 44;
step 10: turning over the silicon wafer, thinning the thickness of the silicon wafer, injecting N-type impurities into the back surface of the silicon wafer, adopting multiple laser annealing to manufacture an N-type field stop layer 9 of the device, forming the N-type field stop layer with the thickness of 1-5 mu m, and injecting the ion with the energy of 40-1000 KeV and the injection dosage of 10 KeV 13 ～10 14 Individual/cm 2 ；
Step 11: p-type impurities are injected into the back surface of the N-type field stop layer 9 to form a P-type collector region 10, the thickness of the formed P-type collector region is 0.5-2 microns, the ion implantation energy is 30-100 keV, and the implantation dosage is 10 13 ～10 14 Individual/cm 2 The collector metal 11 is formed by laser annealing and back deposition of a metal 1-6 μm thick, as shown in fig. 45. Thus, the preparation of the three-dimensional trench gate charge storage type IGBT is completed.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.

Claims (9)

1. A three-dimensional trench gate charge storage type IGBT device defines a 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device from the N+ emission region (3) to the gate electrode (71) as an X-axis direction, the direction of the device from the P-type collector region (10) to the collector metal (11) as a Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as a Z-axis direction;
the device comprises collector metal (11), a P-type collector region (10), an N-type field stop layer (9) and an N-drift region (8) which are sequentially stacked from bottom to top along the Y-axis direction; the P-type buried layers (12) are located above the N-drift regions (8), the P-type buried layers (12) are discontinuous along the Z-axis direction, the N-drift regions (8) are arranged between the adjacent P-type buried layers (12) along the Z-axis direction, and the upper surfaces of the P-type buried layers (12) are flush with the upper surface of the N-drift regions (8); an N-type charge storage layer (6) located above the N-drift region (8) and the P-type buried layer (12); a P-type base region (5) located above the N-type charge storage layer (6); n+ emitter regions (3) and P+ emitter regions (4) are alternately arranged above the P-type base region (5) along the Z-axis direction; an emitter metal (1) located above the n+ emitter region (3) and the p+ emitter region (4);
the method is characterized in that: a groove structure is arranged above the N-drift region (8), the groove structure comprises a gate electrode (71), a gate dielectric layer (72), a separation gate electrode (73) and a separation gate dielectric layer (74), the groove structure sequentially penetrates through the N+ emitter region (3), the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6) and the P-type buried layer (12) downwards from the surface of the device and then extends into the N-drift region (8), and the whole groove structure penetrates through the device along the Z-axis direction; the gate electrodes (71) and the separation gate electrodes (73) are alternately arranged along the Z-axis direction, and the length of the gate electrodes (71) along the Z-axis direction is less than or equal to the length of the separation gate electrodes (73); the gate electrode (71) and the separation gate electrode (73) are isolated by a gate dielectric layer (72); the gate electrode (71) downwards passes through the N+ emitter region (3), the P-type base region (5) and the N-type charge storage layer (6) to enter the N-drift region (8), and the depth of the lower surface of the gate electrode (71) is larger than the junction depth of the P-type buried layer (12); the gate electrode (71) is connected with the N+ emission region (3), the P-type base region (5), the N-type charge storage layer (6) and the N-drift region (8) through the gate dielectric layer (72); the separation gate electrode (73) downwards passes through the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6) and the P-type buried layer (12) to enter the N-drift region (8), and the depth of the lower surface of the separation gate electrode (73) is larger than the junction depth of the P-type buried layer (12); the separation gate electrode (73) is connected with the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6), the P-type buried layer (12) and the N-drift region (8) through the separation gate dielectric layer (74); the thickness of the separation gate dielectric layer (74) is greater than or equal to the thickness of the gate dielectric layer (72); the gate electrode (73) is separated from the emitter metal (1) by equipotential.
2. A three-dimensional trench gate charge storage type IGBT device defines a 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device from the N+ emission region (3) to the gate electrode (71) as an X-axis direction, the direction of the device from the P-type collector region (10) to the collector metal (11) as a Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as a Z-axis direction;
the device comprises a back collector metal (11), a P-type collector region (10), an N-type field stop layer (9) and an N-drift region (8) which are sequentially stacked from bottom to top along the Y-axis direction; the semiconductor device comprises a P-type buried layer (12) positioned above an N-drift region (8), wherein the P-type buried layer (12) is discontinuous along the X-axis direction, the N-drift region (8) is arranged between adjacent P-type buried layers (12) along the X-axis direction, and the upper surface of the P-type buried layer (12) is flush with the upper surface of the N-drift region (8); an N-type charge storage layer (6) located above the N-drift region (8) and the P-type buried layer (12); a P-type base region (5) located above the N-type charge storage layer (6); n+ emitter regions (3) and P+ emitter regions (4) are alternately arranged above the P-type base region (5) along the Z-axis direction; an emitter metal (1) located above the n+ emitter region (3) and the p+ emitter region (4);
the method is characterized in that: a groove structure is arranged above the P-type buried layer (12), and the P-type buried layer (12) wraps the bottom of the groove in an L-shaped manner on an XY plane and isolates the groove structure from the N-drift region (8); the trench structure comprises a gate electrode (71), a gate dielectric layer (72), a separation gate electrode (73) and a separation gate dielectric layer (74), the trench structure sequentially penetrates through an N+ emitter region (3), a P+ emitter region (4), a P-type base region (5) and an N-type charge storage layer (6) downwards from the surface of the device and then extends into a P-type buried layer (12), and the whole trench structure penetrates through the device along the Z-axis direction; the gate electrodes (71) and the separation gate electrodes (73) are alternately arranged along the Z-axis direction, and the length of the gate electrodes (71) along the Z-axis direction is less than or equal to the length of the separation gate electrodes (73); the gate electrode (71) and the separation gate electrode (73) are isolated by a gate dielectric layer (72); the gate electrode (71) downwards passes through the N+ emitter region (3), the P-type base region (5) and the N-type charge storage layer (6) to enter the P-type buried layer (12), and the depth of the lower surface of the gate electrode (71) is larger than the junction depth of the N-type charge storage layer (6) and smaller than the junction depth of the P-type buried layer (12); the gate electrode (71) is connected with the N+ emitter region (3), the P-type base region (5), the N-type charge storage layer (6) and the P-type buried layer (12) through the gate dielectric layer (72); the separation gate electrode (73) downwards passes through the P+ emitter region (4), the P-type base region (5) and the N-type charge storage layer (6) to enter the P-type buried layer (12), and the depth of the lower surface of the separation gate electrode (73) is larger than the junction depth of the N-type charge storage layer (6) and smaller than the junction depth of the P-type buried layer (12); the separation gate electrode (73) is connected with the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6) and the P-type buried layer (12) through the separation gate dielectric layer (74); the thickness of the separation gate dielectric layer (74) is greater than or equal to the thickness of the gate dielectric layer (72); the gate electrode (73) is separated from the emitter metal (1) by equipotential.
3. The three-dimensional trench gate charge storage IGBT device of claim 2 wherein: the device comprises a P-type floating void area (13), wherein the P-type floating void area (13) and the whole groove structure are arranged in parallel along the X direction, and the P-type floating void area (13) is positioned outside the device along the X axis direction; the P-type floating zone (13) is connected with the gate electrode (71) through the gate dielectric layer (72), and is connected with the separation gate electrode (73) through the separation gate dielectric layer (74); the P-type buried layer (12) wraps the bottom of the groove in an L-shaped manner on an XY plane, and the junction depth of the P-type floating region (13) is larger than the depth of the groove so that the P-type buried layer (12) and the P-type floating region (13) are connected.
4. A three-dimensional trench gate charge storage type IGBT device defines a 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device from the N+ emission region (3) to the gate electrode (71) as an X-axis direction, the direction of the device from the P-type collector region (10) to the collector metal (11) as a Y-axis direction, and the direction perpendicular to the X-axis and the Y-axis as a Z-axis direction;
the device comprises a back collector metal (11), a P-type collector region (10), an N-type field stop layer (9) and an N-drift region (8) which are sequentially stacked from bottom to top along the Y-axis direction; the P-type buried layers (12) are located above the N-drift regions (8), the P-type buried layers (12) are discontinuous along the Z-axis direction, the N-drift regions (8) are arranged between the adjacent P-type buried layers (12), and the upper surfaces of the P-type buried layers (12) are flush with the upper surface of the N-drift regions (8); an N-type charge storage layer (6) located above the N-drift region (8) and the P-type buried layer (12); a P-type base region (5) located above the N-type charge storage layer (6); n+ emitter regions (3) which are arranged above the P-type base region (5) and distributed at intervals along the Z-axis direction, wherein the P-type base region (5) is arranged between two adjacent N+ emitter regions (3) along the Z-axis direction, and the upper surface of the N+ emitter region (3) is flush with the upper surface of the P-type base region (5); an emitter metal (1) located above the n+ emitter region (3);
The method is characterized in that: the Schottky contact metal (2) is positioned above the P-type base region (5); a groove structure is arranged above the N-drift region (8), the groove structure comprises a gate electrode (71), a gate dielectric layer (72), a separation gate electrode (73) and a separation gate dielectric layer (74), the groove structure sequentially penetrates through the N+ emitter region (3), the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6) and the P-type buried layer (12) downwards from the surface of the device and then extends into the N-drift region (8), and the whole groove structure penetrates through the device along the Z-axis direction; the grid electrodes (71) and the separation grid electrodes (73) are alternately arranged along the Z-axis direction, the relative positions of the grid electrodes (71) along the Z-axis direction are the same as those of the N+ emission region (3), and the length of the grid electrodes (71) along the Z-axis direction is less than or equal to the length of the separation grid electrodes (73); the gate electrode (71) and the separation gate electrode (73) are isolated by a gate dielectric layer (72); the gate electrode (71) passes through the N+ emission region (3), the P-type base region (5) and the N-type charge storage layer (6) downwards and enters the N-drift region (8); the gate electrode (71) is connected with the N+ emission region (3), the P-type base region (5), the N-type charge storage layer (6) and the N-drift region (8) through the gate dielectric layer (72); the separation gate electrode (73) downwards passes through the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6) and the P-type buried layer (12) to enter the N-drift region (8), and the depth of the lower surface of the separation gate electrode (73) is larger than the junction depth of the P-type buried layer (12); the separation gate electrode (73) is connected with the P+ emitter region (4), the P-type base region (5), the N-type charge storage layer (6), the P-type buried layer (12) and the N-drift region (8) through the separation gate dielectric layer (74); the thickness of the separation gate dielectric layer (74) is greater than or equal to the thickness of the gate dielectric layer (72); the gate electrode (73) and the Schottky contact metal (2) are separated from the emitter metal (1) by equipotential.
5. A three-dimensional trench gate charge storage IGBT device according to any one of claims 1 or 4 wherein: the device also comprises a P-type floating hollow area (13), wherein the P-type floating hollow area (13) and the whole groove structure are arranged in parallel along the X axis, and the floating P-type floating hollow area (13) is positioned outside the device along the X axis direction; the P-type floating zone (13) is connected with the gate electrode (71) through the gate dielectric layer (72), and the P-type floating zone (13) is connected with the separation gate electrode (73) through the separation gate dielectric layer (74).
6. The three-dimensional trench gate charge storage IGBT device of claim 5 wherein: in the X-axis direction, the width of the gate electrode (71) plus the gate dielectric layer (72) is smaller than the whole width of the groove, the gate electrode (71) and the gate dielectric layer (72) are not connected with the floating P-type floating zone (13), a separation gate electrode (73) is arranged in the middle of the floating P-type floating zone, and the separation gate electrode (73) is connected with the P-type floating zone (13) through the separation gate dielectric layer (74).
7. A three-dimensional trench gate charge storage IGBT device according to any one of claims 1 to 4 wherein: the doping concentration of the N-type charge storage layer (6) is graded from a region in contact with the trench structure to a middle region away from the trench, wherein the region in contact with the trench structure has the lowest doping concentration and the middle region away from the trench has the highest doping concentration.
8. A three-dimensional trench gate charge storage IGBT device according to any one of claims 1 to 4 wherein: the N-drift region (8) is provided with a super junction P column (14) and a super junction N column (15) which are arranged in parallel; the super junction N column (15) is positioned below the N-type charge storage layer (6); the super junction P column (14) and the super junction N column (15) meet the charge balance requirement.
9. The manufacturing method of the three-dimensional trench gate charge storage type IGBT device is characterized by comprising the following steps of:
step 1: an N-type lightly doped monocrystalline silicon wafer with the thickness of 200-300 mu m is selected to form an N-drift region (8) of the device, and the doping concentration of the N-drift region is 10 13 ～10 14 Individual/cm 3 ；
Step 2: manufacturing a terminal structure of a device on the front surface of a silicon wafer through preoxidation, photoetching, etching, ion implantation and annealing processes on the surface of the silicon wafer;
step 3: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, regrowing a pre-oxide layer, photoetching, and implanting P-type impurities to obtain a P-type buried layer (12), wherein the doping concentration of the P-type buried layer (12) is 10 15 ～10 16 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the An N-type charge storage layer (6) is prepared on the upper surface of the P-type buried layer (12) by ion implantation of N-type impurities, and the doping concentration of the N-type charge storage layer (6) is 10 15 ～10 17 /cm 3 The method comprises the steps of carrying out a first treatment on the surface of the P-type impurities are injected into the upper surface of the N-type charge storage layer (6) and annealed to prepare a P-type base region (5), and the doping concentration of the P-type base region (5) is 10 16 ～10 17 /cm 3 ；
Step 4: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and further etching on the N-drift region (8) to form a separation gate groove, wherein the depth of the separation gate groove is larger than the junction depth of the P-type buried layer (12);
step 5: o at 1050-1150 DEG C 2 Forming a separation gate dielectric layer (74) on the inner wall of the groove under the atmosphere, wherein the thickness of the separation gate dielectric layer (74) is 0.1-0.5 mu m; then depositing polysilicon on the dielectric layer at 750-950 ℃, and then reversely etching off superfluous polysilicon on the surface to prepare a separation gate electrode (73);
step 6: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the polysilicon and the dielectric layer, and further etching the isolation gate grooves to form gate grooves, wherein the gate grooves are distributed at intervals along the Z-axis direction, isolation gate electrodes (73) are arranged between the gate grooves, and the depth of the gate grooves is larger than the junction depth of the P-type buried layer (12);
step 7: forming a gate dielectric layer (72) on the inner wall of the gate trench, wherein the thickness of the dielectric layer is 0.1-0.3 mu m; then, polysilicon is deposited in the gate groove and redundant polysilicon on the surface is reversely etched to prepare a gate electrode (71), the gate electrode (71) is isolated from the separation gate electrode (73) through a gate dielectric layer (72), and the thickness of the gate dielectric layer (72) is smaller than or equal to that of the separation gate dielectric layer (74);
Step 8: n-type impurities and P-type impurities are respectively injected into the top layer of the P-type base region (5) through photoetching and ion injection processes, and N+ emitter regions (3) and P+ emitter regions (4) which are alternately arranged along the Z-axis direction and mutually contacted are manufactured above the P-type base region (5); the junction depth of the N+ emission region (3) and the P+ emission region (4) is 0.2-0.5 mu m; one side of the N+ emission region (3) is connected with the gate electrode (71) along the X-axis direction through the gate dielectric layer (72); the P+ emission region (4) is connected with the separation gate electrode (73) along the X-axis direction of the device through the separation gate dielectric layer (74);
step 9: depositing metal with the thickness of 1-6 mu m on the surface of the device, and forming emitter metal (1) on the upper surfaces of the N+ emitter region (3) and the P+ emitter region (4) by adopting photoetching and etching processes;
step 10: turning over the silicon wafer, thinning the thickness of the silicon wafer, injecting N-type impurities into the back surface of the silicon wafer, and manufacturing an N-type field stop layer (9) of the device through multiple laser annealing, wherein the thickness of the formed N-type field stop layer is 1-6 mu m, the ion injection energy is 40-500 KeV, and the injection dosage is 10 13 ～10 14 Individual/cm 2 ；
Step 11: p-type impurities are injected into the back surface of the N-type field stop layer (9) to form a P-type collector region (10), the thickness of the formed P-type collector region is 0.5-2 microns, the ion implantation energy is 30-100 keV, and the implantation dosage is 10 13 ～10 14 Individual/cm 2 Ion activation is carried out through multiple times of laser annealing, and metal with the thickness of 1-6 mu m is deposited on the back surface to form collector metal (11); thus, the preparation of the three-dimensional trench gate charge storage type IGBT is completed.
CN202111116282.8A 2021-09-23 2021-09-23 Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof Active CN113838919B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111116282.8A CN113838919B (en) 2021-09-23 2021-09-23 Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111116282.8A CN113838919B (en) 2021-09-23 2021-09-23 Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN113838919A CN113838919A (en) 2021-12-24
CN113838919B true CN113838919B (en) 2023-10-24

Family

ID=78969433

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111116282.8A Active CN113838919B (en) 2021-09-23 2021-09-23 Three-dimensional trench gate charge storage type IGBT and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN113838919B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016014224A1 (en) * 2014-07-25 2016-01-28 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same
WO2017178494A1 (en) * 2016-04-11 2017-10-19 Abb Schweiz Ag Insulated gate power semiconductor device and method for manufacturing such a device
CN110137249A (en) * 2018-02-09 2019-08-16 苏州东微半导体有限公司 IGBT power device and its manufacturing method
CN111384153A (en) * 2020-03-20 2020-07-07 电子科技大学 SGT device with grounded P-type region and preparation method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US10861965B2 (en) * 2018-07-12 2020-12-08 Renesas Electronics America Inc. Power MOSFET with an integrated pseudo-Schottky diode in source contact trench

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016014224A1 (en) * 2014-07-25 2016-01-28 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same
WO2017178494A1 (en) * 2016-04-11 2017-10-19 Abb Schweiz Ag Insulated gate power semiconductor device and method for manufacturing such a device
CN110137249A (en) * 2018-02-09 2019-08-16 苏州东微半导体有限公司 IGBT power device and its manufacturing method
CN111384153A (en) * 2020-03-20 2020-07-07 电子科技大学 SGT device with grounded P-type region and preparation method thereof

Also Published As

Publication number Publication date
CN113838919A (en) 2021-12-24

Similar Documents

Publication Publication Date Title
CN107623027B (en) Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof
CN107731897B (en) Trench gate charge storage type IGBT and manufacturing method thereof
CN107799582B (en) Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof
CN108321196B (en) Trench gate charge storage type IGBT and manufacturing method thereof
CN108321193B (en) trench gate charge storage type IGBT and manufacturing method thereof
CN113838921B (en) Three-dimensional trench charge storage type IGBT and manufacturing method thereof
CN109713037B (en) Insulated gate bipolar transistor device and preparation method thereof
CN107731899B (en) Trench gate charge storage type IGBT device with clamping structure and manufacturing method thereof
CN110600537B (en) Separation gate CSTBT with PMOS current clamping and manufacturing method thereof
CN107731898B (en) CSTBT device and manufacturing method thereof
CN113838917B (en) Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof
CN110504310B (en) RET IGBT with self-bias PMOS and manufacturing method thereof
CN113838916B (en) Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof
CN109314141B (en) Semiconductor device with a plurality of semiconductor chips
CN113838922B (en) Separated gate super-junction IGBT device structure with carrier concentration enhancement and method
CN110518058B (en) Transverse groove type insulated gate bipolar transistor and preparation method thereof
CN112701159A (en) Multi-channel groove insulated gate bipolar transistor and manufacturing method thereof
CN116504817B (en) RC-IGBT structure with high switching speed and low loss and preparation method thereof
CN110473917B (en) Transverse IGBT and manufacturing method thereof
CN112038401A (en) Insulated gate bipolar transistor structure and preparation method thereof
CN113838920B (en) Separation gate CSTBT with self-bias PMOS and manufacturing method thereof
CN113838914B (en) RET IGBT device structure with separation gate structure and manufacturing method
CN110504313B (en) Transverse groove type insulated gate bipolar transistor and preparation method thereof
CN110459596B (en) Transverse insulated gate bipolar transistor and preparation method thereof
CN113838913B (en) Segmented injection self-clamping IGBT device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant