CN106298966A - Semiconductor device and preparation method thereof and electronic installation - Google Patents
Semiconductor device and preparation method thereof and electronic installation Download PDFInfo
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- CN106298966A CN106298966A CN201510270513.9A CN201510270513A CN106298966A CN 106298966 A CN106298966 A CN 106298966A CN 201510270513 A CN201510270513 A CN 201510270513A CN 106298966 A CN106298966 A CN 106298966A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 238000009434 installation Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims description 60
- -1 phosphonium ion Chemical class 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 24
- 239000012535 impurity Substances 0.000 description 20
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 239000012212 insulator Substances 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 238000009826 distribution Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000003519 ventilatory effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000007630 basic procedure Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 241000736199 Paeonia Species 0.000 description 1
- 235000006484 Paeonia officinalis Nutrition 0.000 description 1
- 238000003854 Surface Print Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides the preparation method of a kind of semiconductor device, including: Semiconductor substrate is provided；The first light shield is used to carry out the first ion implanting, to form first well region with the first conduction type in described Semiconductor substrate；The second light shield is used to carry out the second ion implanting, to form second well region with the first conduction type in described Semiconductor substrate；The first diffusion region of the second conduction type is formed in described first well region；The second diffusion region of the first conduction type is formed in described second well region, wherein said second well region is positioned at the outside of described first well region, and the ion concentration of the first conduction type in described first well region is less than the ion concentration of the first conduction type in described second well region.Present invention additionally comprises semiconductor device and electronic installation that described method prepares.Compared with prior art, ESD voltage tolerance and electric current tolerance can be improved according to the semiconductor diode device prepared by the manufacture method of the present invention and electronic installation thereof, and efficiently reduce electric leakage, improve the ESD performance of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and
Preparation method and electronic installation.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly by not
The disconnected size reducing IC-components realizes with the speed improving it.At present, due to
Pursue semi-conductor industry in high device density, high-performance and low cost and have advanced to nanotechnology
Process node.But, this progressive trend can produce disadvantageous shadow to the reliability of end product
Ring: in technical field of semiconductors, static discharge (ESD) phenomenon is to integrated circuit one
Big threat, it can puncture integrated circuit and semiconductor element, promote component ageing, reduces raw
Finished product rate.Therefore, along with the continuous reduction of manufacture of semiconductor process, ESD protection sets
Meter becomes more and more challenging and difficulty in nano level CMOS technology.
In the prior art, multiple layer metal oxide device, ceramic condenser and diode all may be used
To effectively act as ESD protection effect.Wherein prior art generally uses MOS structure two pole
Pipe carries out ESD protection.But owing to the tolerance electric current of MOS structure diode is by channel width
Determine, cause its tolerance electric current relatively low.Therefore, it is necessary to propose a kind of new ESD
Diode component preparation method, improves ESD voltage tolerance and electric current tolerance, and reduces
Electric leakage.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, the present invention provides a kind of semiconductor device preparation side
Method, including:
Step 1: Semiconductor substrate is provided；
Step 2: use the first light shield to carry out the first ion implanting, with in described Semiconductor substrate
Interior formation has the first well region of the first conduction type；
Step 3: use the second light shield to carry out the second ion implanting, with in described Semiconductor substrate
Interior formation has the second well region of the first conduction type；
Step 4: form the first diffusion region of the second conduction type in described first well region；
Step 5: form the second diffusion region of the first conduction type in described second well region, its
Described in the second well region be positioned at the outside of described first well region, first in described first well region is led
The ion concentration of electricity type is less than the ion concentration of the first conduction type in described second well region.
Wherein, the transparent area shape of described second light shield and the first light shield is complimentary to one another.
Wherein, described step 3 and the order intermodulation of step 2.
Wherein, described first conduction type is N-type, and described second conduction type is p-type.
Wherein, first diffusion region and the of described first conduction type of described second conduction type
One well region constitutes the diode for ESD protection circuit.
Wherein, the concentration of described first ion implanting is 2E12.
Wherein, described first ion implanting includes that twice phosphonium ion injects.
Wherein, the energy that described twice phosphonium ion injects be respectively 140 ± 10Kev and 440 ±
30Kev, dosage is respectively 1E12 ± 0.2E12 and 1E12 ± 0.2E12.
The present invention also provides for a kind of method preparing semiconductor device by described method.
The present invention also provides for a kind of electronic installation, including the quasiconductor prepared by described method
Device and the electronic building brick being connected with described semiconductor device.
In sum, the semiconductor device preparation method of the present invention include a kind of semiconductor device and
Its preparation method and electronic installation.Compared with prior art, according to the manufacture method institute of the present invention
The semiconductor diode device of preparation and electronic installation thereof can improve ESD voltage tolerance and electricity
Stream tolerance, and efficiently reduce electric leakage, improve the ESD performance of device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Fig. 1 shows the generalized section of a kind of existing ESD diode structure；
Fig. 2 shows the relevant of the preparation method according to a specific embodiment of the present invention
Step and the generalized section of ESD diode obtained.
Fig. 3 shows phosphorus and the arsenic ion Impurity Distribution concentration of analog figure under different junction depths.
Fig. 4 shows the flow process of the preparation method according to a specific embodiment of the present invention
Figure.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention describes in detail
As follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Embodiment one
Next, with reference to Fig. 1, Fig. 2, the semiconductor device preparation method of the present invention is done in detail
Describe.
As it is shown in figure 1, the semiconductor device of prior art includes Semiconductor substrate 100.Described
Semiconductor substrate 100 can be at least one in the following material being previously mentioned: silicon, insulator
Stacking SiGe on stacking silicon (SSOI), insulator on upper silicon (SOI), insulator
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.Described Semiconductor substrate is preferably the P type substrate of B or the Ga element that adulterates.Subsequently at P
N trap 105 is made on type substrate.
N trap 105 can be by one layer of SiO of P type substrate superficial growth2, at SiO2Upper painting
Cover photoresist to carry out photoetching, form N trap doping window, subsequently with at HF etching window
SiO2And remove photoresist.Now can inject N-type impurity at window and form N trap.Described N-type
Impurity preferably employs high energy phosphorus (P) or arsenic (As) ion.Doping implantation dosage refers to impurity
The concentration that atom injects, which determines the power of doped layer conduction, as example, described N
The implantation dosage of type impurity is about 2E13.
Described Semiconductor substrate 100 can also including, shallow trench isolates (STI) structure 101.
Generally, the formation basic procedure of sti structure 101 is: at H2O or O2Under ventilatory conditions right
Substrate carries out thermal oxide, forms SiO2Thin layer, thickness is about 20nm.Subsequently at SiO2Thin layer
On be about the silicon nitride of 250nm with CVD elder generation deposition thickness, then corrode in isolation area and one
The groove of depthkeeping degree, then carry out side wall oxidation, by chemical gaseous phase deposition (CVD) method at groove
Middle deposition thickness is about the SiO of 0.5-1.0 μm2, finally by chemically mechanical polishing (CMP)
Method planarizes, and removing surface oxide layer, till silicon nitride layer, uses hot phosphoric acid subsequently
At 180 DEG C, perform etching removing silicon nitride layer Deng wet etching, ultimately form channel separating zone
101 and active area.It should be noted that the step forming shallow groove isolation structure can formed
Before the step of N trap 200.
Subsequently, use N+ mask plate to carry out N+ ion implantation doping and diffusion advances, form N
Diffusion region 102, wherein N+ ion is mainly phosphorus or arsenic.In like manner, P+ mask plate is used to carry out
P+ ion implantation doping and diffusion advance, and form P diffusion region 103, and wherein P+ ion is main
It is boron or gallium.
Fig. 2 shows the preparation method of ESD diode of the present invention.An example
In, first at H2O or O2Under ventilatory conditions, Semiconductor substrate 200 is carried out thermal oxide, shape
Become SiO2Thin layer, thickness is about 20nm.Subsequently at SiO2First deposit thickness with CVD on thin layer
Degree is about the silicon nitride of 250nm, then corrodes the groove certain depth in isolation area, then
The SiO of 0.5-1.0 μm it is about with chemical gaseous phase deposition (CVD) method deposition thickness in the trench2,
Finally by chemically mechanical polishing (CMP) method planarize, remove surface oxide layer until
Till silicon nitride layer, the wet etchings such as hot phosphoric acid are used to perform etching removing at 180 DEG C subsequently
Silicon nitride layer, ultimately forms channel separating zone 201 and active area.It should be noted that formation
The step of shallow groove isolation structure can be carried out after being subsequently formed the first well region and the second well region.
Subsequently, the committed step of ESD diode preparation method of the present invention is carried out.Make
For example, at one layer of SiO of P type substrate superficial growth2, at SiO2Upper covering the first light shield with
Carry out photoetching, the subsequently SiO at etching window2And after removing light shield, carry out the first ion note
Enter, in described Semiconductor substrate, form first well region 205 with the first conduction type；Enter
After row surface clean is to remove surface impurity and oxide；At another SiO of superficial growth2Protection
Layer, at SiO2Upper covering the second light shield carries out photoetching, etches the SiO at this window2And remove
After light shield, carry out the second ion implanting, with described first well region in described Semiconductor substrate
The outside of 205 forms second well region 210 with the first conduction type.It should be noted that
The part surface that first light covers on 210 regions as shown in Figure 2 is light tight so that this 210th district
Territory cannot accept the first ion implanting；Second light covers on the surface printing opacity in 210 regions, this layer of light
Cover enables to 210 regions shown in Fig. 2 and accepts the second ion implanting, is formed such as Fig. 2 institute
The second well region 210 region shown.
Described first light shield and the second light shield (photomask board, mask plate) mainly by quartz glass,
Crome metal and photoresists composition.Wherein, quartz glass is used as substrate, on described quartz glass
Plating layer of metal chromium and photoresists, make sensitive material.The predefined figure of described light shield
Be exposed on photoresists by electronic laser equipment, the region being exposed can developed out,
Crome metal is formed this predefined figure, becomes the photomask of the egative film after similar exposure,
It is then applied to projective iteration, by litho machine, the predefined figure projected is carried out photetching
Carving, its production and processing operation is: exposure, and development is removed photoresists, is finally applied to photoetch.
After arranging the first light shield, as example, transparent area carry out to region 205 first from
Son injects, and the described first ion injected is N-ion, to be formed at described Semiconductor substrate
Interior first well region 205 with the first conduction type.Doping implantation dosage refers to foreign atom
The concentration injected, which determines the power of doped layer conduction.The ion typical case of the first ion implanting
For phosphorus or arsenic ion.As example, described first ion implanting includes that twice phosphonium ion injects,
The energy of twice phosphonium ion injection is respectively 140 ± 10Kev and 440 ± 30Kev, and dosage is respectively
For 1E12 ± 0.2E12 and 1E12 ± 0.2E12.As an alternative, described ion implantation process makes
Ion can also is that the V race ions such as arsenic (As) ion.
After arranging the second light shield, as example, transparent area P type substrate carried out second from
Son inject, described N-type impurity preferably employs high energy phosphorus (P) or arsenic (As) ion, with
The outside of the first well region 205 in described Semiconductor substrate is formed dense with the first well region 205 ion
Spend the second different well regions 210.As example, the N-type impurity of described second time ion implanting
Implantation dosage be about 2E13.As an alternative, described second ion implantation process use from
Son can also is that the V race ions such as arsenic (As) ion.
It should be noted that the ion concentration of described first well region 205 is less than the second well region 210
Ion concentration.The transparent area shape complementarity of the first light shield and the second light shield, thus at quasiconductor
The first well region 205 and the second well region 210 connected is formed on substrate.
In described ion implantation process, bombard silicon chip surface by high energy phosphorus or arsenic ion bundle,
Through above two-layer light shield, photoengraving is controlled, forms doping window.At the first well region
At the doping window in 205 regions, foreign matter of phosphor or arsenic ion are injected into silicon body, and such as 210
Other positions in region etc., foreign matter of phosphor or arsenic ion are by the protective layer SiO of silicon face2Shielding,
Complete to select the process of doping.Enter the foreign matter of phosphor in silicon or arsenic ion to be formed in certain position
Certain distribution.Generally, the degree of depth (mean range) of ion implanting is shallower and concentration is relatively big, must
Them must be again made to redistribute.The degree of depth of doping is determined by energy and the quality of implanting impurity ion
Fixed, the concentration of doping is determined by the number (dosage) of implanting impurity ion.
It is further noted that carry out described first time ion implanting and form the first well region
The process of 205 with carry out described second time ion implanting and form the process of the second well region 210 can
To exchange, i.e. can advanced row second time ion implanting molding the second well region 210, the most again
Carry out first time ion implanting and form the first well region 205.
Subsequently, in described first well region 205, form the first diffusion region of the second conduction type
203；The second diffusion region 202 of the first conduction type is formed in described second well region 210.
First diffusion region 203 of the second conduction type and the first well region 205 of described first conduction type
Constitute the diode for ESD protection circuit.As example, the second conduction type is P
Type, the first conduction type is N-type.It is additionally included in described Semiconductor substrate formation with described
The first electrical contact 204 and lead with described first that first diffusion region of the second conduction type is connected
The second electrical contact 208 that second diffusion region of electricity type is connected.Additionally, this electrostatic discharge (ESD) protection
Diode can form electrostatic as a kind of electronic device and coupled electronic building brick to be prevented
Protect electronic installation.
After ion implantation, it is also possible to carry out annealing steps.Annealing steps preferably exists
The H of 600-1000 DEG C2Environment heats, for repairing the Si surface crystal that ion implanting causes
Damaging and electrically activate implanted dopant, meanwhile, annealing also can make impurity spread further.
Annealing steps is preferably used rapid heating process (RTP), to reduce impurity diffusion.
In described diode preparation technology, wherein, junction depth X is defined as surface from silicon
To diffusion layer concentration equal to the distance between substrate concentration, typically measure in units of micron.
Therefore, on the premise of the size scaled down of integrated circuit, wait electric field requirement junction depth X
Reducing identical multiple, the requirement of device resistance is then to try to little by modern technologies simultaneously, because of
This needs to meet the deep and highly doped both sides requirement of shallow junction simultaneously.Ion according to different junction depths
Doping content, can make Impurity Distribution shape graph (doping profile), to know difference
The distribution situation of different dopant ions in the case of junction depth, thus be conducive to the work according to different junction depths
Skill requires to select dopant ion and process optimization.
Fig. 3 shows that the phosphorus according to detailed description of the invention of the present invention and arsenic ion be not
With the Impurity Distribution concentration of analog figure under junction depth.Dopant ion phosphorus and arsenic are noted with the form of ion beam
Entering in quasiconductor, impurity concentration produces peak Distribution in quasiconductor, Impurity Distribution mainly by from
Protonatomic mass and Implantation Energy are determined.In figure 3, transverse axis is the junction depth X measured in microns,
The longitudinal axis be every cubic centimetre in dopant ion concentration, wherein peony curve represents phosphonium ion and mixes
Miscellaneous, and light green color curve represents arsenic ion doping.From figure 3, it can be seen that arsenic ion is at knot
Time below deep about 0.15 μm, doping content is higher, and phosphonium ion more than junction depth about 0.15 μm time
Doping content higher.
Such as table 1 below, it is shown that prevent according to ESD prepared by semiconductor device technology of the present invention
Protect the leakage analog data of diode.As seen from the table, according to semiconductor device of the present invention
The electrical leakage quantity of the ESD protection diode prepared by part technique is compared base case and is decreased about 3.6
Times, effectively reduce the electric leakage of diode.
Table 1: diode leakage analog data
Fig. 4 shows the flow process of the preparation method according to a specific embodiment of the present invention
Figure.Wherein, S401 provides Semiconductor substrate；S402 uses the first light shield to carry out the first ion
Inject, to form first well region with the first conduction type in described Semiconductor substrate；
S403 uses the second light shield to carry out the second ion implanting, with the institute in described Semiconductor substrate
The outside stating the first well region forms second well region with the first conduction type；S404 is first
The first diffusion region of the second conduction type is formed in well region；S405 forms in the second well region
Second diffusion region of one conduction type, the first conduction type in wherein said first well region from
Sub-concentration is less than the ion concentration of the first conduction type in described second well region.
Embodiment two
Next, with reference to Fig. 2, the semiconductor device of the present invention is described in detail.
As in figure 2 it is shown, the semiconductor device of the present invention includes Semiconductor substrate 200.Described half
Conductor substrate can be at least one in the following material being previously mentioned: silicon, silicon-on-insulator
(SOI), stacking SiGe (S-SiGeOI) on stacking silicon (SSOI), insulator on insulator,
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Described partly lead
Body substrate is preferably the P type substrate of B or the Ga element that adulterates.
Can also include that shallow trench isolates (STI) structure 201 on the semiconductor substrate.
Generally, the formation basic procedure of sti structure 201 is: at H2O or O2Under ventilatory conditions right
Substrate carries out thermal oxide, forms SiO2Thin layer, thickness is about 20nm.Subsequently at SiO2Thin layer
On be about the silicon nitride of 250nm with CVD elder generation deposition thickness, then corrode in isolation area and one
The groove of depthkeeping degree, then carry out side wall oxidation, by chemical gaseous phase deposition (CVD) method at groove
Middle deposition thickness is about the SiO of 0.5-1.0 μm2, finally by chemically mechanical polishing (CMP)
Method planarizes, and removing surface oxide layer, till silicon nitride layer, uses hot phosphoric acid subsequently
At 180 DEG C, perform etching removing silicon nitride layer Deng wet etching, ultimately form channel separating zone
201 and active area.
What the semiconductor device of the present invention was included in described Semiconductor substrate has the first conduction
First well region 205 of type；In described Semiconductor substrate, there is the of the first conduction type
There is in one well region 205 the N-ion of injection, be typically phosphorus or arsenic ion.As example,
Described first well region can include the phosphonium ion being divided into twice injection, the phosphonium ion of twice injection
Energy is respectively 140 ± 10Kev and 440 ± 30Kev, and dosage is respectively 1E12 ± 0.2E12
With 1E12 ± 0.2E12.As an alternative, the ion of described injection can also is that arsenic (As) from
Zi Deng V race ion.
The first well region 205 that the semiconductor device of the present invention is additionally included in described Semiconductor substrate
Outside formed second well region 210 different from the first well region 205 ion concentration.Institute
State the outside of the first well region 205 in Semiconductor substrate is formed and the first well region 205 ion
Having N-type impurity in the second well region 210 that concentration is different, described N-type impurity preferably employs
High energy phosphorus (P) or arsenic (As) ion, using as example, the injectant of described N-type impurity
Amount is about 2E13.As an alternative, described N-type impurity can also is that the V such as arsenic (As) ion
Race's ion.
It should be noted that the ion concentration of described first well region 205 is less than the second well region 210
Ion concentration.And the first well region 205 and the second well region 210 formed on a semiconductor substrate
Adjoin one another.Further, the sequence of steps forming the first well region 205 and the second well region 210 is can
With exchange.
Additionally, what the semiconductor device of the present invention was formed in being additionally included in described first well region 205
First diffusion region 203 of the second conduction type, and in described second well region 210, form the
Second diffusion region 202 of one conduction type.First diffusion region 203 of the second conduction type and institute
The first well region 205 stating the first conduction type constitutes two poles for ESD protection circuit
Pipe.As example, the second conduction type is p-type, and the first conduction type is N-type.
In another embodiment, be additionally included in described Semiconductor substrate formed with described
The first electrical contact 204 and lead with described first that first diffusion region of the second conduction type is connected
The second electrical contact 208 that second diffusion region of electricity type is connected.
The ESD protection diode component using the manufacture method of the present invention to be formed includes being positioned at half
The first well region in conductor substrate and the second well region, the first well region and the second well region have different
Doping content, is also formed with diffusion region, diffusion region and well region in the first well region and the second well region
It is collectively forming ESD diode, for electrostatic discharge (ESD) protection.Compared with prior art, this
The first bright well region has relatively low doping content, reduces the electrical leakage quantity of device, therefore passes through
The semiconductor device that the preparation technology of the present invention is formed has stronger ESD protection characteristic and Shandong
Rod, it is provided that preferably ESD protection performance.
Embodiment three
The present invention also provides for a kind of electronic installation, and this electronic installation includes described in embodiment two
Semiconductor device and the electronic building brick being connected with described semiconductor device.
Wherein said semiconductor device includes: Semiconductor substrate；Shape in described Semiconductor substrate
First well region with the first conduction type become；In described Semiconductor substrate described first
Second well region with the first conduction type that the outside of well region is formed；In described first well region
First diffusion region of the second conduction type formed；First formed in described second well region is led
Second diffusion region of electricity type, the ion of the first conduction type in wherein said first well region is dense
Degree is less than the ion concentration of the first conduction type in described second well region.Second conduction type
First well region of the first diffusion region and described first conduction type collectively forms for static discharge
The diode of protection circuit.In addition formation it is additionally may included in described Semiconductor substrate with described
First diffusion region of the second conduction type be connected first electrical contact and with described first conductive-type
The second electrical contact that second diffusion region of type is connected.
Or, this electronic installation includes the semiconductor device that the method described in embodiment one makes
And the electronic building brick being connected with this semiconductor device.
Semiconductor device owing to including has more preferable ESD protection performance, this electronic installation
There is above-mentioned advantage equally.
This electronic installation, can be mobile phone, panel computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment, it is also possible to be that there is above-mentioned quasiconductor
The intermediate products of device, such as: there is the cell phone mainboard etc. of this integrated circuit.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. the preparation method of a semiconductor device, it is characterised in that including:
Step 1: Semiconductor substrate is provided；
Step 2: use the first light shield to carry out the first ion implanting, with in described Semiconductor substrate
Interior formation has the first well region of the first conduction type；
Step 3: use the second light shield to carry out the second ion implanting, with in described Semiconductor substrate
Interior formation has the second well region of the first conduction type；
Step 4: form the first diffusion region of the second conduction type in described first well region；
Step 5: form the second diffusion region of the first conduction type in described second well region, its
Described in the second well region be positioned at the outside of described first well region, first in described first well region is led
The ion concentration of electricity type is less than the ion concentration of the first conduction type in described second well region.
Preparation method the most according to claim 1, wherein said second light shield and first
The transparent area shape of light shield is complimentary to one another.
Preparation method the most according to claim 1, wherein said step 3 and step 2
Order intermodulation.
Preparation method the most according to claim 1, wherein said first conduction type is
N-type, described second conduction type is p-type.
Preparation method the most according to claim 1, wherein said second conduction type
First well region of the first diffusion region and described first conduction type is constituted for electrostatic discharge (ESD) protection
The diode of circuit.
Preparation method the most according to claim 1, wherein said first ion implanting
Concentration is 2E12.
Preparation method the most according to claim 1, wherein said first ion implanting bag
Include twice phosphonium ion to inject.
Preparation method the most according to claim 7, wherein said twice phosphonium ion injects
Energy be respectively 140 ± 10Kev and 440 ± 30Kev, dosage is respectively 1E12 ± 0.2E12
With 1E12 ± 0.2E12.
9. one kind uses the semiconductor device that the described method of one of claim 1-8 prepares.
10. an electronic installation, including the semiconductor device described in claim 9 and with institute
State the electronic building brick that semiconductor device is connected.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054215A (en) * | 2017-12-21 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Junction field effect transistor and preparation method thereof |
| CN113791276A (en) * | 2021-09-16 | 2021-12-14 | 长鑫存储技术有限公司 | Method for testing resistance value of resistor |
| CN114520268A (en) * | 2020-11-19 | 2022-05-20 | 无锡华润微电子有限公司 | Photodiode unit and photodiode array |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1482680A (en) * | 2002-09-10 | 2004-03-17 | 萨尔诺夫公司 | Electrostatic discharge protection silicon controlled rectifier (esd-scr) for silicon germanium technologies |
| US20120025351A1 (en) * | 2010-07-29 | 2012-02-02 | Renesas Electronics Corporation | Semiconductor device |
| US20150001679A1 (en) * | 2009-03-11 | 2015-01-01 | Renesas Electronics Corporation | Esd protection element |
-
2015
- 2015-05-25 CN CN201510270513.9A patent/CN106298966B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1482680A (en) * | 2002-09-10 | 2004-03-17 | 萨尔诺夫公司 | Electrostatic discharge protection silicon controlled rectifier (esd-scr) for silicon germanium technologies |
| US20150001679A1 (en) * | 2009-03-11 | 2015-01-01 | Renesas Electronics Corporation | Esd protection element |
| US20120025351A1 (en) * | 2010-07-29 | 2012-02-02 | Renesas Electronics Corporation | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054215A (en) * | 2017-12-21 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Junction field effect transistor and preparation method thereof |
| CN108054215B (en) * | 2017-12-21 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Junction field effect transistor and manufacturing method thereof |
| CN114520268A (en) * | 2020-11-19 | 2022-05-20 | 无锡华润微电子有限公司 | Photodiode unit and photodiode array |
| CN114520268B (en) * | 2020-11-19 | 2024-01-30 | 无锡华润微电子有限公司 | Photodiode unit and photodiode array |
| CN113791276A (en) * | 2021-09-16 | 2021-12-14 | 长鑫存储技术有限公司 | Method for testing resistance value of resistor |
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| CN106298966B (en) | 2020-05-12 |
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