CN110534537B - CMOS image sensor pixel structure and manufacturing method thereof - Google Patents
CMOS image sensor pixel structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a CMOS image sensor pixel structure and a manufacturing method thereof, which mainly solve the problems of low signal acquisition speed, signal charge backflow and low charge transfer efficiency in the prior art and comprise a substrate (1), an epitaxial layer (2), a shallow trench isolation layer (3), a gate oxide layer (4), a polysilicon gate (5) and a passivation layer (6), wherein a drain electrode (11) is deposited below the substrate, a source electrode (10) is deposited at the upper right corner of the epitaxial layer, a pump gate electrode (8) and a transmission gate electrode (9) are deposited above the polysilicon gate, a charge storage region (21), a photoelectric response region (22) and a threshold voltage adjusting region (23) are arranged, and pixel interconnection metal (7) is deposited above the pump gate electrode and the transmission gate electrode. The invention improves the acquisition speed and charge transfer efficiency of photoelectric signal charges, improves the detection precision of the three-dimensional depth imaging radar system, and can be used for virtual reality, unmanned aerial vehicles and automatic driving radar systems.
Description
Technical Field
The invention belongs to the technical field of photoelectrons, and particularly relates to a CMOS image sensor pixel structure which can be used for a three-dimensional imaging radar system required by virtual reality, unmanned aerial vehicles and automatic driving.
Background
The CMOS image sensor occupies most of the commercial-grade and industrial-grade image sensor markets due to its advantages of low power consumption, high integration, low cost, etc., and the CMOS image sensor having high-quality imaging capability is also gradually expanded to the application fields of scientific research experiments, medical treatment, etc. With the rapid development of the internet of things, the CMOS image sensor has become the most widely used photoelectric detection chip today. With the development of the three-dimensional detection theory, the three-dimensional imaging image sensor is applied to devices such as a mobile terminal. The time flight TOF technology is used as one of three main flow schemes of structured light, TOF and stereoscopic vision in the field of three-dimensional depth vision, and besides being applied to a mobile phone terminal, the TOF technology can also be applied to multiple fields of VR/AR gesture interaction, environment measurement, automobile electronic ADAS, security monitoring, new retail and the like, so that the application prospect is very wide. For professional-level scenarios such as automotive and industrial scenarios, the design of TOF sensing systems requires not only a balanced design in terms of accuracy, range, response time, resolution, cost, power consumption, and packaging requirements. And the response speed, sensitivity and anti-interference performance of the sensor are extremely high when the sensor is applied in different practical environments. In order to realize low cost of TOF technology and expand the application market thereof, a silicon-based CMOS image sensor with low cost, high integration and compatibility with an analog integrated circuit becomes the first choice of a TOF three-dimensional imaging system. Improving the analysis precision of the TOF technology to the laser pulse wave is a necessary condition for improving the detection precision of the TOF three-dimensional imaging radar system. Therefore, it is necessary to increase the transfer speed of the photoelectric signal charges in the CMOS image sensor so that the CMOS image sensor obtains a higher pulse modulation demodulation contrast of the photoelectric signal. Especially, pixels of a large-size high-speed charge transfer CMOS image sensor applied to remote three-dimensional image detection chips such as an automobile automatic driving radar, an unmanned aerial vehicle radar and the like are hot spots and focuses of domestic and foreign research and application.
However, in the conventional CMOS image sensor, the low signal charge transfer speed greatly prolongs the reading time of the photoelectric signal in the sensor pixel by the signal sampling circuit, and the shooting frame rate of the camera is seriously lowered. When a low-frame-rate camera is used for shooting an object in high-speed motion, an image trailing phenomenon occurs, namely, an image of a current frame contains an image signal of a previous frame, and ghost imaging is caused. When an object in ultrahigh-speed motion is shot, image deformation, namely image distortion, can be caused under severe conditions, so that the traditional CMOS image sensor chip cannot meet the requirements of a TOF three-dimensional image system with a very wide application prospect. Because there is no high-speed image sensing pixel meeting the requirement, the TOF three-dimensional depth camera cannot achieve high demodulation contrast of signal pulses, that is, the depth detection precision of the three-dimensional camera is seriously reduced, so that the current TOF three-dimensional depth vision technology cannot achieve high depth resolution, and the defects seriously restrict the application field of the three-dimensional depth vision technology, that is, the application of the TOF three-dimensional depth vision technology in unmanned aerial vehicles, automobiles or industrial robots is inhibited.
In order to solve the above problems, researchers at home and abroad have proposed some solutions:
SANG-MAN HAN et al, 9.2014, proposed a lateral electric field modulation LEFM technique that adjusts the potential distribution gradient across the photodiode by means of a combination of four polysilicon gates. In order to improve the Modulation capability of the polysilicon gate on photoelectrons in the photodiode, each polysilicon gate needs to be overlapped With the photodiode, and the overlapping of the large-area polysilicon gate and the photodiode seriously reduces the fill factor of the pixel, namely reduces the quantum efficiency and the detection sensitivity of a unit pixel, which is referred to in ATime-of-light Range Image Sensor With Background Long Electron Field Charge Modulation, IEEE Journal of the Electron Devices Society, pp.267-275, VOLUME 3, NO.3, and MAY 2015.
In 2017, Terrence Cole Millar et al reported the effect of different photodiode shapes on the potential on the electron transport path, comparing the performance of square, triangular, dumbbell, and right-angled photodiodes, respectively, where the right-angled photodiode has the highest charge transfer rate. Although The Photodiode with a special structure can improve The transfer speed of signal charges, The Photodiode with The special structure has a smaller detection area compared with The traditional structure, and The photoelectric performance of The sensor is also reduced, see The Effect of a Pinned Photodiode Shape ON time-of-light modulation control, IEEE TRANSACTIONS ON ELECTRON DEVICES, pp.414-419, VOL.64, NO.5 and MAY 2017.
Dondongwa et al, DONALD b.hon dongwa, 8.2017, reported that a monotonically increasing built-in drift field is formed in a photodiode region by improving a mask for photodiode ion implantation or optimizing an incident angle for ion implantation, so that rapid charge transfer can be achieved in a large-sized photodiode. The conventional process uses an ion implantation angle of 7 ° to prevent the channel effect of the CMOS process, and the paper proposes that the ion implantation angle of 12.5 °, 15 °, and 17.5 ° may seriously affect the electrical performance of the MOS transistor around the photodiode, thereby requiring a Large amount of process experiments by a manufacturer, and increasing the cost of technical communication, see, for example, dry Field implantation in Large pin Photodiodes for Improved Charge Transfer specification, IEEE Journal of the Electron Devices Society, pp.267-275, and VOLUME 6,2018.
The technical scheme of the image sensor has the following defects: firstly, the backflow problem of signal charge is serious, the charge transfer efficiency is low, the acquisition speed of photoelectric signal charge is low, the modulation and demodulation contrast ratio of distance detection is reduced, the detection precision of a three-dimensional depth imaging radar system is reduced, secondly, extra process steps are added on the manufacturing process of a standard CMOS image sensor, the cost of process manufacturing is increased, thirdly, a non-traditional process manufacturing technology is adopted, the difficulty of work-in-place manufacturing is increased, and the yield is reduced.
Disclosure of Invention
The present invention is directed to provide a CMOS image sensor pixel structure and a method for fabricating the same, so as to reduce the backflow of signal charges, improve the charge transfer efficiency and the collection speed of photoelectric signal charges, improve the detection accuracy of a three-dimensional depth imaging radar system, reduce the manufacturing cost, and improve the yield.
In order to achieve the purpose, the technical scheme of the invention is as follows:
pixel structure of device
A CMOS image sensor pixel structure comprises a substrate, an epitaxial layer, a shallow trench isolation layer, a gate oxide layer, a polysilicon gate and a passivation layer, wherein a drain electrode is deposited below the substrate, a source electrode is deposited at the upper right corner of the epitaxial layer, a pump gate electrode and a transmission gate electrode are deposited above the polysilicon gate, pixel interconnection metal is deposited above the pump gate electrode and the transmission gate electrode, and a charge storage region, a photoelectric response region and a threshold voltage adjusting region are arranged on the epitaxial layer, and the CMOS image sensor pixel structure is characterized in that:
the charge storage area is composed of a pre-storage node, a pre-storage node protection isolation and a floating diffusion node, and the pre-storage node is arranged at the upper part of the pre-storage node protection isolation;
the photoelectric response region consists of a clamping layer, a potential barrier adjusting layer, a P-type well region and an N-type region of the photodiode, wherein the clamping layer is arranged at the upper part of the potential barrier adjusting layer, and the P-type well region is arranged at two sides of the N-type region of the photodiode;
the threshold voltage adjusting region is composed of an N-type channel adjusting layer and a P-type channel adjusting layer, and the N-type channel adjusting layer is arranged on the left side of the P-type channel adjusting layer;
the polysilicon gate is composed of a pump gate and a transmission gate, the pump gate is positioned on the upper part of the P-type channel adjusting layer, and the transmission gate is positioned on the upper part of the N-type channel adjusting layer.
Further, it is characterized in that the relationship between the impurity concentration x of the pre-stored node and the impurity concentration y of the pre-stored node protection isolation is: y ═ 3 × 1013ln(x)-9×1014And the impurity concentration range is 1 × 10 |11＜x＜5×1014The unit of impurity concentration: cm-3。
Further, the junction depth a of the clamp layer is 0.1 to 0.2 μm; the junction depth b of the N-type region of the photodiode is 1.0-2.0 μm.
Further, the pump grid is characterized in that the length c of the pump grid is 0.8-2.0 μm, and the thickness d is 0.2-0.3 μm; the length e of the transmission gate is 0.4-1.0 μm, and the thickness f is 0.2-0.3 μm.
The P-type well region is composed of a floating diffusion node protection isolation layer, a transmission gate threshold adjustment layer and a P-type well, wherein the floating diffusion node protection isolation layer is positioned on the upper portion of the transmission gate threshold adjustment layer, and the transmission gate threshold adjustment layer is positioned on the upper portion of the P-type well;
further, the N-type region of the photodiode is composed of two parts, i.e., a tilted implantation region and a non-tilted implantation region, and the tilted implantation region is located above the non-tilted implantation region.
Second, method for manufacturing CMOS image sensor pixel
A. Using chemical vapor deposition process on the substrate 1, the epitaxial growth thickness ta is 13 μm-20 μm, and the doping concentration is 1 × 1013～8×1013 cm -32;
B. manufacturing a shallow trench isolation layer 3 on the epitaxial layer 2:
B1) manufacturing a first mask on the upper part of the epitaxial layer 2, and forming a shallow trench with the depth td of 0.3-0.4 mu m on the epitaxial layer 2 by using the mask and an etching process;
B2) forming a silicon dioxide layer with the thickness of 0.3-0.4 mu m on the shallow trench by using a plasma enhanced chemical vapor deposition process;
B3) removing the silicon dioxide material on the upper part of the epitaxial layer 2 by using a chemical mechanical polishing process to form a shallow trench isolation layer (3);
C. forming a P-type well region 223 on the epitaxial layer 2:
C1) forming a shallow trench isolation layer 3 on the substrate with a thickness of
A silicon dioxide layer of (a);
C2) a second mask is made, and a first ion implantation is performed on both sides of the epitaxial layer 2 using the second mask, i.e., at an implant dose of 5 × 1013～9×1013cm-2Forming a transfer gate threshold adjustment layer 2231 by a P-type impurity with energy of 120 to 153 kev;
C3) a third mask is formed, and a second ion implantation is performed below the transfer gate threshold adjustment layer 2231 using the third mask, i.e., at an implant dose of 5 × 1012～9×1012cm-2Forming a floating diffusion node protective isolation layer 2232 by using P-type impurities with energy of 70-85 kev;
C4) making a fourth mask, and performing a third ion implantation with a dose of 1 × 10 under the floating diffusion node protective isolation layer 223211～4×1011cm-2Forming a P well 2233 by using P-type impurities with energy of 10-15 kev;
D. the N-type region 224 of the photodiode is fabricated on the epitaxial layer 2:
D1) a fifth mask is formed, and a fourth ion implantation is performed in the middle of the P-well 223 with an implant dose of 1 × 1012～3×1012cm-2Forming an inclined implantation region 2241 by using N-type impurities with energy of 100-130 kev;
D2) a sixth sub-mask is formed, and the process is performed under the inclined implantation region 2241 using the sixth sub-maskFifth ion implantation with a 4X 10 implantation dose11～8×1011cm-2Forming a non-inclined implantation region 2242 by using N-type impurities with energy of 100-130 kev;
E. and manufacturing a gate oxide layer 4.
E1) A seventh mask is made, and a sixth ion implantation is performed on the upper portion of the N-type region 224 of the photodiode using the seventh mask, i.e., the implantation dose is 1 × 1012～3×1012cm-2Forming a clamp layer 221 by using a P-type impurity with energy of 18-25 kev;
E2) an eighth mask is formed, and a seventh ion implantation is performed using the eighth mask at a dose of 2 × 10 below the clamp layer 22112～6×1012cm-2Forming a barrier adjustment layer 222 by using a P-type impurity with energy of 6-10 kev;
E3) a ninth mask is formed, and an eighth ion implantation is performed on the right side of the barrier adjusting layer 222 using the ninth mask, that is, the implantation dose is 4 × 1011～8×1011cm-2, an N-type impurity with energy of 20 to 30kev, forming an N-type channel adjustment layer 231;
E4) a tenth mask is formed, and a ninth ion implantation is performed at the right side of the N-type channel adjustment layer 231 using the tenth mask, i.e., at an implantation dose of 2 × 1012～5×1012cm-2Forming a P-type channel adjusting layer 232 by using P-type impurities with energy of 8-14 kev, and annealing at 900-1200 ℃ for 18-20 s;
E5) a thermal oxidation process is performed on the upper portion of the P-type channel adjustment layer 232 to form a thickness of
A gate oxide layer 4;
F. and (3) manufacturing a polysilicon gate 5 on the upper part of the gate oxide layer 4:
F1) depositing a polysilicon layer with the thickness tf of 0.18-0.2 mu m on the upper part of the gate oxide layer 4 by using a chemical vapor deposition process;
F2) making an eleventh mask, and forming a pump gate 51 and a transfer gate 52 on the upper part of the polysilicon layer by using an etching process using the eleventh mask;
G. and manufacturing a side wall 53 around the polysilicon gate 5.
G1) Depositing a silicon nitride layer with the thickness of 0.03-0.05 mu m above the polysilicon gate 5 by using a chemical vapor deposition process;
G2) etching 30-50% of the silicon nitride layer around the polysilicon gate 5 by using an etching process to form a side wall 53;
H. by ion implantation, the floating diffusion node 213 is formed.
H1) A twelfth mask is made, and a tenth ion implantation is performed on the right side of the pump gate 51 using the twelfth mask to form a pre-stored node 211 having an N-type impurity concentration x, which is 1 × 1011＜x＜5×1014The unit of impurity concentration: cm-3；
H2) Making a thirteenth mask, and performing an eleventh ion implantation on the lower portion of the pre-stored node 211 by using the thirteenth mask to form a pre-stored node protection isolation 212 with P-type impurity concentration y, where y satisfies the relationship: y ═ 3 × 1013ln(x)-9×1014I, impurity concentration unit: cm-3；
H3) Making a fourteenth mask, and performing a twelfth ion implantation using the fourteenth mask at the right side of the pre-stored node protection isolation 212, i.e. with an implantation dose of 1 × 1015～1×1016cm-2Forming floating diffusion node 213 by using N-type impurities with energy of 10-30 kev, and annealing at 900-1200 ℃ for 10-16 s;
I. a passivation layer 6 is formed on the upper part of the polysilicon gate 5 by using a plasma enhanced chemical vapor deposition process to form a film with a thickness of
The passivation layer 6;
J. the pixel interconnection metal 7, the pump gate electrode 8, the transfer gate electrode 9 and the source electrode 10 are fabricated on the passivation layer 6:
J1) a fifteenth mask is made, and a pump gate electrode 8, a transfer gate electrode 9 and a source electrode 10 are respectively formed on the passivation layer 6 by using a metal deposition process through the fifteenth mask;
J2) making a sixteenth-time making mask, and using the sixteenth-time making mask to make pixel interconnection metal 7 by using a metal deposition process on the upper parts of the pump gate electrode 8 and the transfer gate electrode 9;
K. and (4) manufacturing a drain electrode 11 on the back surface of the substrate 1 by using a metal deposition process, thereby completing the manufacture of the whole device.
Compared with the traditional CMOS image sensor pixel, the invention has the following advantages:
first, the charge transfer speed is improved.
The invention adopts the pump grid technology, so that the electric field modulation capability of the pump grid is far higher than that of the transmission grid. When the pump gate voltage is the turn-on voltage, the pump gate generates a larger electric field strength on the photodiode, thereby increasing the transfer speed of charges on the photodiode.
Second, the transfer efficiency of charges is improved.
According to the invention, the N-type channel adjusting layer is manufactured below the pump gate, and when the pump gate is switched on to be high voltage, a monotonically increasing potential is generated between the N-type region of the photodiode and the N-type channel adjusting layer, so that the charge transfer efficiency of the device is improved, the charge transfer efficiency of the device reaches 99.999%, and further, the detection precision of the three-dimensional depth imaging radar system is improved
Simulation results show that the invention adopts the technological parameters of the standard CMOS image sensor to design and verify the device, thereby reducing the manufacturing cost of the device and improving the cost performance.
Drawings
FIG. 1 is a block diagram of a conventional CMOS image sensor pixel;
FIG. 2 is a diagram of a CMOS image sensor pixel structure according to the present invention
FIG. 3 is a flow chart of a CMOS image sensor pixel fabrication process according to the present invention;
FIG. 4 is a simulation plot of charge transfer rate for a pixel of a CMOS image sensor of the present invention and a conventional CMOS image sensor;
FIG. 5 is a graph of the potential distribution of a pixel of a CMOS image sensor of the present invention and conventional;
FIG. 6 is a timing diagram illustrating the operation of the simulation of the present invention.
Detailed Description
The embodiments and effects of the present invention will be further described with reference to the accompanying drawings.
Referring to fig. 2, the pixel structure of the CMOS image sensor of the present invention includes a substrate 1, an epitaxial layer 2, a shallow trench isolation layer 3, a gate oxide layer 4, a polysilicon gate 5, and a passivation layer 6. A drain electrode 11 is deposited below the substrate 1 and a source electrode 10 is deposited at the upper right hand corner of the epitaxial layer 2.
The epitaxial layer 2 is provided with a charge storage region 21, a photoresponsive region 22, and a threshold voltage adjusting region 23.
And the charge storage region 21 is composed of a pre-storage node 211, a pre-storage node protection isolation 212 and a floating diffusion node 213, and the pre-storage node 211 is arranged at the upper part of the pre-storage node protection isolation 212. Wherein, the relationship between the impurity concentration x of the pre-stored node 211 and the impurity concentration y of the pre-stored node protection isolation 212 is as follows: y ═ 3 × 1013ln(x)-9×1014And the impurity concentration range is 1 × 10 |11＜x＜5×1014The unit of impurity concentration: cm-3。
The photoresponsive region 22 is composed of a clamp layer 221, a barrier adjustment layer 222, a P-type well region 223 and an N-type region 224 of the photodiode, wherein the clamp layer 221 is on the upper portion of the barrier adjustment layer 222, and the P-type well region 223 is on both sides of the N-type region 224 of the photodiode. Wherein the junction depth a of the clamp layer 221 is 0.1 μm to 0.2 μm, the junction depth b of the N-type region 224 of the photodiode is 1.0 μm to 2.0 μm, the P-type well region 223 is composed of a floating diffusion node protection isolation layer 2231, a transfer gate threshold adjustment layer 2232, and a P-type well 2233, the floating diffusion node protection isolation layer 2231 is located above the transfer gate threshold adjustment layer 2232, and the transfer gate threshold adjustment layer 2232 is located above the P-type well 2233;
the N-type region 224 of the photodiode is composed of two parts, i.e., a tilted implantation region 2241 and a non-tilted implantation region 2242, and the tilted implantation region 2241 is located above the non-tilted implantation region 2242.
The threshold voltage adjustment region 23 is composed of an N-type channel adjustment layer 231 and a P-type channel adjustment layer 232, and the N-type channel adjustment layer 231 is located on the left side of the P-type channel adjustment layer 232.
The shallow trench isolation layer 3 is positioned at two sides of the epitaxial layer 2, and the gate oxide layer 4 is positioned at the upper part of the epitaxial layer 2.
The polysilicon gate 5 is located on the gate oxide layer 4 and is composed of a pump gate 51 and a transmission gate 52, the pump gate 51 is located on the P-type channel adjustment layer 232, and the transmission gate 52 is located on the N-type channel adjustment layer 231. Wherein, the length c of the pump gate 51 is 0.8 μm to 2.0 μm, the thickness d is 0.2 μm to 0.3 μm, the length e of the transmission gate 52 is 0.4 μm to 1.0 μm, and the thickness f is 0.2 μm to 0.3 μm.
The passivation layer 6 covers the polysilicon gate 5, a pump gate electrode 8 and a transfer gate electrode 9 are deposited on the polysilicon gate 5, and pixel interconnection metal 7 is deposited on the pump gate electrode 8 and the transfer gate electrode 9.
Referring to fig. 3, the method for fabricating a pixel structure of a CMOS image sensor according to the present invention provides the following three embodiments:
the first embodiment is as follows: and manufacturing the CMOS image sensor pixel with the length c of the pump gate being 0.8 mu m, the thickness d being 0.2 mu m, the length e of the transfer gate being 0.4 mu m and the thickness f being 0.2 mu m.
Placing a substrate 1 in a reaction chamber, performing chemical vapor deposition on the substrate 1, and epitaxially growing to a thickness ta of 13 μm and a doping concentration of 1 × 1013cm-3E.g. as in fig. 3 a.
Wherein the properties of the substrate 1: the conductive type is p type, the diameter of the silicon wafer is 8 inches, and the resistivity of the silicon wafer is p of 50 omega cm+The silicon type has radial nonuniformity of resistivity less than 5%, minority carrier lifetime greater than 100 μ s, and impurity concentration in 1.0 × 1019In a crystal orientation of<111>The silicon wafer is in a grinding plate shape, the thickness range of the silicon wafer is 600 mu m, the thickness tolerance is 5 mu m, the total thickness deviation is less than 10 mu m, the bending deviation is less than 10 mu m, the surface quality has no holes, cracks and oxidation patterns, and the dislocation density is less than 100cm-2Carbon content of less than 5X 1016atoms/cm-2Oxygen content of less than 1X 1018atoms/cm-2。
The chemical vapor deposition process conditions are as follows: the temperature of the reaction chamber is 1200 ℃, SiCl4At H2The mole percentage of (1) is 5%, and the film growth rate is 0.5 μm/min.
And 2, manufacturing a shallow trench isolation layer 3 on the epitaxial layer 2.
2.1) manufacturing a first mask on the upper part of the epitaxial layer 2, and forming a shallow trench with the depth Td of 0.3 μm on the epitaxial layer 2 by using the mask and an etching process, as shown in b in FIG. 3;
2.2) forming a silicon dioxide layer with the thickness of 0.3 μm on the shallow trench by using plasma enhanced chemical vapor deposition. Wherein, the plasma enhanced chemical vapor deposition process conditions are as follows: n is a radical of2O flow rate of 850sccm, SiH4Flow rate of 200sccm, temperature of 250 deg.C, RF power of 25W, and pressure of 1100mT, as shown in c of FIG. 3;
2.3) removing the silicon dioxide material on the upper part of the epitaxial layer 2 by using a chemical mechanical polishing process to form a shallow trench isolation layer 3, as shown in d in fig. 3;
and 3, manufacturing P-type well regions 223 on two sides of the epitaxial layer 2.
3.1) forming a shallow trench isolation layer 3 on top of the substrate with a thickness of
The silicon dioxide layer of (1). Wherein, the plasma enhanced chemical vapor deposition process conditions are as follows: n is a radical of2O flow rate of 850sccm, SiH4Flow rate of 200sccm, temperature of 250 deg.C, RF power of 25W, and pressure of 1100mT, as shown in e of FIG. 3;
3.2) making a second mask, and using the second mask, performing a first ion implantation on both sides of the epitaxial layer 2, i.e. with an implantation dose of 5 × 1013cm-2, P-type impurity of energy 120kev, forming a transfer gate threshold adjustment layer 2231, f in fig. 3;
3.3) making a third mask, and performing a second ion implantation with a dose of 5 × 10 below the transfer gate threshold adjustment layer 223112cm-2, P-type impurity with energy of 70kev, forming a floating diffusion node protective isolation layer 2232, g in fig. 3;
3.4) preparation of the fourth timeA mask for performing a third ion implantation with a dose of 1 × 10 under the floating diffusion node protective isolation layer 223211cm-2, P-type impurity with energy of 10kev, forming P-well 2233, h in fig. 3.
And 4, manufacturing an N-type region 224 of the photodiode in the middle of the epitaxial layer 2.
4.1) making a fifth mask, and performing a fourth ion implantation with the mask in the middle of the P-type well region 223 with an implantation dose of 1 × 1012cm-2, an N-type impurity of energy 100kev, forming an angled implant region 2241, fig. 3 i;
4.2) making a sixth mask, and performing a fifth ion implantation under the inclined implantation region 2241 by using the sixth mask, i.e. the implantation dose is 4 × 1011cm-2, an N-type impurity with an energy of 100kev, forming a non-angled implant region 2242, j in fig. 3.
And 5, manufacturing a gate oxide layer 4 on the upper part of the epitaxial layer 2.
5.1) making a seventh mask, and performing a sixth ion implantation on the upper part of the N-type region 224 of the photodiode by using the seventh mask, wherein the implantation dose is 1 × 1012cm-2, P-type impurity with energy of 18kev, forming clamp layer 221, k in fig. 3;
5.2) making an eighth mask, and performing a seventh ion implantation under the clamp layer 221 by using the eighth mask, i.e. with an implantation dose of 2 × 1012cm-2, P-type impurity with energy of 6kev, forming the barrier adjusting layer 222, l in fig. 3;
5.3) making a ninth mask, and performing an eighth ion implantation on the right side of the barrier adjusting layer 222 using the ninth mask, i.e., with an implantation dose of 4 × 1011cm-2, an N-type impurity of 20kev in energy to form an N-type channel adjustment layer 231, m in fig. 3;
5.4) making a tenth mask, and performing a ninth ion implantation with the mask on the right side of the N-type channel adjustment layer 231, i.e. with an implantation dose of 2 × 1012cm-2, a P-type impurity of 8kev energy to form the P-type channel adjustment layer 232, and annealing at 900 deg.c for 18s, as n in fig. 3;
5.5) adjustment in P-type channelThe upper portion of layer 232 is formed to a thickness of
A gate oxide layer 4. Wherein, the thermal oxidation process conditions are as follows: the temperature of the oxidation chamber is 800 ℃ and O2The partial pressure was 760Torr, as shown by o in FIG. 3.
And 6, manufacturing a polysilicon gate 5 on the upper part of the gate oxide layer 4.
6.1) depositing a polysilicon layer with the thickness tf of 0.18 mu m on the upper part of the gate oxide layer 4 by using a chemical vapor deposition process, wherein the chemical vapor deposition process conditions are as follows: the temperature of the reaction chamber is 1270 ℃, SiCl4At H2The mole percentage of (1) is 5%, and the film growth rate is 2.5 μm/min, p in FIG. 3.
6.2) an eleventh sub-mask is made, with which a pump gate 51 with a length c of 0.8 μm and a thickness d of 0.2 μm and a transfer gate 52 with a length e of 0.4 μm and a thickness f of 0.2 μm are formed using an etching process on top of the polysilicon layer, as indicated by q in fig. 3.
And 7, manufacturing a side wall 53 around the polysilicon gate 5.
7.1) depositing a silicon nitride layer with a thickness of 0.03 μm over the polysilicon gate 5 using a plasma enhanced chemical vapor deposition process, wherein the plasma enhanced chemical vapor deposition conditions are: the gas being NH3、N2And SiH4The gas flow rates were 2.5sccm, 950sccm and 250sccm, respectively, and the temperature, RF power and pressure were 300 deg.C, 25W and 950mT, respectively, as r in FIG. 3;
7.2) etching 30% of the silicon nitride layer around the polysilicon gate 5 using an etching process to form the spacers 53, as shown by s in fig. 3.
And 8, forming a floating diffusion node 213 by using ion implantation.
8.1) a twelfth mask is made, and a tenth ion implantation is performed on the right side of the pump gate 51 using the twelfth mask to form a pre-stored node 211 having an N-type impurity concentration x, where x is 1 × 1011The unit of impurity concentration: cm-3T in fig. 3;
8.2) making a thirteenth mask, using the maskPerforming an eleventh ion implantation on the lower portion of the pre-storage node 211 to form a pre-storage node protection isolation 212 with P-type impurity concentration y, where y is 1.4014 × 1014The unit of impurity concentration: cm-3U in fig. 3;
8.3) making a fourteenth mask, and using the fourteenth mask to perform a twelfth ion implantation on the right side of the pre-stored node protection isolation 212, i.e. the implantation dose is 1 × 1015cm-2, an N-type impurity with energy of 10kev, forming a floating diffusion node 213, and annealing at 900 ℃ for 10s, as shown by v in FIG. 3;
step 9, manufacturing a passivation layer 6 on the upper part of the polysilicon gate 5, and forming the passivation layer with the thickness of
Wherein, the plasma enhanced chemical vapor deposition process conditions are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the RF power was 25W, and the pressure was 1100mT, as indicated by W in FIG. 3.
And 10, manufacturing a pixel interconnection metal 7, a pump gate electrode 8, a transmission gate electrode 9 and a source electrode 10 on the passivation layer 6.
10.1) making a fifteenth mask, using which a pump gate electrode 8 is formed on the pump gate 51, a transfer gate electrode 9 is formed on the transfer gate 52, and a source electrode 10 is formed on the floating diffusion node 213, using a metal deposition process on the passivation layer 6, as shown by x in fig. 3;
10.2) a sixteenth manufacturing mask is made with which a metal deposition process is used on top of the pump gate electrode 8, the transfer gate electrode 9 to make the pixel interconnect metal 7, y in fig. 3.
And 11, manufacturing the drain electrode 11 on the back surface of the substrate 1 by using a metal deposition process, namely completing the manufacture of the whole device, such as z in fig. 3.
Example two: and manufacturing the CMOS image sensor pixel with the length c of the pump gate being 2.0 mu m, the thickness d being 0.3 mu m, the length e of the transfer gate being 1.0 mu m and the thickness f being 0.3 mu m.
Step one, a P-type silicon semiconductor material is extended on a substrate 1 to form an epitaxial layer 2.
The substrate 1 was placed in a reaction chamber at 1250 ℃ in SiCl4At H2The mol percentage of the silicon nitride is 10 percent, the epitaxial growth thickness of the silicon nitride is 20 mu m on the substrate 1 under the chemical vapor deposition process condition that the film growth rate is 1.0 mu m/min, and the doping concentration is 8 multiplied by 1013cm-3 epitaxial layer 2, wherein the properties of substrate 1 are the same as described in step 1 of example 1, as in a of fig. 3.
And step two, manufacturing a shallow trench isolation layer 3 on the epitaxial layer 2.
2a) A first mask is made on the upper part of the epitaxial layer 2, and a shallow trench with a depth Td of 0.3 μm is formed on the epitaxial layer 2 by using an etching process using the mask, as shown in b of fig. 3;
2b) a silicon dioxide layer with a thickness of 0.3 μm is formed on the shallow trench using a plasma enhanced chemical vapor deposition process. Wherein, the plasma enhanced chemical vapor deposition process conditions are as follows: n is a radical of2O flow rate of 880sccm, SiH4A flow rate of 220sccm, a temperature of 250 ℃, an RF power of 25W, and a pressure of 1100mT, as shown in c of FIG. 3;
2c) removing the silicon dioxide material on the upper portion of the epitaxial layer 2 by using a chemical mechanical polishing process to form a shallow trench isolation layer 3, as shown in d of fig. 3;
and step three, manufacturing P-type well regions 223 on two sides of the epitaxial layer 2.
3a) In N2O flow rate of 880sccm, SiH4Forming a shallow trench isolation layer 3 with a thickness of 220sccm on the upper part under the conditions of a plasma enhanced chemical vapor deposition process with a flow rate of 250 ℃, an RF power of 25W and a pressure of 1100mT
E in fig. 3;
3b) a second mask is made, and a first ion implantation is performed on both sides of the epitaxial layer 2 using the second mask, i.e., at a dose of 9 × 1013cm-2, P-type impurity of energy 153kev, forming a transfer gate threshold adjustment layer 2231, f in fig. 3;
3c) a third mask is formed, and a second ion implantation is performed below the transfer gate threshold adjustment layer 2231 using the third mask, i.e., at a dose of 9 × 1012cm-2, P-type impurity of energy 85kev, forming a floating diffusion node protective isolation layer 2232, g in fig. 3;
3d) making a fourth mask, and performing a third ion implantation with a dose of 4 × 10 under the floating diffusion node protective isolation layer 223211cm-2, P-type impurity with energy of 15kev, forming P-well 2233, h in fig. 3.
And fourthly, manufacturing an N-type region 224 of the photodiode in the middle of the epitaxial layer 2.
4a) A fifth mask is formed, and a fourth ion implantation is performed in the middle of the P-well 223 with a dose of 3 × 1012cm-2, an N-type impurity with an energy of 130kev, forming an angled implant region 2241, fig. 3 i;
4b) a sixth mask is formed, and a fifth ion implantation is performed at a lower portion of the inclined implantation region 2241 using the sixth mask, that is, an implantation dose of 8 × 1011cm-2, an N-type impurity with an energy of 130kev, forming a non-angled implant region 2242, j in fig. 3.
And step five, manufacturing the gate oxide layer 4.
5a) A seventh mask is made and a sixth ion implantation is performed using the seventh mask at the upper portion of the N-type region 224 of the photodiode, i.e., at a dose of 3 × 1012cm-2, P-type impurity with energy of 25kev, forming clamp layer 221, k in fig. 3;
5b) an eighth mask is formed, and a seventh ion implantation is performed using the eighth mask at a dose of 6 × 10 below the clamp layer 22112cm-2, P-type impurity with energy of 10kev, forming the barrier adjusting layer 222, l in fig. 3;
5c) a ninth mask is formed, and an eighth ion implantation is performed on the right side of the barrier adjusting layer 222 using the ninth mask, that is, the implantation dose is 8 × 1011cm-2, an N-type impurity of energy 30kev, forming an N-type channel adjustment layer 231, m in fig. 3;
5d) making a tenth sub-mask using the maskThe mold performs a ninth ion implantation at the right side of the N-type channel adjustment layer 231, i.e. the implantation dose is 5 × 1012cm-2, a P-type impurity of energy 14kev, forming a P-type channel adjusting layer 232, and annealing at a temperature of 1200 ℃ for 20s, as shown by n in fig. 3;
5e) at an oxidation chamber temperature of 850 deg.C, O2Forming a thickness of 780Torr on the upper portion of the P-type channel adjustment layer 232 by thermal oxidation
Such as o in fig. 3.
And sixthly, manufacturing a polysilicon gate 5 on the upper part of the gate oxide layer 4.
6a) At 1270 deg.C of reaction chamber temperature, SiCl4At H2The mol percentage in the figure is 10%, and a polycrystalline silicon layer with the thickness of 0.2 mu m, such as p in the figure 3, is deposited on the upper part of the gate oxide layer 4 under the chemical vapor deposition process condition that the film growth rate is 3.0 mu m/min;
6b) an eleventh sub-mask is made, and an etching process is used on the upper portion of the polysilicon layer using the mask to form a pump gate 51 having a length c of 2.0 μm and a thickness d of 0.3 μm and a transfer gate 52 having a length e of 1.0 μm and a thickness f of 0.3 μm, as shown by q in fig. 3.
And step seven, manufacturing a side wall 53 around the polysilicon gate 5.
7a) In the presence of NH as gas3、N2And SiH4Depositing a silicon nitride layer with a thickness of 0.05 μm, as shown by r in fig. 3, over the polysilicon gate 5 under the plasma enhanced chemical vapor deposition process conditions of a gas flow of 2.5sccm, 950sccm and 250sccm, a temperature, an RF power and a pressure of 300 ℃, 25W and 950mT, respectively;
7b) an etching process is used to etch 50% of the silicon nitride layer around the polysilicon gate 5 to form the spacers 53, s in fig. 3.
And step eight, respectively forming a pre-storage node 211, a pre-storage node protection isolation 212 and a floating diffusion node 213 by using ion implantation.
8a) A twelfth mask is made, and a tenth shot is performed on the right side of the pump gate 51 using the twelfth maskSub-implanting to form a pre-stored node 211 with an N-type impurity concentration of x, where x is 5 × 1014The unit of impurity concentration: cm-3T in fig. 3;
8b) making a thirteenth mask, and performing an eleventh ion implantation under the pre-storage node 211 by using the thirteenth mask to form a pre-storage node protection isolation 212 with P-type impurity concentration of y, where y is 1.15368 × 1014The unit of impurity concentration: cm-3U in fig. 3;
8c) making a fourteenth mask, and performing a twelfth ion implantation using the fourteenth mask at the right side of the pre-stored node protection isolation 212, i.e. with an implantation dose of 1 × 1016cm-2, an N-type impurity with an energy of 30kev, forming a floating diffusion node 213, and annealed at a temperature of 1200 c for 16s, v in fig. 3.
Step nine, in N2O flow rate of 880sccm, SiH4Forming a polysilicon gate 5 with a thickness of 220sccm on the upper part thereof under the conditions of a plasma enhanced chemical vapor deposition process at a temperature of 250 ℃, an RF power of 25W and a pressure of 1100mT
Such as w in fig. 3.
And step ten, manufacturing a pixel interconnection metal 7, a pump gate electrode 8, a transmission gate electrode 9 and a source electrode 10 on the passivation layer 6.
10a) Making a fifteenth sub-mask by which a pump gate electrode 8 is formed on the pump gate 51, a transfer gate electrode 9 is formed on the transfer gate 52, and a source electrode 10 is formed on the floating diffusion node 213, using a metal deposition process on the passivation layer 6, as shown by x in fig. 3;
10b) a sixteenth production mask is produced with which a metal deposition process is used on top of the pump gate electrode 8, the transfer gate electrode 9 to produce the pixel interconnection metal 7, y in fig. 3.
Step eleven, manufacturing the drain electrode 11 on the back surface of the substrate 1 by using a metal deposition process, namely completing the manufacture of the whole device, such as z in fig. 3.
Example three: a CMOS image sensor pixel with a pump gate length c of 1.5 μm, a thickness d of 0.25 μm, a transfer gate length e of 0.8 μm, and a thickness f of 0.25 μm was fabricated.
Step A, extending a P-type silicon semiconductor material on a substrate 1 to form an epitaxial layer 2.
Placing a substrate 1 in a reaction chamber, epitaxially growing on the substrate 1 by chemical vapor deposition to a thickness of 18 μm and a doping concentration of 5 × 1013cm-3 epitaxial layer 2, fig. 3 a.
The chemical vapor deposition process has the following conditions: the temperature of the reaction chamber is 1270 ℃, SiCl4At H2The mole percentage of (1) is 15%, and the film growth rate is 1.5 μm/min.
The substrate 1 had the same properties as those described in step 1 of example 1.
And B, manufacturing a shallow trench isolation layer 3 on the epitaxial layer 2.
B1) A first mask is made on the upper part of the epitaxial layer 2, and a shallow trench with the depth of 0.35 mu m is formed on the epitaxial layer (2) by using the mask and an etching process, as shown in b in figure 3;
B2) a silicon dioxide layer with a thickness of 0.5 μm is formed on the shallow trench using a plasma enhanced chemical vapor deposition process. Wherein, the plasma enhanced chemical vapor deposition process conditions are as follows: n is a radical of2O flow rate of 900sccm, SiH4The flow rate was 250sccm, the temperature was 250 ℃, the RF power was 25W, and the pressure was 1100mT, as shown in c of FIG. 3.
B3) The silicon dioxide material on the upper portion of the epitaxial layer 2 is removed using a chemical mechanical polishing process to form shallow trench isolation layers 3, as shown in fig. 3 d.
Step c, P-type well regions 223 are formed on both sides of the epitaxial layer 2.
C1) Forming a shallow trench isolation layer 3 on the substrate with a thickness of
The silicon dioxide layer of (1). Wherein, the plasma enhanced chemical vapor deposition process conditions are as follows: n is a radical of2O flow rate of 900sccm, SiH4Flow rate of 250sccm, temperature of 250 deg.C, RFPower 25W and pressure 1100mT, e in fig. 3;
C2) a second mask is formed, and a first ion implantation is performed on both sides of the epitaxial layer 2 using the second mask at an implantation dose of 8 × 1013cm-2, P-type impurity of energy 140kev, forming a transfer gate threshold adjustment layer 2231, f in fig. 3;
C3) a third mask is formed, and a second ion implantation is performed at a dose of 7 × 10 under the transfer gate threshold adjustment layer 2231 using the third mask12cm-2, P-type impurity with energy of 80kev, forming a floating diffusion node protective isolation layer 2232, g in fig. 3;
C4) making a fourth mask, and performing a third ion implantation with a dose of 3 × 10 under the floating diffusion node protective isolation layer 223211cm-2, P-type impurity with energy of 40kev, forming P-well 2233, h in fig. 3.
Step d. an N-type region 224 of the photodiode is fabricated in the middle of the epitaxial layer 2.
D1) A fifth mask is formed, and a fourth ion implantation is performed in the middle of the P-well 223 with an implantation dose of 2 × 1012cm-2, N-type impurity of energy 110kev, forming an angled implant region 2241, as in i of fig. 3;
D2) a sixth mask is formed, and a fifth ion implantation is performed at a dose of 6 × 10 using the sixth mask in a lower portion of the inclined implantation region 224111cm-2, N-type impurity of energy 120kev, forming a non-angled implant region 2242, j in fig. 3.
And E, manufacturing the gate oxide layer 4.
E1) A seventh mask is made, and a sixth ion implantation is performed at a dose of 2 × 10 on the upper portion of the N-type region 224 of the photodiode using the seventh mask12cm-2, P-type impurity with energy of 20kev, forming clamp layer 221, k in fig. 3;
E2) an eighth mask is formed, and a seventh ion implantation is performed at a dose of 4 × 10 under the clamp layer 221 using the eighth mask12cm-2, P-type impurity with energy of 7kev, forming barrier adjusting layer 222, as shown by l in FIG. 3；
E3) A ninth mask is formed, and an eighth ion implantation is performed at a dose of 6 × 10 on the right side of the barrier adjusting layer 222 using the ninth mask11cm-2, an N-type impurity of energy 25kev, forming an N-type channel adjustment layer 231, m in fig. 3;
E4) a tenth mask is formed, and a ninth ion implantation is performed at a dose of 4 × 10 on the right side of the N-type channel adjustment layer 231 using the tenth mask12cm-2, P-type impurity with energy of 10kev, forming a P-type channel adjustment layer 232, and annealing at 980 ℃ for 19s, as shown by n in fig. 3;
E5) forming a thickness of
Such as o in fig. 3.
Wherein, the thermal oxidation process conditions are as follows:
the temperature of the oxidation chamber is 900 ℃ and O2The partial pressure was 800 Torr.
And F, manufacturing a polysilicon gate 5 on the upper part of the gate oxide layer 4.
F1) And depositing a polysilicon layer with the thickness of 0.19 mu m on the upper part of the gate oxide layer 4 by using a chemical vapor deposition process, wherein the chemical vapor deposition process conditions are as follows: the temperature of the reaction chamber is 1270 ℃, SiCl4At H215% and the film growth rate is 3.5 μm/min, p in fig. 3;
F2) making an eleventh mask, and forming a pump gate 51 and a transmission gate 52 on the upper part of the polysilicon layer by using an etching process by using the eleventh mask, wherein the length c of the pump gate is 1.5 μm, and the thickness d of the pump gate is 0.25 μm; the length e of the transfer gate is 0.8 μm and the thickness f is 0.25 μm, q in fig. 3.
And G, manufacturing a side wall 53 around the polysilicon gate 5.
G1) Depositing a silicon nitride layer with the thickness of 0.04 mu m above the polysilicon gate 5 by using a plasma enhanced chemical vapor deposition process, wherein the plasma enhanced chemical vapor deposition process conditions are as follows: NH (NH)3、N2And SiH4The gas flow rates were 2.5sccm, 950sccm and 250sccm, respectively, and the temperature, RF power and pressure were 300 deg.C, 25W and 950mT, respectively, as r in FIG. 3;
G2) an etching process is used to etch 40% of the silicon nitride layer around the polysilicon gate 5 to form the spacers 53, s in fig. 3.
Step h. floating diffusion node 213 is formed by ion implantation.
H1) A twelfth mask is made, and a tenth ion implantation is performed on the right side of the pump gate 51 using the twelfth mask to form a pre-stored node 211 having an N-type impurity concentration x, where x is 1 × 1013The unit of impurity concentration: cm-3T in fig. 3;
H2) making a thirteenth mask, and performing an eleventh ion implantation under the pre-storage node 211 by using the thirteenth mask to form a pre-storage node protection isolation 212 with P-type impurity concentration of y, where y is 1.9918 × 1012The unit of impurity concentration: cm-3U in fig. 3;
H3) making a fourteenth mask, and performing a twelfth ion implantation with a dose of 9 × 10 on the right side of the pre-stored node protection isolation 212 using the fourteenth mask15cm-2, an N-type impurity with an energy of 20kev, forming a floating diffusion node 213, and annealing at 980 ℃ for 15s, v in fig. 3.
Step I, manufacturing a passivation layer 6 on the upper part of the polysilicon gate 5, and forming the passivation layer with the thickness of
For example w in fig. 3, wherein the plasma enhanced chemical vapor deposition process conditions are as follows:
N2the O flow is 900 sccm; SiH4The flow rate is 250 sccm;
the temperature is 250 ℃;
the RF power is 25W;
the pressure was 1100 mT.
Step j. a pixel interconnection metal 7, a pump gate electrode 8, a transfer gate electrode 9 and a source electrode 10 are fabricated on the passivation layer 6.
J1) Making a fifteenth sub-mask by which voids are etched in the passivation layer 6 and using a metal deposition process, forming a pump gate electrode 8 on the pump gate 51, a transfer gate electrode 9 on the transfer gate 52, and a source 10 on the floating diffusion node 213, as shown by x in fig. 3;
J2) a sixteenth production mask is produced with which a metal deposition process is used on top of the pump gate electrode 8, the transfer gate electrode 9 to produce the pixel interconnection metal 7, y in fig. 3.
Step k, the drain 11 is fabricated on the back side of the substrate 1 using a metal deposition process, i.e. the fabrication of the whole device is completed, as shown in fig. 3 z.
The effects of the present invention can be further illustrated by the following simulations.
Simulation conditions
The simulated operation sequence of the present invention is shown in fig. 6, and the pump gate voltage V is set at the same time when t is 0TG3.3V and transmission gate voltage VPGAfter 10ns, the pump gate voltage V is set at 3.3VTG0V and transmission gate voltage VPG0V and the pulse falling edge of the transfer gate is delayed 5ns with respect to the pump gate. After 3ns, the photodiode is exposed and the pump gate voltage V is setTG3.3V and transmission gate voltage VPG3.3V and read the signal.
Second, simulation content and result
Simulation 1: under the above simulation conditions, the charge transfer transient characteristics of the conventional CMOS image sensor shown in fig. 1 and the CMOS image sensor of the present invention shown in fig. 2 were simulated, and the results are shown in fig. 4, in which the solid line is the charge transfer transient characteristic curve of the conventional CMOS image sensor and the dotted line is the charge transfer transient characteristic curve of the CMOS image sensor of the present invention.
As can be seen from fig. 4, when the size of the photodiode is the same as that of the conventional photodiode, the change curve of the electron concentration with time in the CMOS image sensor of the present invention is steeper than that of the conventional CMOS image sensor, indicating that the charge transfer rate of the CMOS image sensor of the present invention is significantly higher than that of the conventional CMOS image sensor. Therefore, the CMOS image sensor can improve the acquisition speed of photoelectric signal charges.
Simulation 2: the potential distribution characteristics of the conventional CMOS image sensor shown in fig. 1 and the CMOS image sensor of the present invention shown in fig. 2 were simulated under the above simulation conditions, and the results are shown in fig. 5, in which the solid line represents the potential distribution characteristic curve of the conventional CMOS image sensor and the dotted line represents the potential distribution characteristic curve of the CMOS image sensor of the present invention.
As can be seen from fig. 5, in the region surrounded by the dotted line in the figure, there is an obvious potential barrier on the potential distribution characteristic curve of the conventional CMOS image sensor, which may reduce the transfer speed of the signal charge, whereas the potential distribution characteristic curve of the CMOS image sensor of the present invention has no potential barrier, which indicates that the present invention may significantly improve the transfer speed of the signal charge and improve the detection accuracy of the three-dimensional depth imaging radar system.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.
Claims (10)
1. The utility model provides a CMOS image sensor pixel structure, including substrate (1), epitaxial layer (2), shallow trench isolation layer (3), gate oxide (4), polycrystalline silicon gate (5), passivation layer (6), the below deposit of substrate (1) has drain electrode (11), the upper right corner deposit of epitaxial layer (2) has source electrode (10), the higher authority deposit of polycrystalline silicon gate (5) has pump gate electrode (8) and transmission gate electrode (9), the higher authority deposit of pump gate electrode (8) and transmission gate electrode (9) has pixel interconnection metal (7), and be equipped with charge storage area (21) on epitaxial layer (2), photoelectric response region (22) and threshold voltage adjustment district (23), its characterized in that:
the charge storage region (21) is composed of a pre-storage node (211), a pre-storage node protection isolation (212) and a floating diffusion node (213), and the pre-storage node (211) is arranged above the pre-storage node protection isolation (212);
the photoelectric response region (22) is composed of a clamping layer (221), a potential barrier adjusting layer (222), a P-type well region (223) and an N-type region (224) of the photodiode, the clamping layer (221) is arranged on the upper portion of the potential barrier adjusting layer (222), and the P-type well region (223) is arranged on two sides of the N-type region (224) of the photodiode;
the threshold voltage adjusting region (23) is composed of an N-type channel adjusting layer (231) and a P-type channel adjusting layer (232), and the N-type channel adjusting layer (231) is arranged on the left side of the P-type channel adjusting layer (232);
the polysilicon gate (5) is composed of a pump gate (51) and a transmission gate (52), the pump gate (51) is positioned on the upper part of the P-type channel adjusting layer (232), and the transmission gate (52) is positioned on the upper part of the N-type channel adjusting layer (231).
2. An arrangement according to claim 1, characterized in that the relation between the impurity concentration x of the pre-stored node (211) and the impurity concentration y of the pre-stored node protection isolation (212) is: y ═ 3 × 1013ln(x)-9×1014And the impurity concentration range is 1 × 10 |11＜x＜5×1014The unit of impurity concentration: cm-3。
3. The structure of claim 1, wherein:
the junction depth a of the clamping layer (221) is 0.1-0.2 μm;
the junction depth b of the N-type region (224) of the photodiode is 1.0-2.0 μm.
4. The structure of claim 1, wherein:
the length c of the pump grid (51) is 0.8-2.0 μm, and the thickness d is 0.2-0.3 μm;
the length e of the transmission gate (52) is 0.4-1.0 μm, and the thickness f is 0.2-0.3 μm.
5. The structure of claim 1, wherein:
the P-type well region (223) is composed of a floating diffusion node protection isolation layer (2231), a transmission gate threshold value adjusting layer (2232) and a P-type well (2233), the floating diffusion node protection isolation layer (2231) is located on the upper portion of the transmission gate threshold value adjusting layer (2232), and the transmission gate threshold value adjusting layer (2232) is located on the upper portion of the P-type well (2233);
the N-type region (224) of the photodiode is composed of an inclined injection region (2241) and a non-inclined injection region (2242), and the inclined injection region (2241) is located above the non-inclined injection region (2242).
6. A method for manufacturing a pixel of a CMOS image sensor is characterized by comprising the following steps:
A. using chemical vapor deposition process on the substrate (1), the epitaxial growth thickness ta is 13-20 μm, and the doping concentration is 1 × 1013～8×1013cm-3An epitaxial layer (2);
B. manufacturing a shallow trench isolation layer (3) on the epitaxial layer (2):
b1) Manufacturing a first mask on the upper part of the epitaxial layer (2), and forming a shallow trench with the depth td of 0.3-0.4 mu m on the epitaxial layer (2) by using the mask and an etching process;
b2) Forming a silicon dioxide layer with the thickness of 0.3-0.4 mu m on the shallow trench by using a plasma enhanced chemical vapor deposition process;
b3) Removing the silicon dioxide material on the upper part of the epitaxial layer (2) by using a chemical mechanical polishing process to form a shallow trench isolation layer (3);
C. forming a P-type well region (223) on the epitaxial layer (2):
C1) forming a shallow trench isolation layer (3) on the upper portion thereof to a thickness of
A silicon dioxide layer of (a);
C2) making a second mask by which a first ion implantation is performed on both sides of the epitaxial layer (2), i.e.The implantation dose is 5 × 1013～9×1013cm-2Forming a transfer gate threshold adjustment layer (2231) by using a P-type impurity with energy of 120-153 kev;
C3) a third mask is made, and a second ion implantation is performed at the lower part of the transfer gate threshold adjusting layer (2231) by using the third mask, i.e. the implantation dose is 5 x 1012～9×1012cm-2Forming a floating diffusion node protection isolation layer (2232) by using P-type impurities with energy of 70-85 kev;
C4) making a fourth mask, and performing a third ion implantation with a dose of 1 × 10 under the floating diffusion node protective isolation layer (2232) by using the fourth mask11～4×1011cm-2Forming a P-well (2233) by using a P-type impurity with energy of 10-15 kev;
D. -forming an N-type region (224) of the photodiode on the epitaxial layer (2):
D1) making a fifth mask, and performing a fourth ion implantation with a dose of 1 × 10 in the middle of the P-type well region (223)12～3×1012cm-2Forming an inclined implantation region (2241) by using N-type impurities with energy of 100-130 kev;
D2) a sixth mask is made, and a fifth ion implantation is performed at the lower part of the inclined implantation region (2241) by using the sixth mask, that is, the implantation dose is 4X 1011～8×1011cm-2Forming a non-inclined implantation region (2242) by using N-type impurities with energy of 100-130 kev;
E. manufacturing a gate oxide layer 4;
E1) a seventh mask is made, and a sixth ion implantation is performed on the upper part of the N-type region (224) of the photodiode by using the seventh mask, namely, the implantation dosage is 1 x 1012～3×1012cm-2Forming a clamp layer (221) by using a P-type impurity with energy of 18-25 kev;
E2) an eighth mask is formed, and a seventh ion implantation is performed using the eighth mask at a dose of 2 × 10 below the clamp layer 22112～6×1012cm-2Forming a barrier adjusting layer (222) by using a P-type impurity with energy of 6-10 kev;
E3) making ofA ninth mask for performing an eighth ion implantation with a dose of 4 × 10 on the right side of the barrier adjusting layer (222)11～8×1011cm-2, an N-type impurity with energy of 20 to 30kev, forming an N-type channel adjustment layer (231);
E4) a tenth mask is formed, and a ninth ion implantation is performed at the right side of the N-type channel adjustment layer (231) using the tenth mask, i.e., at an implantation dose of 2 × 1012～5×1012cm-2Forming a P-type channel adjusting layer (232) by using a P-type impurity with energy of 8-14 kev, and annealing at 900-1200 ℃ for 18-20 s;
E5) a thermal oxidation process is used to form a layer with a thickness of
A gate oxide layer (4);
F. and manufacturing a polysilicon gate (5) on the upper part of the gate oxide layer (4):
F1) depositing a polysilicon layer with the thickness tf of 0.18-0.2 mu m on the upper part of the gate oxide layer (4) by using a chemical vapor deposition process;
F2) making an eleventh mask, and forming a pump gate (51) and a transmission gate (52) on the upper part of the polycrystalline silicon layer by using an etching process by using the eleventh mask;
G. manufacturing side walls (53) on the periphery of the polysilicon gate (5);
G1) depositing a silicon nitride layer with the thickness of 0.03-0.05 mu m above the polysilicon gate (5) by using a chemical vapor deposition process;
G2) etching 30-50% of the silicon nitride layer on the periphery of the polysilicon gate (5) by using an etching process to form a side wall (53);
H. forming a floating diffusion node 213 by ion implantation;
H1) making a twelfth mask, and performing a tenth ion implantation on the right side of the pump gate (51) by using the twelfth mask to form a pre-stored node (211) with an N-type impurity concentration of x, wherein the pre-stored node is 1 × 1011＜x＜5×1014The unit of impurity concentration: cm-3；
H2) Making a thirteenth mask, using the mask, at the lower part of the pre-stored node (211)And eleventh ion implantation to form a pre-stored node protection isolation (212) with P-type impurity concentration y, wherein y satisfies the relation: y ═ 3 × 1013ln(x)-9×1014I, impurity concentration unit: cm-3；
H3) Making a fourteenth mask, and performing a twelfth ion implantation using the fourteenth mask at the right side of the pre-stored node protection isolation (212), i.e. with an implantation dose of 1 × 1015～1×1016cm-2Forming floating diffusion nodes (213) by using N-type impurities with energy of 10-30 kev, and annealing at 900-1200 ℃ for 10-16 s;
I. a passivation layer (6) is manufactured on the upper part of the polysilicon gate (5), and a plasma enhanced chemical vapor deposition process is used to form the polysilicon gate with the thickness of
A passivation layer (6);
J. manufacturing a pixel interconnection metal (7), a pump gate electrode (8), a transmission gate electrode (9) and a source electrode (10) on the passivation layer (6):
J1) manufacturing a fifteenth mask, and respectively forming a pump gate electrode (8), a transmission gate electrode (9) and a source electrode (10) on the passivation layer (6) by using a metal deposition process through the fifteenth mask;
J2) making a sixteenth-time making mask, and using the sixteenth-time making mask to use a metal deposition process on the upper parts of the pump gate electrode (8) and the transmission gate electrode (9) to make pixel interconnection metal (7);
K. and (3) manufacturing a drain electrode (11) on the back surface of the substrate (1) by using a metal deposition process, and finishing the manufacture of the whole device.
7. The method of claim 6 wherein the chemical vapor deposition process conditions in steps a and F1) are as follows:
temperature of the reaction chamber: 1200-1270 ℃;
SiCl4at H2Mole percent of (A): 5-15%;
film growth rate: 0.5 to 1.5 μm/min.
8. The method of claim 6 wherein the plasma enhanced chemical vapor deposition process conditions in steps B2), C1) and I are as follows:
N2o flow rate: 850-900 sccm;
SiH4flow rate: 200-250 sccm;
temperature: 250 ℃;
RF power: 25W;
pressure: 1100 mT.
9. The method of claim 6, wherein the thermal oxidation process conditions in step E5 are as follows:
the temperature of the oxidation chamber is 800-900 ℃;
O2the partial pressure is 760to 800 Torr.
10. The method of claim 6, wherein the plasma enhanced chemical vapor deposition process conditions in step G1) are as follows:
the gas being NH3、N2And SiH4；
The gas flow rates are 2.5sccm, 950sccm and 250sccm respectively;
the temperature, RF power and pressure were 300 deg.C, 25W and 950mT, respectively.
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