CN109638025A - Cmos image sensor and preparation method thereof - Google Patents
Cmos image sensor and preparation method thereof Download PDFInfo
- Publication number
- CN109638025A CN109638025A CN201710929682.8A CN201710929682A CN109638025A CN 109638025 A CN109638025 A CN 109638025A CN 201710929682 A CN201710929682 A CN 201710929682A CN 109638025 A CN109638025 A CN 109638025A
- Authority
- CN
- China
- Prior art keywords
- doped zone
- photodiode
- doped
- image sensor
- cmos image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000005468 ion implantation Methods 0.000 claims description 41
- 150000002500 ions Chemical class 0.000 claims description 36
- 239000010410 layer Substances 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 230000005622 photoelectricity Effects 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- JXASPPWQHFOWPL-UHFFFAOYSA-N Tamarixin Natural products C1=C(O)C(OC)=CC=C1C1=C(OC2C(C(O)C(O)C(CO)O2)O)C(=O)C2=C(O)C=C(O)C=C2O1 JXASPPWQHFOWPL-UHFFFAOYSA-N 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910015900 BF3 Inorganic materials 0.000 description 2
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The present invention provides a kind of cmos image sensor and preparation method thereof, the preparation method includes at least: providing p-type dope semiconductor substrates, the first P-doped zone is formed in p-type dope semiconductor substrates, and first P-doped zone doping concentration be higher than p-type dope semiconductor substrates doping concentration, reset transistor is formed, the first P-doped zone is located at；Further include the steps that preparing photodiode, wherein the projection of the second P-doped zone, N-doped zone on the surface of a semiconductor substrate is entirely located in the projection of third P-doped zone on said surface.Photoelectronic leakage can be effectively suppressed by designing above, reduce the pixel dark current of CIS chip, so as to improve CIS picture element flaw, improve CIS chip quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of cmos image sensor and preparation method thereof.
Background technique
It is compared, cmos image with ccd image sensor (Charge Coupled Device, abbreviation CCD)
Sensor (CMOS image sensor, abbreviation CIS) is in its manufacturing process and existing integrated circuit fabrication process compatibility
With superior performance.CIS can integrate driving circuit and pixel, simplify hardware design, greatly reduce and be
The power consumption of system.CIS can take out electric signal while acquiring optical signal, moreover it is possible to real time processed images information, speed ratio CCD
Imaging sensor is fast, also, CIS also has that cheap, bandwidth is larger, anti-blur, access flexibility and biggish filling
The advantages that coefficient.
Existing CIS can substantially be divided into tri- kinds of PPS, APS and DPS according to its playback mode.Passive type dot structure
(Passive Pixel Sensor, abbreviation PPS), for the structure occurred earliest, it includes a photodiode
(Photodiode) and a row selects (Row-select) transistor, and photodiode is substantially one by P-type semiconductor and N
Type semiconductor group at PN junction, it can be equivalent to a reverse bias diode and a mos capacitance parallel connection.When reading, beat
Start and select transistor, charge is integrated by the integrator of the column, finally reads voltage.With passive type dot structure phase
Than active dot structure (Active Pixel Sensor, abbreviation APS) includes a source follower (Source
Follower), the number of the transistor according to included by a pixel unit circuit, existing active dot structure are divided into 3T type
Structure and 4T type structure can also have 5T type structure.As shown in Figure 1, being a 4T type active dot structure, structure is usually wrapped
Include reset (Reset) transistor, a source follower (Source follower), row choosing (Row-select) crystalline substance
Body pipe (not regarding out in figure), a transfering transistor (TX), a photodiode (Photo Diode, PD), transfering transistor are used
A floating diffusion region (Floating Diffusion, FD) is input in the electric signal for generating photodiode.Using active
Dot structure amplifies and buffers PD signal just in pixel unit due to joined active circuit in pixel unit,
Improve the sensitivity of CIS imaging sensor, and signal reading speed is fast and signal-to-noise ratio with higher, therefore is made extensively
With.
In CIS chip, it is frequently encountered the phenomenon that causing chip functions to decline due to picture element flaw, in pixel region
" dark current " is the main reason for causing picture element flaw, and " dark current " mainly due to caused by photoelectronic dissipation, so
Reducing " pixel dark current " is the key that improve CIS pixel qualities direction.It is main in traditional CIS manufacturing process that there are three former
Because leading to photoelectronic dissipation: first, it is less isolated between pixel, cause photoelectron gradually to be revealed to the substrate of adjacent pixel；
Second, the photoelectron that photostage generates cannot control well in the trap of photodiode, cause photoelectron gradually to picture
The surfaces of active regions of plain unit is revealed；The space dissipation region of third, reset transistor is excessive, causes photoelectron gradually to reset
The source/drain of transistor is revealed.
So needing to improve the manufacturing process of CIS to reduce photoelectronic dissipation, so as to improve picture element flaw, to improve
CIS chip quality.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of cmos image sensor and its
Preparation method, there are photoelectron leakages for the manufacturing process for solving CIS in the prior art, so as to cause CIS chip dark current
The problem of.
In order to achieve the above objects and other related objects, cmos image sensor preparation method provided by the invention, at least
It include: that p-type dope semiconductor substrates are provided；
The first P-doped zone, and the doping of first P-doped zone are formed in the p-type dope semiconductor substrates
Concentration is higher than the doping concentration of the p-type dope semiconductor substrates；
Reset transistor is formed, first P-doped zone is located at.
Preferably, first P-doped zone with a thickness ofDoped ions are boron difluoride.
Preferably, the preparation method further includes preparing photodiode, and first P-doped zone is located at the photoelectricity two
The periphery of pole pipe, the step of preparing the photodiode include:
Photoresist layer is formed on p-type dope semiconductor substrates surface；
The photoresist layer is exposed and the photoresist layer for being formed and having the first ion implantation window that develops；
N-type ion injection is carried out in the p-type dope semiconductor substrates by first ion implantation window, is formed
The N-doped zone of the photodiode；
P-type ion injection is carried out in the N-doped zone of the photodiode by first ion implantation window,
The second P-doped zone is formed in the surface layer of the N-doped zone；
Part photoresist is removed along the side of first ion implantation window, to expand ion implantation window, forms tool
There is the photoresist layer of the second ion implantation window；
P-type ion injection, Yu Suoshu are carried out in second P-doped zone by second ion implantation window
The surface layer of two P-doped zones forms third P-doped zone, so that second P-doped zone, N-doped zone are partly led described
Projection on the surface of body substrate is entirely located in the projection of the third P-doped zone on said surface.
By the way that third P-doped zone is arranged, and make second P-doped zone, N-doped zone in the semiconductor substrate
Surface on projection be entirely located in the projection of the third P-doped zone on said surface, the light can be effectively suppressed
The photoelectron that electric diode generates is revealed by the third P-doped zone to surfaces of active regions, meanwhile, forming the third
When P-doped zone, only part photoresist need to be removed using oxygen on the basis of original photoresist layer 241, so also not needing
Increase exposure mask amount.
Further, boundary and the reset transistor of first P-doped zone close to the photodiode
Boundary alignment of the source electrode close to the photodiode；Alternatively,
First P-doped zone is close close to the source electrode that the boundary of the photodiode is located at the reset transistor
Between the boundary and photodiode of the photodiode；Alternatively,
First P-doped zone is aligned close to the boundary of the photodiode with the photodiode.
Further, the ion implantation energy for forming the photodiode N-doped zone is 160kev-180kev, is mixed
Heteroion is phosphorus or arsenic, and doping thickness isAlternatively,
The ion implantation energy for forming second P-doped zone is 25kev-35kev, second P-doped zone
Doped ions are boron difluoride；Alternatively,
The ion implantation energy for forming the third P-doped zone is 25kev-35kev, the third P-doped zone
Doped ions are boron difluoride.
Further, the overall thickness of second P-doped zone and the third P-doped zone is
Preferably, the step of preparing the reset transistor include:
The grid of reset transistor is formed on first P-doped zone surface；
N-type ion injection is carried out in the first P-doped zone of the grid two sides of the reset transistor, is formed described multiple
The source electrode and drain electrode of bit transistor.
By the way that the first P-doped zone is arranged, the photodiode surrounding in each active pixel area is by with concentration ladder
The p type island region domain of degree surrounds, and the concentration gradient is formed by p-type dope semiconductor substrates and the first P-doped zone, has been increased
Isolation effect between source pixel, so that the photoelectron that effectively limitation photodiode generates passes through p-type dope semiconductor substrates
It is revealed to adjacent pixel unit；In addition, the doping concentration due to first P-doped zone is higher than the p-type doped semiconductor
The doping concentration of substrate effectively inhibits the parasitic triode effect of CMOS tube, can effectively cut off photoelectron and be mixed by the p-type
Source electrode or drain electrode leakage of the miscellaneous semiconductor substrate to the reset transistor, while also improving the breakdown of the reset transistor
Voltage, the leakage current for reducing the reset transistor and the space depleted region for reducing the reset transistor, thus
Improve the performance of the reset transistor.
Preferably, the step of preparing the reset transistor further includes that ion is infused on the first P-doped zone of Yu Suoshu surface
Enter to be formed the 4th P-doped zone, the 4th P-doped zone is located between the source electrode and drain electrode of the reset transistor, and should
The doping concentration of 4th P-doped zone is greater than the doping concentration of first P-doped zone, is mixed by forming the 4th p-type
The channel inversion ability of reset transistor can be improved in miscellaneous area.
Preferably, the preparation method further includes preparation between the photodiode and the reset transistor
The step of transfering transistor, and the transfering transistor and the reset transistor common-source, the N-type of the light emitting diode
Doped region is also used as the drain electrode of the transfering transistor.
Correspondingly, the present invention also proposes a kind of cmos image prepared by the preparation method using above-mentioned cmos image sensor
Sensor, comprising:
P-type dope semiconductor substrates；
The first P-doped zone, and the doping of first P-doped zone are formed in the p-type dope semiconductor substrates
Concentration is higher than the doping concentration of the p-type dope semiconductor substrates；
Reset transistor is located at first P-doped zone.
Preferably, first P-doped zone with a thickness ofDoped ions are boron difluoride.
Preferably, further includes: photodiode, first P-doped zone are located at the periphery of the photodiode, institute
Stating photodiode includes:
The N-doped zone being formed on the P-type semiconductor substrate；
The second P-doped zone being formed in the N-doped zone；
The third P-doped zone being formed in second P-doped zone, second P-doped zone, N-doped zone
Projection on the surface of the semiconductor substrate is entirely located in the projection of the third P-doped zone on said surface.
Further, boundary and the reset transistor of first P-doped zone close to the photodiode
Boundary alignment of the source electrode close to the photodiode；Alternatively,
First P-doped zone is close close to the source electrode that the boundary of the photodiode is located at the reset transistor
Between the boundary and photodiode of the photodiode；Alternatively,
First P-doped zone is aligned close to the boundary of the photodiode with the photodiode.
Further, the ion implantation energy for forming the photodiode N-doped zone is 160kev-180kev, is mixed
Heteroion is phosphorus or arsenic, and doping thickness isAlternatively,
The ion implantation energy for forming second P-doped zone is 25kev-35kev, second P-doped zone
Doped ions are boron difluoride；Alternatively,
The ion implantation energy for forming the third P-doped zone is 25kev-35kev, the third P-doped zone
Doped ions are boron difluoride.
Preferably, the overall thickness of second P-doped zone and the third P-doped zone is
Preferably, the reset transistor includes:
It is formed in the grid of the reset transistor on first P-doped zone surface；
It is formed in the source electrode and drain electrode of the reset transistor of the reset transistor gate two sides, the source electrode and drain electrode position
In in first P-doped zone.
Preferably, the reset transistor further includes that the 4th p-type being formed on first P-doped zone surface is mixed
Miscellaneous area, the 4th P-doped zone are located between the source electrode and drain electrode of the reset transistor, and the 4th P-doped zone
Doping concentration be greater than first P-doped zone doping concentration.
Preferably, the cmos image sensor further includes between the photodiode and the reset transistor
Transfering transistor, the transfering transistor and the reset transistor common-source, the N-doped zone of the light emitting diode
Drain electrode also as the transfering transistor.
Photoelectronic leakage can be effectively suppressed by designing above, reduce the pixel dark current of CIS chip, so as to improve
CIS picture element flaw improves CIS chip quality.
Detailed description of the invention
Fig. 1 is shown as the equivalent circuit of the pixel unit circuit of the cmos image sensor of 4T type structure in the prior art
Structural schematic diagram.
Fig. 2 is shown as the step of preparation process in the active pixel area of the cmos image sensor of one embodiment of the invention.
The formation stages that Fig. 3-Figure 12 is shown as the active pixel area of the cmos image sensor of one embodiment of the invention show
It is intended to.
Figure 13 is shown as the structural schematic diagram of the cmos image sensor of the 4T type structure of one embodiment of the invention.
Component label instructions
1 p-type dope semiconductor substrates
2 photodiodes
21 N-doped zones
22 second P-doped zones
23 third P-doped zones
24 photoresist layers
241 photoresist layers with the first ion implantation window
242 photoresist layers with the second ion implantation window
3 reset transistors
31 first P-doped zones
32 the 4th P-doped zones
33 reset transistor gate polycrystal layers
34 reset transistor gate dielectric layers
35 reset transistor source electrodes
The drain electrode of 36 reset transistors
4 transfering transistors
41 transfer transistor gate dielectric layers
42 transfer transistor gate polycrystal layers
The step of preparation process of S10~S19 cmos image sensor
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
It should be noted that the basic conception that only the invention is illustrated in a schematic way is illustrated provided in the present embodiment,
Then only shown in schema with it is of the invention in related component rather than component count, shape and size when according to actual implementation draw
System, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel can also
It can be increasingly complex.
The preparation method of cmos image sensor of the invention is applicable to any field of pixel design, preferably, answering
Used in 3T or 4T structure.Below by taking 4T structure as an example, the preparation method of the present invention will be described in detail cmos image sensor.It is easy reason
Xie Di, those skilled in the art can make other dot structures, such as 3T structure according to the preparation method of the 4T structure.
Next having for cmos image sensor active pixel dark current will be reduced to of the invention in conjunction with Fig. 2~Figure 12
The preparation method in source pixel area is described in detail, comprising the following steps:
S10: as shown in figure 3, providing p-type dope semiconductor substrates 1, the shape on 1 surface of p-type dope semiconductor substrates
At photoresist layer 24.
S11: as shown in figure 4, being exposed to the photoresist layer 24 has the first ion implantation window with formation of developing
Photoresist layer 241.
S12: as shown in figure 5, carrying out N in p-type dope semiconductor substrates 1 by first ion implantation window 241
Type ion implanting forms N-doped zone 21.
As an example, the ion implantation energy of the N-doped zone 21 be 160kev-180kev, Doped ions be phosphorus or
Arsenic, doping thickness are
S13: as shown in fig. 6, carried out in the N-doped zone 21 by first ion implantation window 241 p-type from
The surface of son injection, Yu Suoshu N-doped zone forms the second P-doped zone 22.
As an example, the ion implantation energy of second P-doped zone 22 is 25kev-35kev, Doped ions two
Boron fluoride.
S14: as shown in fig. 7, part photoresist is removed using oxygen along the side of first ion implantation window, such as
Removal width is D, forms the photoresist layer 242 with the second ion implantation window.
S15: as shown in figure 8, carried out in the second P-doped zone 22 by second ion implantation window 242 p-type from
Son injection forms third P-doped zone 23 in the surface of the second P-doped zone 22, and second P-doped zone 22, N-type are mixed
Projection of the miscellaneous area 21 on the surface of the semiconductor substrate is entirely located in the third P-doped zone 23 on said surface
In projection, the second ion implantation window 242 is removed, to form photodiode 2.
As an example, the ion implantation energy of the third P-doped zone 23 is 25kev-35kev, Doped ions two
Boron fluoride.
As an example, the overall thickness of second P-doped zone 22 and the third P-doped zone 23 is
Second P-doped zone 22, projection of the N-doped zone 21 on the surface of the semiconductor substrate are entirely located in
In the projection of the third P-doped zone 23 on said surface, the photoelectron that the photodiode 2 generates can be effectively suppressed
It is revealed by the third P-doped zone 23 to surfaces of active regions, meanwhile, it, need to be when forming the third P-doped zone
Photoresist layer 242 is formed using oxygen removal part photoresist on the basis of original photoresist layer 241, so also not needing to increase
Exposure mask amount.
S16: as shown in figure 9, ion implanting forms the first P-doped zone 31 in the p-type dope semiconductor substrates 1,
First P-doped zone 31 is formed in the side of the photodiode 2, while the doping of first P-doped zone 31 is dense
Degree is higher than the doping concentration of the p-type dope semiconductor substrates 1, and will be formed in first P-doped zone 31 and reset crystalline substance
Body pipe 3.
As an example, first P-doped zone 31 with a thickness ofDoped ions are boron difluoride.
S17: as shown in Figure 10, carrying out P-type ion injection on 31 surface of the first P-doped zone, brilliant in the reset
31 surface of the first P-doped zone in 3 region of body pipe forms the 4th P-doped zone 32, in conjunction with Figure 13, when the reset transistor
After 3 prepare, the 4th P-doped zone 32 is located between the source electrode 35 of the reset transistor 3 and drain electrode 36, and the 4th p-type
32 doping concentration of doped region is higher than first P-doped zone 31.Reset can be improved by forming the 4th P-doped zone 32
The channel inversion ability of transistor 3, so those skilled in the art's alternative setting as the case may be, that is, may be selected ion
The 4th P-doped zone 32 is injected, or the road technique is omitted in selection.
As an example, the 4th P-doped zone 32 with a thickness ofDoped ions are boron difluoride.
S18: as shown in figure 11, the grid of reset transistor 3, the grid are formed on the surface of the 4th P-doped zone 32
Pole includes that reset transistor gate dielectric layer 34 and reset transistor gate polycrystal layer 33 are being located at the photodiode 2 and institute
The grid that transfering transistor is formed between reset transistor 3 is stated, which includes transfer transistor gate dielectric layer 41 and transfer
Transistor gate polycrystal layer 42, the drain electrode of the transfering transistor 4 share the N-doped zone 21 of the photodiode 2.
As an example, the reset transistor gate dielectric layer 33 with a thickness ofThe transfer crystal
Tube grid dielectric layer 41 with a thickness of
S19: as shown in figure 12, the reset transistor gate two sides 32 surface of the 4th P-doped zone carry out N-type from
Son injection, forms source electrode 35 and the drain electrode 36 of reset transistor, and the source electrode 35 of the reset transistor and the thickness of drain electrode 36 are big
In the 4th P-doped zone thickness, and the source electrode of the transfering transistor 4 shares the source electrode 35 of the reset transistor.
As an example, the reset transistor 3 drain electrode 36 and source electrode 35 with a thickness ofAnd adulterate from
Son is phosphorus or arsenic.
As described above, reset transistor 3 is formed in first P-doped zone 31, and 31 shape of the first P-doped zone
The side of photodiode 2 described in Cheng Yu, then first P-doped zone 31 has three close to the boundary of the photodiode 2
Kind may, the first, the boundary alignment of the source electrode 35 of the boundary and the reset transistor close to the photodiode 2；The
Two kinds, the boundary be located at the source electrode 35 of the reset transistor close to the boundary of the photodiode 2 and photodiode 2 it
Between；The third, which is aligned with the photodiode 2.Optionally, as shown in this embodiment, referring to Fig.1 2, it is alternative
Be arranged the boundary be located at the source electrode 35 of the reset transistor close to the boundary of the photodiode 2 and photodiode 2 it
Between, the grid part of transfering transistor 4 is formed on the surface of first P-doped zone 31 at this time, is partially formed in the P
On the surface of type semiconductor substrate 1.
By the way that first P-doped zone 31 is arranged, 2 surrounding of the photodiode in each active pixel area by
P type island region domain with concentration gradient surrounds, and the concentration gradient is by the different p-type dope semiconductor substrates of doping concentration and the
One P-doped zone is formed, and which increase the isolation effects between active pixel area, to effectively photodiode 2 be inhibited to generate
Photoelectron by the p-type dope semiconductor substrates 1 to neighboring active pixel region reveal；In addition, since first p-type is mixed
The doping concentration in miscellaneous area 31 is higher than the doping concentration of the p-type dope semiconductor substrates 1, effectively inhibits the parasitism three of CMOS tube
Pole pipe effect can effectively cut off source electrode 35 of the photoelectron by the p-type dope semiconductor substrates 1 to the reset transistor 3
Or 36 leakage of drain electrode, while the leakage for also improving the breakdown voltage of the reset transistor 3, reducing the reset transistor 3
Electric current and the space depleted region for reducing the reset transistor 3, to improve the performance of the reset transistor.
Other known process methods can also be used in the step of 4T type active pixel area made above.It is to be understood that this
Embodiment only lists a pixel unit of the cmos image sensor, and actual quantity is not restricted by, can be according to specific
Situation setting is multiple.
Correspondingly, the present invention also provides a kind of cmos image sensors, according to the preparation side of above-mentioned cmos image sensor
Method is formed, and Figure 13 is please referred to, and is the 4T type active pixel structure prepared according to method described in specific embodiment of the invention Fig. 2,
Including p-type dope semiconductor substrates 1；Photodiode 2 and the reset transistor 3 for being formed in 2 side of photodiode, are prepared in
In the p-type dope semiconductor substrates 1；Wherein, it is formed with the first P-doped zone 31 in the p-type dope semiconductor substrates 1,
First P-doped zone 31 at least surrounds source electrode 35, drain electrode 36 and the channel region of the reset transistor, and described first
The doping concentration of P-doped zone 31 is higher than the doping concentration of the p-type dope semiconductor substrates 1, to reduce the dark of active pixel
Electric current；In addition, the cmos image sensor further includes between the photodiode 2 and the reset transistor 3
Transfering transistor 4 and output circuit.
As described above, reset transistor 3 at least surrounds source electrode 35, drain electrode 36 and the channel region of the reset transistor 3,
And first P-doped zone 31 is formed in the side of the photodiode 2, then first P-doped zone 31 is close to described
It is possible that there are three types of the boundaries of photodiode 2, the first, the source electrode 35 of the boundary and the reset transistor is close to the photoelectricity
The boundary alignment of diode 2；Second, which is located at the source electrode 35 of the reset transistor close to the photodiode 2
Boundary and photodiode 2 between；The third, which is aligned with the photodiode 2.Optionally, such as the present embodiment
It is shown, alternative be arranged the boundary be located at the source electrode 35 of the reset transistor close to the boundary of the photodiode 2 and
Between photodiode 2, the grid part of transfering transistor 4 is formed on the surface of first P-doped zone 31 at this time, portion
Divide and is formed on the surface of the P-type semiconductor substrate 1.
The photodiode 2 includes p-type dope semiconductor substrates 1, the N-type being formed on the P-type semiconductor substrate
Doped region 21, is formed in second P-doped zone 22 the second P-doped zone 22 being formed in the N-doped zone 21
Third P-doped zone 23, and second P-doped zone, projection of the N-doped zone on the surface of the semiconductor substrate
It is entirely located in the projection of the third P-doped zone on said surface.
Preferably selection, the ion implantation energy for forming the photodiode N-doped zone 21 is 160kev-
180kev, Doped ions are phosphorus or arsenic, and the ion implantation energy for forming second P-doped zone 22 is 25kev-35kev, shape
Ion implantation energy at the third P-doped zone 23 is 25kev-35kev, the doping of second P-doped zone 22 from
The Doped ions of the sub and described third P-doped zone 23 are boron difluoride.
As an example, the overall thickness that second P-doped zone 22 and the third P-doped zone 23 may be selected is The N-doped zone 21 with a thickness of
The reset transistor 3 includes p-type dope semiconductor substrates 1, the first P-doped zone 31, the 4th P-doped zone
32, reset transistor gate dielectric layer 34, reset transistor gate polycrystal layer 33, reset transistor source electrode 35, reset transistor
Drain electrode 36, first P-doped zone 31 at least surround source electrode 35, drain electrode 36 and the channel region of the reset transistor, institute
The doping concentration for stating the 4th P-doped zone 32 is greater than the doping concentration of first P-doped zone 31, and doping thickness is
Preferably selection, the source electrode and drain electrode of the reset transistor with a thickness ofAnd the doping
Ion is phosphorus or arsenic, the gate dielectric layer of the reset transistor with a thickness of
The channel inversion ability of reset transistor 3 can be improved in 4th P-doped zone 32, so those skilled in the art
After known scheme provided in this embodiment, it can selectively be arranged according to concrete condition, that is, the 4th P-doped zone of setting may be selected
32, or select to omit the layer.
The transfering transistor 4 is between the photodiode 2 and the reset transistor 3, including transfer crystal
The grid of pipe, source electrode and drain electrode, and the drain electrode of the transfering transistor shares the N-doped zone 21 of the light emitting diode, institute
The source electrode for stating transfering transistor shares the source electrode 35 of the reset transistor.
As an example, the gate dielectric layer 41 of the transfering transistor with a thickness of
Any field of pixel design is applicable to according to method made above cmos image sensor of the invention,
Preferably, applying in 3T or 4T structure.Be readily appreciated that ground, those skilled in the art can according to the preparation method of the above 4T structure,
Make other dot structures, such as 3T structure.
The present invention can effectively improve product yield, and facts proved that, product structure and method through the invention, product is good
Rate is improved from 90.9% before improvement to improved 95.8%, and Product Process stability is increased dramatically.
In conclusion cmos image sensor provided by the invention and preparation method thereof, by forming reset transistor
When, in p-type dope semiconductor substrates formed one first P-doped zone, and first P-doped zone at least surround it is described multiple
Source electrode, drain electrode and the channel region of bit transistor, then the photodiode surrounding is wrapped by the p type island region domain with concentration gradient
It encloses, increases the isolation effect between pixel, so that the photoelectron that effectively limitation photodiode generates is adulterated by the p-type
Semiconductor substrate is revealed to adjacent pixel unit；In addition, the doping concentration due to first P-doped zone is higher than the p-type
The doping concentration of dope semiconductor substrates effectively inhibits the parasitic triode effect of CMOS tube, and it is logical can effectively to cut off photoelectron
The p-type dope semiconductor substrates are crossed to the source electrode of the reset transistor or drain electrode leakage, while also improving the reset
The breakdown voltage of transistor, the leakage current for reducing the reset transistor and the space for reducing the reset transistor
Depleted region, to improve the performance of the reset transistor.By the way that the third P-doped zone is arranged, and make the 2nd P
The projection of type doped region, N-doped zone on the surface of the semiconductor substrate is entirely located in the third P-doped zone in institute
State in the projection on surface, can be effectively suppressed photoelectron that the photodiode generates by the third P-doped zone to
Surfaces of active regions leakage, while not increasing exposure mask amount yet.Photoelectronic leakage can be effectively suppressed by designing above, reduce pixel
Dark current improves CIS chip quality so as to improve sensor pixel defect.So the present invention effectively overcomes in the prior art
Various shortcoming and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (18)
1. a kind of preparation method of cmos image sensor, which is characterized in that the preparation method includes at least:
P-type dope semiconductor substrates are provided；
The first P-doped zone, and the doping concentration of first P-doped zone are formed in the p-type dope semiconductor substrates
Higher than the doping concentration of the p-type dope semiconductor substrates；
Reset transistor is formed, first P-doped zone is located at.
2. the preparation method of cmos image sensor according to claim 1, it is characterised in that: the first p-type doping
Area with a thickness ofDoped ions are boron difluoride.
3. the preparation method of cmos image sensor according to claim 1, which is characterized in that further include: prepare photoelectricity
The step of diode, first P-doped zone is located at the periphery of the photodiode, prepares the photodiode includes:
Photoresist layer is formed on p-type dope semiconductor substrates surface；
The photoresist layer is exposed and the photoresist layer for being formed and having the first ion implantation window that develops；
N-type ion injection is carried out in the p-type dope semiconductor substrates by first ion implantation window, described in formation
The N-doped zone of photodiode；
P-type ion injection is carried out in the N-doped zone of the photodiode by first ion implantation window, in institute
The surface layer for stating N-doped zone forms the second P-doped zone；
Part photoresist is removed along the side of first ion implantation window, to expand ion implantation window, being formed has the
The photoresist layer of two ion implantation windows；
P-type ion injection, the 2nd P of Yu Suoshu are carried out in second P-doped zone by second ion implantation window
The surface layer of type doped region forms third P-doped zone, so that second P-doped zone, N-doped zone are served as a contrast in the semiconductor
Projection on the surface at bottom is entirely located in the projection of the third P-doped zone on said surface.
4. cmos image sensor according to claim 3, it is characterised in that: first P-doped zone is close to described
Boundary alignment of the source electrode of the boundary of photodiode and the reset transistor close to the photodiode；Alternatively,
First P-doped zone is located at the source electrode of the reset transistor close to described close to the boundary of the photodiode
Between the boundary and photodiode of photodiode；Alternatively,
First P-doped zone is aligned close to the boundary of the photodiode with the photodiode.
5. the preparation method of cmos image sensor according to claim 3, it is characterised in that: form two pole of photoelectricity
The ion implantation energy of pipe N-doped zone is 160kev-180kev, and Doped ions are phosphorus or arsenic, and doping thickness is Alternatively,
The ion implantation energy for forming second P-doped zone is 25kev-35kev, the doping of second P-doped zone
Ion is boron difluoride；Alternatively,
The ion implantation energy for forming the third P-doped zone is 25kev-35kev, the doping of the third P-doped zone
Ion is boron difluoride.
6. the preparation method of cmos image sensor according to claim 3, it is characterised in that: the second p-type doping
Area and the overall thickness of the third P-doped zone are
7. the preparation method of cmos image sensor according to claim 1, it is characterised in that: prepare the reset crystal
The step of pipe includes:
The grid of reset transistor is formed on first P-doped zone surface；
N-type ion injection is carried out in the first P-doped zone of the grid two sides of the reset transistor, and it is brilliant to form the reset
The source electrode and drain electrode of body pipe.
8. the preparation method of cmos image sensor according to claim 1, it is characterised in that: prepare the reset crystal
The step of pipe further includes that ion implanting forms the 4th P-doped zone, the 4th p-type on the first P-doped zone of Yu Suoshu surface
Doped region is located between the source electrode and drain electrode of the reset transistor, and the doping concentration of the 4th P-doped zone is greater than described
The doping concentration of first P-doped zone.
9. the preparation method of cmos image sensor according to claim 3, it is characterised in that: the preparation method is also wrapped
Include the step of preparing the transfering transistor between the photodiode and the reset transistor, and the transfer crystal
Pipe and the reset transistor common-source, the N-doped zone of the light emitting diode are also used as the leakage of the transfering transistor
Pole.
10. a kind of cmos image sensor, which is characterized in that the cmos image sensor includes:
P-type dope semiconductor substrates；
The first P-doped zone, and the doping concentration of first P-doped zone are formed in the p-type dope semiconductor substrates
Higher than the doping concentration of the p-type dope semiconductor substrates；
Reset transistor is located at first P-doped zone.
11. cmos image sensor according to claim 10, it is characterised in that: the thickness of first P-doped zone
ForDoped ions are boron difluoride.
12. cmos image sensor according to claim 10, which is characterized in that further include: photodiode, described
One P-doped zone is located at the periphery of the photodiode, and the photodiode includes:
The N-doped zone being formed in the P-type semiconductor substrate；
The second P-doped zone being formed in the N-doped zone；
The third P-doped zone being formed in second P-doped zone, second P-doped zone, N-doped zone are in institute
The projection on the surface of semiconductor substrate is stated to be entirely located in the projection of the third P-doped zone on said surface.
13. cmos image sensor according to claim 12, it is characterised in that: first P-doped zone is close to institute
State photodiode boundary and the reset transistor source electrode close to the photodiode boundary alignment；Alternatively,
First P-doped zone is located at the source electrode of the reset transistor close to described close to the boundary of the photodiode
Between the boundary and photodiode of photodiode；Alternatively,
First P-doped zone is aligned close to the boundary of the photodiode with the photodiode.
14. cmos image sensor according to claim 12, it is characterised in that: form the photodiode N-type and mix
The ion implantation energy in miscellaneous area is 160kev-180kev, and Doped ions are phosphorus or arsenic, and doping thickness isOr
Person,
The ion implantation energy for forming second P-doped zone is 25kev-35kev, the doping of second P-doped zone
Ion is boron difluoride；Alternatively,
The ion implantation energy for forming the third P-doped zone is 25kev-35kev, the doping of the third P-doped zone
Ion is boron difluoride.
15. cmos image sensor according to claim 12, it is characterised in that: second P-doped zone with it is described
The overall thickness of third P-doped zone is
16. cmos image sensor according to claim 10, which is characterized in that the reset transistor includes:
It is formed in the grid of the reset transistor on first P-doped zone surface；
It is formed in the source electrode and drain electrode of the reset transistor of the reset transistor gate two sides, the source electrode and drain electrode is located at institute
It states in the first P-doped zone.
17. cmos image sensor according to claim 10, it is characterised in that: the reset transistor further includes a shape
The 4th P-doped zone on first P-doped zone surface described in Cheng Yu, the 4th P-doped zone are located at the reset crystal
Between the source electrode and drain electrode of pipe, and the doping concentration of the 4th P-doped zone is dense greater than the doping of first P-doped zone
Degree.
18. cmos image sensor according to claim 12, it is characterised in that: the cmos image sensor further includes
Transfering transistor between the photodiode and the reset transistor, the transfering transistor and the reset are brilliant
Body pipe common-source, the N-doped zone of the light emitting diode are also used as the drain electrode of the transfering transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710929682.8A CN109638025B (en) | 2017-10-09 | 2017-10-09 | CMOS image sensor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710929682.8A CN109638025B (en) | 2017-10-09 | 2017-10-09 | CMOS image sensor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109638025A true CN109638025A (en) | 2019-04-16 |
| CN109638025B CN109638025B (en) | 2020-10-16 |
Family
ID=66051188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710929682.8A Active CN109638025B (en) | 2017-10-09 | 2017-10-09 | CMOS image sensor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109638025B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534537A (en) * | 2019-08-30 | 2019-12-03 | 西安电子科技大学 | A kind of CMOS image sensor pixel structure and preparation method thereof |
| CN112599549A (en) * | 2020-12-14 | 2021-04-02 | 华虹半导体(无锡)有限公司 | CMOS image sensor |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020190288A1 (en) * | 2001-06-19 | 2002-12-19 | Samsung Electronics Co., Ltd. | CMOS type image sensor |
| US20070158771A1 (en) * | 2005-12-29 | 2007-07-12 | Magnachip Semiconductor Ltd. | Stratified photodiode for high resolution CMOS image sensor implemented with STI technology |
| CN101192570A (en) * | 2006-11-27 | 2008-06-04 | 东部高科股份有限公司 | CMOS image sensor |
| KR100836507B1 (en) * | 2006-12-27 | 2008-06-09 | 동부일렉트로닉스 주식회사 | Method for fabricating cmos image sensor |
| CN101752394A (en) * | 2008-12-08 | 2010-06-23 | 全视科技有限公司 | CMOS image sensor with improved backside surface treatment |
| CN103500750A (en) * | 2013-10-21 | 2014-01-08 | 上海华力微电子有限公司 | Structure of active pixel of CMOS (Complementary Metal Oxide Semiconductor) image sensor and manufacturing method thereof |
| CN103904092A (en) * | 2014-03-14 | 2014-07-02 | 复旦大学 | Silicon-based CMOS image sensor and method for improving electron transfer efficiency of silicon-based CMOS image sensor |
| CN104992954A (en) * | 2015-05-27 | 2015-10-21 | 上海华力微电子有限公司 | Method for reducing dark current of image sensor |
-
2017
- 2017-10-09 CN CN201710929682.8A patent/CN109638025B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020190288A1 (en) * | 2001-06-19 | 2002-12-19 | Samsung Electronics Co., Ltd. | CMOS type image sensor |
| US20070158771A1 (en) * | 2005-12-29 | 2007-07-12 | Magnachip Semiconductor Ltd. | Stratified photodiode for high resolution CMOS image sensor implemented with STI technology |
| CN101192570A (en) * | 2006-11-27 | 2008-06-04 | 东部高科股份有限公司 | CMOS image sensor |
| KR100836507B1 (en) * | 2006-12-27 | 2008-06-09 | 동부일렉트로닉스 주식회사 | Method for fabricating cmos image sensor |
| CN101752394A (en) * | 2008-12-08 | 2010-06-23 | 全视科技有限公司 | CMOS image sensor with improved backside surface treatment |
| CN103500750A (en) * | 2013-10-21 | 2014-01-08 | 上海华力微电子有限公司 | Structure of active pixel of CMOS (Complementary Metal Oxide Semiconductor) image sensor and manufacturing method thereof |
| CN103904092A (en) * | 2014-03-14 | 2014-07-02 | 复旦大学 | Silicon-based CMOS image sensor and method for improving electron transfer efficiency of silicon-based CMOS image sensor |
| CN104992954A (en) * | 2015-05-27 | 2015-10-21 | 上海华力微电子有限公司 | Method for reducing dark current of image sensor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534537A (en) * | 2019-08-30 | 2019-12-03 | 西安电子科技大学 | A kind of CMOS image sensor pixel structure and preparation method thereof |
| CN110534537B (en) * | 2019-08-30 | 2021-10-29 | 西安电子科技大学 | CMOS image sensor pixel structure and manufacturing method thereof |
| CN112599549A (en) * | 2020-12-14 | 2021-04-02 | 华虹半导体(无锡)有限公司 | CMOS image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109638025B (en) | 2020-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101352436B1 (en) | An image sensor | |
| JP5295105B2 (en) | Low crosstalk PMOS pixel structure | |
| US6713796B1 (en) | Isolated photodiode | |
| CN102362351B (en) | Back-illuminated cmos image sensors | |
| CN104517983B (en) | Solid state image pickup device, its manufacture method and imaging system | |
| US7651883B2 (en) | High energy implant photodiode stack | |
| CN103500750B (en) | The structure of a kind of cmos image sensor active pixel and manufacture method thereof | |
| US10325955B2 (en) | CMOS image sensor with backside biased substrate | |
| CN101388360B (en) | Image sensor and method for manufacturing the same | |
| CN104377216B (en) | Image sensor and fabricating method of image sensor | |
| US9287319B2 (en) | CMOS multi-pinned (MP) pixel | |
| JP2005310826A (en) | Solid-state imaging device | |
| TWI451564B (en) | Image sensor having two epitaxial layers and method for making the same | |
| JP2009065155A (en) | Image sensor | |
| CN109638025A (en) | Cmos image sensor and preparation method thereof | |
| US7948018B2 (en) | Multilayer image sensor structure for reducing crosstalk | |
| US10304882B1 (en) | Source follower device for enhanced image sensor performance | |
| TWI637495B (en) | Cmos image sensor, a photodiode thereof and a method of forming the same | |
| CN101471367B (en) | Image sensor and method for manufacturing the sensor | |
| KR20100080149A (en) | Method for manufacturing an image sensor | |
| CN101471372A (en) | Image sensor and method for manufacturing the sensor | |
| KR100790584B1 (en) | Image sensor having a partially fully depletion floating diffusion node | |
| JP2018139328A (en) | Solid-state imaging apparatus and imaging system | |
| KR100718775B1 (en) | Image sensor and method for manufacturing the same | |
| KR101038886B1 (en) | Image Sensor and Method for Manufacturing thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |