CN109638025B - CMOS image sensor and preparation method thereof - Google Patents
CMOS image sensor and preparation method thereof Download PDFInfo
- Publication number
- CN109638025B CN109638025B CN201710929682.8A CN201710929682A CN109638025B CN 109638025 B CN109638025 B CN 109638025B CN 201710929682 A CN201710929682 A CN 201710929682A CN 109638025 B CN109638025 B CN 109638025B
- Authority
- CN
- China
- Prior art keywords
- type doped
- doped region
- photodiode
- reset transistor
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000005468 ion implantation Methods 0.000 claims description 55
- 239000010410 layer Substances 0.000 claims description 31
- 150000002500 ions Chemical class 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 21
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 4
- JXASPPWQHFOWPL-UHFFFAOYSA-N Tamarixin Natural products C1=C(O)C(OC)=CC=C1C1=C(OC2C(C(O)C(O)C(CO)O2)O)C(=O)C2=C(O)C=C(O)C=C2O1 JXASPPWQHFOWPL-UHFFFAOYSA-N 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention provides a CMOS image sensor and a preparation method thereof, wherein the preparation method at least comprises the following steps: providing a P-type doped semiconductor substrate, forming a first P-type doped region in the P-type doped semiconductor substrate, wherein the doping concentration of the first P-type doped region is higher than that of the P-type doped semiconductor substrate, and forming a reset transistor which is positioned in the first P-type doped region; the method also comprises a step of preparing the photodiode, wherein the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all positioned in the projection of the third P-type doped region on the surface. Through the design, the leakage of photoelectrons can be effectively inhibited, and the pixel dark current of the CIS chip is reduced, so that the CIS pixel defect is improved, and the CIS chip quality is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a CMOS image sensor and a preparation method thereof.
Background
Compared with a Charge Coupled Device (CCD) image sensor, a CMOS Image Sensor (CIS) has superior performance in terms of compatibility between its manufacturing process and the existing integrated circuit manufacturing process. The CIS can integrate the driving circuit and the pixels, thereby simplifying the hardware design and greatly reducing the power consumption of the system. The CIS can take out the electric signal while collecting the optical signal, can process image information in real time, has a speed higher than that of a CCD image sensor, and has the advantages of low price, large bandwidth, anti-blur, access flexibility, large filling coefficient and the like.
Conventional CIS is roughly classified into PPS, APS, and DPS depending on the reading method. A Passive Pixel Sensor (PPS) is the earliest appearing structure, and includes a Photodiode (Photodiode) and a Row-select (Row-select) transistor, where the Photodiode is essentially a PN junction composed of a P-type semiconductor and an N-type semiconductor, and the Photodiode can be equivalently a reverse biased diode connected in parallel with a MOS capacitor. When reading, the row selection transistor is opened, the charges are integrated by the integrator of the column, and finally the voltage is read out. Compared with a passive Pixel structure, an Active Pixel Structure (APS) includes a source follower (Sourcefollower), and the conventional Active Pixel structure is divided into a 3T structure and a 4T structure according to the number of transistors included in a Pixel unit circuit, and may further include a 5T structure. As shown in fig. 1, a 4T active pixel structure generally includes a Reset (Reset) transistor, a Source follower (Source follower), a Row-select (Row-select) transistor (not shown), a transfer Transistor (TX), and a Photodiode (PD), wherein the transfer transistor is used for inputting an electrical signal generated by the photodiode to a Floating Diffusion (FD). Due to the fact that the active circuit is added in the pixel unit, the PD signal is amplified and buffered in the pixel unit, the sensitivity of the CIS image sensor is improved, the signal reading speed is high, and the signal-to-noise ratio is high, so that the active pixel structure is widely used.
In the CIS chip, a phenomenon of a decrease in the function of the chip due to a pixel defect is often encountered, and a "dark current" in a pixel region is a main cause of the pixel defect, and the "dark current" is mainly caused by dissipation of photoelectrons, so that the decrease of the "pixel dark current" is a key direction for improving the quality of the CIS pixel. There are three main reasons in the conventional CIS manufacturing process for the dissipation of photoelectrons: first, weak isolation between pixels, resulting in gradual leakage of photoelectrons to the substrate of adjacent pixels; secondly, photoelectrons generated in the illumination stage cannot be well controlled in a well of the photodiode, so that the photoelectrons gradually leak to the surface of an active area of the pixel unit; third, the space dissipation area of the reset transistor is too large, causing photoelectrons to gradually leak to the source/drain of the reset transistor.
There is a need to improve the manufacturing process of CIS to reduce the dissipation of photoelectrons, thereby improving pixel defects to improve the quality of CIS chips.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a CMOS image sensor and a method for fabricating the same, which are used to solve the problem of dark current of a CIS chip due to photoelectron leakage in the fabrication process of the CIS in the prior art.
In order to achieve the above and other related objects, the present invention provides a CMOS image sensor manufacturing method, which at least includes: providing a P-type doped semiconductor substrate;
forming a first P-type doped region in the P-type doped semiconductor substrate, wherein the doping concentration of the first P-type doped region is higher than that of the P-type doped semiconductor substrate;
and forming a reset transistor which is positioned in the first P-type doped region.
Preferably, the thickness of the first P-type doped region is
The dopant ion is boron difluoride.
Preferably, the preparation method further includes preparing a photodiode, the first P-type doped region is located at the periphery of the photodiode, and the step of preparing the photodiode includes:
forming a photoresist layer on the surface of the P-type doped semiconductor substrate;
exposing and developing the photoresist layer to form a photoresist layer with a first ion implantation window;
performing N-type ion implantation on the P-type doped semiconductor substrate through the first ion implantation window to form an N-type doped region of the photodiode;
performing P-type ion implantation on the N-type doped region of the photodiode through the first ion implantation window, and forming a second P-type doped region on the surface layer of the N-type doped region;
removing part of the photoresist along the peripheral side of the first ion implantation window to enlarge the ion implantation window and form a photoresist layer with a second ion implantation window;
and performing P-type ion implantation on the second P-type doped region through the second ion implantation window, and forming a third P-type doped region on the surface layer of the second P-type doped region, so that the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all positioned in the projection of the third P-type doped region on the surface.
By arranging the third P-type doped region and enabling the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate to be all positioned in the projection of the third P-type doped region on the surface, the photoelectrons generated by the photodiode can be effectively inhibited from leaking to the surface of the active region through the third P-type doped region, and meanwhile, when the third P-type doped region is formed, only oxygen is used for removing part of photoresist on the basis of the original photoresist layer 241, so that the mask amount is not required to be increased.
Further, the boundary of the first P-type doped region close to the photodiode is aligned with the boundary of the source of the reset transistor close to the photodiode; or,
the boundary of the first P-type doped region close to the photodiode is positioned between the boundary of the source of the reset transistor close to the photodiode and the photodiode; or,
the first P-type doped region is aligned with the photodiode near a boundary of the photodiode.
Furthermore, the ion implantation energy for forming the photodiode N-type doped region is 160-180 kev, the doped ions are phosphorus or arsenic, and the doping thickness is
Or,
the ion implantation energy for forming the second P-type doped region is 25-35 kev, and the doped ions of the second P-type doped region are boron difluoride; or,
the ion implantation energy for forming the third P-type doped region is 25-35 kev, and the doped ions of the third P-type doped region are boron difluoride.
Further, the total thickness of the second P-type doped region and the third P-type doped region is
Preferably, the step of preparing the reset transistor includes:
forming a grid electrode of a reset transistor on the surface of the first P-type doped region;
and carrying out N-type ion implantation on the first P-type doped regions at two sides of the grid of the reset transistor to form a source electrode and a drain electrode of the reset transistor.
By arranging the first P-type doped region, the periphery of the photodiode in each active pixel region is surrounded by the P-type region with concentration gradient, the concentration gradient is formed by the P-type doped semiconductor substrate and the first P-type doped region, the isolation effect between active pixels is increased, and therefore photoelectrons generated by the photodiode are effectively limited from leaking to adjacent pixel units through the P-type doped semiconductor substrate; in addition, because the doping concentration of the first P-type doping region is higher than that of the P-type doping semiconductor substrate, the parasitic triode effect of a CMOS (complementary metal oxide semiconductor) tube is effectively inhibited, photoelectrons can be effectively cut off from leaking to the source electrode or the drain electrode of the reset transistor through the P-type doping semiconductor substrate, the breakdown voltage of the reset transistor is improved, the leakage current of the reset transistor is reduced, the space depletion region of the reset transistor is reduced, and therefore the performance of the reset transistor is improved.
Preferably, the step of manufacturing the reset transistor further includes forming a fourth P-type doped region by ion implantation on the surface of the first P-type doped region, where the fourth P-type doped region is located between the source and the drain of the reset transistor, and the doping concentration of the fourth P-type doped region is greater than that of the first P-type doped region, and the forming of the fourth P-type doped region can improve the channel inversion capability of the reset transistor.
Preferably, the preparation method further comprises the step of preparing a transfer transistor between the photodiode and the reset transistor, the transfer transistor and the reset transistor share a source, and the N-type doped region of the light emitting diode also serves as a drain of the transfer transistor.
Accordingly, the present invention also provides a CMOS image sensor manufactured by the above method for manufacturing a CMOS image sensor, comprising:
a P-type doped semiconductor substrate;
a first P-type doped region is formed in the P-type doped semiconductor substrate, and the doping concentration of the first P-type doped region is higher than that of the P-type doped semiconductor substrate;
and the reset transistor is positioned in the first P-type doped region.
Preferably, the thickness of the first P-type doped region is
The dopant ion is boron difluoride.
Preferably, the method further comprises the following steps: a photodiode, the first P-type doped region being located at a periphery of the photodiode, the photodiode comprising:
an N-type doped region formed on the P-type semiconductor substrate;
a second P-type doped region formed on the N-type doped region;
and the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all positioned in the projection of the third P-type doped region on the surface.
Further, the boundary of the first P-type doped region close to the photodiode is aligned with the boundary of the source of the reset transistor close to the photodiode; or,
the boundary of the first P-type doped region close to the photodiode is positioned between the boundary of the source of the reset transistor close to the photodiode and the photodiode; or,
the first P-type doped region is aligned with the photodiode near a boundary of the photodiode.
Furthermore, the ion implantation energy for forming the photodiode N-type doped region is 160-180 kev, the doped ions are phosphorus or arsenic, and the doping thickness is
Or,
the ion implantation energy for forming the second P-type doped region is 25-35 kev, and the doped ions of the second P-type doped region are boron difluoride; or,
the ion implantation energy for forming the third P-type doped region is 25-35 kev, and the doped ions of the third P-type doped region are boron difluoride.
Preferably, the total thickness of the second P-type doped region and the third P-type doped region is
Preferably, the reset transistor includes:
a gate of the reset transistor formed on a surface of the first P-type doped region;
and the source electrode and the drain electrode of the reset transistor are formed at two sides of the grid electrode of the reset transistor and are positioned in the first P-type doped region.
Preferably, the reset transistor further includes a fourth P-type doped region formed on the surface of the first P-type doped region, the fourth P-type doped region is located between the source and the drain of the reset transistor, and the doping concentration of the fourth P-type doped region is greater than the doping concentration of the first P-type doped region.
Preferably, the CMOS image sensor further comprises a transfer transistor located between the photodiode and the reset transistor, the transfer transistor and the reset transistor share a source, and the N-type doped region of the light emitting diode also serves as a drain of the transfer transistor.
Through the design, the leakage of photoelectrons can be effectively inhibited, and the pixel dark current of the CIS chip is reduced, so that the CIS pixel defect is improved, and the CIS chip quality is improved.
Drawings
Fig. 1 is a schematic diagram showing an equivalent circuit structure of a pixel unit circuit of a CMOS image sensor of a 4T type structure in the related art.
Fig. 2 shows a process step of fabricating an active pixel region of a CMOS image sensor according to an embodiment of the invention.
Fig. 3-12 are schematic diagrams illustrating stages in forming an active pixel region of a CMOS image sensor according to an embodiment of the invention.
Fig. 13 is a schematic structural diagram of a CMOS image sensor with a 4T-shaped structure according to an embodiment of the invention.
Description of the element reference numerals
1P-type doped semiconductor substrate
2 photodiode
21N type doped region
22 second P-type doped region
23 third P-type doped region
24 photo resist layer
241 photoresist layer with first ion implantation window
242 photoresist layer with second ion implantation window
3 reset transistor
31 first P-type doped region
32 fourth P-type doped region
33 reset transistor gate poly
34 reset transistor gate dielectric layer
35 reset transistor source
36 reset transistor drain
4-transfer transistor
41 transfer transistor gate dielectric layer
42 transfer transistor gate poly
Preparation process steps of S10-S19 CMOS image sensor
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The preparation method of the CMOS image sensor can be suitable for any field of pixel design, and is preferably applied to a 3T or 4T structure. The following describes the method for fabricating a CMOS image sensor according to the present invention in detail, taking a 4T structure as an example. It is easily understood that other pixel structures, such as a 3T structure, can be fabricated by those skilled in the art according to the method for fabricating the 4T structure.
The following will describe in detail a method for manufacturing an active pixel region capable of reducing dark current of an active pixel of a CMOS image sensor according to the present invention with reference to fig. 2 to 12, including the following steps:
s10: as shown in fig. 3, a P-type doped semiconductor substrate 1 is provided, and a photoresist layer 24 is formed on the surface of the P-type doped semiconductor substrate 1.
S11: as shown in fig. 4, the photoresist layer 24 is exposed and developed to form a photoresist layer 241 having a first ion implantation window.
S12: as shown in fig. 5, N-type ion implantation is performed on the P-type doped semiconductor substrate 1 through the first ion implantation window 241 to form an N-type doped region 21.
As an example, the ion implantation energy of the N-type doped region 21 is 160kev to 180kev, the doped ions are phosphorus or arsenic, and the doping thickness is
S13: as shown in fig. 6, P-type ions are implanted into the N-type doped region 21 through the first ion implantation window 241, so as to form a second P-type doped region 22 on the surface of the N-type doped region.
As an example, the ion implantation energy of the second P-type doped region 22 is 25kev to 35kev, and the dopant ions are boron difluoride.
S14: as shown in fig. 7, a photoresist layer 242 having a second ion implantation window is formed by removing a portion of the photoresist along the peripheral side of the first ion implantation window, for example, by a width D.
S15: as shown in fig. 8, P-type ions are implanted into the second P-type doped region 22 through the second ion implantation window 242, a third P-type doped region 23 is formed on the surface of the second P-type doped region 22, and the projections of the second P-type doped region 22 and the N-type doped region 21 on the surface of the semiconductor substrate are all located in the projection of the third P-type doped region 23 on the surface, and the second ion implantation window 242 is removed, thereby forming the photodiode 2.
As an example, the ion implantation energy of the third P-type doped region 23 is 25kev to 35kev, and the dopant ion is boron difluoride.
As an example, the total thickness of the second P-type doped region 22 and the third P-type doped region 23 is
The projections of the second P-type doped region 22 and the N-type doped region 21 on the surface of the semiconductor substrate are all located in the projection of the third P-type doped region 23 on the surface, which can effectively inhibit the photoelectrons generated by the photodiode 2 from leaking to the surface of the active region through the third P-type doped region 23, and meanwhile, when the third P-type doped region is formed, only oxygen is used to remove a part of photoresist on the basis of the original photoresist layer 241 to form the photoresist layer 242, so that the mask amount does not need to be increased.
S16: as shown in fig. 9, a first P-type doped region 31 is formed on the P-type doped semiconductor substrate 1 by ion implantation, the first P-type doped region 31 is formed on one side of the photodiode 2, the doping concentration of the first P-type doped region 31 is higher than that of the P-type doped semiconductor substrate 1, and a reset transistor 3 is formed in the first P-type doped region 31. .
As an example, the thickness of the first P-type doped region 31 is
The dopant ion is boron difluoride.
S17: as shown in fig. 10, P-type ion implantation is performed on the surface of the first P-type doped region 31, a fourth P-type doped region 32 is formed on the surface of the first P-type doped region 31 in the reset transistor 3 region, and in combination with fig. 13, after the reset transistor 3 is prepared, the fourth P-type doped region 32 is located between the source 35 and the drain 36 of the reset transistor 3, and the doping concentration of the fourth P-type doped region 32 is higher than that of the first P-type doped region 31. The channel inversion capability of the reset transistor 3 can be improved by forming the fourth P-type doped region 32, so that a person skilled in the art can selectively set the fourth P-type doped region 32 according to specific situations, i.e., selectively implant ions into the fourth P-type doped region 32, or selectively omit the process.
As an example, the thickness of the fourth P-type doped region 32 is
The dopant ion is boron difluoride.
S18: as shown in fig. 11, a gate of the reset transistor 3 is formed on the surface of the fourth P-type doped region 32, the gate includes a reset transistor gate dielectric layer 34 and a reset transistor gate poly layer 33, the gate of the transfer transistor is formed between the photodiode 2 and the reset transistor 3, the gate includes a transfer transistor gate dielectric layer 41 and a transfer transistor gate poly layer 42, and the drain of the transfer transistor 4 shares the N-type doped region 21 of the photodiode 2.
As an example, the thickness of the reset transistor gate dielectric layer 33Is composed of
The thickness of the gate dielectric layer 41 of the transfer transistor is
S19: as shown in fig. 12, N-type ion implantation is performed on the surface of the fourth P-type doped region 32 on both sides of the gate of the reset transistor to form a source 35 and a drain 36 of the reset transistor, the thickness of the source 35 and the drain 36 of the reset transistor is greater than that of the fourth P-type doped region, and the source 35 of the reset transistor is shared by the sources of the transfer transistor 4.
As an example, the drain 36 and source 35 of the reset transistor 3 have a thickness of
And the dopant ions are phosphorus or arsenic.
As described above, the reset transistor 3 is formed in the first P-type doped region 31, and the first P-type doped region 31 is formed at one side of the photodiode 2, there are three possibilities that the first P-type doped region 31 is close to the boundary of the photodiode 2, and the boundary is aligned with the boundary of the source 35 of the reset transistor close to the photodiode 2; second, the boundary is located between the boundary of the source 35 of the reset transistor near the photodiode 2 and the photodiode 2; thirdly, the boundary is aligned with the photodiode 2. Alternatively, as shown in this embodiment, referring to fig. 12, the boundary may be selectively set between the boundary of the source 35 of the reset transistor close to the photodiode 2 and the photodiode 2, and at this time, the gate of the transfer transistor 4 is partially formed on the surface of the first P-type doped region 31 and partially formed on the surface of the P-type semiconductor substrate 1.
By arranging the first P-type doped region 31, the periphery of the photodiode 2 in each active pixel region is surrounded by a P-type region with a concentration gradient, the concentration gradient is formed by a P-type doped semiconductor substrate with different doping concentrations and the first P-type doped region, the isolation effect between the active pixel regions is increased, and therefore photoelectrons generated by the photodiode 2 are effectively prevented from leaking to the adjacent active pixel regions through the P-type doped semiconductor substrate 1; in addition, since the doping concentration of the first P-type doped region 31 is higher than that of the P-type doped semiconductor substrate 1, a parasitic triode effect of a CMOS transistor is effectively suppressed, photoelectrons can be effectively cut off from leaking to the source 35 or the drain 36 of the reset transistor 3 through the P-type doped semiconductor substrate 1, and meanwhile, the breakdown voltage of the reset transistor 3 is also improved, the leakage current of the reset transistor 3 is reduced, and the space depletion region of the reset transistor 3 is reduced, thereby improving the performance of the reset transistor.
Other well-known processes can be used in the above steps for preparing the 4T-type active pixel region. It is to be understood that the present embodiment only exemplifies one pixel unit of the CMOS image sensor, and the actual number thereof is not limited, and a plurality thereof may be provided according to specific situations.
Accordingly, the present invention further provides a CMOS image sensor formed according to the above-mentioned CMOS image sensor manufacturing method, please refer to fig. 13, which is a 4T-type active pixel structure manufactured according to the method described in fig. 2 of the present invention, and includes a P-type doped semiconductor substrate 1; a photodiode 2 and a reset transistor 3 formed at one side of the photodiode 2, which are prepared on the P-type doped semiconductor substrate 1; a first P-type doped region 31 is formed on the P-type doped semiconductor substrate 1, the first P-type doped region 31 at least surrounds the source 35, the drain 36 and the channel region of the reset transistor, and the doping concentration of the first P-type doped region 31 is higher than that of the P-type doped semiconductor substrate 1, so as to reduce the dark current of the active pixel; in addition, the CMOS image sensor further includes a transfer transistor 4 and an output circuit between the photodiode 2 and the reset transistor 3.
As described above, the reset transistor 3 surrounds at least the source 35, the drain 36 and the channel region of the reset transistor 3, and the first P-type doped region 31 is formed at one side of the photodiode 2, there are three possibilities that the first P-type doped region 31 is close to the boundary of the photodiode 2, and the boundary is aligned with the boundary of the source 35 of the reset transistor close to the photodiode 2; second, the boundary is located between the boundary of the source 35 of the reset transistor near the photodiode 2 and the photodiode 2; thirdly, the boundary is aligned with the photodiode 2. Alternatively, as shown in this embodiment, the boundary may be selectively set between the boundary of the source 35 of the reset transistor close to the photodiode 2 and the photodiode 2, and at this time, the gate of the transfer transistor 4 is partially formed on the surface of the first P-type doped region 31 and partially formed on the surface of the P-type semiconductor substrate 1.
The photodiode 2 comprises a P-type doped semiconductor substrate 1, an N-type doped region 21 formed on the P-type doped semiconductor substrate, a second P-type doped region 22 formed on the N-type doped region 21, and a third P-type doped region 23 formed on the second P-type doped region 22, wherein the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all located in the projection of the third P-type doped region on the surface.
Preferably, the ion implantation energy for forming the photodiode N-type doped region 21 is 160kev to 180kev, the dopant ion is phosphorus or arsenic, the ion implantation energy for forming the second P-type doped region 22 is 25kev to 35kev, the ion implantation energy for forming the third P-type doped region 23 is 25kev to 35kev, and the dopant ion for forming the second P-type doped region 22 and the dopant ion for forming the third P-type doped region 23 are boron difluoride.
As an example, the total thickness of the second P-type doped region 22 and the third P-type doped region 23 may be selected to be
The thickness of the N-type doped region 21 is
The reset transistor 3 comprises a P-type doped semiconductor substrate 1, a first P-type doped region 31, a fourth P-type doped region 32, a reset transistor gate dielectric layer 34, a reset transistor gate polycrystalline layer 33, a reset transistor source 35 and a reset transistor drain 36, wherein the first P-type doped region 31 at least surrounds the source 35, the drain 36 and a channel region of the reset transistor, the doping concentration of the fourth P-type doped region 32 is greater than that of the first P-type doped region 31, and the doping thickness is equal to
Preferably, the source and drain of the reset transistor have a thickness of
The doped ions are phosphorus or arsenic, and the thickness of the grid dielectric layer of the reset transistor is
The fourth P-type doped region 32 can improve the channel inversion capability of the reset transistor 3, so that after the solution provided by the embodiment is known to those skilled in the art, the fourth P-type doped region 32 can be selectively disposed according to specific situations, i.e., the layer can be selectively omitted.
The transfer transistor 4 is located between the photodiode 2 and the reset transistor 3, and includes a gate, a source and a drain of the transfer transistor, the drain of the transfer transistor shares the N-type doped region 21 of the light emitting diode, and the source of the transfer transistor shares the source 35 of the reset transistor.
By way of example, the thickness of the gate dielectric layer 41 of the transfer transistor is
According to the above manufacturing method, the CMOS image sensor of the present invention can be applied to any field of pixel design, preferably, to 3T or 4T structures. It is easily understood that other pixel structures, such as 3T structures, can be fabricated by those skilled in the art according to the above method for fabricating 4T structures.
The invention can effectively improve the yield of products, and the fact proves that the yield of the products is improved from 90.9 percent before improvement to 95.8 percent after improvement by the product structure and the method, and the process stability of the products is greatly improved.
In summary, according to the CMOS image sensor and the method for manufacturing the same provided by the present invention, when the reset transistor is formed, the first P-type doped region is formed on the P-type doped semiconductor substrate, and the first P-type doped region at least surrounds the source, the drain and the channel region of the reset transistor, so that the photodiode is surrounded by the P-type region with a concentration gradient, thereby increasing the isolation effect between pixels, and effectively limiting the leakage of photoelectrons generated by the photodiode to the adjacent pixel units through the P-type doped semiconductor substrate; in addition, because the doping concentration of the first P-type doping region is higher than that of the P-type doping semiconductor substrate, the parasitic triode effect of a CMOS (complementary metal oxide semiconductor) tube is effectively inhibited, photoelectrons can be effectively cut off from leaking to the source electrode or the drain electrode of the reset transistor through the P-type doping semiconductor substrate, the breakdown voltage of the reset transistor is improved, the leakage current of the reset transistor is reduced, the space depletion region of the reset transistor is reduced, and therefore the performance of the reset transistor is improved. Through the arrangement of the third P-type doped region, and the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all positioned in the projection of the third P-type doped region on the surface, the photoelectrons generated by the photodiode can be effectively inhibited from leaking to the surface of the active region through the third P-type doped region, and the mask amount is not increased. Through the design, the leakage of photoelectrons can be effectively inhibited, and the pixel dark current is reduced, so that the pixel defect of the sensor is improved, and the quality of a CIS chip is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (16)
1. A method for manufacturing a CMOS image sensor, the method at least comprising:
providing a P-type doped semiconductor substrate;
forming a first P-type doped region in the P-type doped semiconductor substrate, wherein the doping concentration of the first P-type doped region is higher than that of the P-type doped semiconductor substrate;
forming a reset transistor which is positioned in the first P-type doped region;
preparing a photodiode, wherein the first P-type doped region is positioned at the periphery of the photodiode, and the step of preparing the photodiode comprises the following steps:
forming a photoresist layer on the surface of the P-type doped semiconductor substrate;
exposing and developing the photoresist layer to form a photoresist layer with a first ion implantation window;
performing N-type ion implantation on the P-type doped semiconductor substrate through the first ion implantation window to form an N-type doped region of the photodiode;
performing P-type ion implantation on the N-type doped region of the photodiode through the first ion implantation window, and forming a second P-type doped region on the surface layer of the N-type doped region;
removing part of the photoresist along the peripheral side of the first ion implantation window to enlarge the ion implantation window and form a photoresist layer with a second ion implantation window;
and performing P-type ion implantation on the second P-type doped region through the second ion implantation window, and forming a third P-type doped region on the surface layer of the second P-type doped region, so that the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all positioned in the projection of the third P-type doped region on the surface.
2. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the thickness of the first P-type doped region is
The dopant ion is boron difluoride.
3. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the boundary of the first P-type doped region close to the photodiode is aligned with the boundary of the source electrode of the reset transistor close to the photodiode; or,
the boundary of the first P-type doped region close to the photodiode is positioned between the boundary of the source of the reset transistor close to the photodiode and the photodiode; or,
the first P-type doped region is aligned with the photodiode near a boundary of the photodiode.
4. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the ion implantation energy for forming the photodiode N-type doped region is 160-180 kev, the doped ions are phosphorus or arsenic, and the doping thickness is
Or,
the ion implantation energy for forming the second P-type doped region is 25-35 kev, and the doped ions of the second P-type doped region are boron difluoride; or,
the ion implantation energy for forming the third P-type doped region is 25-35 kev, and the doped ions of the third P-type doped region are boron difluoride.
5. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the total thickness of the second P-type doped region and the third P-type doped region is
6. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the step of preparing the reset transistor includes:
forming a grid electrode of a reset transistor on the surface of the first P-type doped region;
and carrying out N-type ion implantation on the first P-type doped regions at two sides of the grid of the reset transistor to form a source electrode and a drain electrode of the reset transistor.
7. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the step of preparing the reset transistor further comprises the step of forming a fourth P-type doped region by ion implantation on the surface of the first P-type doped region, wherein the fourth P-type doped region is positioned between the source electrode and the drain electrode of the reset transistor, and the doping concentration of the fourth P-type doped region is greater than that of the first P-type doped region.
8. The method for manufacturing a CMOS image sensor according to claim 1, wherein: the preparation method also comprises the step of preparing a transfer transistor positioned between the photodiode and the reset transistor, wherein the transfer transistor and the reset transistor share a source electrode, and the N-type doped region of the photodiode also serves as a drain electrode of the transfer transistor.
9. A CMOS image sensor, comprising:
a P-type doped semiconductor substrate;
a first P-type doped region is formed in the P-type doped semiconductor substrate, and the doping concentration of the first P-type doped region is higher than that of the P-type doped semiconductor substrate;
the reset transistor is positioned in the first P-type doped region;
a photodiode, the first P-type doped region being located at a periphery of the photodiode, the photodiode comprising:
an N-type doped region formed in the P-type semiconductor substrate;
a second P-type doped region formed on the N-type doped region;
and the projections of the second P-type doped region and the N-type doped region on the surface of the semiconductor substrate are all positioned in the projection of the third P-type doped region on the surface.
10. The CMOS image sensor of claim 9, wherein: the thickness of the first P-type doped region is
The dopant ion is boron difluoride.
11. The CMOS image sensor of claim 9, wherein: the boundary of the first P-type doped region close to the photodiode is aligned with the boundary of the source electrode of the reset transistor close to the photodiode; or,
the boundary of the first P-type doped region close to the photodiode is positioned between the boundary of the source of the reset transistor close to the photodiode and the photodiode; or,
the first P-type doped region is aligned with the photodiode near a boundary of the photodiode.
12. The CMOS image sensor of claim 9, wherein: the ion implantation energy for forming the photodiode N-type doped region is 160-180 kev, the doped ions are phosphorus or arsenic, and the doping thickness is
Or,
the ion implantation energy for forming the second P-type doped region is 25-35 kev, and the doped ions of the second P-type doped region are boron difluoride; or,
the ion implantation energy for forming the third P-type doped region is 25-35 kev, and the doped ions of the third P-type doped region are boron difluoride.
13. The CMOS image sensor of claim 9, wherein: the total thickness of the second P-type doped region and the third P-type doped region is
14. The CMOS image sensor of claim 9, wherein the reset transistor comprises:
a gate of the reset transistor formed on a surface of the first P-type doped region;
and the source electrode and the drain electrode of the reset transistor are formed at two sides of the grid electrode of the reset transistor and are positioned in the first P-type doped region.
15. The CMOS image sensor of claim 9, wherein: the reset transistor also comprises a fourth P-type doped region formed on the surface of the first P-type doped region, the fourth P-type doped region is positioned between the source electrode and the drain electrode of the reset transistor, and the doping concentration of the fourth P-type doped region is greater than that of the first P-type doped region.
16. The CMOS image sensor of claim 9, wherein: the CMOS image sensor also comprises a transfer transistor positioned between the photodiode and the reset transistor, the transfer transistor and the reset transistor share a source electrode, and the N-type doped region of the photodiode also serves as a drain electrode of the transfer transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710929682.8A CN109638025B (en) | 2017-10-09 | 2017-10-09 | CMOS image sensor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710929682.8A CN109638025B (en) | 2017-10-09 | 2017-10-09 | CMOS image sensor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109638025A CN109638025A (en) | 2019-04-16 |
| CN109638025B true CN109638025B (en) | 2020-10-16 |
Family
ID=66051188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710929682.8A Active CN109638025B (en) | 2017-10-09 | 2017-10-09 | CMOS image sensor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109638025B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534537B (en) * | 2019-08-30 | 2021-10-29 | 西安电子科技大学 | CMOS image sensor pixel structure and manufacturing method thereof |
| CN112599549A (en) * | 2020-12-14 | 2021-04-02 | 华虹半导体(无锡)有限公司 | CMOS image sensor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192570A (en) * | 2006-11-27 | 2008-06-04 | 东部高科股份有限公司 | CMOS image sensor |
| KR100836507B1 (en) * | 2006-12-27 | 2008-06-09 | 동부일렉트로닉스 주식회사 | Method for fabricating cmos image sensor |
| CN101752394A (en) * | 2008-12-08 | 2010-06-23 | 全视科技有限公司 | CMOS image sensor with improved backside surface treatment |
| CN103500750A (en) * | 2013-10-21 | 2014-01-08 | 上海华力微电子有限公司 | Structure of active pixel of CMOS (Complementary Metal Oxide Semiconductor) image sensor and manufacturing method thereof |
| CN103904092A (en) * | 2014-03-14 | 2014-07-02 | 复旦大学 | Silicon-based CMOS image sensor and method for improving electron transfer efficiency of silicon-based CMOS image sensor |
| CN104992954A (en) * | 2015-05-27 | 2015-10-21 | 上海华力微电子有限公司 | Method for reducing dark current of image sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020096336A (en) * | 2001-06-19 | 2002-12-31 | 삼성전자 주식회사 | Cmos type image sensor |
| US7633134B2 (en) * | 2005-12-29 | 2009-12-15 | Jaroslav Hynecek | Stratified photodiode for high resolution CMOS image sensor implemented with STI technology |
-
2017
- 2017-10-09 CN CN201710929682.8A patent/CN109638025B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192570A (en) * | 2006-11-27 | 2008-06-04 | 东部高科股份有限公司 | CMOS image sensor |
| KR100836507B1 (en) * | 2006-12-27 | 2008-06-09 | 동부일렉트로닉스 주식회사 | Method for fabricating cmos image sensor |
| CN101752394A (en) * | 2008-12-08 | 2010-06-23 | 全视科技有限公司 | CMOS image sensor with improved backside surface treatment |
| CN103500750A (en) * | 2013-10-21 | 2014-01-08 | 上海华力微电子有限公司 | Structure of active pixel of CMOS (Complementary Metal Oxide Semiconductor) image sensor and manufacturing method thereof |
| CN103904092A (en) * | 2014-03-14 | 2014-07-02 | 复旦大学 | Silicon-based CMOS image sensor and method for improving electron transfer efficiency of silicon-based CMOS image sensor |
| CN104992954A (en) * | 2015-05-27 | 2015-10-21 | 上海华力微电子有限公司 | Method for reducing dark current of image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109638025A (en) | 2019-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100381026B1 (en) | CMOS Image sensor capable of increasing punch through voltage and charge integration of photodiode and method for forming the same | |
| KR100760913B1 (en) | CMOS Image Sensor and Method for Manufacturing the same | |
| KR100535926B1 (en) | Method for Manufacturing CMOS Image Sensor | |
| US7855407B2 (en) | CMOS image sensor and method for manufacturing the same | |
| JP3584196B2 (en) | Light receiving element and photoelectric conversion device having the same | |
| US20090121264A1 (en) | Cmos image sensor and method of forming the same | |
| US20030151076A1 (en) | Image sensor having photo diode and method for manufacturing the same | |
| KR100660275B1 (en) | Transfer Transistor of CMOS Image Sensor and Manufacturing Method Thereof | |
| US7678643B2 (en) | Method for manufacturing a CMOS image sensor | |
| KR100558530B1 (en) | CMOS Image Sensor And Method For Manufacturing The Same | |
| CN109638025B (en) | CMOS image sensor and preparation method thereof | |
| CN110797368A (en) | Image sensor unit and method for manufacturing the same | |
| JP2004312039A (en) | Photoelectric conversion device | |
| US20110187909A1 (en) | Method and system for cmos image sensing device | |
| CN110021614B (en) | Source follower device for enhanced image sensor performance | |
| KR20070071040A (en) | Cmos image sensor and method for manufacturing the same | |
| US6194260B1 (en) | Method of forming a CMOS sensor | |
| KR20110000853A (en) | Image sensor and method for manufacturing thereof | |
| KR100861607B1 (en) | Optical sensor and manufacturing method of the same | |
| JP2018067615A (en) | Solid-state imaging device, method of manufacturing the same, and electronic device | |
| CN100413052C (en) | CMOS image sensor and a method for fabricating the same | |
| KR100871798B1 (en) | Image sensor and method for manufacturing thereof | |
| KR20040095910A (en) | Cmos image sensor and method of manufacturing the same | |
| JP4700919B2 (en) | Solid-state image sensor | |
| KR20080008543A (en) | Cmos image sensor and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |